WO2012063787A1 - Display device - Google Patents

Display device Download PDF

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Publication number
WO2012063787A1
WO2012063787A1 PCT/JP2011/075624 JP2011075624W WO2012063787A1 WO 2012063787 A1 WO2012063787 A1 WO 2012063787A1 JP 2011075624 W JP2011075624 W JP 2011075624W WO 2012063787 A1 WO2012063787 A1 WO 2012063787A1
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WO
WIPO (PCT)
Prior art keywords
coordinate detection
pixel
data signal
signal line
display device
Prior art date
Application number
PCT/JP2011/075624
Other languages
French (fr)
Japanese (ja)
Inventor
耕平 田中
誠一 内田
杉田　靖博
Original Assignee
シャープ株式会社
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Publication date
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Publication of WO2012063787A1 publication Critical patent/WO2012063787A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels

Definitions

  • the present invention relates to a display device having a touch panel function.
  • a display device in which the display panel itself has an input position detection function (touch panel function) has been proposed.
  • touch panel function various problems associated with the conventional configuration in which the transparent tablet is provided independently on the front surface of the display panel can be solved.
  • the problems include a decrease in light transmittance from the display panel due to the presence of the transparent tablet, an increase in parallax between the input position and the display position, an increase in cost, and an increase in module thickness and module area.
  • the display panel includes a data signal line DL and a coordinate detection line SL extending in the column direction (vertical direction in the drawing), a scanning signal line GL extending in the row direction (horizontal direction in the drawing), and a storage capacitor.
  • the wiring CSL and the reference wiring Com are provided with pixels arranged in the row and column directions.
  • the data signal line DL, the scanning signal line GL, and the storage capacitor line CSL are provided on the active matrix substrate, and the coordinate detection line SL and the reference line Com are provided on the counter substrate.
  • Each pixel has the same structure, and one data signal line DL, coordinate detection line SL, scanning signal line GL, storage capacitor line CSL, and reference line Com are provided for each pixel. .
  • the pixel electrode is connected to the data signal line DL through a transistor connected to the scanning signal line GL, and a storage capacitor Ch is formed between the pixel electrode and the storage capacitor line CSL.
  • a liquid crystal capacitor Clc is formed between the pixel electrode and the reference line Com, while a mutual capacitor Cf is formed between the coordinate detection line SL and the reference line Com on the counter substrate.
  • the reference wiring Com is electrically connected to the storage capacitor wiring CSL at the transition portion, and a signal (Vcom) supplied to the reference wiring Com is a signal (storage capacitor wiring signal) supplied to the storage capacitor wiring CSL. ).
  • the coordinate detection line SL and the reference wiring line Com when the coordinate detection target object approaches or contacts the display panel, the coordinate detection line SL and the reference wiring line Com when the coordinate detection target object approaches or contacts the display panel By reading the change in the mutual capacitance Cf, the input position of the coordinate detection object can be detected.
  • the present invention has been made in view of the above problems, and an object of the present invention is to reduce the frame size and increase the definition of a display panel in a display device having an input position detection function.
  • the display device of the present invention provides A first substrate on which a reference wiring, a scanning signal line, a transistor having a control terminal connected to the scanning signal line, and a pixel electrode; A second substrate on which data signal lines are formed; A display device comprising a display panel including a liquid crystal layer sandwiched between the first and second substrates, The pixel electrode is electrically connected to the reference wiring through the transistor and overlaps the data signal line through the liquid crystal layer.
  • a coordinate detection line is formed on the second substrate via an insulating layer, A capacitor is formed between the coordinate detection line and the data signal line.
  • the data signal line is provided on a second substrate different from the first substrate on which the scanning signal line is provided, and also has a function as a signal line for coordinate detection, and the coordinate detection line provided on the second substrate.
  • the capacitance is formed between the two. Therefore, unlike the prior art, it is not necessary to connect the signal line for coordinate detection to the signal line on the first substrate side, so that the display panel can be made narrower and higher in definition.
  • the pixel electrode is electrically connected to the reference wiring through the transistor and overlaps the data signal line through the liquid crystal layer.
  • the second substrate is characterized in that a coordinate detection line that overlaps the data signal line is formed through an insulating layer, and a capacitor is formed between the coordinate detection line and the data signal line.
  • the display panel can be made narrower and higher in definition.
  • FIG. 2 is an equivalent circuit diagram of a display panel in the display device shown in FIG. 1.
  • FIG. 3 is an equivalent circuit diagram for explaining the operation of the display panel in the display device shown in FIG. 1.
  • FIG. 2 is a perspective view illustrating a configuration of a display panel in the display device illustrated in FIG. 1.
  • FIG. 2 is a cross-sectional view illustrating a configuration of a display panel in the display device illustrated in FIG. 1.
  • FIG. 2 is a plan view illustrating a configuration of a display panel in the display device illustrated in FIG. 1.
  • FIG. 10 is a plan view showing a configuration of a display panel of another mode (Modification 1) of the display device according to Embodiment 1.
  • FIG. 11 is a plan view showing a configuration of a display panel of another form (Modification 2) of the display device according to Embodiment 1.
  • FIG. 10 is a plan view showing a configuration of a display panel of another mode (Modification 1) of the display device according to Embodiment 1.
  • FIG. 11 is a plan view showing a configuration of a display panel of another form (Modification 2) of the display device according to Embodiment 1.
  • FIG. 10 is a plan view showing a configuration of a display panel of another mode (Modification 3) of the display device according to Embodiment 1. It is the top view which showed the structure of the display apparatus which concerns on Embodiment 2 of this invention. It is an equivalent circuit schematic of the display panel in the display device according to Embodiment 3 of the present invention.
  • FIG. 10 is an equivalent circuit diagram of a display panel in a display device according to Embodiment 4 of the present invention. It is sectional drawing which showed the structure of the display panel in the display apparatus shown in FIG. 15 is a timing chart showing an operation of the display panel shown in FIG. It is the block diagram which showed the structure of the display apparatus which concerns on Embodiment 5 of this invention. It is an equivalent circuit diagram which shows the structure of the conventional liquid crystal display.
  • a display device having an input position detection function (touch panel function) according to the present invention will be described below.
  • the display device according to the present invention can be mounted on any device having a liquid crystal display device as a display device having a touch panel function on a display panel having a display function. As an example, it can be applied to a portable terminal.
  • FIG. 1 is a block diagram of the display device according to the first embodiment.
  • the display device shown in FIG. 1 includes a display panel 1 having both an image display function and a mutual capacitive touch panel function, a scanning signal line driving circuit 2 and a data signal line driving circuit 3 for driving the display panel 1, and a scanning signal.
  • a display control circuit 4 for supplying display control signals to the line drive circuit 2 and the data signal line drive circuit 3, a timing controller 6, a coordinate detection line readout circuit 7, a coordinate detection circuit 8, a reference wiring drive circuit 9, and a power source Circuit 10.
  • the display panel 1 is an active matrix type liquid crystal display panel in which a liquid crystal layer is sandwiched between two opposing substrates (active matrix substrate, counter substrate).
  • FIG. 2 shows an equivalent circuit of the display panel 1.
  • the display panel 1 includes a data signal line 12 extending in the column direction (vertical direction in the drawing), a scanning signal line 14 extending in the row direction (horizontal direction in the drawing), a reference wiring 13, and coordinate detection. It comprises pixels arranged in line 20, row and column directions.
  • the scanning signal line 14 and the reference wiring 13 are provided on the active matrix substrate (first substrate), and the data signal line 12 and the coordinate detection line 20 are provided on the counter substrate (second substrate).
  • each pixel is the same, and one data signal line 12, one coordinate detection line 20, one scanning signal line 14, and one reference wiring 13 are provided corresponding to one pixel.
  • the pixel electrode 15 is connected to the reference wiring 13 via a transistor (TFT) 17 connected to the scanning signal line 14, and in the counter substrate, the data signal line 12 is connected to the counter electrode. 16 is connected.
  • a liquid crystal capacitor Clc is formed between the pixel electrode 15 and the counter electrode 16, and a mutual capacitor Cf is formed between the coordinate detection line 20 and the data signal line 12.
  • the transistor 17 provided in each pixel has a source electrode connected to the pixel electrode 15, a drain electrode connected to the reference wiring 13, and a gate electrode connected to the scanning signal line 14. Thereby, the transistor 17 is controlled to be turned on / off by the scanning signal (gate signal) supplied from the scanning signal line 14, and in response to the data signal applied between the reference wiring 13 and the data signal line 12 when turned on.
  • the voltage is applied to the liquid crystal layer, and the voltage is held when the transistor 17 is turned off.
  • This configuration is shown separately in FIG. 3 when n lines are selected and when n + 1 lines are selected.
  • the coordinate detection line 20 (FIG. 2) is omitted for convenience of explanation.
  • FIG. 2 the coordinate detection line 20
  • the scanning signal line 14 (n) is on and the scanning signal line 14 (n + 1) is off when the n line is selected, and the scanning signal line 14 (n) is off when the n + 1 line is selected.
  • the signal line 14 (n + 1) is on.
  • the transistor 17 is turned on and a voltage corresponding to the data signal is applied to the liquid crystal layer.
  • the transistor 17 is turned off and the voltage corresponding to the data signal is applied to the liquid crystal capacitor. It can be seen that Clc is retained.
  • FIG. 4 is a schematic perspective view of three pixels arranged in the row direction in the display panel 1
  • FIG. 5 is a schematic cross-sectional view of four pixels arranged in the column direction in the display panel 1.
  • FIG. 3 is a top view of the display panel 1.
  • the data signal line 12, the pixel electrode 15, the scanning signal line 14, the reference wiring 13, and the coordinate detection line 20 are drawn so as to be seen through the counter substrate 22.
  • the display panel 1 includes an active matrix substrate 21 made of glass or the like and an optical matrix made of glass or the like facing the active matrix substrate 21 at a predetermined interval.
  • the substrate 22 is composed of a liquid crystal layer (not shown) sandwiched between the active matrix substrate 21 and the counter substrate 22.
  • the liquid crystal layer various types of liquid crystal layers can be used.
  • the active matrix substrate 21 is electrically connected to the transistor 17, the scanning signal line 14 that partially becomes the gate electrode 23 of the transistor 17, and the drain electrode 24 of the transistor 17 on the surface facing the counter substrate 22.
  • the reference wiring 13 and the pixel electrode 15 electrically connected to the source electrode 25 of the transistor 17 are formed.
  • the reference wiring 13 and the scanning signal line 14 are formed of the same metal layer such as a tantalum layer, but may be formed of different metal layers.
  • a gate insulating film such as a silicon nitride film is typically formed on substantially the entire surface of the active matrix substrate 21 so as to cover the gate electrode 23 and the scanning signal line 14 of the transistor 17.
  • an active semiconductor layer (not shown) constituting the transistor 17, a drain electrode 24, a source electrode 25, and a pixel electrode 15 are formed.
  • the pixel electrode 15 is formed of a transparent conductive film such as ITO.
  • a stripe-shaped counter electrode 16 common to all the pixels arranged in the column direction and a stripe-shaped coordinate detection line 20 arranged in the row direction are formed on the counter substrate 22 .
  • An insulating layer 18 is formed between the counter electrode 16 and the coordinate detection line 20 (FIG. 5).
  • the counter electrode 16 is formed transparently by an ITO layer or the like, and one end of the counter electrode 16 is different from the data signal line input portion formed on the active matrix substrate 21 in the transition portion provided outside the display area in the display panel 1. They are electrically connected by a isotropic conductive film or the like.
  • the counter electrode 16 may be configured to be connected to the data signal line input unit via an FPC provided on the counter substrate 22 side. As described above, the counter electrode 16 also functions as the data signal line 12.
  • the counter electrode 16 is referred to as a data signal line 12.
  • the coordinate detection line 20 can be formed of the same ITO layer as the counter electrode 16, but may be formed of a different metal layer. As shown in FIG. 1, one end of the coordinate detection line 20 is connected to the coordinate detection line readout circuit 7, and one end of the data signal line 12 is connected to the data signal line drive circuit 3.
  • the coordinate detection line 20 is formed so as to overlap the scanning signal line 14 and / or the reference wiring 13 when the display panel 1 is viewed in plan (from the observer side). Therefore, it is possible to prevent a decrease in transmittance due to the provision of the coordinate detection line 20.
  • the counter electrode 16 (data signal line 12) and the coordinate detection line 20 overlap with each other through the insulating layer 18 at a portion where they intersect each other, and a mutual capacitance Cf is formed at this intersection. It has become. Note that the counter electrode 16 (data signal line 12) and the coordinate detection line 20 may be formed in the same layer, and only the intersection may overlap with the insulating layer 18 interposed therebetween.
  • the timing controller 6 generates timing control signals such as various synchronization signals and supplies them to the data signal line drive circuit 3, the display control circuit 4, the coordinate detection line readout circuit 7, and the coordinate detection circuit 8.
  • the display control circuit 4 detects image display timing based on a timing control signal supplied from the timing controller 6 and displays an image on the display panel 1 based on display data and a synchronization signal input from the outside.
  • the display control signal is generated.
  • the generated display control signal is supplied to the scanning signal line driving circuit 2 and the data signal line driving circuit 3 to control the operations of the scanning signal line driving circuit 2 and the data signal line driving circuit 3.
  • the display control circuit 4 generates a coordinate detection pulse signal based on the timing control signal supplied from the timing controller 6, and supplies the generated coordinate detection pulse signal to the data signal line drive circuit 3.
  • the scanning signal line drive circuit 2 sequentially supplies a scanning signal (gate signal) to each scanning signal line 14 of the display panel 1 shown in FIG. 2 based on the display control signal output from the display control circuit 4. As a result, the transistor 17 whose gate electrode is a part of the scanning signal line 14 supplied with the scanning signal is turned on.
  • the data signal line driving circuit 3 supplies a data signal to the data signal line 12 via the data signal line input unit based on the display control signal. As a result, a voltage corresponding to the data signal is applied to the liquid crystal layer through the transistor 17 in the on state, and image information is written.
  • the data signal line driving circuit 3 sequentially supplies the coordinate detection pulse signal supplied from the display control circuit 4 to the data signal line 12 based on the timing control signal supplied from the timing controller 6.
  • the coordinate detection line readout circuit 7 detects the fluctuation (change amount) of the charge (current) of the coordinate detection line 20 based on the timing control signal supplied from the timing controller 6.
  • the coordinate detection circuit 8 detects the coordinate detection timing based on the timing control signal supplied from the timing controller 6, and calculates the coordinates of the coordinate detection target object based on the amount of change in the charge acquired by the coordinate detection line readout circuit 7. To detect.
  • the scanning signal generated by the scanning signal line driving circuit 2 and the data signal generated by the data signal line driving circuit 3 are generated based on the bias voltage from the power supply circuit 10.
  • the reference wiring drive circuit 9 supplies a reference voltage (for example, Vcom) of a predetermined level generated by the bias voltage supplied from the power supply circuit 10 to the reference wiring 13.
  • Vcom a reference voltage
  • the scanning signal line driving circuit 2, the data signal line driving circuit 3, the display control circuit 4, and the reference wiring driving circuit 9 constitute display control means, and the data signal line driving circuit 3
  • the coordinate detection line readout circuit 7 and the coordinate detection circuit 8 constitute position detection means.
  • the data signal line 12 has both a function as a signal line for image display and a function as a signal line for coordinate detection.
  • one frame period is time-divided into a display data writing period for displaying an image on the display panel 1 and a display data holding period such as a vertical blanking period.
  • the display data writing period is basically the same as the operation in a normal active matrix type liquid crystal display device, it will be briefly described. That is, based on the display control signal supplied from the display control circuit 4, the scanning signal line driving circuit 2 sequentially selects the scanning signal lines 14 for each row, and the data signal line driving circuit 3 selects all the data signal lines 12. The signal potential corresponding to the display data is supplied. When the transistor 17 is turned off, the potential difference (voltage) between the data signal line 12 (counter electrode 16) and the reference wiring 13 is held in the liquid crystal capacitor Clc connected to the transistor 17, and an image is displayed.
  • the position detection in the present invention uses a so-called mutual capacitance method.
  • the principle of this method is that a pulse voltage is applied to the drive electrode using the drive electrode and the receive electrode, and a mutual capacitance is formed between the drive electrode and the receive electrode.
  • the position is detected by utilizing this change in mutual capacitance when approaching or touching.
  • Coordinate detection (hereinafter also referred to as position detection) is performed in synchronization with a timing control signal supplied from the timing controller 6 in order along the row direction along a plurality of data signal lines 12 with pulse voltages (coordinates). Detection pulse signal) is applied, and the amount of change in the charge on the coordinate detection line 20 corresponding to the change in the mutual capacitance Cf formed between the coordinate detection line 20 and the coordinate detection line 20 is detected.
  • FIGS. 8A to 8C are diagrams illustrating the principle of position detection realized by the display panel 1 in the display device shown in FIG.
  • (I) Assume a display panel configuration in which data signal lines (ii) and data signal lines (iii) are arranged in this order in the row direction ((b) in FIG. 8). In the configuration shown in FIG. 8, the multipoint in the case where two points of the coordinate detection line (A) and the data signal line (i) and the coordinate detection line (C) and the data signal line (iii) are touched. The touch will be described.
  • the pulse signal (coordinate detection pulse signal) in the order of the data signal line (i), the data signal line (ii), and the data signal line (iii).
  • the pulse signal Is input, during the period (t1 to t2) in which the pulse signal is input to the data signal line (i), the charge that flows through the coordinate detection line (A) according to the change in the mutual capacitance Cf by touching. Changes, and the amount of change in the charge is converted into a voltage value (detection pulse I in (a) in FIG. 8).
  • the coordinates of the intersection of the coordinate detection line (A) and the data signal line (i) can be specified.
  • the electric charge flowing in the coordinate detection line is changed by touching, and the coordinate (position) of the coordinate detection object can be specified by reading the change amount of the electric charge.
  • the coordinate detection line 20 arranged in the row direction on the counter substrate 22 of the display panel 1 and the data signal line 12 arranged in the column direction on the counter substrate 22 are used to coordinate.
  • the coordinate position of the detection object can be detected. That is, since the data signal line 12 can also be used as a position detection drive electrode, the display panel 1 can be made narrower and higher in definition.
  • the configuration has been described in which the counter substrate 22 is the outermost surface and a coordinate detection target object such as a finger approaches or contacts the counter substrate 22, but the present invention is not limited to this.
  • another member may be disposed on the surface side of the counter substrate 22 as long as the detection operation described above is not hindered.
  • a polarizing layer and / or a cover layer are mentioned, for example.
  • the position detection operation is performed once in the display data holding period in one frame (60 Hz) in FIG. 7A, but the present invention is not limited to this.
  • one frame (60 Hz) may be performed twice in the display data holding period.
  • the sensing frequency becomes 120 Hz, the coordinate detection speed of the coordinate detection object can be further increased, and it is possible to cope with faster operations (such as pen input).
  • the sensing may be performed three or more times during the display data holding period.
  • sensing may be performed once or a plurality of times for each of a plurality of frames (n (n is an integer of 2 or more) frames).
  • n is an integer of 2 or more
  • the coordinate detection pulse signal is sequentially supplied for each data signal line 12 in the position detection operation.
  • the present invention is not limited to this, and each of the plurality of data signal lines 12 is not limited thereto. It is good also as a structure supplied sequentially. The same applies to each form to be described later.
  • the present invention is not limited to this.
  • the coordinate detection line 20 may be used as a drive electrode
  • the data signal line 12 may be used as a reception electrode.
  • one end of the data signal line 12 may be connected to the data signal line driving circuit 3 and the other end may be connected to the coordinate detection line readout circuit 7.
  • display is performed by supplying display data to each data signal line 12, and in the position detection operation, the display control circuit 4 detects the coordinates based on the timing control signal supplied from the timing controller 6.
  • the pulse signal is sequentially supplied to the coordinate detection line 20, the coordinate detection line readout circuit 7 reads the amount of change in the charge of the data signal line 12, and the coordinate detection circuit 8 converts the amount of change into a voltage value.
  • the position of the coordinate detection object can be specified.
  • FIG. 10 is a top view when the display panel 1 according to Modification 2 is viewed from above.
  • each data signal line 12 is provided with a notch 12a at the intersection with the coordinate detection line 20, and the line width of the data signal line 12 is narrowed at that portion.
  • the notch part 12a the area of the part which the data signal line 12 and the coordinate detection line 20 overlap becomes small. Therefore, unnecessary parasitic capacitance is reduced, and the mutual capacitance Cf formed by the coordinate detection line 20 and the data signal line 12 can be relatively increased. Thereby, since a signal can be raised, the precision of the coordinate detection of a coordinate detection target object can be raised.
  • FIG. 11 is a top view when the display panel 1 according to Modification 3 is viewed from above.
  • each coordinate detection line 20 extends in the row direction, and a branched coordinate detection line 20 a is formed in a region that does not overlap the data signal lines 12, that is, a region between the data signal lines 12.
  • the detection signal can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection object can be increased.
  • Embodiment 2 Another embodiment according to the present invention will be described below with reference to FIG.
  • the same member number is attached
  • each coordinate detection line 20 as a reception electrode is connected to the coordinate detection line readout circuit 7 and a position detection operation is performed for each coordinate detection line 20.
  • the coordinate detection lines 20 are electrically bundled at one end every several lines, and the coordinate detection lines are read out for each bundle (group).
  • the position detection operation is performed by being connected to the circuit 7.
  • the coordinate detection pulse signal is sequentially applied to the data signal line 12 as the drive electrode, and the charge change is performed for each bundle of coordinate detection lines 20 (20A, 20B, 20C,).
  • the position of the coordinate detection object is specified by reading the quantity.
  • the amount of change in the charge of the coordinate detection line 20 analyzed by the coordinate detection circuit 8 does not represent the change in the mutual capacitance Cf for each coordinate detection line 20, but a bundle (group). Is equivalent to an accumulation of changes in the mutual capacitance Cf in the plurality of coordinate detection lines 20 (20A, 20B, 20C,). Therefore, since the signal can be increased, the accuracy of coordinate detection of the coordinate detection target can be increased.
  • Embodiment 3 Another embodiment according to the present invention will be described below with reference to FIG.
  • the same member number is attached
  • one pixel includes three sub pixels (R sub pixel, G sub pixel, and B sub pixel), and in each pixel, the R sub pixel, the G sub pixel, and the B sub pixel are the same.
  • the sub-pixels of the same color are arranged side by side in the pixels arranged in order in the column direction and adjacent in the row direction. Further, one scanning signal line 14, one reference wiring 13, and one coordinate detection line 20 are provided corresponding to one subpixel.
  • the number of coordinate detection lines 20 can be increased as compared with the configuration of the display device according to the first embodiment, and thus the mutual capacitance formed by the coordinate detection lines 20 and the data signal lines 12.
  • the amount of change in Cf can be increased. Therefore, the detection signal can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection target can be further increased.
  • the display device according to the present invention can also be applied to a so-called multi-pixel form in which one pixel includes two sub-pixels (first and second sub-pixels).
  • FIG. 14 is an equivalent circuit of a multi-pixel display panel provided in the display device of the present embodiment
  • FIG. 15 is a schematic cross-sectional view of four pixels arranged in the column direction of the display panel.
  • the data signal lines 12 are formed on the counter substrate 22 as in the display panels of the above-described embodiments.
  • each pixel electrode included in each sub-pixel in one pixel is connected to one scanning signal line extending in the row direction via different transistors 17.
  • the first sub-pixel and the second sub-pixel are arranged in this order in the column direction, and in the two pixels arranged in the column direction, the pixel of the first sub-pixel in one pixel
  • the electrode and the pixel electrode of the second subpixel in the other pixel are connected to the same reference wiring 13 via different transistors 17. That is, one reference wiring 13 is arranged so as to be shared by two adjacent pixels.
  • the coordinate detection line 20 is formed so as to overlap the scanning signal line 14 or the reference wiring 13 when the display panel 1 is viewed in plan (from the observer side). Decrease in transmittance due to the provision of 20 can be prevented.
  • Reference voltages Com1 and Com2 having different potential levels are alternately supplied to the reference wirings 13 arranged in the column direction in the column direction. That is, in the first frame, in one pixel, a reference voltage of High level (Com1) is applied to the pixel electrode of one subpixel through the reference wiring 13, and the reference wiring is applied to the pixel electrode of the other subpixel. A low level (Com 2) reference voltage is applied via 13. Thereby, in the display data writing period of the first frame, one pixel can be a dark pixel and the other pixel can be a bright pixel. In the second frame, since the potential levels of the reference voltages Com1 and Com2 are reversed, one pixel can be a bright pixel and the other pixel can be a dark pixel. Thereby, in the display apparatus of this Embodiment, a viewing angle characteristic can be improved.
  • the mutual capacitance Cf formed by the coordinate detection line 20 and the data signal line 12 changes with the approach or contact of the coordinate detection object, Perform position detection.
  • the display device is configured to include a mutual capacitive touch panel function, but may be configured to include a self-capacitive touch panel function as another method.
  • a display device having a self-capacitance type touch panel function will be described focusing on differences from the display device of the first embodiment.
  • members having the same functions as those explained in the first embodiment are given the same member numbers, and explanation thereof is omitted.
  • FIG. 17 is a block diagram of the display device according to the present embodiment.
  • the display device shown in FIG. 17 includes a display panel 1 having both an image display function and a self-capacitance touch panel function, a scanning signal line driving circuit 2 and a data signal line driving circuit 3 for driving the display panel 1, and a scanning signal.
  • the equivalent circuit of the display panel 1 is as shown in FIG.
  • Each pixel has the same structure, and one coordinate detection line 20, one scanning signal line 14, and one reference wiring 13 are provided in the row direction corresponding to one pixel, and the data signal line 12 is arranged in the column direction.
  • the pixel electrode 15 is connected to the reference wiring 13 via a transistor (TFT) 17 connected to the scanning signal line 14, and in the counter substrate, the data signal line 12 is connected to the counter electrode. 16 is connected.
  • a liquid crystal capacitor Clc is formed between the pixel electrode 15 and the counter electrode 16.
  • one end of the coordinate detection line 20 is connected to the coordinate detection line drive circuit 11, and one end of the data signal line 12 is connected to the data signal line drive circuit 3.
  • the timing controller 6 generates timing control signals such as various synchronization signals and supplies them to the data signal line drive circuit 3, the display control circuit 4, the coordinate detection line drive circuit 11, and the coordinate detection circuit 8.
  • the data signal line driving circuit 3 supplies a data signal to the data signal line 12 via the data signal line input unit based on the display control signal. As a result, a voltage corresponding to the data signal is applied to the liquid crystal layer through the transistor 17 in the on state, and image information is written.
  • the coordinate detection line drive circuit 11 and the data signal line drive circuit 3 each function as a pulse signal readout circuit. That is, the coordinate detection line drive circuit 11 detects the capacitance (self-capacitance) formed between the coordinate detection line 20 and the coordinate detection object, and the data signal line drive circuit 3 detects the coordinate with the data signal line 12. A capacitance (self-capacitance) formed between the object and the object is detected.
  • the coordinate detection circuit 8 specifies the position of the coordinate detection object based on the respective capacities detected by the coordinate detection line drive circuit 11 and the data signal line drive circuit 3.
  • the position of the coordinate detection object can be specified.
  • the self-capacitance touch panel function can also be applied to the display devices according to the above embodiments.
  • the coordinate detection target based on the change in the capacity when the coordinate detection target object approaches or contacts the display panel during a display data holding period other than the display data writing period in which data corresponding to the display image is written to each pixel. It can also be set as the structure which detects the position coordinate of an object.
  • the coordinate detection object may be configured to be located on the opposite side of the second substrate from the first substrate side.
  • the detection intensity ratio can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection object can be increased.
  • the coordinate detection line may be extended in a direction intersecting with the data signal line.
  • the crossing portion of the data signal line with the coordinate detection line may be configured to have a narrower line width than the non-crossing portion.
  • the coordinate detection line may be formed so as to be branched in the extending direction of the data signal line so as to overlap an area between the data signal lines.
  • the change in the capacity formed by the coordinate detection line and the data signal line is increased, and the accuracy of coordinate detection of the coordinate detection target can be further increased.
  • the coordinate detection lines are divided into a plurality of groups in which at least two coordinate detection lines are configured as one group, It can also be set as the structure which detects the change of the said capacity
  • the data signal lines are divided into a plurality of groups in which at least two of the data signal lines are configured as one group, It can also be set as the structure which detects the change of the said capacity
  • Each of the plurality of pixels arranged in the row direction and the column direction includes an R sub-pixel corresponding to the R color, a G sub-pixel corresponding to the G color, and a B sub-pixel corresponding to the B color.
  • the R subpixel, the G subpixel, and the B subpixel may be arranged side by side in a direction in which the data signal line extends.
  • the number of coordinate detection lines can be increased, the amount of change in the capacitance formed by the coordinate detection lines and the data signal lines can be increased. Therefore, the detection signal can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection target can be further increased.
  • the first sub-pixel and the second sub-pixel are arranged in this order in the extending direction of the data signal line,
  • the pixel electrode of the first subpixel and the pixel electrode of the second subpixel are connected to the same scanning signal line through different transistors,
  • the pixel electrode of the first sub-pixel in one pixel and the pixel electrode of the second sub-pixel in the other pixel are the same reference It can also be set as the structure connected to wiring.
  • the above configuration can be applied to a display device having a multi-pixel configuration.
  • the potential level of the signal supplied to the first reference wiring to which the pixel electrode of the first sub-pixel is connected and the second reference wiring to which the pixel electrode of the second sub-pixel is connected are supplied.
  • the signal potential levels may be different from each other.
  • the change in the capacity may be detected at least once in the display data holding period in each frame.
  • the detection frequency is doubled (120 Hz), so the coordinate detection speed of the coordinate detection target object Can be further enhanced. Thereby, it becomes possible to cope with a quicker operation (such as pen input).
  • n is an integer of 2 or more
  • the sensing frequency can be set without depending on the display frame, the design flexibility of the display device can be increased.
  • the present invention can be mounted on any device having a liquid crystal display device as a display device having a touch panel function on a liquid crystal panel having a display function.

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Abstract

The purpose of the present invention is to improve the definition and decrease the frame width of a display panel in a display device that has input-position detection functionality. The display device in the present invention is provided with: a first substrate (21) on which pixel electrodes (15), which are electrically connected to reference wires (13) via transistors (17), are formed; a second substrate (22) on which data-signal lines (12), which also serve as opposing electrodes (16), and coordinate-detection lines (20) are formed; and a liquid-crystal layer sandwiched between said substrates (21 and 22). The pixel electrodes (15) overlap the data-signal lines (12) with the liquid-crystal layer interposed therebetween, and mutual capacitance occurs between the coordinate-detection lines (20) and the data-signal lines (12).

Description

表示装置Display device
　本発明は、タッチパネル機能を有する表示装置に関する。 The present invention relates to a display device having a touch panel function.
　近年、表示パネル自身が入力位置検出機能（タッチパネル機能）を有する表示装置が提案されている。この構成によれば、透明タブレットが表示パネルの前面に独立して設けられた従来の構成が抱える種々の問題を解消することができる。当該問題とは、透明タブレットの存在による表示パネルからの光の透過率低下や、入力位置と表示位置との視差の増大、コストの増加、モジュール厚およびモジュール面積の増大等である。 Recently, a display device in which the display panel itself has an input position detection function (touch panel function) has been proposed. According to this configuration, various problems associated with the conventional configuration in which the transparent tablet is provided independently on the front surface of the display panel can be solved. The problems include a decrease in light transmittance from the display panel due to the presence of the transparent tablet, an increase in parallax between the input position and the display position, an increase in cost, and an increase in module thickness and module area.
　上記のようなタッチパネル機能を有する表示装置の一例として、特許文献１の液晶ディスプレイが挙げられる。この液晶ディスプレイを構成する表示パネルの等価回路を図１８に示す。同図に示すように、表示パネルは、列方向（図中上下方向）に延伸するデータ信号線ＤＬおよび座標検知線ＳＬ、行方向（図中左右方向）に延伸する走査信号線ＧＬおよび保持容量配線ＣＳＬ並びに基準配線Ｃｏｍ、行および列方向に並べられた画素を備えている。データ信号線ＤＬ、走査信号線ＧＬ、および保持容量配線ＣＳＬはアクティブマトリクス基板に設けられ、座標検知線ＳＬおよび基準配線Ｃｏｍは対向基板に設けられている。 As an example of a display device having a touch panel function as described above, there is a liquid crystal display disclosed in Patent Document 1. An equivalent circuit of a display panel constituting this liquid crystal display is shown in FIG. As shown in the figure, the display panel includes a data signal line DL and a coordinate detection line SL extending in the column direction (vertical direction in the drawing), a scanning signal line GL extending in the row direction (horizontal direction in the drawing), and a storage capacitor. The wiring CSL and the reference wiring Com are provided with pixels arranged in the row and column directions. The data signal line DL, the scanning signal line GL, and the storage capacitor line CSL are provided on the active matrix substrate, and the coordinate detection line SL and the reference line Com are provided on the counter substrate.
　各画素の構造は同一の構成であり、１つの画素に対応してデータ信号線ＤＬと座標検知線ＳＬと走査信号線ＧＬと保持容量配線ＣＳＬと基準配線Ｃｏｍとが１本ずつ設けられている。また、各画素では、アクティブマトリクス基板において、画素電極が、走査信号線ＧＬに接続されたトランジスタを介してデータ信号線ＤＬに接続され、画素電極および保持容量配線ＣＳＬ間に保持容量Ｃｈが形成され、画素電極および基準配線Ｃｏｍ間に液晶容量Ｃｌｃが形成されている一方、対向基板において、座標検知線ＳＬおよび基準配線Ｃｏｍ間に相互容量Ｃｆが形成されている。また、基準配線Ｃｏｍは、転移部において保持容量配線ＣＳＬと電気的に接続されており、基準配線Ｃｏｍに供給される信号（Ｖｃｏｍ）は、保持容量配線ＣＳＬに供給される信号（保持容量配線信号）に同期している。 Each pixel has the same structure, and one data signal line DL, coordinate detection line SL, scanning signal line GL, storage capacitor line CSL, and reference line Com are provided for each pixel. . In each pixel, in the active matrix substrate, the pixel electrode is connected to the data signal line DL through a transistor connected to the scanning signal line GL, and a storage capacitor Ch is formed between the pixel electrode and the storage capacitor line CSL. A liquid crystal capacitor Clc is formed between the pixel electrode and the reference line Com, while a mutual capacitor Cf is formed between the coordinate detection line SL and the reference line Com on the counter substrate. The reference wiring Com is electrically connected to the storage capacitor wiring CSL at the transition portion, and a signal (Vcom) supplied to the reference wiring Com is a signal (storage capacitor wiring signal) supplied to the storage capacitor wiring CSL. ).
　上記液晶ディスプレイにおいて、表示パネル上の指やペンなどの座標検出対象物の入力位置を検出する場合、座標検出対象物が表示パネルに接近あるいは接触したときの、座標検知線ＳＬおよび基準配線Ｃｏｍ間の相互容量Ｃｆの変化を読み取ることにより、座標検出対象物の入力位置を検出することができる。 In the liquid crystal display, when detecting the input position of a coordinate detection target object such as a finger or a pen on the display panel, the coordinate detection line SL and the reference wiring line Com when the coordinate detection target object approaches or contacts the display panel By reading the change in the mutual capacitance Cf, the input position of the coordinate detection object can be detected.
日本国公開特許公報「特表２００９－５４０３７４号公報（２００９年１１月１９日公表）」Japanese Patent Publication “Special Table 2009-540374 (published on November 19, 2009)”
　しかしながら、上記特許文献１の液晶ディスプレイでは、基準配線Ｃｏｍを行ごとに独立して設けるとともに、基準配線Ｃｏｍおよび保持容量配線ＣＳＬを電気的に接続する必要があるため、表示パネルの狭額縁化および高精細化が困難である。 However, in the liquid crystal display of Patent Document 1, it is necessary to provide the reference wiring Com independently for each row and to electrically connect the reference wiring Com and the storage capacitor wiring CSL. High definition is difficult.
　本発明は、上記の問題点に鑑みなされたものであり、その目的は、入力位置検出機能を有する表示装置において、表示パネルの狭額縁化および高精細化を図ることにある。 The present invention has been made in view of the above problems, and an object of the present invention is to reduce the frame size and increase the definition of a display panel in a display device having an input position detection function.
　本発明の表示装置は、上記課題を解決するために、
　基準配線と、走査信号線と、制御端子が上記走査信号線に接続されたトランジスタと、画素電極とが形成された第１基板と、
　データ信号線が形成された第２基板と、
　上記第１および第２基板間に狭持された液晶層と、を含む表示パネルを備えた表示装置であって、
　上記画素電極は、上記トランジスタを介して上記基準配線に電気的に接続されるとともに、上記液晶層を介して上記データ信号線に重なっており、
　上記第２基板には、絶縁層を介して重なる座標検知線が形成され、
　上記座標検知線と上記データ信号線との間に容量が形成されていることを特徴とする。 In order to solve the above problems, the display device of the present invention provides
A first substrate on which a reference wiring, a scanning signal line, a transistor having a control terminal connected to the scanning signal line, and a pixel electrode;
A second substrate on which data signal lines are formed;
A display device comprising a display panel including a liquid crystal layer sandwiched between the first and second substrates,
The pixel electrode is electrically connected to the reference wiring through the transistor and overlaps the data signal line through the liquid crystal layer.
A coordinate detection line is formed on the second substrate via an insulating layer,
A capacitor is formed between the coordinate detection line and the data signal line.
　上記の構成によれば、座標検知線とデータ信号線との間で容量（例えば、相互容量）が形成されているため、表示パネルに指等の座標検出対象物が接近または接触したときの上記容量の変化を検出することにより、座標検出対象物の位置を特定することができる。また、データ信号線は、走査信号線が設けられる第１基板とは異なる第２基板に設けられるとともに、座標検出用の信号線としての機能を兼ね備えており、第２基板に設けられる座標検知線との間で上記容量が形成されている。そのため、従来のように、座標検出用の信号線を第１基板側の信号線に接続する必要がないため、表示パネルの狭額縁化および高精細化を図ることができる。 According to the above configuration, since a capacitance (for example, mutual capacitance) is formed between the coordinate detection line and the data signal line, the above described when the coordinate detection target object such as a finger approaches or contacts the display panel. By detecting the change in the capacity, the position of the coordinate detection target can be specified. In addition, the data signal line is provided on a second substrate different from the first substrate on which the scanning signal line is provided, and also has a function as a signal line for coordinate detection, and the coordinate detection line provided on the second substrate. The capacitance is formed between the two. Therefore, unlike the prior art, it is not necessary to connect the signal line for coordinate detection to the signal line on the first substrate side, so that the display panel can be made narrower and higher in definition.
　本発明に係る表示装置は、以上のように、上記画素電極は、上記トランジスタを介して上記基準配線に電気的に接続されるとともに、上記液晶層を介して上記データ信号線に重なっており、上記第２基板には、絶縁層を介して上記データ信号線に重なる座標検知線が形成され、上記座標検知線と上記データ信号線との間に容量が形成されていることを特徴としている。 In the display device according to the present invention, as described above, the pixel electrode is electrically connected to the reference wiring through the transistor and overlaps the data signal line through the liquid crystal layer. The second substrate is characterized in that a coordinate detection line that overlaps the data signal line is formed through an insulating layer, and a capacitor is formed between the coordinate detection line and the data signal line.
　これにより、入力位置検出機能を有する表示装置において、表示パネルの狭額縁化および高精細化を図ることができる。 As a result, in a display device having an input position detection function, the display panel can be made narrower and higher in definition.
本発明の実施の形態１に係る表示装置の構成を示したブロック図である。It is the block diagram which showed the structure of the display apparatus which concerns on Embodiment 1 of this invention. 図１に示した表示装置における表示パネルの等価回路図である。FIG. 2 is an equivalent circuit diagram of a display panel in the display device shown in FIG. 1. 図１に示した表示装置における表示パネルの動作を説明するための等価回路図である。FIG. 3 is an equivalent circuit diagram for explaining the operation of the display panel in the display device shown in FIG. 1. 図１に示した表示装置における表示パネルの構成を示した斜視図である。FIG. 2 is a perspective view illustrating a configuration of a display panel in the display device illustrated in FIG. 1. 図１に示した表示装置における表示パネルの構成を示した断面図である。FIG. 2 is a cross-sectional view illustrating a configuration of a display panel in the display device illustrated in FIG. 1. 図１に示した表示装置における表示パネルの構成を示した平面図である。FIG. 2 is a plan view illustrating a configuration of a display panel in the display device illustrated in FIG. 1. １フレーム期間における位置検出動作の様子を模式的に示す図であり、（ａ）は１フレームの表示データ保持期間に位置検出動作を１回行う場合を示し、（ｂ）は１フレームの表示データ保持期間に位置検出動作を２回行う場合を示している。It is a figure which shows typically the mode of the position detection operation | movement in 1 frame period, (a) shows the case where a position detection operation is performed once in the display data holding period of 1 frame, (b) is display data of 1 frame. The case where the position detection operation is performed twice during the holding period is shown. （ａ）～（ｃ）は、図１に示した表示装置における表示パネルで実現される位置検出の原理を説明した図である。(A)-(c) is a figure explaining the principle of position detection implement | achieved by the display panel in the display apparatus shown in FIG. 実施の形態１に係る表示装置の他の形態（変形例１）の表示パネルの構成を示した平面図である。FIG. 10 is a plan view showing a configuration of a display panel of another mode (Modification 1) of the display device according to Embodiment 1. 実施の形態１に係る表示装置の他の形態（変形例２）の表示パネルの構成を示した平面図である。FIG. 11 is a plan view showing a configuration of a display panel of another form (Modification 2) of the display device according to Embodiment 1. 実施の形態１に係る表示装置の他の形態（変形例３）の表示パネルの構成を示した平面図である。FIG. 10 is a plan view showing a configuration of a display panel of another mode (Modification 3) of the display device according to Embodiment 1. 本発明の実施の形態２に係る表示装置の構成を示した平面図である。It is the top view which showed the structure of the display apparatus which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る表示装置における表示パネルの等価回路図である。It is an equivalent circuit schematic of the display panel in the display device according to Embodiment 3 of the present invention. 本発明の実施の形態４に係る表示装置における表示パネルの等価回路図である。FIG. 10 is an equivalent circuit diagram of a display panel in a display device according to Embodiment 4 of the present invention. 図１４に示した表示装置における表示パネルの構成を示した断面図である。It is sectional drawing which showed the structure of the display panel in the display apparatus shown in FIG. 図１４に示した表示パネルの動作を示すタイミングチャートである。15 is a timing chart showing an operation of the display panel shown in FIG. 本発明の実施の形態５に係る表示装置の構成を示したブロック図である。It is the block diagram which showed the structure of the display apparatus which concerns on Embodiment 5 of this invention. 従来の液晶ディスプレイの構成を示す等価回路図である。It is an equivalent circuit diagram which shows the structure of the conventional liquid crystal display.
　〔実施の形態１〕
　本発明に係る入力位置検出機能（タッチパネル機能）を有する表示装置（以下、表示装置という）の一実施の形態について以下に説明する。 [Embodiment 1]
An embodiment of a display device (hereinafter referred to as a display device) having an input position detection function (touch panel function) according to the present invention will be described below.
　本発明に係る表示装置は、表示機能を有する表示パネルにタッチパネル機能を兼ね備えた表示装置として、液晶表示装置を具備するあらゆる機器に搭載することができる。一例として、携帯型端末に適用することができる。 The display device according to the present invention can be mounted on any device having a liquid crystal display device as a display device having a touch panel function on a display panel having a display function. As an example, it can be applied to a portable terminal.
　（表示装置の構成）
　図１は、本実施の形態１に係る表示装置のブロック図である。 (Configuration of display device)
FIG. 1 is a block diagram of the display device according to the first embodiment.
　図１に示す表示装置は、画像表示機能と相互容量方式のタッチパネル機能とを兼ね備えた表示パネル１と、表示パネル１を駆動する走査信号線駆動回路２およびデータ信号線駆動回路３と、走査信号線駆動回路２およびデータ信号線駆動回路３に表示制御信号を供給する表示制御回路４と、タイミングコントローラ６、座標検知線読み出し回路７と、座標検出回路８と、基準配線駆動回路９と、電源回路１０とを備えている。 The display device shown in FIG. 1 includes a display panel 1 having both an image display function and a mutual capacitive touch panel function, a scanning signal line driving circuit 2 and a data signal line driving circuit 3 for driving the display panel 1, and a scanning signal. A display control circuit 4 for supplying display control signals to the line drive circuit 2 and the data signal line drive circuit 3, a timing controller 6, a coordinate detection line readout circuit 7, a coordinate detection circuit 8, a reference wiring drive circuit 9, and a power source Circuit 10.
　表示パネル１は、対向する２つの基板（アクティブマトリクス基板、対向基板）の間に液晶層を挟持させたアクティブマトリクス型の液晶表示パネルである。図２に、表示パネル１の等価回路を示す。 The display panel 1 is an active matrix type liquid crystal display panel in which a liquid crystal layer is sandwiched between two opposing substrates (active matrix substrate, counter substrate). FIG. 2 shows an equivalent circuit of the display panel 1.
　表示パネル１は、図２に示すように、列方向（図中上下方向）に延伸するデータ信号線１２、行方向（図中左右方向）に延伸する走査信号線１４と基準配線１３と座標検知線２０、行および列方向に並べられた画素を備えている。走査信号線１４および基準配線１３はアクティブマトリクス基板（第１基板）に設けられ、データ信号線１２および座標検知線２０は対向基板（第２基板）に設けられている。 As shown in FIG. 2, the display panel 1 includes a data signal line 12 extending in the column direction (vertical direction in the drawing), a scanning signal line 14 extending in the row direction (horizontal direction in the drawing), a reference wiring 13, and coordinate detection. It comprises pixels arranged in line 20, row and column directions. The scanning signal line 14 and the reference wiring 13 are provided on the active matrix substrate (first substrate), and the data signal line 12 and the coordinate detection line 20 are provided on the counter substrate (second substrate).
　各画素の構造は同一の構成であり、１つの画素に対応してデータ信号線１２と座標検知線２０と走査信号線１４と基準配線１３とが１本ずつ設けられている。各画素では、アクティブマトリクス基板において、画素電極１５が、走査信号線１４に接続されたトランジスタ（ＴＦＴ）１７を介して基準配線１３に接続されており、対向基板において、データ信号線１２が対向電極１６に接続されている。画素電極１５と対向電極１６との間には液晶容量Ｃｌｃが形成されており、座標検知線２０とデータ信号線１２との間には相互容量Ｃｆが形成されている。 The structure of each pixel is the same, and one data signal line 12, one coordinate detection line 20, one scanning signal line 14, and one reference wiring 13 are provided corresponding to one pixel. In each pixel, in the active matrix substrate, the pixel electrode 15 is connected to the reference wiring 13 via a transistor (TFT) 17 connected to the scanning signal line 14, and in the counter substrate, the data signal line 12 is connected to the counter electrode. 16 is connected. A liquid crystal capacitor Clc is formed between the pixel electrode 15 and the counter electrode 16, and a mutual capacitor Cf is formed between the coordinate detection line 20 and the data signal line 12.
　各画素に設けられたトランジスタ１７は、ソース電極が画素電極１５に接続され、ドレイン電極が基準配線１３に接続され、ゲート電極が走査信号線１４に接続されている。これにより、トランジスタ１７は、走査信号線１４から供給される走査信号（ゲート信号）によってオン／オフ制御され、オン時に、基準配線１３とデータ信号線１２との間に印加されるデータ信号に応じた電圧が液晶層に印加され、トランジスタ１７がオフ時に、該電圧が保持される構成となっている。この構成を、図３にｎライン選択時とｎ＋１ライン選択時とに分けて示している。なお、図３では、説明の便宜上、座標検知線２０（図２）は省略している。また、図３では、ｎライン選択時において走査信号線１４（ｎ）がオン、走査信号線１４（ｎ＋１）がオフであり、ｎ＋１ライン選択時において走査信号線１４（ｎ）がオフで、走査信号線１４（ｎ＋１）がオンである。ｎライン選択時では、トランジスタ１７がオン状態になってデータ信号に応じた電圧が液晶層に印加され、ｎ＋１ライン選択時では、トランジスタ１７がオフ状態になってデータ信号に応じた電圧が液晶容量Ｃｌｃに保持されることがわかる。 The transistor 17 provided in each pixel has a source electrode connected to the pixel electrode 15, a drain electrode connected to the reference wiring 13, and a gate electrode connected to the scanning signal line 14. Thereby, the transistor 17 is controlled to be turned on / off by the scanning signal (gate signal) supplied from the scanning signal line 14, and in response to the data signal applied between the reference wiring 13 and the data signal line 12 when turned on. The voltage is applied to the liquid crystal layer, and the voltage is held when the transistor 17 is turned off. This configuration is shown separately in FIG. 3 when n lines are selected and when n + 1 lines are selected. In FIG. 3, the coordinate detection line 20 (FIG. 2) is omitted for convenience of explanation. In FIG. 3, the scanning signal line 14 (n) is on and the scanning signal line 14 (n + 1) is off when the n line is selected, and the scanning signal line 14 (n) is off when the n + 1 line is selected. The signal line 14 (n + 1) is on. When the n line is selected, the transistor 17 is turned on and a voltage corresponding to the data signal is applied to the liquid crystal layer. When the n + 1 line is selected, the transistor 17 is turned off and the voltage corresponding to the data signal is applied to the liquid crystal capacitor. It can be seen that Clc is retained.
　ここで、具体的な画素構成について説明する。図４は、表示パネル１における行方向に並べられた３画素分の模式斜視図であり、図５は、表示パネル１における列方向に並べられた４画素分の模式断面図であり、図６は、表示パネル１の上面図である。なお、図６では、説明の便宜上、データ信号線１２、画素電極１５、走査信号線１４、基準配線１３、座標検知線２０を、対向基板２２を透過して見えるように描いている。 Here, a specific pixel configuration will be described. 4 is a schematic perspective view of three pixels arranged in the row direction in the display panel 1, and FIG. 5 is a schematic cross-sectional view of four pixels arranged in the column direction in the display panel 1. FIG. 3 is a top view of the display panel 1. In FIG. 6, for convenience of explanation, the data signal line 12, the pixel electrode 15, the scanning signal line 14, the reference wiring 13, and the coordinate detection line 20 are drawn so as to be seen through the counter substrate 22.
　表示パネル１は、図４に示すように、ガラス等でなる絶縁性を有するアクティブマトリクス基板２１と、このアクティブマトリクス基板２１に対して所定の間隔で対向するガラス等でなる光透過性を有する対向基板２２と、アクティブマトリクス基板２１と対向基板２２との間に挟持された液晶層（図示せず）とで構成される。液晶層としては、種々のタイプの液晶層を用いることができる。 As shown in FIG. 4, the display panel 1 includes an active matrix substrate 21 made of glass or the like and an optical matrix made of glass or the like facing the active matrix substrate 21 at a predetermined interval. The substrate 22 is composed of a liquid crystal layer (not shown) sandwiched between the active matrix substrate 21 and the counter substrate 22. As the liquid crystal layer, various types of liquid crystal layers can be used.
　アクティブマトリクス基板２１には、対向基板２２に対向する側の面に、トランジスタ１７と、一部がトランジスタ１７のゲート電極２３となる走査信号線１４と、トランジスタ１７のドレイン電極２４に電気的に接続された基準配線１３と、トランジスタ１７のソース電極２５に電気的に接続された画素電極１５とが形成されている。 The active matrix substrate 21 is electrically connected to the transistor 17, the scanning signal line 14 that partially becomes the gate electrode 23 of the transistor 17, and the drain electrode 24 of the transistor 17 on the surface facing the counter substrate 22. The reference wiring 13 and the pixel electrode 15 electrically connected to the source electrode 25 of the transistor 17 are formed.
　基準配線１３および走査信号線１４は、タンタル層等の同じ金属層で形成されているが、異なる金属層によって形成されていてもよい。また、トランジスタ１７のゲート電極２３および走査信号線１４を覆うように、典型的にはアクティブマトリクス基板２１の略全面に、窒化シリコン膜等のゲート絶縁膜（図示せず）が形成されている。そして、このゲート絶縁膜上に、トランジスタ１７を構成する活性半導体層（図示せず）、ドレイン電極２４、ソース電極２５および画素電極１５が形成されている。画素電極１５は、例えばＩＴＯ等の透明導電膜で形成されている。 The reference wiring 13 and the scanning signal line 14 are formed of the same metal layer such as a tantalum layer, but may be formed of different metal layers. A gate insulating film (not shown) such as a silicon nitride film is typically formed on substantially the entire surface of the active matrix substrate 21 so as to cover the gate electrode 23 and the scanning signal line 14 of the transistor 17. On the gate insulating film, an active semiconductor layer (not shown) constituting the transistor 17, a drain electrode 24, a source electrode 25, and a pixel electrode 15 are formed. The pixel electrode 15 is formed of a transparent conductive film such as ITO.
　一方、対向基板２２には、列方向に配列された全画素に共通のストライプ状の対向電極１６と、行方向に配列されたストライプ状の座標検知線２０とが形成されている。対向電極１６と座標検知線２０との間には絶縁層１８が形成されている（図５）。対向電極１６はＩＴＯ層等によって透明に形成されており、その一端は、表示パネル１における表示領域外に設けられた転移部において、アクティブマトリクス基板２１に形成されているデータ信号線入力部に異方性導電膜等によって電気的に接続されている。なお、対向電極１６は、対向基板２２側に設けられたＦＰＣを介してデータ信号線入力部に接続されている構成であってもよい。このように、対向電極１６は、データ信号線１２としても機能する。以下、対向電極１６をデータ信号線１２という。 On the other hand, on the counter substrate 22, a stripe-shaped counter electrode 16 common to all the pixels arranged in the column direction and a stripe-shaped coordinate detection line 20 arranged in the row direction are formed. An insulating layer 18 is formed between the counter electrode 16 and the coordinate detection line 20 (FIG. 5). The counter electrode 16 is formed transparently by an ITO layer or the like, and one end of the counter electrode 16 is different from the data signal line input portion formed on the active matrix substrate 21 in the transition portion provided outside the display area in the display panel 1. They are electrically connected by a isotropic conductive film or the like. The counter electrode 16 may be configured to be connected to the data signal line input unit via an FPC provided on the counter substrate 22 side. As described above, the counter electrode 16 also functions as the data signal line 12. Hereinafter, the counter electrode 16 is referred to as a data signal line 12.
　座標検知線２０は、対向電極１６と同じＩＴＯ層で形成することができるが、異なる金属層によって形成されていてもよい。座標検知線２０は、図１に示すように、一端が座標検知線読み出し回路７に接続されており、データ信号線１２は、一端がデータ信号線駆動回路３に接続されている。 The coordinate detection line 20 can be formed of the same ITO layer as the counter electrode 16, but may be formed of a different metal layer. As shown in FIG. 1, one end of the coordinate detection line 20 is connected to the coordinate detection line readout circuit 7, and one end of the data signal line 12 is connected to the data signal line drive circuit 3.
　また、座標検知線２０は、図５および図６に示すように、表示パネル１を平面的に（観察者側から）見て、走査信号線１４および／または基準配線１３に重なるように形成されているため、座標検知線２０を設けることによる透過率の低下を防ぐことができる。 Further, as shown in FIGS. 5 and 6, the coordinate detection line 20 is formed so as to overlap the scanning signal line 14 and / or the reference wiring 13 when the display panel 1 is viewed in plan (from the observer side). Therefore, it is possible to prevent a decrease in transmittance due to the provision of the coordinate detection line 20.
　以上のように、対向電極１６（データ信号線１２）と座標検知線２０とは、互いが交差する部分において絶縁層１８を介して重なっており、この交差部に相互容量Ｃｆが形成される構成となっている。なお、対向電極１６（データ信号線１２）及び座標検知線２０は、同層に形成され、上記交差部のみが絶縁層１８を介して重なる構成とすることもできる。 As described above, the counter electrode 16 (data signal line 12) and the coordinate detection line 20 overlap with each other through the insulating layer 18 at a portion where they intersect each other, and a mutual capacitance Cf is formed at this intersection. It has become. Note that the counter electrode 16 (data signal line 12) and the coordinate detection line 20 may be formed in the same layer, and only the intersection may overlap with the insulating layer 18 interposed therebetween.
　タイミングコントローラ６は、各種同期信号等のタイミング制御信号を生成し、データ信号線駆動回路３、表示制御回路４、座標検知線読み出し回路７、および、座標検出回路８に供給する。 The timing controller 6 generates timing control signals such as various synchronization signals and supplies them to the data signal line drive circuit 3, the display control circuit 4, the coordinate detection line readout circuit 7, and the coordinate detection circuit 8.
　表示制御回路４は、タイミングコントローラ６から供給されたタイミング制御信号に基づいて画像表示タイミングを検知して、外部から入力された表示データおよび同期信号に基づいて、表示パネル１に画像を表示するための表示制御信号を生成する。そして、生成した表示制御信号を走査信号線駆動回路２およびデータ信号線駆動回路３に供給して走査信号線駆動回路２およびデータ信号線駆動回路３の動作を制御する。 The display control circuit 4 detects image display timing based on a timing control signal supplied from the timing controller 6 and displays an image on the display panel 1 based on display data and a synchronization signal input from the outside. The display control signal is generated. Then, the generated display control signal is supplied to the scanning signal line driving circuit 2 and the data signal line driving circuit 3 to control the operations of the scanning signal line driving circuit 2 and the data signal line driving circuit 3.
　また、表示制御回路４は、タイミングコントローラ６から供給されるタイミング制御信号に基づいて、座標検知用パルス信号を生成し、生成した座標検知用パルス信号をデータ信号線駆動回路３に供給する。 Further, the display control circuit 4 generates a coordinate detection pulse signal based on the timing control signal supplied from the timing controller 6, and supplies the generated coordinate detection pulse signal to the data signal line drive circuit 3.
　走査信号線駆動回路２は、表示制御回路４から出力される表示制御信号に基づいて、走査信号（ゲート信号）を、図２に示す表示パネル１の各走査信号線１４に順次供給する。これにより、走査信号が供給された走査信号線１４の一部をゲート電極とするトランジスタ１７がオン状態になる。 The scanning signal line drive circuit 2 sequentially supplies a scanning signal (gate signal) to each scanning signal line 14 of the display panel 1 shown in FIG. 2 based on the display control signal output from the display control circuit 4. As a result, the transistor 17 whose gate electrode is a part of the scanning signal line 14 supplied with the scanning signal is turned on.
　データ信号線駆動回路３は、表示制御信号に基づいて、データ信号をデータ信号線入力部を介してデータ信号線１２に供給する。これにより、オン状態になっているトランジスタ１７を介して液晶層にデータ信号に応じた電圧が印加されて画像情報が書き込まれる。 The data signal line driving circuit 3 supplies a data signal to the data signal line 12 via the data signal line input unit based on the display control signal. As a result, a voltage corresponding to the data signal is applied to the liquid crystal layer through the transistor 17 in the on state, and image information is written.
　また、データ信号線駆動回路３は、表示制御回路４から供給される座標検知用パルス信号を、タイミングコントローラ６から供給されるタイミング制御信号に基づいて、データ信号線１２に順次供給する。 Further, the data signal line driving circuit 3 sequentially supplies the coordinate detection pulse signal supplied from the display control circuit 4 to the data signal line 12 based on the timing control signal supplied from the timing controller 6.
　座標検知線読み出し回路７は、タイミングコントローラ６から供給されたタイミング制御信号に基づいて、座標検知線２０の電荷（電流）の変動（変化量）を検出する。 The coordinate detection line readout circuit 7 detects the fluctuation (change amount) of the charge (current) of the coordinate detection line 20 based on the timing control signal supplied from the timing controller 6.
　座標検出回路８は、タイミングコントローラ６から供給されたタイミング制御信号に基づいて座標検出タイミングを検知して、座標検知線読み出し回路７が取得した電荷の変化量に基づいて座標検出対象物の座標を検出する。 The coordinate detection circuit 8 detects the coordinate detection timing based on the timing control signal supplied from the timing controller 6, and calculates the coordinates of the coordinate detection target object based on the amount of change in the charge acquired by the coordinate detection line readout circuit 7. To detect.
　なお、走査信号線駆動回路２が生成する走査信号、データ信号線駆動回路３が生成するデータ信号は、電源回路１０からのバイアス電圧に基づいて生成される。 The scanning signal generated by the scanning signal line driving circuit 2 and the data signal generated by the data signal line driving circuit 3 are generated based on the bias voltage from the power supply circuit 10.
　基準配線駆動回路９は、電源回路１０から供給されたバイアス電圧によって生成される所定レベルの基準電圧（例えば、Ｖｃｏｍ）を、基準配線１３に供給する。 The reference wiring drive circuit 9 supplies a reference voltage (for example, Vcom) of a predetermined level generated by the bias voltage supplied from the power supply circuit 10 to the reference wiring 13.
　以上のように、本表示装置は、走査信号線駆動回路２、データ信号線駆動回路３、表示制御回路４、および、基準配線駆動回路９によって表示制御手段が構成され、データ信号線駆動回路３、座標検知線読み出し回路７、および、座標検出回路８によって位置検出手段が構成される。データ信号線１２は、画像表示用の信号線としての機能と、座標検出用の信号線としての機能とを兼ね備えている。 As described above, in this display device, the scanning signal line driving circuit 2, the data signal line driving circuit 3, the display control circuit 4, and the reference wiring driving circuit 9 constitute display control means, and the data signal line driving circuit 3 The coordinate detection line readout circuit 7 and the coordinate detection circuit 8 constitute position detection means. The data signal line 12 has both a function as a signal line for image display and a function as a signal line for coordinate detection.
　（表示装置の動作）
　次に、上記構成の表示装置の動作について説明する。 (Operation of display device)
Next, the operation of the display device having the above configuration will be described.
　図７に示すように、１フレーム期間を、表示パネル１に画像を表示する表示データ書き込み期間と、垂直帰線期間等の表示データ保持期間とに時分割する。 As shown in FIG. 7, one frame period is time-divided into a display data writing period for displaying an image on the display panel 1 and a display data holding period such as a vertical blanking period.
　＜表示データ書き込み期間（表示動作）＞
　表示データ書き込み期間については、通常のアクティブマトリクス型の液晶表示装置における動作と基本的には同じであるため簡単に説明する。すなわち、表示制御回路４から供給された表示制御信号に基づいて、走査信号線駆動回路２によって走査信号線１４を行ごとに順次選択し、データ信号線駆動回路３から全データ信号線１２に対して表示データに応じた信号電位を供給する。そして、トランジスタ１７をオフすると、データ信号線１２（対向電極１６）と基準配線１３との電位差（電圧）が当該トランジスタ１７に接続された液晶容量Ｃｌｃに保持されて画像が表示される。 <Display data writing period (display operation)>
Since the display data writing period is basically the same as the operation in a normal active matrix type liquid crystal display device, it will be briefly described. That is, based on the display control signal supplied from the display control circuit 4, the scanning signal line driving circuit 2 sequentially selects the scanning signal lines 14 for each row, and the data signal line driving circuit 3 selects all the data signal lines 12. The signal potential corresponding to the display data is supplied. When the transistor 17 is turned off, the potential difference (voltage) between the data signal line 12 (counter electrode 16) and the reference wiring 13 is held in the liquid crystal capacitor Clc connected to the transistor 17, and an image is displayed.
　＜表示データ保持期間（位置検出動作）＞
　表示データ保持期間については、図７に示すように、一部を位置検出期間に割り当てる。なお、表示データ保持期間は、トランジスタ１７はオフ状態になる。 <Display data retention period (position detection operation)>
As shown in FIG. 7, a part of the display data holding period is assigned to the position detection period. Note that the transistor 17 is off in the display data holding period.
　本発明における位置検出は、いわゆる相互容量方式を用いる。当該方式の原理は、駆動電極と受信電極とを用いて駆動電極にパルス電圧を与えて、駆動電極と受信電極との間で相互容量を形成しておき、座標検出対象物（誘電体）が接近あるいは接触したときにこの相互容量が変化することを利用して位置を検出するものである。 The position detection in the present invention uses a so-called mutual capacitance method. The principle of this method is that a pulse voltage is applied to the drive electrode using the drive electrode and the receive electrode, and a mutual capacitance is formed between the drive electrode and the receive electrode. The position is detected by utilizing this change in mutual capacitance when approaching or touching.
　本実施の形態では、座標検知線２０を上記受信電極として用い、データ信号線１２を上記駆動電極として用いる構成について説明する。 In the present embodiment, a configuration in which the coordinate detection line 20 is used as the reception electrode and the data signal line 12 is used as the drive electrode will be described.
　座標検出（以下、位置検出と記載することもある）は、タイミングコントローラ６から供給されるタイミング制御信号に同期させて、複数のデータ信号線１２に行方向に沿って、順次、パルス電圧（座標検知用パルス信号）を印加するとともに、座標検知線２０との間に形成される相互容量Ｃｆの変化に応じた座標検知線２０の電荷の変化量を検出することにより行う。以下、図８に示す具体例を挙げて説明する。図８の（ａ）～（ｃ）は、図１に示した表示装置における表示パネル１で実現される位置検出の原理を説明した図である。 Coordinate detection (hereinafter also referred to as position detection) is performed in synchronization with a timing control signal supplied from the timing controller 6 in order along the row direction along a plurality of data signal lines 12 with pulse voltages (coordinates). Detection pulse signal) is applied, and the amount of change in the charge on the coordinate detection line 20 corresponding to the change in the mutual capacitance Cf formed between the coordinate detection line 20 and the coordinate detection line 20 is detected. Hereinafter, a specific example shown in FIG. 8 will be described. FIGS. 8A to 8C are diagrams illustrating the principle of position detection realized by the display panel 1 in the display device shown in FIG.
　列方向に座標検知線（Ａ）、座標検知線（Ｂ）、座標検知線（Ｃ）がこの順で並んでいて、且つ、これら３本の座標検知線に直交する方向に延びたデータ信号線（i）、データ信号線（ii）、データ信号線（iii）が行方向にこの順で並んでいる表示パネル構成を仮定する（図８中の（ｂ））。そして、図８に示す当該構成において、座標検知線（Ａ）とデータ信号線（i）、および、座標検知線（Ｃ）とデータ信号線（iii）の２点をタッチしている場合のマルチタッチについて説明する。 A data signal line in which the coordinate detection line (A), the coordinate detection line (B), and the coordinate detection line (C) are arranged in this order in the column direction, and extend in a direction orthogonal to the three coordinate detection lines. (I) Assume a display panel configuration in which data signal lines (ii) and data signal lines (iii) are arranged in this order in the row direction ((b) in FIG. 8). In the configuration shown in FIG. 8, the multipoint in the case where two points of the coordinate detection line (A) and the data signal line (i) and the coordinate detection line (C) and the data signal line (iii) are touched. The touch will be described.
　上記構成において、図８中の（ｃ）のタイミングチャートに示すように、データ信号線（i）、データ信号線（ii）、データ信号線（iii）の順でパルス信号（座標検知用パルス信号）が入力されると、データ信号線（i）にパルス信号が入力される期間（ｔ１～ｔ２）では、タッチすることにより、相互容量Ｃｆの変化に応じて座標検知線（Ａ）に流れる電荷が変化し、この電荷の変化量が、電圧値に変換される（図８中の（ａ）の検出パルスI）。これにより、座標検知線（Ａ）とデータ信号線（ｉ）の交点の座標を特定することができる。 In the above configuration, as shown in the timing chart of (c) in FIG. 8, the pulse signal (coordinate detection pulse signal) in the order of the data signal line (i), the data signal line (ii), and the data signal line (iii). ) Is input, during the period (t1 to t2) in which the pulse signal is input to the data signal line (i), the charge that flows through the coordinate detection line (A) according to the change in the mutual capacitance Cf by touching. Changes, and the amount of change in the charge is converted into a voltage value (detection pulse I in (a) in FIG. 8). Thereby, the coordinates of the intersection of the coordinate detection line (A) and the data signal line (i) can be specified.
　続いて、データ信号線（ii）にパルス信号（座標検知用パルス信号）が入力される期間（ｔ２～ｔ３）では、相互容量Ｃｆに変化が生じないため、座標検知線（Ａ）、座標検知線（Ｂ）、座標検知線（Ｃ）のそれぞれの電荷は変化しない。 Subsequently, in the period (t2 to t3) in which the pulse signal (coordinate detection pulse signal) is input to the data signal line (ii), the mutual capacitance Cf does not change, so the coordinate detection line (A), the coordinate detection The charges on the line (B) and the coordinate detection line (C) do not change.
　最後に、データ信号線（iii）にパルス信号（座標検知用パルス信号）が入力される期間（ｔ３～ｔ４）では、タッチすることにより、相互容量Ｃｆの変化に応じて座標検知線（Ｃ）に流れる電荷が変化し、この電荷の変化量が、電圧値に変換される（図８中の（ａ）の検出パルスII）。これにより、座標検知線（Ｃ）とデータ信号線（iii）の交点の座標を特定することができる。 Finally, during a period (t3 to t4) in which a pulse signal (coordinate detection pulse signal) is input to the data signal line (iii), the coordinate detection line (C) is touched according to the change in the mutual capacitance Cf. The amount of change in the charge is converted into a voltage value (detection pulse II in (a) in FIG. 8). Thereby, the coordinates of the intersection of the coordinate detection line (C) and the data signal line (iii) can be specified.
　以上のように、タッチすることにより、座標検知線に流れる電荷が変化し、その電荷の変化量を読み取ることによって、座標検出対象物の座標（位置）を特定することができる。 As described above, the electric charge flowing in the coordinate detection line is changed by touching, and the coordinate (position) of the coordinate detection object can be specified by reading the change amount of the electric charge.
　本実施の形態の構成によれば、表示パネル１の対向基板２２に行方向に配された座標検知線２０と、対向基板２２に列方向に配されたデータ信号線１２とを用いて、座標検出対象物の座標位置を検出することができる。すなわち、データ信号線１２を位置検出用の駆動電極として兼用することができるため、表示パネル１の狭額縁化および高精細化を図ることができる。 According to the configuration of the present embodiment, the coordinate detection line 20 arranged in the row direction on the counter substrate 22 of the display panel 1 and the data signal line 12 arranged in the column direction on the counter substrate 22 are used to coordinate. The coordinate position of the detection object can be detected. That is, since the data signal line 12 can also be used as a position detection drive electrode, the display panel 1 can be made narrower and higher in definition.
　なお、本実施の形態では、対向基板２２が最表面になっていて対向基板２２に指などの座標検出対象物が接近あるいは接触する構成について説明したが、本発明はこれに限定されるものではなく、上述した検出動作を妨げないものであれば、対向基板２２よりも表面側に別の部材が配設されていてもよい。別の部材としては、例えば、偏光層および／またはカバー層が挙げられる。 In the present embodiment, the configuration has been described in which the counter substrate 22 is the outermost surface and a coordinate detection target object such as a finger approaches or contacts the counter substrate 22, but the present invention is not limited to this. Alternatively, another member may be disposed on the surface side of the counter substrate 22 as long as the detection operation described above is not hindered. As another member, a polarizing layer and / or a cover layer are mentioned, for example.
　ここで、位置検出動作（センシング）は、図７の（ａ）では、１フレーム（６０Ｈｚ）において、表示データ保持期間に１回行われているが、本発明はこれに限定されるものではなく、図７の（ｂ）に示すように、１フレーム（６０Ｈｚ）において、表示データ保持期間に２回行われてもよい。これにより、センシング周波数は１２０Ｈｚとなり、座標検出対象物の座標検出の速度をさらに高めることができ、より素早い操作（ペン入力など）に対応することが可能になる。なお、表示データ保持期間にセンシングを３回以上行う構成としても良い。 Here, the position detection operation (sensing) is performed once in the display data holding period in one frame (60 Hz) in FIG. 7A, but the present invention is not limited to this. As shown in (b) of FIG. 7, one frame (60 Hz) may be performed twice in the display data holding period. As a result, the sensing frequency becomes 120 Hz, the coordinate detection speed of the coordinate detection object can be further increased, and it is possible to cope with faster operations (such as pen input). Note that the sensing may be performed three or more times during the display data holding period.
　また、検出速度を落としても良い場合には、複数フレーム（ｎ（ｎは２以上の整数）フレーム）ごとに、１回あるいは複数回センシングを行う構成としても良い。この構成では、表示フレームに依存せずにセンシング周波数を設定することができるため、表示装置の設計自由度を高めることができる。 If the detection speed may be lowered, sensing may be performed once or a plurality of times for each of a plurality of frames (n (n is an integer of 2 or more) frames). In this configuration, since the sensing frequency can be set without depending on the display frame, the degree of freedom in designing the display device can be increased.
　また、上記の説明では、位置検出動作において、座標検知用パルス信号を、データ信号線１２ごとに順次供給する構成としているが、これに限定されるものではなく、複数本のデータ信号線１２ごとに順次供給する構成としても良い。後述する各形態においても同様である。 In the above description, the coordinate detection pulse signal is sequentially supplied for each data signal line 12 in the position detection operation. However, the present invention is not limited to this, and each of the plurality of data signal lines 12 is not limited thereto. It is good also as a structure supplied sequentially. The same applies to each form to be described later.
　（変形例１）
　上述した実施の形態では、位置検出動作を実現するにあたって、データ信号線１２を駆動電極として用い、座標検知線２０を受信電極として用いる構成について説明したが、本発明はこれに限定されるものではなく、座標検知線２０を駆動電極として用い、データ信号線１２を受信電極として用いてもよい。この場合は、図９に示すように、データ信号線１２の一端をデータ信号線駆動回路３に接続するとともに、他端を座標検知線読み出し回路７に接続する構成とすればよい。そして、表示動作時には、各データ信号線１２に表示データを供給することにより表示を行い、位置検出動作時には、表示制御回路４が、タイミングコントローラ６から供給されるタイミング制御信号に基づいて、座標検知用パルス信号を座標検知線２０に順次供給するとともに、座標検知線読み出し回路７がデータ信号線１２の電荷の変化量を読み取り、座標検出回路８がこの変化量を電圧値に変換することにより、座標検出対象物の位置を特定することができる。 (Modification 1)
In the above-described embodiment, the configuration in which the data signal line 12 is used as the drive electrode and the coordinate detection line 20 is used as the reception electrode in realizing the position detection operation has been described, but the present invention is not limited to this. Alternatively, the coordinate detection line 20 may be used as a drive electrode, and the data signal line 12 may be used as a reception electrode. In this case, as shown in FIG. 9, one end of the data signal line 12 may be connected to the data signal line driving circuit 3 and the other end may be connected to the coordinate detection line readout circuit 7. In the display operation, display is performed by supplying display data to each data signal line 12, and in the position detection operation, the display control circuit 4 detects the coordinates based on the timing control signal supplied from the timing controller 6. The pulse signal is sequentially supplied to the coordinate detection line 20, the coordinate detection line readout circuit 7 reads the amount of change in the charge of the data signal line 12, and the coordinate detection circuit 8 converts the amount of change into a voltage value. The position of the coordinate detection object can be specified.
　（変形例２）
　上述した実施の形態では、データ信号線１２は列方向に一定の線幅で延伸しているが、本発明はこれに限定されるものではなく、以下の構成としてもよい。図１０は、変形例２に係る表示パネル１を上面からみたときの上面図である。 (Modification 2)
In the above-described embodiment, the data signal line 12 extends with a constant line width in the column direction. However, the present invention is not limited to this, and may have the following configuration. FIG. 10 is a top view when the display panel 1 according to Modification 2 is viewed from above.
　図１０に示すように、各データ信号線１２は、座標検知線２０との交差部分において、切り欠き部１２ａが設けられており、当該部分においてデータ信号線１２の線幅が狭くなっている。このように切り欠き部１２ａが設けられることによって、データ信号線１２と座標検知線２０とが重なり合う部分の面積が小さくなる。そのため、不要な寄生容量が低減され、座標検知線２０とデータ信号線１２とにより形成される相互容量Ｃｆを相対的に大きくすることができる。これにより、シグナルを高めることができるため、座標検出対象物の座標検出の精度を高めることができる。 As shown in FIG. 10, each data signal line 12 is provided with a notch 12a at the intersection with the coordinate detection line 20, and the line width of the data signal line 12 is narrowed at that portion. Thus, by providing the notch part 12a, the area of the part which the data signal line 12 and the coordinate detection line 20 overlap becomes small. Therefore, unnecessary parasitic capacitance is reduced, and the mutual capacitance Cf formed by the coordinate detection line 20 and the data signal line 12 can be relatively increased. Thereby, since a signal can be raised, the precision of the coordinate detection of a coordinate detection target object can be raised.
　（変形例３）
　上述した実施の形態では、座標検知線２０は行方向に一定の線幅で延伸しているが、本発明はこれに限定されるものではなく、以下の構成としてもよい。図１１は、変形例３に係る表示パネル１を上面からみたときの上面図である。図１１に示すように、各座標検知線２０は、行方向に延伸するとともに、データ信号線１２に重ならない領域、すなわちデータ信号線１２同士の間の領域に、枝分かれした座標検知線２０ａが形成されている。この構成によれば、座標検知線２０とデータ信号線１２とにより形成される相互容量Ｃｆの変化量を大きくすることができるため、検出のシグナルを高めることができる。よって、座標検出対象物の座標検出の精度を高めることができる。 (Modification 3)
In the above-described embodiment, the coordinate detection line 20 extends with a constant line width in the row direction, but the present invention is not limited to this, and may have the following configuration. FIG. 11 is a top view when the display panel 1 according to Modification 3 is viewed from above. As shown in FIG. 11, each coordinate detection line 20 extends in the row direction, and a branched coordinate detection line 20 a is formed in a region that does not overlap the data signal lines 12, that is, a region between the data signal lines 12. Has been. According to this configuration, since the amount of change in the mutual capacitance Cf formed by the coordinate detection line 20 and the data signal line 12 can be increased, the detection signal can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection object can be increased.
　〔実施の形態２〕
　本発明に係る他の実施の形態について、図１２に基づいて説明すれば以下の通りである。なお、本実施の形態では、実施の形態１との相違点について説明するため、説明の便宜上、実施の形態１で説明した部材と同一の機能を有する部材には同一の部材番号を付し、その説明を省略する。 [Embodiment 2]
Another embodiment according to the present invention will be described below with reference to FIG. In addition, in this Embodiment, in order to demonstrate a difference with Embodiment 1, the same member number is attached | subjected to the member which has the same function as the member demonstrated in Embodiment 1 for convenience of explanation, The description is omitted.
　実施の形態１では、受信電極としての各座標検知線２０の一端がそれぞれ座標検知線読み出し回路７に接続されて、座標検知線２０ごとに位置検出動作が行われる。これに対して、本実施の形態では、図１２に示すように、座標検知線２０が数本ごとに一端において電気的に一つに束ねられて、この束（グループ）ごとに座標検知線読み出し回路７に接続されて、位置検出動作が行われる構成となっている。 In the first embodiment, one end of each coordinate detection line 20 as a reception electrode is connected to the coordinate detection line readout circuit 7 and a position detection operation is performed for each coordinate detection line 20. On the other hand, in this embodiment, as shown in FIG. 12, the coordinate detection lines 20 are electrically bundled at one end every several lines, and the coordinate detection lines are read out for each bundle (group). The position detection operation is performed by being connected to the circuit 7.
　すなわち、位置検出動作時において、座標検知用パルス信号を、駆動電極としてのデータ信号線１２に順次印加するとともに、座標検知線２０の束ごと（２０Ａ、２０Ｂ、２０Ｃ、…）に、電荷の変化量を読み取ることによって、座標検出対象物の位置を特定する。 That is, during the position detection operation, the coordinate detection pulse signal is sequentially applied to the data signal line 12 as the drive electrode, and the charge change is performed for each bundle of coordinate detection lines 20 (20A, 20B, 20C,...). The position of the coordinate detection object is specified by reading the quantity.
　また、何本ごとに座標検知線２０を束ねるかは、適宜設定すればよい。また、隣り合う座標検知線２０で束を形成する必要はなく、例えば奇数番目の座標検知線２０を列方向に沿って何本ごとか束ね、偶数番目の座標検知線２０を列方向に沿って何本ごとか束ねるような構成であってもよい。他の例としては、座標検知線２０の総本数がｎ本であり、列方向に沿って１、２、３、…、ｎ－２、ｎ－１、ｎ番目に配列していた場合に、１、２、３、ｎ－２、ｎ－１、ｎ番目の座標検知線２０が１つに束ねられていてもよい。 Moreover, what is necessary is just to set suitably how many the coordinate detection lines 20 are bundled. Further, it is not necessary to form a bundle with adjacent coordinate detection lines 20, for example, odd-numbered coordinate detection lines 20 are bundled along the column direction, and even-numbered coordinate detection lines 20 are aligned along the column direction. A configuration in which several pieces are bundled may be used. As another example, when the total number of coordinate detection lines 20 is n and arranged in the first, second, third,..., N−2, n−1, nth along the column direction, The first, second, third, n-2, n-1, and nth coordinate detection lines 20 may be bundled together.
　本実施の形態の構成によれば、座標検出回路８で解析される座標検知線２０の電荷の変化量は、座標検知線２０ごとの相互容量Ｃｆの変化を表すものではなく、束（グループ）を構成する複数の座標検知線２０（２０Ａ、２０Ｂ、２０Ｃ、…）における相互容量Ｃｆの変化が積算されたものに相当する。そのため、シグナルを高めることができるため、座標検出対象物の座標検出の精度を高めることができる。 According to the configuration of the present embodiment, the amount of change in the charge of the coordinate detection line 20 analyzed by the coordinate detection circuit 8 does not represent the change in the mutual capacitance Cf for each coordinate detection line 20, but a bundle (group). Is equivalent to an accumulation of changes in the mutual capacitance Cf in the plurality of coordinate detection lines 20 (20A, 20B, 20C,...). Therefore, since the signal can be increased, the accuracy of coordinate detection of the coordinate detection target can be increased.
　〔実施の形態３〕
　本発明に係る他の実施の形態について、図１３に基づいて説明すれば以下の通りである。なお、本実施の形態では、実施の形態１との相違点について説明するため、説明の便宜上、実施の形態１で説明した部材と同一の機能を有する部材には同一の部材番号を付し、その説明を省略する。 [Embodiment 3]
Another embodiment according to the present invention will be described below with reference to FIG. In addition, in this Embodiment, in order to demonstrate a difference with Embodiment 1, the same member number is attached | subjected to the member which has the same function as the member demonstrated in Embodiment 1 for convenience of explanation, The description is omitted.
　本実施の形態では、１つの画素が３つのサブ画素（Ｒサブ画素、Ｇサブ画素、Ｂサブ画素）を含んで構成され、各画素において、Ｒサブ画素、Ｇサブ画素、Ｂサブ画素がこの順に列方向に並んで配され、行方向に隣り合う画素同士では、同色のサブ画素が並んで配されている。また、１つのサブ画素に対応して、走査信号線１４と基準配線１３と座標検知線２０とが１本ずつ設けられている。 In this embodiment, one pixel includes three sub pixels (R sub pixel, G sub pixel, and B sub pixel), and in each pixel, the R sub pixel, the G sub pixel, and the B sub pixel are the same. The sub-pixels of the same color are arranged side by side in the pixels arranged in order in the column direction and adjacent in the row direction. Further, one scanning signal line 14, one reference wiring 13, and one coordinate detection line 20 are provided corresponding to one subpixel.
　また、上記構成によれば、座標検知線２０の本数を、実施の形態１に係る表示装置の構成よりも増やすことができるため、座標検知線２０とデータ信号線１２とにより形成される相互容量Ｃｆの変化量を大きくすることができる。そのため、検出のシグナルを高めることができる。よって、座標検出対象物の座標検出の精度をさらに高めることができる。 Further, according to the above configuration, the number of coordinate detection lines 20 can be increased as compared with the configuration of the display device according to the first embodiment, and thus the mutual capacitance formed by the coordinate detection lines 20 and the data signal lines 12. The amount of change in Cf can be increased. Therefore, the detection signal can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection target can be further increased.
　〔実施の形態４〕
　本発明に係る表示装置は、１つの画素が２つのサブ画素（第１、第２サブ画素）で構成される、いわゆるマルチ画素の形態にも適用することができる。 [Embodiment 4]
The display device according to the present invention can also be applied to a so-called multi-pixel form in which one pixel includes two sub-pixels (first and second sub-pixels).
　本実施の形態では、このマルチ画素を有する表示装置の一実施の形態について説明する。なお、本実施の形態では、実施の形態１との相違点について説明するため、説明の便宜上、実施の形態１で説明した部材と同一の機能を有する部材には同一の部材番号を付し、その説明を省略する。 In this embodiment, an embodiment of a display device having the multi-pixel will be described. In addition, in this Embodiment, in order to demonstrate a difference with Embodiment 1, the same member number is attached | subjected to the member which has the same function as the member demonstrated in Embodiment 1 for convenience of explanation, The description is omitted.
　図１４は、本実施の形態の表示装置に設けられたマルチ画素の表示パネルの等価回路であり、図１５は、当該表示パネルにおける列方向に並べられた４画素分の模式断面図である。なお、本実施の形態の表示パネルも、上述した各実施の形態の表示パネルと同様に、データ信号線１２は、対向基板２２に形成されている。 FIG. 14 is an equivalent circuit of a multi-pixel display panel provided in the display device of the present embodiment, and FIG. 15 is a schematic cross-sectional view of four pixels arranged in the column direction of the display panel. In the display panel of the present embodiment, the data signal lines 12 are formed on the counter substrate 22 as in the display panels of the above-described embodiments.
　図１４に示すように、１画素内の各サブ画素に含まれる各画素電極が、互いに異なるトランジスタ１７を介して、行方向に延伸する１本の走査信号線に接続されている。また、各画素において第１サブ画素および第２サブ画素が列方向にこの順に並んで配されており、列方向に並んで配される２つの画素において、一方の画素における第１サブ画素の画素電極および他方の画素における第２サブ画素の画素電極が、異なるトランジスタ１７を介して同一の基準配線１３に接続されている。すなわち、１本の基準配線１３は、隣り合う２つの画素で共有するように配されている。座標検知線２０は、図１５に示すように、表示パネル１を平面的に（観察者側から）見て、走査信号線１４あるいは基準配線１３に重なるように形成されているため、座標検知線２０を設けることによる透過率の低下を防ぐことができる。 As shown in FIG. 14, each pixel electrode included in each sub-pixel in one pixel is connected to one scanning signal line extending in the row direction via different transistors 17. In each pixel, the first sub-pixel and the second sub-pixel are arranged in this order in the column direction, and in the two pixels arranged in the column direction, the pixel of the first sub-pixel in one pixel The electrode and the pixel electrode of the second subpixel in the other pixel are connected to the same reference wiring 13 via different transistors 17. That is, one reference wiring 13 is arranged so as to be shared by two adjacent pixels. As shown in FIG. 15, the coordinate detection line 20 is formed so as to overlap the scanning signal line 14 or the reference wiring 13 when the display panel 1 is viewed in plan (from the observer side). Decrease in transmittance due to the provision of 20 can be prevented.
　ここで図１４の表示装置における駆動方法の一例として、ドット反転駆動のタイミングチャートを図１６に示す。 Here, as an example of a driving method in the display device of FIG. 14, a timing chart of dot inversion driving is shown in FIG.
　列方向に並べられた基準配線１３には、互いに電位レベルが異なる基準電圧Ｃｏｍ１、Ｃｏｍ２が列方向に交互に供給される。すなわち、第１フレームでは、１つの画素において、一方のサブ画素の画素電極には基準配線１３を介してＨｉｇｈレベル（Ｃｏｍ１）の基準電圧が印加され、他方のサブ画素の画素電極には基準配線１３を介してＬｏｗレベル（Ｃｏｍ２）の基準電圧が印加される。これにより、第１フレームの表示データ書き込み期間では、一方の画素を暗画素とし、他方の画素を明画素とすることができる。また、第２フレームでは、基準電圧Ｃｏｍ１、Ｃｏｍ２の電位レベルが逆転するため、一方の画素を明画素とし、他方の画素を暗画素とすることができる。これにより、本実施の形態の表示装置では、視野角特性を高めることができる。 Reference voltages Com1 and Com2 having different potential levels are alternately supplied to the reference wirings 13 arranged in the column direction in the column direction. That is, in the first frame, in one pixel, a reference voltage of High level (Com1) is applied to the pixel electrode of one subpixel through the reference wiring 13, and the reference wiring is applied to the pixel electrode of the other subpixel. A low level (Com 2) reference voltage is applied via 13. Thereby, in the display data writing period of the first frame, one pixel can be a dark pixel and the other pixel can be a bright pixel. In the second frame, since the potential levels of the reference voltages Com1 and Com2 are reversed, one pixel can be a bright pixel and the other pixel can be a dark pixel. Thereby, in the display apparatus of this Embodiment, a viewing angle characteristic can be improved.
　表示データ保持期間では、実施の形態１と同様、座標検知線２０とデータ信号線１２とにより形成される相互容量Ｃｆが座標検出対象物の接近あるいは接触に伴って変化することを利用して、位置検出動作を行う。 In the display data holding period, as in the first embodiment, the mutual capacitance Cf formed by the coordinate detection line 20 and the data signal line 12 changes with the approach or contact of the coordinate detection object, Perform position detection.
　〔実施の形態５〕
　上記各実施の形態に係る表示装置は、相互容量方式のタッチパネル機能を備える構成であるが、他の方式として、自己容量方式のタッチパネル機能を備える構成であってもよい。以下では、自己容量方式のタッチパネル機能を備える表示装置について、実施の形態１の表示装置との相違点を中心に説明する。説明の便宜上、実施の形態１で説明した部材と同一の機能を有する部材には同一の部材番号を付し、その説明を省略する。 [Embodiment 5]
The display device according to each of the above embodiments is configured to include a mutual capacitive touch panel function, but may be configured to include a self-capacitive touch panel function as another method. Hereinafter, a display device having a self-capacitance type touch panel function will be described focusing on differences from the display device of the first embodiment. For convenience of explanation, members having the same functions as those explained in the first embodiment are given the same member numbers, and explanation thereof is omitted.
　図１７は、本実施の形態に係る表示装置のブロック図である。 FIG. 17 is a block diagram of the display device according to the present embodiment.
　図１７に示す表示装置は、画像表示機能と自己容量方式のタッチパネル機能とを兼ね備えた表示パネル１と、表示パネル１を駆動する走査信号線駆動回路２およびデータ信号線駆動回路３と、走査信号線駆動回路２およびデータ信号線駆動回路３に表示制御信号を供給する表示制御回路４と、タイミングコントローラ６、座標検知線駆動回路１１と、座標検出回路８と、基準配線駆動回路９と、電源回路１０とを備えている。 The display device shown in FIG. 17 includes a display panel 1 having both an image display function and a self-capacitance touch panel function, a scanning signal line driving circuit 2 and a data signal line driving circuit 3 for driving the display panel 1, and a scanning signal. A display control circuit 4 for supplying display control signals to the line drive circuit 2 and the data signal line drive circuit 3, a timing controller 6, a coordinate detection line drive circuit 11, a coordinate detection circuit 8, a reference wiring drive circuit 9, and a power supply Circuit 10.
　表示パネル１の等価回路は図２に示したとおりである。 The equivalent circuit of the display panel 1 is as shown in FIG.
　各画素の構造は同一の構成であり、１つの画素に対応して、座標検知線２０と走査信号線１４と基準配線１３とが行方向に１本ずつ設けられ、データ信号線１２が列方向に１本ずつ設けられている。各画素では、アクティブマトリクス基板において、画素電極１５が、走査信号線１４に接続されたトランジスタ（ＴＦＴ）１７を介して基準配線１３に接続されており、対向基板において、データ信号線１２が対向電極１６に接続されている。画素電極１５と対向電極１６との間には液晶容量Ｃｌｃが形成されている。 Each pixel has the same structure, and one coordinate detection line 20, one scanning signal line 14, and one reference wiring 13 are provided in the row direction corresponding to one pixel, and the data signal line 12 is arranged in the column direction. One for each. In each pixel, in the active matrix substrate, the pixel electrode 15 is connected to the reference wiring 13 via a transistor (TFT) 17 connected to the scanning signal line 14, and in the counter substrate, the data signal line 12 is connected to the counter electrode. 16 is connected. A liquid crystal capacitor Clc is formed between the pixel electrode 15 and the counter electrode 16.
　座標検知線２０は、図１７に示すように、一端が座標検知線駆動回路１１に接続されており、データ信号線１２は、一端がデータ信号線駆動回路３に接続されている。 As shown in FIG. 17, one end of the coordinate detection line 20 is connected to the coordinate detection line drive circuit 11, and one end of the data signal line 12 is connected to the data signal line drive circuit 3.
　タイミングコントローラ６は、各種同期信号等のタイミング制御信号を生成し、データ信号線駆動回路３、表示制御回路４、座標検知線駆動回路１１、および、座標検出回路８に供給する。 The timing controller 6 generates timing control signals such as various synchronization signals and supplies them to the data signal line drive circuit 3, the display control circuit 4, the coordinate detection line drive circuit 11, and the coordinate detection circuit 8.
　データ信号線駆動回路３は、表示制御信号に基づいて、データ信号を、データ信号線入力部を介してデータ信号線１２に供給する。これにより、オン状態になっているトランジスタ１７を介して液晶層にデータ信号に応じた電圧が印加されて画像情報が書き込まれる。 The data signal line driving circuit 3 supplies a data signal to the data signal line 12 via the data signal line input unit based on the display control signal. As a result, a voltage corresponding to the data signal is applied to the liquid crystal layer through the transistor 17 in the on state, and image information is written.
　座標検知線駆動回路１１およびデータ信号線駆動回路３は、それぞれパルス信号読み出し回路として機能する。すなわち、座標検知線駆動回路１１は、座標検知線２０と座標検出対象物との間に形成される容量（自己容量）を検出し、データ信号線駆動回路３は、データ信号線１２と座標検出対象物との間に形成される容量（自己容量）を検出する。 The coordinate detection line drive circuit 11 and the data signal line drive circuit 3 each function as a pulse signal readout circuit. That is, the coordinate detection line drive circuit 11 detects the capacitance (self-capacitance) formed between the coordinate detection line 20 and the coordinate detection object, and the data signal line drive circuit 3 detects the coordinate with the data signal line 12. A capacitance (self-capacitance) formed between the object and the object is detected.
　座標検出回路８は、座標検知線駆動回路１１およびデータ信号線駆動回路３が検出したそれぞれの容量に基づいて座標検出対象物の位置を特定する。 The coordinate detection circuit 8 specifies the position of the coordinate detection object based on the respective capacities detected by the coordinate detection line drive circuit 11 and the data signal line drive circuit 3.
　このように、本実施の形態に係る表示装置においても、座標検出対象物の位置を特定することができる。なお、上記各実施の形態に係る表示装置についても、自己容量方式のタッチパネル機能を適用することができる。 Thus, also in the display device according to the present embodiment, the position of the coordinate detection object can be specified. Note that the self-capacitance touch panel function can also be applied to the display devices according to the above embodiments.
　例えば、図１０に示す表示パネル１に自己容量方式を採用した場合には、データ信号線１２と座標検知線２０との重なり面積が小さくなるため、不要な寄生容量を低減することができる。これにより、座標検知線２０と座標検出対象物との間に形成される容量を相対的に大きくすることができるため、強度比率を高めることができる。よって、座標検出対象物の座標検出の精度をさらに高めることができる。 For example, when the self-capacitance method is adopted for the display panel 1 shown in FIG. 10, since the overlapping area of the data signal line 12 and the coordinate detection line 20 becomes small, unnecessary parasitic capacitance can be reduced. Thereby, since the capacity | capacitance formed between the coordinate detection line 20 and a coordinate detection target object can be enlarged relatively, an intensity | strength ratio can be raised. Therefore, the accuracy of coordinate detection of the coordinate detection target can be further increased.
　ここで、本発明の表示装置では、
　表示画像に応じたデータを各画素に書き込む表示データ書き込み期間以外の表示データ保持期間に、上記表示パネルに座標検出対象物が接近または接触したときの上記容量の変化に基づいて、上記座標検出対象物の位置座標を検出する構成とすることもできる。 Here, in the display device of the present invention,
The coordinate detection target based on the change in the capacity when the coordinate detection target object approaches or contacts the display panel during a display data holding period other than the display data writing period in which data corresponding to the display image is written to each pixel. It can also be set as the structure which detects the position coordinate of an object.
　また、上記表示装置では、
　上記座標検出対象物は、上記第２基板における、上記第１基板側とは反対側に位置している構成とすることもできる。 In the display device,
The coordinate detection object may be configured to be located on the opposite side of the second substrate from the first substrate side.
　上記の構成によれば、上記容量の変化量を大きくすることができるため、検出の強度比率を高めることができる。よって、座標検出対象物の座標検出の精度を高めることができる。 According to the above configuration, since the amount of change in the capacity can be increased, the detection intensity ratio can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection object can be increased.
　また、上記表示装置では、
　上記座標検知線は、上記データ信号線と交差する方向に延伸している構成とすることもできる。 In the display device,
The coordinate detection line may be extended in a direction intersecting with the data signal line.
　また、上記表示装置では、
　上記データ信号線における上記座標検知線との交差部分は、当該交差していない部分と比較して、線幅が狭くなっている構成とすることもできる。 In the display device,
The crossing portion of the data signal line with the coordinate detection line may be configured to have a narrower line width than the non-crossing portion.
　上記の構成によれば、データ信号線と座標検知線との重なり面積が小さくなるため、不要な寄生容量を低減することができる。これにより、座標検知線とデータ信号線とにより形成される上記容量の変化を相対的に大きくすることができる。よって、座標検出対象物の座標検出の精度をさらに高めることができる。 According to the above configuration, since the overlapping area of the data signal line and the coordinate detection line becomes small, unnecessary parasitic capacitance can be reduced. Thereby, the change in the capacitance formed by the coordinate detection line and the data signal line can be relatively increased. Therefore, the accuracy of coordinate detection of the coordinate detection target can be further increased.
　また、上記表示装置では、
　上記座標検知線は、さらに、上記データ信号線同士の間の領域に重なるように、上記データ信号線が延伸する方向に枝分かれして形成されている構成とすることもできる。 In the display device,
Further, the coordinate detection line may be formed so as to be branched in the extending direction of the data signal line so as to overlap an area between the data signal lines.
　上記の構成によれば、座標検知線とデータ信号線とにより形成される上記容量の変化が大きくなり、座標検出対象物の座標検出の精度をさらに高めることができる。 According to the above configuration, the change in the capacity formed by the coordinate detection line and the data signal line is increased, and the accuracy of coordinate detection of the coordinate detection target can be further increased.
　また、上記表示装置では、
　上記座標検知線は、少なくとも２本の上記座標検知線が１つのグループとして構成された複数のグループに分かれており、
　上記グループごとに、上記容量の変化を検出する構成とすることもできる。 In the display device,
The coordinate detection lines are divided into a plurality of groups in which at least two coordinate detection lines are configured as one group,
It can also be set as the structure which detects the change of the said capacity | capacitance for every said group.
　上記の構成によれば、グループを構成する複数の座標検知線における上記容量の変化が積算されたものに相当するので、座標検出の精度をさらに高めることができる。 According to the above configuration, since the change in the capacity of the plurality of coordinate detection lines constituting the group corresponds to the integrated value, the accuracy of coordinate detection can be further increased.
　また、上記表示装置では、
　上記データ信号線は、少なくとも２本の上記データ信号線が１つのグループとして構成された複数のグループに分かれており、
　上記グループごとに、上記容量の変化を検出する構成とすることもできる。 In the display device,
The data signal lines are divided into a plurality of groups in which at least two of the data signal lines are configured as one group,
It can also be set as the structure which detects the change of the said capacity | capacitance for every said group.
　上記の構成によれば、グループを構成する複数のデータ信号線に対応する上記容量の変化が積算されたものに相当するので、座標検出の精度をさらに高めることができる。 According to the above configuration, since the change in the capacity corresponding to the plurality of data signal lines constituting the group corresponds to the integrated value, the accuracy of coordinate detection can be further increased.
　また、上記表示装置では、
　行方向および列方向に複数配された画素のそれぞれは、Ｒ色に対応するＲサブ画素、Ｇ色に対応するＧサブ画素、Ｂ色に対応するＢサブ画素を含んで構成され、
　上記Ｒサブ画素、上記Ｇサブ画素、および上記Ｂサブ画素は、上記データ信号線が延伸する方向に並んで配されている構成とすることもできる。 In the display device,
Each of the plurality of pixels arranged in the row direction and the column direction includes an R sub-pixel corresponding to the R color, a G sub-pixel corresponding to the G color, and a B sub-pixel corresponding to the B color.
The R subpixel, the G subpixel, and the B subpixel may be arranged side by side in a direction in which the data signal line extends.
　上記の構成によれば、座標検知線の本数を増やすことができるため、座標検知線とデータ信号線とにより形成される上記容量の変化量を大きくすることができる。そのため、検出のシグナルを高めることができる。よって、座標検出対象物の座標検出の精度をさらに高めることができる。 According to the above configuration, since the number of coordinate detection lines can be increased, the amount of change in the capacitance formed by the coordinate detection lines and the data signal lines can be increased. Therefore, the detection signal can be increased. Therefore, the accuracy of coordinate detection of the coordinate detection target can be further increased.
　また、上記表示装置では、
　行方向および列方向に複数配された画素のそれぞれには、上記データ信号線の延伸する方向に、第１サブ画素および第２サブ画素がこの順に並んで配されており、
　上記第１サブ画素の画素電極および上記第２サブ画素の画素電極は、互いに異なるトランジスタを介して、同一の走査信号線に接続され、
　上記データ信号線が延伸する方向に並んで配される２つの画素において、一方の画素における上記第１サブ画素の画素電極および他方の画素における上記第２サブ画素の画素電極が、同一の上記基準配線に接続されている構成とすることもできる。 In the display device,
In each of the plurality of pixels arranged in the row direction and the column direction, the first sub-pixel and the second sub-pixel are arranged in this order in the extending direction of the data signal line,
The pixel electrode of the first subpixel and the pixel electrode of the second subpixel are connected to the same scanning signal line through different transistors,
In two pixels arranged side by side in the extending direction of the data signal line, the pixel electrode of the first sub-pixel in one pixel and the pixel electrode of the second sub-pixel in the other pixel are the same reference It can also be set as the structure connected to wiring.
　上記の構成によれば、マルチ画素の構成を有する表示装置に適用することができる。 The above configuration can be applied to a display device having a multi-pixel configuration.
　また、上記表示装置では、
　各画素において、上記第１サブ画素の画素電極が接続される第１基準配線に供給される信号の電位レベルと、上記第２サブ画素の画素電極が接続される第２基準配線に供給される信号の電位レベルとは、互いに異なっている構成とすることもできる。 In the display device,
In each pixel, the potential level of the signal supplied to the first reference wiring to which the pixel electrode of the first sub-pixel is connected and the second reference wiring to which the pixel electrode of the second sub-pixel is connected are supplied. The signal potential levels may be different from each other.
　また、上記表示装置では、
　各フレームにおける上記表示データ保持期間において、少なくとも１回、上記容量の変化を検出する構成とすることもできる。 In the display device,
The change in the capacity may be detected at least once in the display data holding period in each frame.
　例えば、各フレーム（６０Ｈｚ）における上記表示データ保持期間において、２回上記容量の変化を検出する構成とした場合、検出周波数が２倍（１２０Ｈｚ）になるため、座標検出対象物の座標検出の速度をさらに高めることができる。これにより、より素早い操作（ペン入力など）に対応することが可能になる。 For example, when the change in the capacity is detected twice in the display data holding period in each frame (60 Hz), the detection frequency is doubled (120 Hz), so the coordinate detection speed of the coordinate detection target object Can be further enhanced. Thereby, it becomes possible to cope with a quicker operation (such as pen input).
　また、上記表示装置では、
　ｎ（ｎは２以上の整数）フレームごとに、少なくとも１回、上記容量の変化を検出する構成とすることもできる。 In the display device,
It is also possible to adopt a configuration in which the change in the capacity is detected at least once every n (n is an integer of 2 or more) frames.
　上記の構成では、表示フレームに依存せずにセンシングの周波数を設定することができるため、表示装置の設計自由度を高めることができる。 In the above configuration, since the sensing frequency can be set without depending on the display frame, the design flexibility of the display device can be increased.
　本発明は上述した各実施の形態に限定されるものではなく、請求項に示した範囲で種々の変更が可能である。 The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope indicated in the claims.
　本発明は、表示機能を有する液晶パネルにタッチパネル機能を兼ね備えた表示装置として、液晶表示装置を具備するあらゆる機器に搭載することができる。 The present invention can be mounted on any device having a liquid crystal display device as a display device having a touch panel function on a liquid crystal panel having a display function.
１　　表示パネル
２　　走査信号線駆動回路
３　　データ信号線駆動回路
４　　表示制御回路
６　　タイミングコントローラ
７　　座標検知線読み出し回路
８　　座標検出回路
９　　基準配線駆動回路
１０　電源回路
１１　座標検知線駆動回路
１２　データ信号線（Ｄａｔａ ｍ、Ｄａｔａ ｍ＋１、Ｄａｔａ ｍ＋２）
１２ａ　切り欠き部
１３　基準配線（Ｃｏｍ、Ｃｏｍ１、Ｃｏｍ２）
１４　走査信号線（Ｇｎ、Ｇｎ＋１、Ｇｎ＋２）
１５　画素電極
１６　対向電極
１７　トランジスタ（ＴＦＴ）
１８　絶縁層
２０　座標検知線
２０ａ　（枝分かれした）座標検知線
２１　アクティブマトリクス基板（第１基板）
２２　対向基板（第２基板）
２３　ゲート電極
２４　ドレイン電極
２５　ソース電極
Ｃｌｃ　液晶容量
Ｃｆ　　相互容量 DESCRIPTION OF SYMBOLS 1 Display panel 2 Scan signal line drive circuit 3 Data signal line drive circuit 4 Display control circuit 6 Timing controller 7 Coordinate detection line readout circuit 8 Coordinate detection circuit 9 Reference wiring drive circuit 10 Power supply circuit 11 Coordinate detection line drive circuit 12 Data signal line (Data m, Data m + 1, Data m + 2)
12a Notch 13 Reference wiring (Com, Com1, Com2)
14 Scanning signal lines (Gn, Gn + 1, Gn + 2)
15 Pixel electrode 16 Counter electrode 17 Transistor (TFT)
18 Insulating layer 20 Coordinate detection line 20a (branched) coordinate detection line 21 Active matrix substrate (first substrate)
22 Counter substrate (second substrate)
23 Gate electrode 24 Drain electrode 25 Source electrode Clc Liquid crystal capacitance Cf Mutual capacitance

Claims (13)

  1. 　基準配線と、走査信号線と、制御端子が上記走査信号線に接続されたトランジスタと、画素電極とが形成された第１基板と、
    　データ信号線が形成された第２基板と、
    　上記第１および第２基板間に狭持された液晶層と、を含む表示パネルを備えた表示装置であって、
    　上記画素電極は、上記トランジスタを介して上記基準配線に電気的に接続されるとともに、上記液晶層を介して上記データ信号線に重なっており、
    　上記第２基板には、絶縁層を介して、上記データ信号線に重なる座標検知線が形成され、
    　上記座標検知線と上記データ信号線との間に容量が形成されていることを特徴とする表示装置。     A first substrate on which a reference wiring, a scanning signal line, a transistor having a control terminal connected to the scanning signal line, and a pixel electrode;
    A second substrate on which data signal lines are formed;
    A display device comprising a display panel including a liquid crystal layer sandwiched between the first and second substrates,
    The pixel electrode is electrically connected to the reference wiring through the transistor and overlaps the data signal line through the liquid crystal layer.
    The second substrate is provided with a coordinate detection line that overlaps the data signal line through an insulating layer,
    A display device, wherein a capacitance is formed between the coordinate detection line and the data signal line.
  2. 　表示画像に応じたデータを各画素に書き込む表示データ書き込み期間以外の表示データ保持期間に、上記表示パネルに座標検出対象物が接近または接触したときの上記容量の変化に基づいて、上記座標検出対象物の位置座標を検出することを特徴とする請求項１に記載の表示装置。 The coordinate detection target based on the change in the capacity when the coordinate detection target object approaches or contacts the display panel during a display data holding period other than the display data writing period in which data corresponding to the display image is written to each pixel. The display device according to claim 1, wherein position coordinates of an object are detected.
  3. 　上記座標検出対象物は、上記第２基板における、上記第１基板側とは反対側に位置していることを特徴とする請求項２に記載の表示装置。 3. The display device according to claim 2, wherein the coordinate detection object is located on a side of the second substrate opposite to the first substrate.
  4. 　上記座標検知線は、上記データ信号線と交差する方向に延伸していることを特徴とする請求項１に記載の表示装置。 The display device according to claim 1, wherein the coordinate detection line extends in a direction intersecting with the data signal line.
  5. 　上記データ信号線における上記座標検知線との交差部分は、当該交差していない部分と比較して、線幅が狭くなっていることを特徴とする請求項４に記載の表示装置。 5. The display device according to claim 4, wherein a line width of an intersection of the data signal line with the coordinate detection line is narrower than that of the non-intersecting part.
  6. 　上記座標検知線は、さらに、上記データ信号線同士の間の領域に重なるように、上記データ信号線が延伸する方向に枝分かれして形成されていることを特徴とする請求項１に記載の表示装置。 2. The display according to claim 1, wherein the coordinate detection line is further branched in the extending direction of the data signal line so as to overlap an area between the data signal lines. apparatus.
  7. 　上記座標検知線は、少なくとも２本の上記座標検知線が１つのグループとして構成された複数のグループに分かれており、
    　上記グループごとに、上記容量の変化を検出することを特徴とする請求項２に記載の表示装置。     The coordinate detection lines are divided into a plurality of groups in which at least two coordinate detection lines are configured as one group,
    The display device according to claim 2, wherein a change in the capacity is detected for each group.
  8. 　上記データ信号線は、少なくとも２本の上記データ信号線が１つのグループとして構成された複数のグループに分かれており、
    　上記グループごとに、上記容量の変化を検出することを特徴とする請求項２に記載の表示装置。     The data signal lines are divided into a plurality of groups in which at least two of the data signal lines are configured as one group,
    The display device according to claim 2, wherein a change in the capacity is detected for each group.
  9. 　行方向および列方向に複数配された画素のそれぞれは、Ｒ色に対応するＲサブ画素、Ｇ色に対応するＧサブ画素、Ｂ色に対応するＢサブ画素を含んで構成され、
    　上記Ｒサブ画素、上記Ｇサブ画素、および上記Ｂサブ画素は、上記データ信号線が延伸する方向に並んで配されていることを特徴とする請求項１に記載の表示装置。     Each of the plurality of pixels arranged in the row direction and the column direction includes an R sub-pixel corresponding to the R color, a G sub-pixel corresponding to the G color, and a B sub-pixel corresponding to the B color.
    The display device according to claim 1, wherein the R sub-pixel, the G sub-pixel, and the B sub-pixel are arranged side by side in a direction in which the data signal line extends.
  10. 　行方向および列方向に複数配された画素のそれぞれには、上記データ信号線の延伸する方向に、第１サブ画素および第２サブ画素がこの順に並んで配されており、
    　上記第１サブ画素の画素電極および上記第２サブ画素の画素電極は、互いに異なるトランジスタを介して、同一の走査信号線に接続され、
    　上記データ信号線が延伸する方向に並んで配される２つの画素において、一方の画素における上記第１サブ画素の画素電極および他方の画素における上記第２サブ画素の画素電極が、同一の上記基準配線に接続されていることを特徴とする請求項１に記載の表示装置。     In each of the plurality of pixels arranged in the row direction and the column direction, the first sub-pixel and the second sub-pixel are arranged in this order in the extending direction of the data signal line,
    The pixel electrode of the first subpixel and the pixel electrode of the second subpixel are connected to the same scanning signal line through different transistors,
    In two pixels arranged side by side in the extending direction of the data signal line, the pixel electrode of the first sub-pixel in one pixel and the pixel electrode of the second sub-pixel in the other pixel are the same reference The display device according to claim 1, wherein the display device is connected to wiring.
  11. 　各画素において、上記第１サブ画素の画素電極が接続される第１基準配線に供給される信号の電位レベルと、上記第２サブ画素の画素電極が接続される第２基準配線に供給される信号の電位レベルとは、互いに異なっていることを特徴とする請求項１０に記載の表示装置。 In each pixel, the potential level of the signal supplied to the first reference wiring to which the pixel electrode of the first sub-pixel is connected and the second reference wiring to which the pixel electrode of the second sub-pixel is connected are supplied. The display device according to claim 10, wherein the potential levels of the signals are different from each other.
  12. 　各フレームにおける上記表示データ保持期間において、少なくとも１回、上記容量の変化を検出することを特徴とする請求項２に記載の表示装置。 3. The display device according to claim 2, wherein the change in the capacity is detected at least once in the display data holding period in each frame.
  13. 　ｎ（ｎは２以上の整数）フレームごとに、少なくとも１回、上記容量の変化を検出することを特徴とする請求項２に記載の表示装置。 3. The display device according to claim 2, wherein the change in the capacity is detected at least once every n (n is an integer of 2 or more) frames.
PCT/JP2011/075624 2010-11-10 2011-11-07 Display device WO2012063787A1 (en)

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