WO2012040917A1 - Shallow junction solar battery and manufacturing method thereof - Google Patents
Shallow junction solar battery and manufacturing method thereof Download PDFInfo
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- WO2012040917A1 WO2012040917A1 PCT/CN2010/077442 CN2010077442W WO2012040917A1 WO 2012040917 A1 WO2012040917 A1 WO 2012040917A1 CN 2010077442 W CN2010077442 W CN 2010077442W WO 2012040917 A1 WO2012040917 A1 WO 2012040917A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/03529—Shape of the potential jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Definitions
- the present invention relates to the field of solar cell device manufacturing technology, and in particular, to a shallow junction solar cell and a method of fabricating the same. Background technique
- a conventionally prepared solar cell is an implanted silicon solar cell fabricated by a conventional diffusion method, having a junction depth of about 0.5 ⁇ m and a diffusion resistance R of about right and left.
- the ⁇ + ⁇ junction as an example, the ⁇ + phosphorus diffusion impurity distribution is not a typical residual error function distribution, and has an almost constant concentration near the surface, the value of which depends on the solid solubility of phosphorus in silicon at the phosphorus diffusion temperature.
- its surface is a heavily doped layer. Due to the heavy doping effect and severe lattice defects and distortion, the heavily doped layer becomes the recombination center of the carrier, making the layer have a very low lifetime, so the layer is called a "composite layer".
- the technical problem to be solved by the present invention is to provide a shallow junction solar cell and a preparation method thereof, and the shallow junction solar cell prepared by the method can shorten the carrier transmission path and reduce the thickness of the "composite layer", effectively Preventing the recombination of carriers near the surface of the n + layer or the p + layer, increasing the probability of collection of photogenerated carriers, and improving the photoelectric conversion efficiency.
- the present invention provides a shallow junction solar cell including a metal gate electrode, a passivation layer, a crystalline silicon and a metal back electrode; the metal back electrode is located in the crystalline silicon a back surface, the passivation layer is located above the crystalline silicon, the metal gate electrode is located above the passivation layer, the crystalline silicon includes a PN junction, and the PN junction has a depth of 10 nm to 200 nm .
- the present invention has the following features: the surface of the crystalline silicon is a plane or a curved surface, and the interface of the PN junction is a plane or a curved surface similar to the surface of the crystalline silicon.
- the surface of the crystalline silicon is a composite surface composed of a plane and a curved surface
- the interface of the PN junction is a composite surface similar to the surface of the crystalline silicon.
- the present invention has the following features: the crystalline silicon is single crystal silicon or polycrystalline silicon, the metal back electrode is made of aluminum, copper, silver, gold or platinum, and the metal gate electrode is made of aluminum, copper, silver. Made of gold or platinum.
- the present invention has the following features: the thickness of the metal back electrode is 10 to 15 ⁇ m; the thickness of the crystalline silicon is 100 to 300 ⁇ m; and the thickness of the passivation layer is 50 to 200 nm;
- the metal gate electrode has a thickness of 2 to 10 ⁇ m, and the metal gate electrode has a width of 30 to 150 ⁇ m and a pitch of 2 to 3 mm.
- the present invention also provides a method of fabricating a shallow junction solar cell, the method comprising: Pretreatment of crystalline silicon;
- a metal back electrode and a metal gate electrode are respectively formed on the back surface of the crystalline silicon and the passivation layer. Further, the present invention has the following features, the step of pretreating the crystalline silicon includes cleaning, de-damaging or texturing the crystalline silicon.
- the step of preparing a PN junction on the crystalline silicon by using a plasma immersion ion implantation process specifically includes:
- the plasma immersion ion implantation apparatus generates a plasma into which doped ions in the plasma are implanted.
- the present invention has the following features: the step of placing the crystalline silicon in an implantation chamber of the plasma immersion ion implantation apparatus further comprises electrically connecting the crystalline silicon to a power source to which a bias voltage can be applied;
- the process parameters include the background pressure and the working pressure of the injection chamber, the flow rate, composition and volume ratio of the mixed gas injected into the injection chamber, the output power of the plasma power source, the bias voltage, and the plasma injection.
- the background pressure range is 1 (T 3 Pa ⁇ lOOPa, the working pressure range is 0.1 Pa ⁇ 50 Pa;
- the mixed gas is composed of a gas containing P, As or B elements, the containing P or As
- the gas of the element includes B 2 H 6 , B(OCH 3 ) 3 , PH 3 or AsH 3 .
- the present invention has the following features: changing the PN junction by adjusting the bias voltage, the plasma injection time, the flow rate and composition ratio of the mixed gas, or the output power of the plasma power source depth. Further, the present invention further has the following features.
- the step of preparing a PN junction on the crystalline silicon and performing a passivation treatment on the PN junction further includes:
- the heat treated crystal silicon is etched and edge-treated.
- the passivation treatment is performed by a surface oxidation growth SiO 2 passivation method, or a PECVD grown SiNx or Si0 2 passivation method is used, or a plasma immersion implantation process is used. After injecting 0 or N into the crystalline silicon, Si0 2 or SiNx is formed.
- the structure of the shallow junction solar cell provided by the invention can form a very shallow PN junction on the crystalline silicon, which reduces the thickness of the "composite layer” and shortens the carrier transmission path;
- the invention utilizes plasma immersion ion implantation to prepare a PN junction, and can form a PN junction with a small junction-controllable U ⁇ at an interface of any shape, which is beneficial to prevent carriers from being on the surface of the n + layer or the p + layer.
- the nearby compounding increases the probability of collection of photogenerated carriers and improves conversion efficiency;
- the interface shape of the PN junction can be closer to the surface shape of the crystalline silicon; that is, when the surface shape of the crystalline silicon is a curved surface, the interface shape of the PN junction is The curved surface closer to the surface shape of the crystalline silicon overcomes the problem that the interface area of the PN junction is smaller than the surface area of the crystalline silicon due to the deep junction in the prior art (when the surface of the crystalline silicon is curved), therefore, the present invention is adopted.
- the area of the PN junction can be increased, which is advantageous for the generation and separation of photogenerated carriers and improves the conversion efficiency;
- the preparation method of the shallow junction solar cell provided by the invention is unique and easy to grasp, has the characteristics of convenient operation, repeated and reliable, and has a clear industrialization prospect.
- FIG. 1 is a schematic structural view of a first embodiment of a shallow junction solar cell of the present invention
- FIG. 2 is a schematic structural view of a second embodiment of the shallow junction solar cell of the present invention.
- FIG. 3 is a schematic structural view of a third embodiment of the shallow junction solar cell of the present invention.
- FIG. 4 is a schematic structural view of a fourth embodiment of the shallow junction solar cell of the present invention.
- FIG. 5 is a flow chart of a method for preparing a shallow junction solar cell according to an embodiment of the present invention. detailed description
- a first embodiment of the present invention provides a shallow junction solar cell comprising a metal back electrode 1, a crystalline silicon 2, a passivation layer 4, and a metal gate electrode 5.
- the metal back electrode 1 is located on the back surface of the crystalline silicon 2, and the metal back electrode may be made of metal such as aluminum (Al), copper (Cu), silver (Ag), gold (Au) or platinum (Pt), or may be made of a plurality of metals.
- the material is mixed, and the crystalline silicon 2 may be p-type single crystal silicon, p-type polycrystalline silicon, n-type single crystal silicon or n-type polycrystalline silicon.
- the PN junction 3 is located in the crystalline silicon 2, and the junction region is indicated by a broken line, and the solid line in the junction region indicates the interface of the PN junction.
- the PN junction 3 may be formed by doping a crystalline silicon (including single crystal silicon and polycrystalline silicon) by a plasma immersion ion implantation process, and the doping type is opposite to that of the crystalline silicon, for example: if the crystalline silicon is p-type, Then, an n-type impurity is doped; if the crystalline silicon is an n-type, a p-type impurity is doped.
- the PN junction 3 has a depth of 10 nm to 200 nm. In the present embodiment, the interface of the PN junction 3 is a flat surface.
- the passivation layer 4 is located on the crystalline silicon 2, and the passivation layer can be formed by surface oxidation by SiO 2 passivation, or by SiCVD or Si0 2 passivation by PECVD, or by plasma immersion implantation. After injecting 0 or N into the silicon, Si0 2 or SiNx is formed.
- the metal gate electrode 5 is located on the passivation layer 4, which may be aluminum (Al), copper (Cu), silver Made of metal such as (Ag), gold (Au) or platinum (Pt), or a mixture of various metal materials.
- the thickness of the metal back electrode 1 is 1 to 100 micrometers, preferably 10 to 15 micrometers; the thickness of the crystalline silicon 2 is 10 to 1000 meters, preferably 100 to 300 meters; and the thickness of the passivation layer 4 is 1 to 500 nanometers.
- the thickness of the metal gate electrode 5 is 1 to 50 ⁇ m, preferably 2 to 10 ⁇ m, and the width of the metal gate electrode is 10 to 1000 ⁇ m, preferably 30 to 150 ⁇ m, and the pitch is 1 to 10 Millimeters, preferably 2 to 3 mm.
- the structure of the shallow junction solar cell provided by the embodiment provides a shallow junction of the PN junction in the solar cell, and the junction depth is less than 200 nm, so that the thickness of the "composite layer" is reduced, and the carrier is prevented from being in the n + layer or The recombination near the surface of the p + layer increases the probability of collection of photogenerated carriers and improves conversion efficiency.
- the shallower the depth of the PN junction the closer the interface shape of the PN junction can be to the surface shape of the crystalline silicon.
- the surface shape of the crystalline silicon is a curved surface, a needle-like or a penguin-like curved surface or a composite surface (the crystalline silicon of the surface has a high light absorption property)
- the PN junction can be prepared by the prior art, and only the junction can be prepared.
- a PN junction with a depth of about 0.5 ⁇ m may cause the interface area of the PN junction to be inconsistent with the surface area of the crystalline silicon.
- the interface area of the deep PN junction is usually smaller than the surface area of the crystalline silicon. Therefore, the shallow junction structure of the present invention can increase the area of the PN junction, facilitate the generation and separation of photogenerated carriers, and improve the conversion efficiency.
- FIG. 2 is a schematic structural view of a second embodiment of the shallow junction solar cell of the present invention.
- the interface of the PN junction 3 of the second embodiment is a curved surface, and the curved surface has a concavo-convex shape.
- 3 is a schematic structural view of a third embodiment of the shallow junction solar cell of the present invention, which differs from FIG. 1 in that the interface of the PN junction 3 of the third embodiment is a composite surface composed of a plane and a curved surface.
- 4 is a schematic view showing the structure of a fourth embodiment of the shallow junction solar cell of the present invention, which is different from that of FIG. 1 in that the interface of the PN junction 3 of the fourth embodiment is another composite surface composed of a plane and a curved surface.
- the interface of the PN junction 3 of the shallow junction solar cell of the present invention may also be any shape composed of planes, bevels, and/or curved surfaces. Shape.
- the interface shape of the PN junction is similar or identical to the surface shape of the crystalline silicon.
- the interface shape of the so-called PN junction is similar to the surface shape of the crystalline silicon, meaning that the PN junction interface is substantially parallel to the surface of the crystalline silicon, and the PN junction
- the linearity, radius of curvature, or degree of curvature of the interface is substantially the same as the surface of the crystalline silicon.
- an embodiment of the present invention further provides a method for preparing a shallow junction solar cell, the method comprising the following steps:
- Step 101 cleaning and de-damaging the crystalline silicon
- the apparatus used for plasma immersion ion implantation also commonly referred to as a plasma immersion ion implanter, generally includes an implantation chamber and a plasma source; a sample stage on which a sample can be placed, on a side opposite to the sample stage, a plasma source is provided; the plasma source includes an evacuation system that can evacuate the injection chamber to a preset background pressure range; a gas system that fills the injection chamber with the required gas and can adjust various parameters of the gas according to certain control rules, such as gas flow rate, extraction speed, gas composition ratio And the concentration and other parameters, when the gas is charged into the injection chamber, the pressure of the injection chamber can be brought into a preset working pressure range; and the plasma power source can be a radio frequency
- the plasma immersion ion implantation process is: placing crystalline silicon in the implantation chamber; adjusting the process parameters of the plasma immersion ion implanter into a preset numerical range; the plasma immersion ion implanter generates a plasma, The doping ions in the plasma are implanted into the crystalline silicon to complete the doping of the crystalline silicon; the type of the doping ions is opposite to the original doping type of the crystalline silicon, for example: if the crystalline silicon is P-type, the incorporation is N-type ion; if the crystalline silicon is N-type, P-type ions are doped, thereby forming a PN junction; the depth of the PN junction to be formed can be changed by adjusting the corresponding process parameters, that is,
- the interface shape of the so-called PN junction is similar to the surface shape of the crystalline silicon, which means that the interface of the PN junction is substantially parallel to the surface of the crystalline silicon.
- the process parameters to be adjusted include the background pressure and working pressure of the injection chamber, the flow rate of the injected gas, the velocity of the extracted gas, the composition of the mixed gas, the composition ratio and concentration, the output power and frequency of the plasma power source, and the bias can be applied.
- the bias voltage applied by the voltage supply, if pulsed, includes pulse width, duty cycle, and frequency;
- the base pressure range may be injected into the chamber l (T 7 Pa ⁇ lOOOPa, may be preferably l (T 3 Pa ⁇ lOOPa; working pressure range may be injected into the chamber 10_ 3 Pa ⁇ lOOOPa, preferably O.OlPa ⁇ lOOPa, more preferably 0.1Pa ⁇ 50Pa;
- the gas composition of the As, B or B element, the gas containing the B, P or As element includes B 2 H 6 , B(OCH 3 ) 3 , PH 3 or AsH 3 ; the corresponding doping ions generated by these injection gases include B Ion, P ion or As ion;
- the output power of the plasma power source is 1 to 100000 W, preferably 10 to 50000 W, and more preferably 100 to 800 W; the applied bias voltage is -100,000 to 100,000 V, preferably -50000 50000V, more preferably -500 ⁇ 30000 V; pulse width 1us ⁇ Is, preferably lus ⁇ 0.1s, more preferably lus ⁇ lms; duty ratio 1% ⁇ 99%, preferred It is 10% to 90%, more preferably 20% to 80%, and the frequency of the plasma power source is DC ⁇ 10 GHz, preferably 1 MHz ⁇ 5 GHz, more preferably 13.56 MHz ⁇ 5 GHz; bias can be applied The frequency of the voltage source is DC ⁇ 10 GHz; the plasma injection time is 10 ⁇ 30 minutes;
- Step 103 heat treating the doping
- the crystalline silicon is placed in an annealing furnace for rapid thermal annealing, and the atmosphere is a protective atmosphere, which may be N 2 , Ar, etc., at a temperature of 800 to 1300 ° C;
- Step 104 etching and removing the crystalline silicon
- CF 4 gas a high-frequency glow discharge reaction is used to activate the reaction gas to form active particles. These active particles diffuse to the portion where the crystalline silicon needs to be etched, and chemically react with the material to be etched at the site to form a volatile substance. And removed;
- Step 105 Passivating the PN junction to form a passivation layer
- surface oxidation growth Si0 2 passivation can be used for treatment
- PECVD growth SiN x or Si0 2 passivation can also be used for processing
- plasma immersion implantation process can be used to implant 0 or N into crystalline silicon.
- SiO 2 or SiNx is formed; the embodiment is treated by surface oxidation growth SiO 2 passivation, and includes the following steps: oxidizing the crystal silicon in a dry oxygen atmosphere at a temperature of 800 to 1000 ° C for a time of 20 ⁇ 40 minutes, and then annealed at the same temperature in a nitrogen atmosphere, annealing time is 5 to 20 minutes;
- Step 106 preparing a metal back electrode on the back side of the crystalline silicon
- the metal back electrode in this embodiment is an A1 electrode, and may also be a Cu electrode, an Ag electrode, an Au electrode or a Pt electrode;
- a metal A1 having a thickness of 10 to 15 ⁇ m is deposited on the back side of the crystalline silicon; After annealing in a protective atmosphere at 350 ⁇ 450 °C for 20 ⁇ 40 minutes, forming a metal A1 back electrode with ohmic contact; in this step, annealing at 350 ⁇ 450 °C instead of high temperature sintering process can avoid induced by high temperature sintering process.
- the damage of the stress on the crystalline silicon is beneficial to reduce the thickness of the crystalline silicon;
- Step 107 preparing a metal gate electrode on the passivation layer
- the metal gate electrode in this embodiment is an Ag electrode, and may also be a Cu electrode, an Ag electrode, an Au electrode or a Pt electrode;
- Screen printing is used to print silver paste on the surface of the passivation layer by a special printer and template to form an Ag gate electrode.
- the gate electrode has a thickness of 2 to 10 ⁇ m and the gate electrode has a width of 30 to 150 ⁇ m. , the huge is 2 ⁇ 3 mm.
- the crystalline silicon may be a single crystal silicon or a polycrystalline silicon; the surface of the crystalline silicon may be a plane, a curved surface or a composite surface composed of a plane and a curved surface.
- the invention can be implemented. In step 101 of the above embodiment, it may further comprise texturing the crystalline silicon.
- the preparation method of the shallow junction solar cell provided by the embodiment is unique and easy to grasp, and has the characteristics of convenient operation, repeatability and reliability, and has a clear industrialization prospect.
Abstract
A shallow junction solar battery and its manufacturing method are provided, which belongs to the manufacturing technique of solar battery device. The shallow junction solar battery includes metal grid electrodes(5), a passivation layer(4), a crystal silicon(2), and metal back electrodes(1). The metal back electrodes(1) are on the back surface of the crystal silicon(2), the passivation layer(4) is on the crystal silicon(2), and the metal grid electrodes(5) are on the passivation layer(4). The crystal silicon(2) has a PN junction, whose depth is 10-200nm. The manufacturing method includes: pretreating the crystal silicon(2), forming the PN junction on the crystal silicon(2) by plasma immersion ion implantation process, and passivating the PN junction so as to form the passivation layer(4), and forming the metal back electrodes(1) and the metal grid electrodes(5) on the back surface of the crystal silicon(2) and on the passivation layer(4), respectively. The shallow solar battery can shorten the carrier transport path, so as to increase the photoelectric conversion efficiency, and the method is simple and controllable.
Description
一种浅结太阳能电池及其制备方法 Shallow junction solar cell and preparation method thereof
技术领域 Technical field
本发明涉及太阳能电池器件制造技术领域， 特别涉及一种浅结太阳能电池 及其制备方法。 背景技术 The present invention relates to the field of solar cell device manufacturing technology, and in particular, to a shallow junction solar cell and a method of fabricating the same. Background technique
面对当前的能源危机和化石类燃料的大量耗用所引发的温室效应、 酸雨等 环境问题， 迫切需要在世界范围内开发和有效利用新能源。 太阳能是一种取材 方便、 绿色环保的可再生能源。 在不远的将来， 太阳能将成为世界能源供应的 主体。 太阳能电池作为一种清洁高效的绿色可持续能源， 将为太阳能的有效利 用提供更广阔的前景， 但是目前的太阳能电池的光电转换效率相当低， 一般都 在 20%以下， 因此， 如何提高太阳能电池光电转换效率是当前技术人员需要解 决的难题之一。 In the face of the current energy crisis and environmental problems such as the greenhouse effect and acid rain caused by the large consumption of fossil fuels, there is an urgent need to develop and effectively utilize new energy sources worldwide. Solar energy is a renewable energy source that is convenient and green. In the near future, solar energy will become the mainstay of the world's energy supply. As a clean and efficient green sustainable energy source, solar cells will provide a broader prospect for the effective use of solar energy. However, the photoelectric conversion efficiency of current solar cells is quite low, generally below 20%. Therefore, how to improve solar cells Photoelectric conversion efficiency is one of the problems that current technicians need to solve.
常规制备的太阳能电池是用普通扩散法制造的注入硅太阳能电池， 其结深 约 0.5μηι, 扩散电阻 R约为 左右。 例如， 以 η+ρ结为例， η+磷扩散杂质分 布不是典型的余误差函数分布， 在表面附近具有几乎恒定的浓度， 其数值取决 于在磷扩散温度下磷在硅中的固溶度， 因而， 其表面是重掺杂层。 由于重掺杂 效应以及严重的晶格缺陷和畸变， 此重掺杂层成为载流子的复合中心， 使得该 层少子寿命极低， 所以称该层为 "复合层"。 由于"复合层 "的存在， 光生载流子可 能会提前在此复合， 从而无法到达收集电极， 因而使太阳能电池的光电转换效 率大大降低。 通常一次扩散的 ΡΝ结越深， 则"复合层"越厚， 光生载流子复合越 严重， 太阳能电池的光电转换效率越低。
发明内容 A conventionally prepared solar cell is an implanted silicon solar cell fabricated by a conventional diffusion method, having a junction depth of about 0.5 μm and a diffusion resistance R of about right and left. For example, taking the η + ρ junction as an example, the η + phosphorus diffusion impurity distribution is not a typical residual error function distribution, and has an almost constant concentration near the surface, the value of which depends on the solid solubility of phosphorus in silicon at the phosphorus diffusion temperature. Thus, its surface is a heavily doped layer. Due to the heavy doping effect and severe lattice defects and distortion, the heavily doped layer becomes the recombination center of the carrier, making the layer have a very low lifetime, so the layer is called a "composite layer". Due to the existence of the "composite layer", photo-generated carriers may be recombined here in advance, so that the collecting electrode cannot be reached, thereby greatly reducing the photoelectric conversion efficiency of the solar cell. Generally, the deeper the tantalum knot is, the thicker the "composite layer" is, and the more serious the photo-generated carrier recombination is, the lower the photoelectric conversion efficiency of the solar cell is. Summary of the invention
本发明需要解决的技术问题是提供一种浅结太阳能电池及其制备方法， 利 用此方法制备的浅结太阳能电池， 能够缩短载流子的传输路径， 减小 "复合层" 的厚度， 有效地防止载流子在 n+层或 p+层表面附近的复合， 提高光生载流子的 收集几率， 使光电转换效率提高。 The technical problem to be solved by the present invention is to provide a shallow junction solar cell and a preparation method thereof, and the shallow junction solar cell prepared by the method can shorten the carrier transmission path and reduce the thickness of the "composite layer", effectively Preventing the recombination of carriers near the surface of the n + layer or the p + layer, increasing the probability of collection of photogenerated carriers, and improving the photoelectric conversion efficiency.
为了解决上述技术问题， 本发明提供了一种浅结太阳能电池， 所述浅结太 阳能电池包括金属栅电极、 钝化层、 晶硅和金属背电极； 所述金属背电极位于 所述晶硅的背面， 所述钝化层位于所述晶硅的上面， 所述金属栅电极位于所述 钝化层的上面， 所述晶硅包括有 PN结， 所述 PN结的深度为 10纳米到 200纳 米。 In order to solve the above technical problem, the present invention provides a shallow junction solar cell including a metal gate electrode, a passivation layer, a crystalline silicon and a metal back electrode; the metal back electrode is located in the crystalline silicon a back surface, the passivation layer is located above the crystalline silicon, the metal gate electrode is located above the passivation layer, the crystalline silicon includes a PN junction, and the PN junction has a depth of 10 nm to 200 nm .
进一步地， 本发明具有如下特点： 所述晶硅表面为平面或曲面， 所述 PN结 的界面为与所述晶硅表面相类似的平面或曲面。 Further, the present invention has the following features: the surface of the crystalline silicon is a plane or a curved surface, and the interface of the PN junction is a plane or a curved surface similar to the surface of the crystalline silicon.
可选择地， 本发明具有如下特点： 所述晶硅表面为由平面和曲面构成的复 合面， 所述 PN结的界面为与所述晶硅表面相类似的复合面。 Alternatively, the present invention has the following features: The surface of the crystalline silicon is a composite surface composed of a plane and a curved surface, and the interface of the PN junction is a composite surface similar to the surface of the crystalline silicon.
进一步地， 本发明还具有如下特点： 所述晶硅为单晶硅或多晶硅， 所述金 属背电极由铝、 铜、 银、 金或铂制成， 所述金属栅电极由铝、 铜、 银、 金或铂 制成。 Further, the present invention has the following features: the crystalline silicon is single crystal silicon or polycrystalline silicon, the metal back electrode is made of aluminum, copper, silver, gold or platinum, and the metal gate electrode is made of aluminum, copper, silver. Made of gold or platinum.
进一步地，本发明还具有如下特点：所述金属背电极的厚度为 10 ~ 15微米； 所述晶硅的厚度为 100 ~ 300微米； 所述钝化层的厚度为 50 ~ 200纳米； 所述金 属栅电极的厚度为 2 ~ 10微米， 所述金属栅电极的宽度为 30 ~ 150微米， 间距 为 2 ~ 3毫米。 Further, the present invention has the following features: the thickness of the metal back electrode is 10 to 15 μm; the thickness of the crystalline silicon is 100 to 300 μm; and the thickness of the passivation layer is 50 to 200 nm; The metal gate electrode has a thickness of 2 to 10 μm, and the metal gate electrode has a width of 30 to 150 μm and a pitch of 2 to 3 mm.
根据本发明的另一个方面， 本发明还提供了一种浅结太阳能电池的制备方 法， 所述方法包括：
对晶硅进行预处理； According to another aspect of the present invention, the present invention also provides a method of fabricating a shallow junction solar cell, the method comprising: Pretreatment of crystalline silicon;
利用等离子体浸没离子注入工艺， 在所述晶硅上制备 PN结， 并对所述 PN 结进行钝化处理， 形成钝化层； Using a plasma immersion ion implantation process, preparing a PN junction on the crystalline silicon, and passivating the PN junction to form a passivation layer;
分别在所述晶硅的背面和所述钝化层上制备金属背电极和金属栅电极。 进一步地， 本发明还具有如下特点， 所述对晶硅进行预处理的步骤包括对 晶硅进行清洗、 去损伤或制绒。 A metal back electrode and a metal gate electrode are respectively formed on the back surface of the crystalline silicon and the passivation layer. Further, the present invention has the following features, the step of pretreating the crystalline silicon includes cleaning, de-damaging or texturing the crystalline silicon.
进一步地， 本发明还具有如下特点， 所述利用等离子体浸没离子注入工艺， 在所述晶硅上制备 PN结的步骤具体包括： Further, the present invention has the following features: the step of preparing a PN junction on the crystalline silicon by using a plasma immersion ion implantation process specifically includes:
将所述晶硅放置于等离子体浸没离子注入设备的注入腔室内； Depositing the crystalline silicon in an implantation chamber of a plasma immersion ion implantation apparatus;
调整所述等离子体浸没离子注入设备的工艺参数进入预先设置的数值范 围； Adjusting the process parameters of the plasma immersion ion implantation apparatus into a preset numerical range;
所述等离子体浸没离子注入设备产生等离子体， 所述等离子体中的掺杂离 子注入至所述晶硅内。 The plasma immersion ion implantation apparatus generates a plasma into which doped ions in the plasma are implanted.
进一步地， 本发明还具有如下特点： 所述将所述晶硅放置于等离子体浸没 离子注入设备的注入腔室内的步骤还包括将所述晶硅与可施加偏置电压的电源 电气连接； 所述工艺参数包括所述注入腔室的本底压强和工作压强， 注入至所 述注入腔室的混合气体的流量、 组成成分和体积比， 等离子体电源的输出功率、 偏置电压以及等离子体注入时间； 所述本底压强范围为 l(T3Pa ~ lOOPa, 所述工 作压强范围为 0.1Pa ~ 50Pa; 所述混合气体由含有 P、 As或 B元素的气体组成， 所述含有 P或 As元素的气体包括 B2H6、 B(OCH3)3、 PH3或 AsH3。 Further, the present invention has the following features: the step of placing the crystalline silicon in an implantation chamber of the plasma immersion ion implantation apparatus further comprises electrically connecting the crystalline silicon to a power source to which a bias voltage can be applied; The process parameters include the background pressure and the working pressure of the injection chamber, the flow rate, composition and volume ratio of the mixed gas injected into the injection chamber, the output power of the plasma power source, the bias voltage, and the plasma injection. The background pressure range is 1 (T 3 Pa ~ lOOPa, the working pressure range is 0.1 Pa ~ 50 Pa; the mixed gas is composed of a gas containing P, As or B elements, the containing P or As The gas of the element includes B 2 H 6 , B(OCH 3 ) 3 , PH 3 or AsH 3 .
进一步地， 本发明还具有如下特点： 通过调节所述偏置电压、 所述等离子 体注入时间、 所述混合气体的流量及组成比例或所述等离子体电源的输出功率 来改变所述 PN结的深度。
进一步地， 本发明还具有如下特点， 在所述晶硅上制备 PN结和对所述 PN 结进行钝化处理的步骤之间还包括： Further, the present invention has the following features: changing the PN junction by adjusting the bias voltage, the plasma injection time, the flow rate and composition ratio of the mixed gas, or the output power of the plasma power source depth. Further, the present invention further has the following features. The step of preparing a PN junction on the crystalline silicon and performing a passivation treatment on the PN junction further includes:
对所述 PN结进行热处理； Heat treating the PN junction;
对热处理后的晶硅进行刻蚀去边处理。 The heat treated crystal silicon is etched and edge-treated.
进一步地， 本发明还具有如下特点： 所述钝化处理采用表面氧化生长 Si02 钝化方式进行处理， 或采用 PECVD生长 SiNx或 Si02钝化方式进行处理， 或采 用等离子体浸没注入工艺向所述晶硅中注入 0或 N后， 形成 Si02或 SiNx。 Further, the present invention has the following features: the passivation treatment is performed by a surface oxidation growth SiO 2 passivation method, or a PECVD grown SiNx or Si0 2 passivation method is used, or a plasma immersion implantation process is used. After injecting 0 or N into the crystalline silicon, Si0 2 or SiNx is formed.
与现有技术相比， 本发明技术方案产生的有益效果如下： Compared with the prior art, the beneficial effects produced by the technical solution of the present invention are as follows:
1、本发明提供的浅结太阳能电池的结构筒单，能够在晶硅上形成很浅的 PN 结， 减少了 "复合层"的厚度， 缩短了载流子的传输路径； 1. The structure of the shallow junction solar cell provided by the invention can form a very shallow PN junction on the crystalline silicon, which reduces the thickness of the "composite layer" and shortens the carrier transmission path;
2、 本发明利用等离子体浸没离子注入制备 PN结， 可在任意形状的界面上 制得结深可控 U艮小的 PN结， 这样有利于防止载流子在 n+层或 p+层表面附近 的复合， 提高了光生载流子的收集几率， 提高了转换效率； 2. The invention utilizes plasma immersion ion implantation to prepare a PN junction, and can form a PN junction with a small junction-controllable U艮 at an interface of any shape, which is beneficial to prevent carriers from being on the surface of the n + layer or the p + layer. The nearby compounding increases the probability of collection of photogenerated carriers and improves conversion efficiency;
3、 由于本发明浅结太阳能电池中的 PN结的深度浅， 所以 PN结的界面形 状可更加接近于晶硅的表面形状； 即当晶硅的表面形状为曲面时， PN结的界面 形状为与晶硅表面形状更加接近的曲面， 克服了现有技术中因结深大而造成 PN 结的界面面积小于晶硅的表面面积的问题（当晶硅表面为曲面时）， 因此， 采用 本发明可增大 PN结的面积， 这样有利于光生载流子的产生和分离，提高了转换 效率； 3. Since the depth of the PN junction in the shallow junction solar cell of the present invention is shallow, the interface shape of the PN junction can be closer to the surface shape of the crystalline silicon; that is, when the surface shape of the crystalline silicon is a curved surface, the interface shape of the PN junction is The curved surface closer to the surface shape of the crystalline silicon overcomes the problem that the interface area of the PN junction is smaller than the surface area of the crystalline silicon due to the deep junction in the prior art (when the surface of the crystalline silicon is curved), therefore, the present invention is adopted. The area of the PN junction can be increased, which is advantageous for the generation and separation of photogenerated carriers and improves the conversion efficiency;
4、 本发明提供的浅结太阳能电池的制备方法筒单独特、 易于掌握， 具有操 作方便、 重复可靠的特点， 具有明确的产业化前景。
附图说明 4. The preparation method of the shallow junction solar cell provided by the invention is unique and easy to grasp, has the characteristics of convenient operation, repeated and reliable, and has a clear industrialization prospect. DRAWINGS
图 1是本发明浅结太阳能电池的第一种实施方式的结构示意图； 1 is a schematic structural view of a first embodiment of a shallow junction solar cell of the present invention;
图 2是本发明浅结太阳能电池的第二种实施方式的结构示意图； 2 is a schematic structural view of a second embodiment of the shallow junction solar cell of the present invention;
图 3是本发明浅结太阳能电池的第三种实施方式的结构示意图； 3 is a schematic structural view of a third embodiment of the shallow junction solar cell of the present invention;
图 4是本发明浅结太阳能电池的第四种实施方式的结构示意图； 4 is a schematic structural view of a fourth embodiment of the shallow junction solar cell of the present invention;
图 5是本发明实施方式提供的浅结太阳能电池的制备方法流程图。 具体实施方式 FIG. 5 is a flow chart of a method for preparing a shallow junction solar cell according to an embodiment of the present invention. detailed description
下面结合附图和实施方式， 对本发明技术方案作进一步描述。 The technical solutions of the present invention are further described below in conjunction with the accompanying drawings and embodiments.
参见图 1 , 本发明的第一种实施方式提供了一种浅结太阳能电池， 包括金属 背电极 1、 晶硅 2、 钝化层 4和金属栅电极 5。 Referring to Fig. 1, a first embodiment of the present invention provides a shallow junction solar cell comprising a metal back electrode 1, a crystalline silicon 2, a passivation layer 4, and a metal gate electrode 5.
金属背电极 1位于晶硅 2的背面， 该金属背电极可由铝 （Al )、 铜 （Cu )、 银（Ag )、 金（Au )或铂（Pt )等金属制成， 也可由多种金属材料混合制成， 而 晶硅 2可为 p型单晶硅、 p型多晶硅、 n型单晶硅或 n型多晶硅。 The metal back electrode 1 is located on the back surface of the crystalline silicon 2, and the metal back electrode may be made of metal such as aluminum (Al), copper (Cu), silver (Ag), gold (Au) or platinum (Pt), or may be made of a plurality of metals. The material is mixed, and the crystalline silicon 2 may be p-type single crystal silicon, p-type polycrystalline silicon, n-type single crystal silicon or n-type polycrystalline silicon.
PN结 3位于晶硅 2内， 用虚线表示结区， 结区中的实线表示 PN结的界面。 The PN junction 3 is located in the crystalline silicon 2, and the junction region is indicated by a broken line, and the solid line in the junction region indicates the interface of the PN junction.
PN结 3可为利用等离子体浸没离子注入工艺对晶硅（包括单晶硅和多晶硅）进 行掺杂而形成， 掺杂类型与晶硅的掺杂类型相反， 例如： 若晶硅为 p型， 则掺 入 n型杂质； 若晶硅为 n型， 则掺入 p型杂质。 PN结 3的深度为 10纳米到 200 纳米。 在本实施方式中， PN结 3的界面为平面。 The PN junction 3 may be formed by doping a crystalline silicon (including single crystal silicon and polycrystalline silicon) by a plasma immersion ion implantation process, and the doping type is opposite to that of the crystalline silicon, for example: if the crystalline silicon is p-type, Then, an n-type impurity is doped; if the crystalline silicon is an n-type, a p-type impurity is doped. The PN junction 3 has a depth of 10 nm to 200 nm. In the present embodiment, the interface of the PN junction 3 is a flat surface.
钝化层 4位于晶硅 2上， 钝化层可通过采用表面氧化生长 Si02钝化方式形 成， 也可通过采用 PECVD生长 SiNx或 Si02钝化方式形成， 或者采用等离子体 浸没注入工艺向晶硅中注入 0或 N后， 形成 Si02或 SiNx。 The passivation layer 4 is located on the crystalline silicon 2, and the passivation layer can be formed by surface oxidation by SiO 2 passivation, or by SiCVD or Si0 2 passivation by PECVD, or by plasma immersion implantation. After injecting 0 or N into the silicon, Si0 2 or SiNx is formed.
金属栅电极 5位于钝化层 4上， 该金属栅电极可由铝（Al )、 铜 （Cu )、 银
( Ag )、 金（Au )或铂（Pt )等金属制成， 也可由多种金属材料混合制成。 The metal gate electrode 5 is located on the passivation layer 4, which may be aluminum (Al), copper (Cu), silver Made of metal such as (Ag), gold (Au) or platinum (Pt), or a mixture of various metal materials.
其中， 金属背电极 1 的厚度为 1 ~ 100微米， 优选为 10 ~ 15微米； 晶硅 2 的厚度为 10 ~ 1000 米， 优选为 100 ~ 300 米； 钝化层 4的厚度为 1 ~ 500纳 米， 优选为 50 ~ 200纳米； 金属栅电极 5的厚度为 1 ~ 50微米， 优选为 2 ~ 10 微米， 金属栅电极的宽度为 10 ~ 1000微米， 优选为 30 ~ 150微米， 间距为 1 ~ 10毫米， 优选为 2 ~ 3毫米。 The thickness of the metal back electrode 1 is 1 to 100 micrometers, preferably 10 to 15 micrometers; the thickness of the crystalline silicon 2 is 10 to 1000 meters, preferably 100 to 300 meters; and the thickness of the passivation layer 4 is 1 to 500 nanometers. Preferably, the thickness of the metal gate electrode 5 is 1 to 50 μm, preferably 2 to 10 μm, and the width of the metal gate electrode is 10 to 1000 μm, preferably 30 to 150 μm, and the pitch is 1 to 10 Millimeters, preferably 2 to 3 mm.
本实施方式提供的浅结太阳能电池的结构筒单，在此太阳能电池中的 PN结 为浅结， 结深小于 200纳米， 使得"复合层 "厚度减小， 防止载流子在 n+层或 p+ 层表面附近的复合， 提高了光生载流子的收集几率， 提高了转换效率。 The structure of the shallow junction solar cell provided by the embodiment provides a shallow junction of the PN junction in the solar cell, and the junction depth is less than 200 nm, so that the thickness of the "composite layer" is reduced, and the carrier is prevented from being in the n + layer or The recombination near the surface of the p + layer increases the probability of collection of photogenerated carriers and improves conversion efficiency.
此外， PN结的深度越浅， PN结的界面形状可更加接近于晶硅的表面形状。 当晶硅的表面形状为孔状、 针状或类企鹅状等曲面或复合面 （这种表面的晶硅 具有较高的光吸收特性）时， 利用现有技术制备 PN结， 只能制备结深约 0.5μηι 的 PN结， 这一深度可能会造成 PN结的界面面积与晶硅的表面面积不一致。 在 这种情况下， 结深大的 PN结的界面面积通常要小于晶硅的表面面积。 因此， 采 用本发明的浅结结构， 可增大 PN结的面积， 有利于光生载流子的产生和分离， 提高转换效率。 In addition, the shallower the depth of the PN junction, the closer the interface shape of the PN junction can be to the surface shape of the crystalline silicon. When the surface shape of the crystalline silicon is a curved surface, a needle-like or a penguin-like curved surface or a composite surface (the crystalline silicon of the surface has a high light absorption property), the PN junction can be prepared by the prior art, and only the junction can be prepared. A PN junction with a depth of about 0.5 μm may cause the interface area of the PN junction to be inconsistent with the surface area of the crystalline silicon. In this case, the interface area of the deep PN junction is usually smaller than the surface area of the crystalline silicon. Therefore, the shallow junction structure of the present invention can increase the area of the PN junction, facilitate the generation and separation of photogenerated carriers, and improve the conversion efficiency.
图 2是本发明浅结太阳能电池的第二种实施方式的结构示意图， 与图 1 的 区别在于第二种实施方式的 PN结 3的界面为曲面， 此曲面呈凹凸形。 图 3是本 发明浅结太阳能电池的第三种实施方式的结构示意图， 与图 1 的区别在于第三 种实施方式的 PN结 3的界面为由平面和曲面构成的复合面。图 4是本发明浅结 太阳能电池的第四种实施方式的结构示意图， 与图 1 的区别在于第四种实施方 式的 PN结 3的界面为由平面和曲面构成的另一种复合面。 除此之外， 本发明浅 结太阳能电池的 PN结 3的界面还可以为由平面、 斜面和 /或曲面构成的任意形
状。 在这些例子中， PN结的界面形状都与晶硅的表面形状相类似或相同， 所谓 PN结的界面形状与晶硅表面形状相类似是指 PN结界面与晶硅表面基本平行， PN结的界面的线性度、 曲率半径或弯曲程度与晶硅表面大体相同。 2 is a schematic structural view of a second embodiment of the shallow junction solar cell of the present invention. The difference from FIG. 1 is that the interface of the PN junction 3 of the second embodiment is a curved surface, and the curved surface has a concavo-convex shape. 3 is a schematic structural view of a third embodiment of the shallow junction solar cell of the present invention, which differs from FIG. 1 in that the interface of the PN junction 3 of the third embodiment is a composite surface composed of a plane and a curved surface. 4 is a schematic view showing the structure of a fourth embodiment of the shallow junction solar cell of the present invention, which is different from that of FIG. 1 in that the interface of the PN junction 3 of the fourth embodiment is another composite surface composed of a plane and a curved surface. In addition, the interface of the PN junction 3 of the shallow junction solar cell of the present invention may also be any shape composed of planes, bevels, and/or curved surfaces. Shape. In these examples, the interface shape of the PN junction is similar or identical to the surface shape of the crystalline silicon. The interface shape of the so-called PN junction is similar to the surface shape of the crystalline silicon, meaning that the PN junction interface is substantially parallel to the surface of the crystalline silicon, and the PN junction The linearity, radius of curvature, or degree of curvature of the interface is substantially the same as the surface of the crystalline silicon.
参见图 5, 本发明实施方式还提供了一种浅结太阳能电池的制备方法， 该方 法包括以下步骤： Referring to FIG. 5, an embodiment of the present invention further provides a method for preparing a shallow junction solar cell, the method comprising the following steps:
步骤 101 : 对晶硅进行清洗和去损伤处理； Step 101: cleaning and de-damaging the crystalline silicon;
首先， 把晶硅浸入到氢氟酸溶液中 1~10分钟， 去离子水清洗； 然后， 把清 洗后的晶硅浸入到浓度为 1%~30%的氢氧化钠溶液中 1~10分钟， 温度为 50 ~ 80°C , 去除晶硅表面的损伤层； 最后， 用去离子水清洗晶硅， 并用氮气吹干； 步骤 102: 利用等离子体浸没离子注入工艺，对晶硅进行掺杂， 制备 PN结； 在本实施方式中， 等离子体浸没离子注入所使用的设备， 通常也被称为等 离子体浸没离子注入机， 其一般地包括注入腔室和等离子体源； 在注入腔室内， 设有其上可放置样品的样品台， 在与样品台相对的一侧， 设有等离子体源； 等离子体源包括抽真空***， 其可将注入腔室抽真空至预先设置的本底压 强范围； 供气***， 其可向注入腔室充入所需的气体， 并且能够按照一定的控 制规则来调整气体的各种参数， 例如气体的流量、 抽取速度、 气体成分比例和 浓度等参数， 当气体充入注入腔室之后， 可使得注入腔室的压强进入预先设置 的工作压强范围； 以及等离子体电源， 其可为射频电源、 微波电源或直流电源， 这些电源还可以脉沖形式供电， 并且这些电源的频率可为固定频率或可变频率； 此外， 该设备还包括可施加偏置电压的电源， 该可施加偏置电压的电源与注入 腔室内的样品台电气连接， 可施加偏置电压的电源类型与等离子体电源相似， 可为射频电源、 微波电源或直流电源， 这些电源还可以脉沖形式供电， 还可以 是这些电源的任意组合， 进而向样品台提供由多种偏置电压组成的偏置电压；
在本实施方式中， 等离子体浸没离子注入工艺为： 将晶硅放置于注入腔室 内； 调整等离子体浸没离子注入机的工艺参数进入预先设置的数值范围； 等离 子体浸没离子注入机产生等离子体， 该等离子体中的掺杂离子注入至晶硅内， 完成对晶硅的掺杂； 掺杂离子的类型与晶硅的原有掺杂类型相反， 例如： 若晶 硅为 P型， 则掺入 N型离子； 若晶硅为 N型， 则掺入 P型离子， 由此形成 PN 结； 所需形成的 PN结的深度可通过调整相应的工艺参数来改变， 即通过调节偏 置电压、 等离子体注入时间、 混合气体的流量和组成比例或等离子体电源的输 出功率， 来改变 PN结的深度； 其中， 改变偏置电压对 PN结的深度有较大的影 响； 所制成的 PN结的界面形状与晶硅的表面形状相类似， 所谓 PN结的界面形 状与晶硅表面形状相类似是指 PN结界面与晶硅表面基本平行， PN结的界面的 线性度、 曲率半径或弯曲程度与晶硅表面大体相同； First, immerse the crystalline silicon in a hydrofluoric acid solution for 1 to 10 minutes, and wash it with deionized water. Then, immerse the cleaned silicon crystal in a sodium hydroxide solution with a concentration of 1% to 30% for 1 to 10 minutes. The temperature is 50 ~ 80 ° C, the damaged layer on the surface of the crystalline silicon is removed; finally, the crystalline silicon is washed with deionized water and dried with nitrogen; Step 102: doping the crystalline silicon by plasma immersion ion implantation process, preparing PN junction; in the present embodiment, the apparatus used for plasma immersion ion implantation, also commonly referred to as a plasma immersion ion implanter, generally includes an implantation chamber and a plasma source; a sample stage on which a sample can be placed, on a side opposite to the sample stage, a plasma source is provided; the plasma source includes an evacuation system that can evacuate the injection chamber to a preset background pressure range; a gas system that fills the injection chamber with the required gas and can adjust various parameters of the gas according to certain control rules, such as gas flow rate, extraction speed, gas composition ratio And the concentration and other parameters, when the gas is charged into the injection chamber, the pressure of the injection chamber can be brought into a preset working pressure range; and the plasma power source can be a radio frequency power source, a microwave power source or a DC power source, and the power source can also be The power is supplied in a pulse form, and the frequency of the power sources may be a fixed frequency or a variable frequency; further, the device further includes a power source capable of applying a bias voltage, and the power source capable of applying the bias voltage is electrically connected to the sample stage in the injection chamber, The type of power supply to which the bias voltage can be applied is similar to that of a plasma power source. It can be a radio frequency power supply, a microwave power supply, or a direct current power supply. These power supplies can also be supplied in pulses, or any combination of these power supplies, and thus can be supplied to the sample stage. a bias voltage composed of a bias voltage; In this embodiment, the plasma immersion ion implantation process is: placing crystalline silicon in the implantation chamber; adjusting the process parameters of the plasma immersion ion implanter into a preset numerical range; the plasma immersion ion implanter generates a plasma, The doping ions in the plasma are implanted into the crystalline silicon to complete the doping of the crystalline silicon; the type of the doping ions is opposite to the original doping type of the crystalline silicon, for example: if the crystalline silicon is P-type, the incorporation is N-type ion; if the crystalline silicon is N-type, P-type ions are doped, thereby forming a PN junction; the depth of the PN junction to be formed can be changed by adjusting the corresponding process parameters, that is, by adjusting the bias voltage, plasma The body injection time, the flow rate and composition ratio of the mixed gas or the output power of the plasma power source to change the depth of the PN junction; wherein, changing the bias voltage has a greater influence on the depth of the PN junction; The shape of the interface is similar to the surface shape of crystalline silicon. The interface shape of the so-called PN junction is similar to the surface shape of the crystalline silicon, which means that the interface of the PN junction is substantially parallel to the surface of the crystalline silicon. The linearity of the interface, the radius of curvature or a curved surface of substantially the same degree of crystalline silicon;
所需调整的工艺参数包括注入腔室的本底压强和工作压强， 注入气体的流 量， 抽取气体的速度， 混合气体组成成分、 组成比例和浓度， 等离子体电源的 输出功率和频率， 可施加偏置电压的电源所施加的偏置电压， 如果采用脉沖形 式， 还包括脉宽、 占空比和频率； The process parameters to be adjusted include the background pressure and working pressure of the injection chamber, the flow rate of the injected gas, the velocity of the extracted gas, the composition of the mixed gas, the composition ratio and concentration, the output power and frequency of the plasma power source, and the bias can be applied. The bias voltage applied by the voltage supply, if pulsed, includes pulse width, duty cycle, and frequency;
注入腔室的本底压强范围可为 l(T7Pa ~ lOOOPa, 优选地可为 l(T3Pa ~ lOOPa; 注入腔室的工作压强范围可为 10_3Pa ~ lOOOPa, 优选为 O.OlPa ~ lOOPa, 更为优 选地可为 0.1Pa ~ 50Pa; The base pressure range may be injected into the chamber l (T 7 Pa ~ lOOOPa, may be preferably l (T 3 Pa ~ lOOPa; working pressure range may be injected into the chamber 10_ 3 Pa ~ lOOOPa, preferably O.OlPa ~ lOOPa, more preferably 0.1Pa ~ 50Pa;
注入混合气体可由含有？、 As或 B元素的气体组成， 含有 B、 P或 As元素 的气体包括 B2H6、 B(OCH3)3、 PH3或 AsH3; 由这些注入气体所产生的相应掺杂 离子包括 B离子、 P离子或 As离子； What can be injected into the mixed gas? The gas composition of the As, B or B element, the gas containing the B, P or As element includes B 2 H 6 , B(OCH 3 ) 3 , PH 3 or AsH 3 ; the corresponding doping ions generated by these injection gases include B Ion, P ion or As ion;
等离子体电源的输出功率为 1 ~ 100000W, 优选为 10 ~ 50000W, 更为优选 地可为 100 ~ 800W; 所施加偏置电压为 -100000 ~ 100000V, 优选为 -50000 ~
50000V, 更为优选地可为 -500 ~ 30000 V; 脉宽为 1 us ~ Is, 优选为 lus~0.1s, 更为优选地可为 lus~lms; 占空比为 1%~99%, 优选为 10%~90%, 更为优选 地可为 20% ~ 80%,等离子体电源的频率为直流 ~ 10GHz,优选为 1MHz ~ 5GHz, 更为优选地可为 13.56MHz ~ 5GHz; 可施加偏置电压的电源的频率为直流〜 10GHz; 等离子体注入时间为 10 ~ 30分钟； The output power of the plasma power source is 1 to 100000 W, preferably 10 to 50000 W, and more preferably 100 to 800 W; the applied bias voltage is -100,000 to 100,000 V, preferably -50000 50000V, more preferably -500 ~ 30000 V; pulse width 1us ~ Is, preferably lus~0.1s, more preferably lus~lms; duty ratio 1%~99%, preferred It is 10% to 90%, more preferably 20% to 80%, and the frequency of the plasma power source is DC ~ 10 GHz, preferably 1 MHz ~ 5 GHz, more preferably 13.56 MHz ~ 5 GHz; bias can be applied The frequency of the voltage source is DC ~ 10 GHz; the plasma injection time is 10 ~ 30 minutes;
步骤 103: 对掺杂进行热处理； Step 103: heat treating the doping;
把晶硅放入退火炉中进行快速热退火处理， 气氛为保护气氛， 可以为 N2、 Ar等， 温度为 800~ 1300°C; The crystalline silicon is placed in an annealing furnace for rapid thermal annealing, and the atmosphere is a protective atmosphere, which may be N 2 , Ar, etc., at a temperature of 800 to 1300 ° C;
步骤 104: 对晶硅进行刻蚀去边处理； Step 104: etching and removing the crystalline silicon;
利用 CF4气体， 采用高频辉光放电反应， 使反应气体激活生成活性粒子， 这些活性粒子扩散到晶硅需要刻蚀的部位， 在该部位处与被刻蚀材料发生化学 反应， 生成易挥发性物质而被去除； Using CF 4 gas, a high-frequency glow discharge reaction is used to activate the reaction gas to form active particles. These active particles diffuse to the portion where the crystalline silicon needs to be etched, and chemically react with the material to be etched at the site to form a volatile substance. And removed;
步骤 105: 对 PN结进行钝化处理， 形成钝化层； Step 105: Passivating the PN junction to form a passivation layer;
在实际应用中， 可以采用表面氧化生长 Si02钝化方式进行处理， 也可以采 用 PECVD生长 SiNx或 Si02钝化方式进行处理， 还可以采用等离子体浸没注入 工艺向晶硅中注入 0或 N后， 形成 Si02或 SiNx; 本实施方式采用表面氧化生 长 Si02钝化方式进行处理， 包括如下步骤： 将晶硅放入干氧气氛中进行氧化， 温度为 800 ~ 1000 °C , 时间为 20 ~ 40分钟， 然后在氮气气氛中同样温度下进行 退火， 退火时间为 5~20分钟； In practical applications, surface oxidation growth Si0 2 passivation can be used for treatment, PECVD growth SiN x or Si0 2 passivation can also be used for processing, or plasma immersion implantation process can be used to implant 0 or N into crystalline silicon. Thereafter, SiO 2 or SiNx is formed; the embodiment is treated by surface oxidation growth SiO 2 passivation, and includes the following steps: oxidizing the crystal silicon in a dry oxygen atmosphere at a temperature of 800 to 1000 ° C for a time of 20 ~ 40 minutes, and then annealed at the same temperature in a nitrogen atmosphere, annealing time is 5 to 20 minutes;
步骤 106: 在晶硅的背面制备金属背电极； Step 106: preparing a metal back electrode on the back side of the crystalline silicon;
本实施例中的金属背电极为 A1电极， 还可以为 Cu电极、 Ag电极、 Au电 极或 Pt电极； The metal back electrode in this embodiment is an A1 electrode, and may also be a Cu electrode, an Ag electrode, an Au electrode or a Pt electrode;
以高纯铝作为蒸发源， 在晶硅的背面沉积厚度为 10~15微米的金属 A1; 然
后在保护气氛下， 350 ~ 450°C退火 20 ~ 40分钟， 形成欧姆接触的金属 A1背电 极； 在本步骤中， 采用 350 ~ 450°C退火替代高温烧结过程， 可避免高温烧结过 程诱导的应力对晶硅的损伤， 有利于降低晶硅的厚度； Using high-purity aluminum as an evaporation source, a metal A1 having a thickness of 10 to 15 μm is deposited on the back side of the crystalline silicon; After annealing in a protective atmosphere at 350 ~ 450 °C for 20 ~ 40 minutes, forming a metal A1 back electrode with ohmic contact; in this step, annealing at 350 ~ 450 °C instead of high temperature sintering process can avoid induced by high temperature sintering process. The damage of the stress on the crystalline silicon is beneficial to reduce the thickness of the crystalline silicon;
步骤 107: 在钝化层上制备金属栅电极； Step 107: preparing a metal gate electrode on the passivation layer;
本实施例中的金属栅电极为 Ag电极， 还可以为 Cu电极、 Ag电极、 Au电 极或 Pt电极； The metal gate electrode in this embodiment is an Ag electrode, and may also be a Cu electrode, an Ag electrode, an Au electrode or a Pt electrode;
采用丝网印刷法， 即通过特殊的印刷机和模板将银浆印制在钝化层的表面， 形成 Ag栅电极， 栅电极的厚度为 2 ~ 10微米， 栅电极的宽度为 30 ~ 150微米， 间 巨为 2 ~ 3毫米。 Screen printing is used to print silver paste on the surface of the passivation layer by a special printer and template to form an Ag gate electrode. The gate electrode has a thickness of 2 to 10 μm and the gate electrode has a width of 30 to 150 μm. , the huge is 2 ~ 3 mm.
在本制备方法的具体实施方式中， 所述的晶硅可以为单晶晶硅， 也可以为 多晶晶硅； 所述晶硅的表面可为平面、 曲面或由平面和曲面构成的复合面， 均 可以实现本发明。 在上述实施例的步骤 101中， 还可包括对晶硅进行制绒。 In a specific embodiment of the preparation method, the crystalline silicon may be a single crystal silicon or a polycrystalline silicon; the surface of the crystalline silicon may be a plane, a curved surface or a composite surface composed of a plane and a curved surface. The invention can be implemented. In step 101 of the above embodiment, it may further comprise texturing the crystalline silicon.
本实施方式提供的浅结太阳能电池的制备方法筒单独特、 易于掌握， 具有 操作方便、 重复可靠的特点， 具有明确的产业化前景。 The preparation method of the shallow junction solar cell provided by the embodiment is unique and easy to grasp, and has the characteristics of convenient operation, repeatability and reliability, and has a clear industrialization prospect.
以上所述的具体实施方式， 对本发明的目的、 技术方案和有益效果进行了 进一步详细说明， 所应理解的是， 以上所述仅为本发明的具体实施方式而已， 并不用于限制本发明， 凡在本发明的精神和原则之内， 所做的任何修改、 等同 替换、 改进等， 均应包含在本发明的保护范围之内。
The above described embodiments of the present invention are further described in detail, and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.
Claims
1、 一种浅结太阳能电池， 其特征在于： 所述浅结太阳能电池包括金属栅电 极、 钝化层、 晶硅和金属背电极； 所述金属背电极位于所述晶硅的背面， 所述 钝化层位于所述晶硅的上面， 所述金属栅电极位于所述钝化层的上面， 所述晶 硅包括有 PN结， 所述 PN结的深度为 10纳米到 200纳米。 A shallow junction solar cell, characterized in that: the shallow junction solar cell comprises a metal gate electrode, a passivation layer, a crystalline silicon and a metal back electrode; the metal back electrode is located on a back side of the crystalline silicon, A passivation layer is disposed on the surface of the crystalline silicon, the metal gate electrode is located above the passivation layer, and the crystalline silicon includes a PN junction having a depth of 10 nm to 200 nm.
2、 根据权利要求 1所述的浅结太阳能电池， 其特征在于： 所述晶硅表面为 平面或曲面， 所述 PN结的界面为与所述晶硅表面相类似的平面或曲面。 2. The shallow junction solar cell according to claim 1, wherein: the surface of the crystalline silicon is a plane or a curved surface, and an interface of the PN junction is a plane or a curved surface similar to the surface of the crystalline silicon.
3、 根据权利要求 1所述的浅结太阳能电池， 其特征在于： 所述晶硅表面为 由平面和曲面构成的复合面，所述 PN结的界面为与所述晶硅表面相类似的复合 面。 3. The shallow junction solar cell according to claim 1, wherein: the surface of the crystalline silicon is a composite surface composed of a plane and a curved surface, and an interface of the PN junction is a composite similar to the surface of the crystalline silicon. surface.
4、 根据权利要求 2或 3所述的浅结太阳能电池， 其特征在于： 所述晶硅为 单晶硅或多晶硅； 所述金属背电极由铝、 铜、 银、 金或铂制成； 所述金属栅电 极由铝、 铜、 银、 金或铂制成。 The shallow junction solar cell according to claim 2 or 3, wherein: the crystalline silicon is monocrystalline silicon or polycrystalline silicon; and the metal back electrode is made of aluminum, copper, silver, gold or platinum; The metal gate electrode is made of aluminum, copper, silver, gold or platinum.
5、 根据权利要求 4所述的浅结太阳能电池， 其特征在于： 所述金属背电极 的厚度为 10 ~ 15微米； 所述晶硅的厚度为 100 ~ 300微米； 所述钝化层的厚度 为 50 ~ 200纳米； 所述金属栅电极的厚度为 2 ~ 10微米， 所述金属栅电极的宽 度为 30 ~ 150微米， 间距为 2 ~ 3毫米。 The shallow junction solar cell according to claim 4, wherein: the metal back electrode has a thickness of 10 to 15 μm; the crystalline silicon has a thickness of 100 to 300 μm; and the passivation layer has a thickness The metal gate electrode has a thickness of 2 to 10 μm, and the metal gate electrode has a width of 30 to 150 μm and a pitch of 2 to 3 mm.
6、 一种浅结太阳能电池的制备方法， 其特征在于， 所述方法包括： 对晶硅进行预处理； 6. A method of fabricating a shallow junction solar cell, the method comprising: pretreating crystalline silicon;
利用等离子体浸没离子注入工艺， 在所述晶硅上制备 PN结， 并对所述 PN 结进行钝化处理， 形成钝化层； Using a plasma immersion ion implantation process, preparing a PN junction on the crystalline silicon, and passivating the PN junction to form a passivation layer;
分别在所述晶硅的背面和所述钝化层上制备金属背电极和金属栅电极。 A metal back electrode and a metal gate electrode are respectively formed on the back surface of the crystalline silicon and the passivation layer.
7、 根据权利要求 6所述的浅结太阳能电池的制备方法， 其特征在于： 所述 对晶硅进行预处理的步骤包括对晶硅进行清洗、 去损伤或制绒。 7. The method of fabricating a shallow junction solar cell according to claim 6, wherein the step of pretreating the crystalline silicon comprises cleaning, de-damaging or texturing the crystalline silicon.
8、 根据权利要求 6所述的浅结太阳能电池的制备方法， 其特征在于， 所述 利用等离子体浸没离子注入工艺， 在所述晶硅上制备 PN结的步骤具体包括： 将所述晶硅放置于等离子体浸没离子注入设备的注入腔室内； The method for preparing a shallow junction solar cell according to claim 6, wherein the step of preparing a PN junction on the crystalline silicon by using a plasma immersion ion implantation process specifically comprises: Placed in an implantation chamber of a plasma immersion ion implantation apparatus;
调整所述等离子体浸没离子注入设备的工艺参数进入预先设置的数值范 围； Adjusting the process parameters of the plasma immersion ion implantation apparatus into a preset numerical range;
所述等离子体浸没离子注入设备产生等离子体， 所述等离子体中的掺杂离 子注入至所述晶硅内。 The plasma immersion ion implantation apparatus generates a plasma into which doped ions in the plasma are implanted.
9、 根据权利要求 8所述的浅结太阳能电池的制备方法， 其特征在于： 所述 将所述晶硅放置于等离子体浸没离子注入设备的注入腔室内的步骤还包括将所 述晶硅与可施加偏置电压的电源电气连接； 所述工艺参数包括所述注入腔室的 本底压强和工作压强， 注入至所述注入腔室的混合气体的流量、 组成成分和体 积比， 等离子体电源的输出功率、 偏置电压以及等离子体注入时间； 所述本底 压强范围为 10— 3Pa ~ lOOPa, 所述工作压强范围为 O.lPa ~ 50Pa; 所述混合气体由 含有 P、 As或 B元素的气体组成， 所述含有 P或 As元素的气体包括 B2H6、 B(OCH3)3、 PH3或 AsH3。 9. The method of fabricating a shallow junction solar cell according to claim 8, wherein: the step of placing the crystalline silicon in an implantation chamber of a plasma immersion ion implantation apparatus further comprises: a power supply electrical connection to which a bias voltage can be applied; the process parameters including a background pressure and an operating pressure of the injection chamber, a flow rate, a composition ratio, and a volume ratio of the mixed gas injected into the injection chamber, the plasma power source Output power, bias voltage, and plasma injection time; the background pressure range is 10 - 3 Pa ~ 100 Pa, the working pressure range is 0.1 Pa ~ 50 Pa; the mixed gas contains P, As or B The gas composition of the element, the gas containing the P or As element includes B 2 H 6 , B(OCH 3 ) 3 , PH 3 or AsH 3 .
10、 根据权利要求 9所述的浅结太阳能电池的制备方法， 其特征在于： 通 过调节所述偏置电压、 所述等离子体注入时间、 所述混合气体的流量及组成比 例或所述等离子体电源的输出功率来改变所述 PN结的深度。 The method of manufacturing a shallow junction solar cell according to claim 9, wherein: the bias voltage, the plasma injection time, the flow rate and composition ratio of the mixed gas, or the plasma are adjusted The output power of the power supply changes the depth of the PN junction.
11、 根据权利要求 6所述的浅结太阳能电池的制备方法， 其特征在于， 在 所述晶硅上制备 PN结和对所述 PN结进行钝化处理的步骤之间还包括： 对所述 PN结进行热处理； The method for preparing a shallow junction solar cell according to claim 6, wherein the step of preparing a PN junction on the crystalline silicon and performing a passivation treatment on the PN junction further comprises: Heat treating the PN junction;
对热处理后的晶硅进行刻蚀去边处理。 The heat treated crystal silicon is etched and edge-treated.
12、 根据权利要求 6所述的浅结太阳能电池的制备方法， 其特征在于： 所 述钝化处理是采用表面氧化生长 Si02钝化方式进行处理， 或采用 PECVD生长 SiNx或 Si02钝化方式进行处理， 或采用等离子体浸没注入工艺向所述晶硅中注 入 0或 N后， 形成 Si02或SiNx。 The method for preparing a shallow junction solar cell according to claim 6, wherein: the passivation treatment is performed by surface oxidation growth Si0 2 passivation method, or PECVD growth SiNx or Si0 2 passivation method is adopted. After processing, or by implanting 0 or N into the crystalline silicon by a plasma immersion implantation process, SiO 2 or SiNx is formed.
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| CN106409978A (en) * | 2016-11-23 | 2017-02-15 | 中利腾晖光伏科技有限公司 | Preparation method of P-type single crystal solar cell |
| CN108963016A (en) * | 2017-05-23 | 2018-12-07 | 中国科学院宁波材料技术与工程研究所 | A kind of curved surface PN junction and its manufacturing method |
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