WO2012035972A1 - Semiconductor package and semiconductor device - Google Patents

Semiconductor package and semiconductor device Download PDF

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Publication number
WO2012035972A1
WO2012035972A1 PCT/JP2011/069641 JP2011069641W WO2012035972A1 WO 2012035972 A1 WO2012035972 A1 WO 2012035972A1 JP 2011069641 W JP2011069641 W JP 2011069641W WO 2012035972 A1 WO2012035972 A1 WO 2012035972A1
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WO
WIPO (PCT)
Prior art keywords
wiring board
semiconductor element
reinforcing member
semiconductor
package
Prior art date
Application number
PCT/JP2011/069641
Other languages
French (fr)
Japanese (ja)
Inventor
岡田 亮一
賢也 橘
猛 八月朔日
Original Assignee
住友ベークライト株式会社
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Publication date
Application filed by 住友ベークライト株式会社 filed Critical 住友ベークライト株式会社
Priority to JP2012533935A priority Critical patent/JPWO2012035972A1/en
Publication of WO2012035972A1 publication Critical patent/WO2012035972A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the present invention relates to a semiconductor package and a semiconductor device.
  • Interposers used for new packages such as BGA and CSP are generally formed by forming a conductor pattern or a conductor post on a substrate obtained by impregnating a fiber base material with a resin composition.
  • Such an interposer has a large difference in thermal expansion coefficient from the chip. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion that is not in contact with the tip is extremely low in rigidity, and tends to warp due to the difference in thermal expansion between the tip and the interposer as described above.
  • the coefficient of thermal expansion means the length of the object extending per 1 ° C. in the range of 30 to 300 ° C.
  • the rigidity means the difficulty of bending the plate-like substance.
  • An object of the present invention is to provide a semiconductor package and a semiconductor device that can prevent the occurrence of defects due to heat.
  • a first wiring board A first semiconductor element bonded to one surface of the first wiring board; A reinforcing member bonded to a portion of the surface of the first wiring substrate on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring substrate; A second wiring board provided on the side opposite to the first wiring board with respect to the reinforcing member and joined to the first wiring board via two or more metal bumps; A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board; The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
  • first wiring board (3) a first wiring board; A first semiconductor element bonded to one surface of the first wiring board; A reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board; A second wiring board provided on the opposite side of the first wiring board with respect to the first semiconductor element and bonded to the first wiring board via two or more metal bumps; A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board; The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
  • first wiring board A first semiconductor element bonded to one surface of the first wiring board; A reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board; A second wiring board provided on the opposite side of the first wiring board with respect to the first semiconductor element and bonded to the first wiring board via two or more metal bumps; A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board; The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
  • a first wiring board A first semiconductor element bonded to one surface of the first wiring board; A first reinforcing member bonded to a portion of the surface of the first wiring board on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring board; A second reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board; A second wiring board provided on the opposite side of the first wiring board with respect to the first reinforcing member and joined to the first wiring board via two or more metal bumps; A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board; The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
  • (6) a first wiring board; A first semiconductor element bonded to one surface of the first wiring board; A first reinforcing member bonded to a portion of the surface of the first wiring board on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring board; A second reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board; A second wiring board provided on the opposite side of the first wiring board with respect to the first reinforcing member and joined to the first wiring board via two or more metal bumps; A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board; The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
  • the distance between the first semiconductor element and the second wiring board is 0.01 mm or more and 0.8 mm or less.
  • each of the first reinforcing member and the second reinforcing member has a plate shape.
  • each of the first reinforcing member and the second reinforcing member is made of a metal material.
  • a semiconductor device comprising the semiconductor package according to any one of (1) to (17).
  • the step of joining the first reinforcing member to the first wiring board includes: Preparing a laminate of the metal layer and the prepreg, and joining the first reinforcing member to the prepreg side surface of the laminate; A sub-process for forming a through hole in the prepreg; A sub-step of forming a conductor post in the through hole; A sub-process of forming a conductor pattern by patterning the metal layer; A sub-step of curing the prepreg.
  • a spacer is disposed between the top package and the bottom package, and after the top package and the bottom package are joined, the spacer is removed, whereby the second wiring substrate of the top package and the bottom package are removed.
  • top package and the bottom package are pressurized in a direction approaching each other, and the second wiring board of the top package and the first semiconductor element of the bottom package are in contact with each other (19
  • the manufacturing method of the semiconductor package in any one of (22) thru
  • the first wiring board is reinforced by the reinforcing member (particularly, because the reinforcing member is integrated with the first semiconductor element to reinforce the first wiring board). Warpage due to a difference in thermal expansion coefficient between the substrate and the first semiconductor element can be prevented or suppressed.
  • the connection reliability of the metal bumps connecting the second wiring board and the first wiring board, the connection reliability of the metal bumps connecting the first semiconductor element and the first wiring board, the conductor pattern / conductor post inside the wiring board And the connection reliability of the metal bumps connecting the first wiring board and the mother board are improved.
  • the semiconductor package of the present invention when the first semiconductor element and the second wiring board are not in contact with each other, ventilation is performed through a gap formed between the first semiconductor element and the second wiring board.
  • the heat of the first semiconductor element can be efficiently released to the outside.
  • the first semiconductor element and the second wiring board are in contact, the heat of the first semiconductor element can be efficiently released to the outside through the second wiring board.
  • the first wiring board is reinforced as described above, it is not necessary to increase the rigidity of the first wiring board itself, and the thickness of the first wiring board can be reduced. Therefore, the thermal conductivity in the thickness direction of the first wiring board can be increased, and the heat from the first semiconductor element can be efficiently released to the outside through the first wiring board. For these reasons, the semiconductor package of the present invention is excellent in heat dissipation.
  • the semiconductor device of the present invention since the semiconductor package as described above is provided, the reliability is excellent.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention. It is a top view which shows the bottom package with which the semiconductor package shown in FIG. 1 is provided. It is a bottom view which shows the bottom package with which the semiconductor package shown in FIG. 1 is provided. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 3rd Embodiment of this invention. It is sectional drawing which shows typically an example of embodiment of the semiconductor device of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 4th Embodiment of this invention.
  • FIG. 8 It is a top view which shows the bottom package with which the semiconductor package shown in FIG. 8 is provided. It is a bottom view which shows the bottom package with which the semiconductor package shown in FIG. 8 is provided. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor package which concerns on 5th Embodiment of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 6th Embodiment of this invention. It is sectional drawing which shows typically an example of embodiment of the semiconductor device of this invention.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention
  • FIG. 2 is a top view showing the semiconductor package shown in FIG. 1
  • FIG. 3 shows the semiconductor package shown in FIG.
  • FIG. 4 is a bottom view
  • FIG. 4 is a view showing an example of a method for manufacturing the semiconductor package shown in FIG.
  • the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”.
  • each part of the semiconductor package is exaggerated for convenience of explanation.
  • the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member 4, a second reinforcing member 5, a wiring board 301, The semiconductor element 305 mounted on the wiring board 301 and a plurality of metal bumps 400 that connect the wiring board 2 and the wiring board 301 are provided.
  • the semiconductor package 1 includes a bottom package 500 in which a semiconductor element (first semiconductor element) 3 is mounted on a wiring board (first wiring board) 2 and a semiconductor element (second semiconductor element) on a wiring board (second wiring board) 301. )
  • a POP Package On Package
  • the top package 300 mounted with 305 is stacked.
  • the wiring board 2 is reinforced by the first reinforcing member 4 even in a portion other than the portion joined to the semiconductor element 3, the rigidity of the entire bottom package 500 is increased.
  • the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, a substrate 21 described later), the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. The warpage of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be suppressed or prevented.
  • the semiconductor element 3 and the wiring board 301 are not in contact with each other, air is ventilated through a gap formed between the semiconductor element 3 and the wiring board 301, and the heat of the semiconductor element 3 is moved outward. Can be missed efficiently.
  • the wiring board 2 is reinforced as described above, it is not necessary to increase the rigidity of the wiring board 2 itself, and the thickness of the wiring board 2 can be reduced. Thus, the heat conductivity of the semiconductor element 3 can be increased and the heat from the semiconductor element 3 can be released through the wiring board 2. For this reason, the semiconductor package 1 is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
  • the semiconductor package 1 Combined with such excellent heat dissipation of the semiconductor package 1, it is possible to effectively suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. As a result, the electrical connection reliability between the top package 300 and the bottom package 500 can be made excellent.
  • the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5 by bonding the second reinforcing member 5 to the surface (lower surface) opposite to the semiconductor element 3 of the wiring board 2. Therefore, the wiring board 2 can be reinforced more strongly, and the difference in thermal expansion between both surfaces of the wiring board 2 can be suppressed.
  • the second reinforcing member is provided so as to extend between the metal bumps 71 described later, the wiring board 2 can be strongly reinforced.
  • the bottom package (first package) 500 includes a wiring board 2, a semiconductor element 3, a first reinforcing member 4, and a second reinforcing member 5.
  • the wiring board 2 is a board (first wiring board) that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later. is there.
  • the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.
  • the wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, 234, and heat transfer posts 24.
  • the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21.
  • a second conductor pattern electrically connected to the conductor pattern is formed.
  • the substrate 21 is composed of a plurality (five layers in this embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order.
  • the number of insulating layers constituting the substrate 21 is not limited to this, and may be 1 to 4 layers or 6 or more layers.
  • Each insulating layer 211, 212, 213, 214, 215 is made of an insulating material.
  • each insulating layer 211, 212, 213, 214, 215 is composed of a base material (fiber base material) and a resin composition impregnated in the base material.
  • the base material is used as a core material of each insulating layer 211, 212, 213, 214, 215. By having such a base material, the rigidity of the substrate 21 can be increased.
  • the base material examples include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthetic fiber base material, kraft paper composed of woven fabric or non-woven fabric mainly composed of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, etc. And paper base materials mainly composed of cotton linter paper, mixed paper of linter and kraft pulp, and the like. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Further, the thermal expansion coefficient of the substrate 2 can be reduced.
  • Examples of the glass constituting such a glass fiber substrate include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, and H glass.
  • T glass is preferable.
  • the thermal expansion coefficient of a glass fiber base material can be made small, and, thereby, the thermal expansion coefficient of the board
  • substrate 21 can be made small.
  • the content of the base material in the insulating layers 211, 212, 213, 214, and 215 is preferably 30 to 70 wt%, respectively. 40 to 60 wt% is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers.
  • at least one of the insulating layers 211, 212, 213, 214, and 215 may be composed of only the resin composition without including the base material.
  • the resin composition impregnated in such a base material contains a resin material.
  • a resin material a thermosetting resin is preferably used.
  • thermosetting resin examples include novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like.
  • novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like.
  • phenol resin such as resol type phenol resin
  • bisphenol type epoxy resin such as bisphenol A epoxy resin
  • bisphenol F epoxy resin novolac epoxy resin
  • novolac epoxy resin such as novolac epoxy resin, cresol novolac epoxy resin, biphenyl type epoxy resin, etc.
  • resin having triazine ring such as melamine resin, unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate Over preparative resin, silicone resin, resins having a benzoxazine ring, cyanate ester resins.
  • cyanate resin is particularly preferable.
  • substrate 21 can be made small enough.
  • the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.
  • the resin composition preferably contains a filler. That is, each of the insulating layers 211, 212, 213, 214, and 215 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be lowered.
  • the filler is a substance constituting the insulating layer that maintains a solid state even during the manufacturing process and when it becomes a final product.
  • Examples of the filler include various inorganic fillers or organic fillers.
  • Examples of the inorganic filler include oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, and hydroxide such as aluminum hydroxide and magnesium hydroxide.
  • organic filler synthetic resin powder
  • synthetic resin powder examples include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene.
  • various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins may be mentioned.
  • organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.
  • the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be effectively reduced.
  • the heat transfer properties of the insulating layers 211, 212, 213, 214, and 215 can be increased.
  • silica is preferable, and fused silica (especially spherical fused silica) is preferable in terms of excellent low thermal expansion.
  • the average particle size of the inorganic filler is not particularly limited, but is preferably 0.05 to 2.0 ⁇ m, particularly preferably 0.1 to 1.0 ⁇ m.
  • the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, 213, 214, and 215, and the physical strength and insulating properties of the insulating layers 211, 212, 213, 214, and 215 are particularly improved. It can be excellent.
  • the average particle size of the inorganic filler can be measured by, for example, a particle size distribution meter (manufactured by HORIBA, LA-500). Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.
  • the content of the inorganic filler in the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but is preferably 30 to 80 wt% when the resin composition excluding the base material is 100 wt%, particularly 45 to 75 wt% is preferable.
  • the insulating layers 211, 212, 213, 214, and 215 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.
  • the resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin in addition to the thermosetting resin described above.
  • a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin in addition to the thermosetting resin described above.
  • the resin composition may contain additives other than the above components such as pigments and antioxidants as necessary.
  • the insulating layers 211, 212, 213, 214, and 215 may be made of the same material as each other, or may be made of different materials.
  • the average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 ⁇ m or more and 800 ⁇ m or less, and more preferably 30 ⁇ m or more and 400 ⁇ m or less.
  • the conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21.
  • a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213.
  • a conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214.
  • a conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215.
  • a conductor pattern 225 is provided on the upper surface of the insulating layer 211.
  • the conductor patterns 221, 222, 223, 224, and 225 each function as a circuit having a plurality of wirings.
  • the constituent material of the conductor patterns 221, 222, 223, 224, 225 is not particularly limited as long as it has conductivity.
  • various metals such as copper, copper-based alloys, aluminum, aluminum-based alloys, and various types An alloy is mentioned.
  • copper and a copper-based alloys have a relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved.
  • copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
  • the average thickness of the conductor patterns 221, 222, 223, 224, and 225 is not particularly limited, but is preferably 5 ⁇ m or more and 30 ⁇ m or less.
  • a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole.
  • the conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected.
  • a via hole is a through-hole or bottomed hole for conducting a circuit above an insulating layer and a circuit below.
  • the insulating layer 211 has a conductor post (via post) passing through the conductor pattern 221 and the conductor pattern 225 in the thickness direction.
  • a plurality of metal bumps 400 are bonded on the upper surface of the substrate 21 of the conductor pattern 225.
  • Each metal bump 400 makes electrical connection between the top package 300 and the bottom package 500 (more specifically, electrical connection between the wiring board 2 and the wiring board 301).
  • Each metal bump 400 also has a function of performing mechanical connection (fixation) between the wiring board 2 and the wiring board 301.
  • the plurality of metal bumps 400 are arranged along the outer peripheral portion of the wiring board 2 at intervals.
  • each metal bump 400 has a substantially spherical shape.
  • the shape of each metal bump 400 is not limited to this.
  • the size (diameter) of each metal bump 400 is set to such an extent that the semiconductor element 3 and the wiring board 301 are not in contact with each other as will be described later.
  • the constituent material of the metal bump 400 is not particularly limited.
  • Various brazing materials (solder) such as tin-copper and tin-silver-copper can be used.
  • the insulating layer 212 is provided with a conductor post (via post) 232 that penetrates in the thickness direction.
  • the conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.
  • the insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction.
  • the conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.
  • the insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction.
  • the conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.
  • the insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening.
  • Metal bumps 71 are bonded onto the exposed portions (terminals) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21.
  • the metal bump 71 electrically connects the semiconductor package 1 to, for example, a motherboard as described later.
  • the metal bump 71 has a substantially spherical shape.
  • the shape of the metal bump 71 is not limited to this.
  • the constituent material of the metal bump 71 is not particularly limited.
  • tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin-- Various brazing materials (solder) such as copper and tin-silver-copper can be used.
  • the substrate 21 is formed with a plurality of via holes penetrating over the entire area in the thickness direction, and a heat transfer post 24 is provided in each via hole.
  • Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the substrate 21 and its lower end is exposed from the lower surface of the substrate 21.
  • the heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5.
  • each heat transfer post 24 connects the first reinforcing member 4 and the second reinforcing member 5.
  • Each of the heat transfer posts (heat conducting portions) 24 has higher heat transfer performance than the substrate 21 (insulating layer) described above. Thereby, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • each of the heat transfer posts 24 penetrates the substrate 21 in the thickness direction, the heat transfer posts 24 can be formed easily and with high accuracy in the same manner as known conductor posts.
  • each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post
  • each heat transfer post 24 does not contribute to the transmission of electrical signals. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 through the heat transfer post 24.
  • the plurality of heat transfer posts 24 are arranged in parallel along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan.
  • the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.
  • the plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, 224, 225 described above when the wiring board 2 is viewed in plan. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit of the conductor patterns 221, 222, 223, 224, and 225 by the heat transfer post 24 can be prevented.
  • each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.
  • Such metal materials include various metals and various alloys such as copper, copper-based alloys, aluminum, and aluminum-based alloys.
  • a metal material it is preferable to use copper, a copper-based alloy, aluminum, or an aluminum-based alloy because of excellent heat conductivity.
  • the constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 234 described above, but is the same as the constituent material of the conductor posts 231 to 234 (particularly, the constituent material of the conductor posts 234). Is preferred. As a result, the heat transfer posts 24 can be formed simultaneously with the formation of the conductor posts 234. Therefore, the manufacturing of the semiconductor package 1 is simplified, and the semiconductor package 1 can be made inexpensive.
  • the semiconductor element (first semiconductor element) 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light emitting / receiving element.
  • IC integrated circuit element
  • the semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
  • the semiconductor element 3 is provided with a plurality of terminals (not shown) on its lower surface, and each terminal is electrically connected to the conductor post 231 of the wiring board 2 described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2 are electrically connected.
  • the constituent material of the metal bump 31 is not particularly limited, but is similar to the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin Various brazing materials (solder) such as silver-bismuth, tin-copper, tin-silver-copper can be used.
  • the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 through the adhesive layer 32.
  • the adhesive layer 32 is made of a material having adhesiveness and insulating properties, for example, a cured product of an underfill material.
  • the underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.
  • the first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.
  • the first reinforcing member 4 and the substrate 21 can be joined through an adhesive, for example. Thereby, installation of the 1st reinforcement member 4 becomes easy.
  • Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used.
  • an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.
  • the first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.
  • the first reinforcing member 4 has a plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.
  • the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface.
  • the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned.
  • the installation can be performed stably.
  • the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the semiconductor element 3 can be easily installed.
  • the first reinforcing member 4 has a shape surrounding the semiconductor element 3.
  • the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the effect which improves the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.
  • the first reinforcing member 4 is formed with a plurality of openings 42 penetrating in the thickness direction.
  • the metal bump 400 described above is arranged in each opening 42.
  • each opening 42 is provided in one-to-one correspondence with each metal bump 400.
  • Each opening 42 is formed so as to surround each metal bump 400 without contacting each metal bump 400.
  • an insulating material 401 is provided between the first reinforcing member 4 and each metal bump 400 (between the wall surface of the opening 42 and the metal bump 400).
  • the insulating material 401 is shaped to surround the periphery (lower part) of the metal bump 400 on the substrate 21 side, and is joined to each metal bump 400. Thereby, the insulating material 401 reinforces the metal bump 400.
  • the insulating material 401 preferably has higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 400 and the first reinforcing member 4 is excellent, and the heat dissipation of the semiconductor package 1 can be improved.
  • Such an insulating material 401 has an insulating property and includes a resin material, and is not particularly limited. However, like the insulating material 81 described later, the insulating material 401 is formed of, for example, a thermosetting solder bonding resin. Is preferred.
  • the distance between the first reinforcing member 4 and each metal bump 400 extends over the entire circumference of the metal bump 400. It is formed to be constant. Thereby, the integrity of the 1st reinforcement member 4 and each metal bump 400 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.
  • the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.
  • the first reinforcing member 4 has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less.
  • the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the bottom package 500 whole.
  • the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above.
  • a metal material, a ceramic material, or the like can be used. It is preferable to use it.
  • the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the bottom package 500 can be improved.
  • Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
  • Such alloys containing Fe include Fe—Ni alloys, Fe—Co—Cr alloys, Fe—Co alloys, Fe—Pt alloys, Fe—Pd alloys, and the like. It is preferable to use a base alloy.
  • Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.
  • the Fe—Ni alloy is not particularly limited as long as it contains Fe and Ni.
  • the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.
  • Fe—Ni alloys include Fe—Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar).
  • Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy.
  • Fe—Ni—Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, KV-25, and Nivarox. ing.
  • Fe—Ni alloys are commercially available under trade names such as NS-5 and D-1 (manufactured by NEOMAX Materials).
  • Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal Co., Ltd.), EL-3 (manufactured by NEOMAX Material Co., Ltd.), and the like.
  • the Fe—Co—Cr-based alloy is not particularly limited as long as it contains Fe, Co, and Cr.
  • an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is available. Is mentioned.
  • the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.
  • the Fe—Co alloy is not particularly limited as long as it contains Fe and Co, and in addition to Fe and Co, one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt. It may contain seeds or two or more metals.
  • the Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt.
  • one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. It may contain seeds or two or more metals.
  • the Fe—Pd alloy is not particularly limited as long as it contains Fe and Pd.
  • one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.
  • the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy
  • the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less.
  • the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
  • the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less. In addition, although the thickness of the 1st reinforcement member 4 is uniform in this embodiment, you may have a part from which thickness differs. For example, the thickness may decrease or increase continuously or stepwise from the inside to the outside of the first reinforcing member 4.
  • a heat conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3.
  • heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6.
  • the heat dissipation of the semiconductor package 1 can be improved.
  • Such a heat conductive material 6 is not particularly limited, and examples thereof include a resin composition including an inorganic filler and a resin material.
  • Examples of the inorganic filler (inorganic filler) used in the heat conductive material 6 (resin composition) include metals such as Au, Ag, and Pt, silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, Oxides such as magnesium oxide and metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride, and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, calcium carbonate (light and heavy), magnesium carbonate Carbonates such as dolomite and dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate and calcium sulfite, talc, mica, clay, glass fiber, silicates such as calcium silicate, montmorillonite and bentonite, boron Zinc oxide, barium metaborate, aluminum borate, calcium borate, Borate
  • oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite, boron nitride, Nitride such as silicon nitride, gallium nitride and titanium nitride is preferable.
  • examples of the resin material used for the heat conductive material 6 include various thermoplastic resins and various thermosetting resins.
  • thermoplastic resin used for the thermally conductive material 6 examples include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66).
  • thermoplastic elastomers such as polyisoprene, fluororubber, and chlorinated polyethylene, and copolymers, blends, and polymer alloys mainly composed of these, one or two of these The above can
  • thermosetting resin used for the heat conductive material 6 for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, polyurethane Resins etc. are mentioned, 1 type or 2 types or more of these can be mixed and used.
  • the resin material used for the heat conductive material 6 (resin composition)
  • a thermosetting resin particularly, a liquid that forms a liquid before curing
  • a phenol resin or an epoxy resin is particularly preferable to use a phenol resin.
  • the thermal conductive material 6 can be filled between the first reinforcing member 4 and the semiconductor element 3 without a gap, and the thermal expansion coefficient of the thermal conductive material 6 can be effectively suppressed.
  • phenolic resins examples include phenol novolac resins, cresol novolac resins, novolac type phenol resins such as bisphenol A novolac resins, unmodified resole phenol resins, oil-modified resole phenol resins modified with paulownia oil, linseed oil, walnut oil, etc.
  • phenolic resins such as resol type phenolic resins.
  • the heat conductive material 6 may be the same as the adhesive layer 32 (underfill material) described above, and the heat conductive material 6 and the adhesive layer 32 may be formed in a lump. .
  • the second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.
  • the second reinforcing member 5 and the substrate 21 can be joined via an adhesive. Thereby, installation of the 2nd reinforcement member 5 becomes easy.
  • Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used.
  • an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.
  • the second reinforcing member 5 has a smaller thermal expansion coefficient than that of the substrate 21 as in the first reinforcing member 4 described above.
  • the second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.
  • the second reinforcing member 5 includes a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21), and metal bumps. And a portion 53 provided between 71.
  • the second reinforcing member 5 has a plurality of openings 51 formed so as to surround each metal bump 71 in a non-contact manner with each metal bump 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.
  • each opening 51 is circular in plan view.
  • the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
  • each opening 51 is provided corresponding to each metal bump 71 (corresponding one-to-one).
  • the rigidity of the second reinforcing member 5 can be made uniform.
  • the heat dissipation of the 2nd reinforcement member 5 can also be improved.
  • the distance between the second reinforcing member 5 and each metal bump 71 extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.
  • the heat transfer bumps 91 are provided on the lower surface of the second reinforcing member 5.
  • the heat transfer bumps 91 have higher thermal conductivity than the substrate 21 of the wiring board 2 and are bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).
  • the constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.
  • the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less.
  • the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.
  • the second reinforcing member 5 is preferably made of a metal material. Thereby, the heat dissipation of the 2nd reinforcement member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • the metal material is not particularly limited, but it is preferable to use an Fe—Ni-based alloy from the viewpoint of realizing heat dissipation and low thermal expansion.
  • the same material as the first reinforcing member 4 described above can be used.
  • the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable.
  • the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.
  • the average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.
  • an insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be improved while improving the reliability of the semiconductor package 1.
  • the insulating material 81 has a shape surrounding the periphery (upper part) of the metal bump 71 on the substrate 21 side, and is joined to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71.
  • the insulating material 81 preferably has a higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 71 and the second reinforcing member 5 can be made excellent, and the heat dissipation of the semiconductor package 1 can be improved.
  • Such an insulating material 81 has an insulating property and includes a resin material.
  • Such an insulating material 81 is not particularly limited, but is preferably formed from, for example, a solder bonding resin having thermosetting properties.
  • solder bonding resin acts as a flux at the time of solder bonding, and then cures by heating to act as a reinforcing material for the solder bonding portion.
  • the flux is a material that melts before the solder and removes oxides and dirt on the surface of the solder when soldering.
  • the solder bonding resin removes harmful substances such as solder joint surfaces and oxides of the solder material at the time of solder joint, protects the solder joint surface, and refines the solder material to improve the strength. Allows large good joints.
  • the solder bonding resin does not need to be removed by washing or the like after the solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.
  • Such a solder bonding resin can be configured to include, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.
  • the resin (A) having a phenolic hydroxyl group is not particularly limited, and examples thereof include a phenol novolak resin, an alkylphenol novolak resin, a polyhydric phenol novolak resin, a resole resin, and a polyvinyl phenol resin.
  • the content of the resin (A) having a phenolic hydroxyl group is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened
  • the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as solder and oxide on the metal surface by its reducing action, and thus effectively acts as a solder joint flux.
  • examples of the curing agent (B) of the resin (A) having a phenolic hydroxyl group include an epoxy compound and an isocyanate compound.
  • examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.
  • the compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group or isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. If the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, resulting in a decrease in bonding strength and reliability. There is. If the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxide on the solder and metal surface may be reduced, and solder jointability may be deteriorated.
  • solder bonding resin curable flux
  • a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. Therefore, it is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in high temperature and high humidity atmosphere, enabling soldering with high bonding strength and reliability.
  • the solder bonding resin as described above is dispersed in a curable antioxidant (C) and in a microcrystalline state.
  • the top package (second package) 300 includes a wiring substrate 301 and a semiconductor element 305, and a sealing portion 307 that covers the semiconductor element 305 is provided on the surface of the wiring substrate 301 on the semiconductor element 305 side.
  • the configuration of the illustrated top package 300 is an example, and the present invention is not limited to this.
  • the wiring board 301 is a board (second wiring board) that supports the semiconductor element 305.
  • the wiring board 301 is a relay board (interposer) that relays electrical connection between the mounted semiconductor element 305 and the bottom package 500 described above.
  • the wiring board 301 has a shape in plan view generally a quadrangle such as a square or a rectangle.
  • the wiring substrate 301 has a substrate 302.
  • the substrate 302 is composed of an insulating material, and is composed of, for example, a base material (fiber base material) and a resin composition impregnated in the base material.
  • a base material fiber base material
  • resin composition impregnated in the base material.
  • the substrate 302 is formed of a single insulating layer, but may be formed of a plurality of insulating layers.
  • a conductor pattern 308 is provided on the lower surface of the substrate 302.
  • the conductor pattern 308 is bonded to the conductor pattern 225 of the bottom package 500 through the metal bumps 400 described above.
  • These conductor patterns and conductor posts can be configured similarly to the conductor patterns and conductor posts of the wiring board 2 described above.
  • An insulating layer 304 is provided on the lower surface of the substrate 302 so as to cover the conductor pattern 308. Similarly, an insulating layer 303 is provided on the top surface of the substrate 302. The insulating layers 303 and 304 can be formed by, for example, a known solder resist. A semiconductor element 305 is bonded on the upper surface of the wiring substrate 301.
  • the semiconductor element (second semiconductor element) 305 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light emitting / receiving element.
  • the configuration and function of the semiconductor element 305 may be the same as or different from the configuration and function of the semiconductor element 3 described above.
  • the semiconductor element 305 is electrically connected via a plurality of metal wires 306 to a conductor pattern (not shown) provided on the upper surface side of the wiring board 301 described above.
  • Each metal wire 306 is formed by, for example, a known wire bonding technique. This electrical connection may be performed by face-down bonding in the same manner as the bottom package 500 described above, instead of the metal wire.
  • Such a semiconductor element 305 is sealed by a sealing portion 307.
  • the sealing portion 307 is provided on the upper surface of the wiring substrate 301 so as to cover the semiconductor element 305, the rigidity of the top package 300 can be increased. Therefore, warping of the top package 300 can be prevented or suppressed.
  • this sealing part 307 Although it does not specifically limit as a constituent material of this sealing part 307, A well-known sealing resin can be used.
  • the lower surface of the wiring substrate 301 of the top package 300 is not in contact with (separated from) the semiconductor element 3 of the bottom package 500 described above.
  • the entire upper surface of the semiconductor element 3 is separated from the lower surface of the wiring substrate 301. Thereby, air can be ventilated through the gap S1 formed between the semiconductor element 3 and the wiring board 301, and the heat of the semiconductor element 3 can be efficiently released outward.
  • the distance L between the upper surface of the semiconductor element 3 and the lower surface of the wiring board 301 (that is, the length of the gap S1 in the thickness direction) L is 0.01 mm or more and 0.8 mm from the viewpoint of ensuring the above-described ventilation. It is preferable that: L is more preferably 0.05 mm or more and 0.5 mm or less.
  • the lower surface of the wiring board 301 is the same as that of the bottom package 500 described above. 1 Separated from the upper surface of the reinforcing member 4 (non-contacting). In the present embodiment, the entire upper surface of the first reinforcing member 4 is not in contact with the lower surface of the wiring board 301. Air can be ventilated through the gap S2 formed between the first reinforcing member 4 and the wiring board 301, and the heat of the semiconductor element 3 can be efficiently released to the outside. Therefore, the heat dissipation of the semiconductor package 1 can be made excellent. A part of the upper surface of the first reinforcing member 4 may be in contact with the lower surface of the wiring board 301.
  • the wiring board 2 is reinforced by the first reinforcing member 4 even in a portion other than the portion joined to the semiconductor element 3, the rigidity of the bottom package 500 as a whole. Increase.
  • the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, the substrate 21), the wiring is similar to the case where the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. It is possible to suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the substrate 2 and the semiconductor element 3.
  • the semiconductor element 3 and the wiring board 301 are not in contact with each other, air is ventilated through a gap formed between the semiconductor element 3 and the wiring board 301 to efficiently release the heat of the semiconductor element 3 to the outside. be able to.
  • the thermal conductivity in the thickness direction of the wiring board 2 is increased, and the heat from the semiconductor element 3 is increased. It can escape through the wiring board 2.
  • the semiconductor package 1 is excellent in heat dissipation.
  • the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
  • the semiconductor package 1 Combined with such excellent heat dissipation of the semiconductor package 1, it is possible to effectively suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. As a result, the electrical connection reliability between the top package 300 and the bottom package 500 can be made excellent.
  • the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5 by bonding the second reinforcing member 5 to the surface (lower surface) opposite to the semiconductor element 3 of the wiring board 2. Therefore, the wiring board 2 can be reinforced more strongly, and the difference in thermal expansion between both surfaces of the wiring board 2 can be suppressed.
  • the second reinforcing member 5 is provided so as to extend between metal bumps 71 described later, the wiring board 2 can be strongly reinforced.
  • the semiconductor package 1 as described above can be manufactured as follows, for example.
  • the manufacturing method of the semiconductor package 1 is not limited to this.
  • the prepreg 211A is formed by impregnating the base material with the uncured material (semi-cured material) of the resin composition of the insulating layer 211 described above, and forms the insulating layer 211 of the wiring substrate 2 described above.
  • the metal layer 221A is for forming the conductor pattern 221 of the wiring board 2 described above, and is made of the same material as that of the conductor pattern 221.
  • a through hole 2111 (via hole) is formed in the prepreg 211A.
  • the formation method of the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.
  • the laser for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
  • the through-hole 2111 can be formed by machining such as a drill, for example.
  • conductor posts 231 and a conductor pattern 225 are formed in the through hole 2111.
  • the method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.
  • the method for forming the conductor pattern 225 is not particularly limited, and for example, a method of applying a conductive paste, a method of forming a film by electroless plating, or the like can be used.
  • the conductor layer 221 is formed by patterning the metal layer 221A.
  • Such a patterning method is not particularly limited, but etching is preferably used.
  • the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.
  • the heat transfer post 24 is formed using the same method as that for the conductor posts 231, 232, 233, 234, and 235.
  • the prepreg for the insulating layers 211, 212, 213, 214, and 215 is cured (completely cured) to obtain the wiring board 2 as shown in FIG.
  • Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.
  • the method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but for example, heat treatment is preferably used.
  • the heat transfer post 24 is formed at the same time as the conductor posts 231, 232, 233, 234, and 235, and the heat transfer posts are formed on the prepregs for the insulating layers 211, 212, 213, 214, and 215. These heat transfer posts may be connected and formed by laminating these prepregs.
  • solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. ⁇ 10 to 60 seconds. .
  • the insulating material 81A forms the above-described insulating material 81 and is cured by heating, for example.
  • the insulating material 81A When forming the insulating material 81, for example, as shown in FIG. 4F, the insulating material 81A is applied to the lower surface of the wiring board 2, and after the solder bonding as described above, the insulating material 81A is cured by heating. By doing so, the insulating material 81 is obtained.
  • the insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
  • the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.
  • the second reinforcing member 5 is joined to the lower surface of the wiring board 2.
  • the semiconductor element 3 is joined by solder reflow through the metal bumps 31.
  • a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material.
  • a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.
  • the metal bumps 400A and the insulating material 401 are formed in the same manner as the formation of the metal bumps 71 and the insulating material 81 described above.
  • the bottom package 500 is obtained as described above.
  • the top package 300 is prepared, and the top package 300 and the bottom package 500 are joined by solder bonding via the metal bump 400A (metal bump 400).
  • the metal bump 400 expands in the thickness direction with cooling of the metal bump 400 after bonding, and after the bonding, the lower surface of the wiring substrate 301 of the top package 300.
  • the upper surface of the semiconductor element 3 of the bottom package 500 can be separated from each other.
  • a spacer is disposed between the top package 300 and the bottom package 500 at the time of bonding, and the spacer is removed after the bonding, so that after bonding, the lower surface of the wiring substrate 301 of the top package 300 and the semiconductor of the bottom package 500 are bonded.
  • a state in which the upper surface of the element 3 is separated can also be employed.
  • the two packages may be pressed in the direction in which the two packages approach each other with the spacers arranged.
  • the semiconductor package 1 is obtained as described above.
  • FIG. 5 is a cross-sectional view schematically showing a semiconductor package according to the second embodiment of the present invention.
  • the upper side in FIG. 5 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 5, for convenience of explanation, each part of the semiconductor package is exaggerated.
  • the semiconductor package of the second embodiment is the same as that of the first embodiment except that the configuration of the reinforcing member (first reinforcing member) is different.
  • the top package 300 and the bottom package 500 ⁇ / b> A are joined via a plurality of metal bumps 400.
  • the first reinforcing member 4A is joined to the upper surface of the wiring board 2.
  • the surface (that is, the upper surface) opposite to the substrate 21 of the first reinforcing member 4A is located on the substrate 21 side (that is, the lower side) than the surface (that is, the upper surface) opposite to the substrate 21 of the semiconductor element 3. . Accordingly, when the semiconductor element 3 is installed after the first reinforcing member 4 ⁇ / b> A is installed in manufacturing the semiconductor package 1, the semiconductor element 3 can be easily installed.
  • the distance L2 between the upper surface of the first reinforcing member 4A and the lower surface of the wiring substrate 301 is the upper surface of the semiconductor element 3 and the lower surface of the wiring substrate 301. (Ie, the length of the gap S1 in the thickness direction) L1. Accordingly, it is possible to efficiently ventilate through the gap S2 formed between the first reinforcing member 4A and the wiring board 301.
  • the total thickness of the first reinforcing member 4A and the metal bump 31 is smaller than the thickness of the semiconductor element 3. Thereby, the gap S2 as described above can be easily and reliably formed.
  • T2 of the first reinforcing member 4A is 0.04 or more and 0.96 or less. It is preferable that it is 0.1 or more and 0.9 or less.
  • the distance L2 between the first reinforcing member 4A and the wiring board 301 (that is, the length of the gap S2 in the thickness direction) L2 is 0.015 mm or more and 0.8 mm from the viewpoint of ensuring ventilation as described above. It is preferable that: L2 is more preferably 0.05 mm or more and 0.5 mm or less.
  • the semiconductor package 1A of the second embodiment as described above can also prevent the wiring board 2 from warping and improve heat dissipation.
  • FIG. 6 is a cross-sectional view schematically showing a semiconductor package according to the third embodiment of the present invention.
  • the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 6, for convenience of explanation, each part of the semiconductor package is exaggerated.
  • the semiconductor package of the third embodiment is the same as that of the first embodiment except that the first reinforcing member, the heat transfer post, the heat conductive material, and the heat transfer bump are omitted.
  • the top package 300 and the bottom package 500 ⁇ / b> B are joined via a plurality of metal bumps 400.
  • the bottom package 500B has a wiring board 2B configured similarly to the wiring board 2 of the first embodiment described above except that the heat transfer post 24 is omitted.
  • a reinforcing member 5B configured similarly to the second reinforcing member 5 of the first embodiment described above is joined.
  • a reinforcing member intended to reinforce the wiring board 2B is not joined on the upper surface of the wiring board 2B.
  • a gap formed between the wiring board 301 and the wiring board 2B around the semiconductor element 3 on the wiring board 2B can be increased. For this reason, the semiconductor element 3 is efficiently radiated by ventilation through the gap.
  • the semiconductor package 1B according to the third embodiment as described above can also prevent the wiring board 2B from warping and improve heat dissipation.
  • FIG. 7 is a cross-sectional view schematically showing an example of the embodiment of the semiconductor device of the present invention.
  • the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.
  • the metal bumps 71 of the semiconductor package 1 are joined to the terminals 201 of the motherboard 200. Thereby, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.
  • the heat transfer bumps 91 of the semiconductor package 1 are joined to the heat radiation terminals 202 of the motherboard 200.
  • the heat of the semiconductor package 1 can be efficiently released to the mother board 200 through this joint.
  • a heat transfer bump 91 is made of the same material as that of the metal bump 71 described above, the heat transfer bump 91 can be bonded to the mother board 200 at the same time as the metal bump 71 is bonded.
  • the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
  • the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3.
  • the present invention is not limited to this.
  • a cut-out portion (notch) may be formed.
  • the second reinforcing member 5 may be omitted depending on the rigidity of the first reinforcing member 4 and the thickness of the wiring board 2.
  • the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5.
  • a heat conductive member metal member
  • the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21.
  • the reinforcing member 4 and the second reinforcing member 5 may be held from above and below.
  • the opening formed in the first reinforcing member 4 may not correspond to each metal bump 400 on a one-to-one basis. That is, an opening may be formed in the first reinforcing member 4 so that one corresponds to the plurality of metal bumps 400.
  • the opening formed in the second reinforcing member 5 may not correspond to each metal bump 71 on a one-to-one basis. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.
  • FIG. 8 is a cross-sectional view schematically showing a semiconductor package according to the fourth embodiment of the present invention.
  • the upper side in FIG. 8 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 8, for convenience of explanation, each part of the semiconductor package is exaggerated.
  • the semiconductor package of the fourth embodiment will be described focusing on differences from the above-described embodiment, and description of similar matters will be omitted.
  • FIG. 8 the same reference numerals are given to the same configurations as those in the above-described embodiment.
  • the semiconductor package of the fourth embodiment is the same as that of the first embodiment except that the first semiconductor element and the second wiring board are in contact with each other.
  • each metal bump 400 is set to such an extent that the semiconductor element 3 and the wiring board 301 are in contact with each other.
  • the lower surface of the wiring substrate 301 of the top package 300 is in contact with the semiconductor element 3 of the bottom package 500 described above.
  • almost the entire upper surface of the semiconductor element 3 is in contact with the lower surface of the wiring substrate 301.
  • a part of the upper surface of the semiconductor element 3 may not be in contact with the lower surface of the wiring substrate 301.
  • a gap is formed between the semiconductor element 3 and the wiring substrate 301, it is preferable to fill the gap with a heat conductive material (thermal conductive adhesive) similar to the above-described heat conductive material 6. .
  • a heat conductive material thermal conductive adhesive
  • the thermal conductivity between the semiconductor element 3 and the wiring substrate 301 can be made excellent and easy and reliable.
  • the wiring board 301 is reinforced and the rigidity of the entire semiconductor package 1 is increased.
  • the lower surface of the wiring board 301 is the same as that of the bottom package 500 described above. 1
  • the top surface of the reinforcing member 4 is in contact (surface contact).
  • almost the entire upper surface of the first reinforcing member 4 is in contact with the lower surface of the wiring board 301. Since the first reinforcing member 4 is in contact with the wiring board 301 in this manner, heat transfer between the wiring board 2 and the wiring board 301 can be performed via the first reinforcing member 4. Therefore, the heat dissipation of the semiconductor package 1 can be made excellent.
  • a part of the upper surface of the first reinforcing member 4 may not be in contact with the lower surface of the wiring board 301.
  • the gap is filled with the same heat conductive material (heat conductive adhesive) as the heat conductive material 6 described above.
  • heat conductive adhesive heat conductive adhesive
  • the first reinforcing member 4 and the wiring board 301 are bonded via a heat conductive material.
  • the heat conductivity between the 1st reinforcement member 4 and the wiring board 301 can be made excellent easily and reliably.
  • the wiring board 301 is also reinforced by the first reinforcing member 4, and the rigidity of the entire semiconductor package 1 is increased.
  • the semiconductor element 3 and the wiring board 301 are in contact, the heat of the semiconductor element 3 can be efficiently released to the outside through the wiring board 301.
  • the top package 300 is prepared, and the top package 300 and the bottom package 500 are joined to each other by solder bonding via the metal bump 400A (metal bump 400).
  • the top package 300 and the bottom package 500 are pressurized in a direction approaching each other. Thereby, after the joining, the lower surface of the wiring substrate 301 of the top package 300 and the upper surface of the semiconductor element 3 of the bottom package 500 can be brought into contact with each other.
  • the semiconductor package 1 is obtained as described above.
  • FIG. 12 is a cross-sectional view schematically showing a semiconductor package according to the fifth embodiment of the present invention. Also, in FIG. 12, for convenience of explanation, each part of the semiconductor package is exaggerated.
  • the semiconductor package of the fifth embodiment will be described focusing on differences from the above-described embodiment, and description of similar matters will be omitted.
  • FIG. 12 the same components as those in the above-described embodiment are denoted by the same reference numerals.
  • the semiconductor package of the fifth embodiment is the same as that of the second embodiment except that the first semiconductor element and the second wiring board are in contact with each other.
  • the first reinforcing member 4 ⁇ / b> A is not in contact with the wiring board 301. Thereby, ventilation can be performed through the gap S formed between the first reinforcing member 4 ⁇ / b> A and the wiring board 301. Therefore, the heat dissipation of the semiconductor package 1A can be made excellent.
  • the first reinforcing member 4 ⁇ / b> A may partially have a portion in contact with the wiring substrate 301. Even in such a case, a gap for ventilation can be formed between the first reinforcing member 4 ⁇ / b> A and the wiring board 301.
  • the thickness of the first reinforcing member 4A is smaller than the total thickness of the semiconductor element 3 and the metal bump 31. Thereby, the gap S as described above can be easily and reliably formed.
  • the distance L between the first reinforcing member 4A and the wiring board 301 (that is, the length of the gap S in the thickness direction) L is 0.02 mm or more and 0.5 mm from the viewpoint of ensuring ventilation as described above. It is preferable that it is about the following.
  • FIG. 13 is a cross-sectional view schematically showing a semiconductor package according to the sixth embodiment of the present invention.
  • FIG. 13 for convenience of explanation, each part of the semiconductor package is exaggerated.
  • the semiconductor package of the sixth embodiment will be described focusing on the differences from the above-described embodiment, and description of similar matters will be omitted.
  • FIG. 13 the same reference numerals are given to the same configurations as those in the above-described embodiment.
  • the semiconductor package of the sixth embodiment is the same as that of the third embodiment except that the first semiconductor element and the second wiring board are in contact with each other.
  • FIG. 14 is a cross-sectional view schematically showing an example of an embodiment of a semiconductor device of the present invention.
  • the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.

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Abstract

This semiconductor package (1) comprises: a wiring board (2); a semiconductor element (3) joined to one surface of the wiring board (2); a first reinforcement member (4) that is joined to a section of the surface of the wiring board (2) on the semiconductor element (3) side where the semiconductor element (3) is not joined, and that has a smaller coefficient of thermal expansion than that of the wiring board (2); a wiring board (301) that is provided on the side opposite to the wiring board (2) with respect to the first reinforcement member (4), and that is joined to the wiring board (2) via at least two metal bumps (400); and a semiconductor element (305) joined to the surface of the wiring board (301) on the side opposite to the wiring board (2). The semiconductor element (3) either touches or does not touch the wiring board (301).

Description

半導体パッケージおよび半導体装置Semiconductor package and semiconductor device
 本発明は、半導体パッケージおよび半導体装置に関する。 The present invention relates to a semiconductor package and a semiconductor device.
 近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできており、これらの電子機器に使用される半導体パッケージは、従来にも増して益々小型化かつ多ピン化が進んできている。 In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.
 半導体パッケージはその小型化に伴って、従来のようなリードフレームを使用した形態のパッケージでは、小型化に限界がきている。そのため、最近では回路基板上にチップを実装したものとして、BGA(Ball Grid Array)や、CSP(Chip Scale Package)と言った、エリア実装型の新しいパッケージ方式が提案されている。 With the miniaturization of semiconductor packages, there is a limit to the miniaturization of conventional packages using lead frames. Therefore, a new area mounting type package system such as BGA (Ball Grid Array) or CSP (Chip Scale Package) has recently been proposed as a chip mounted on a circuit board.
 BGAやCSP等の新しいパッケージに用いられるインターポーザは、一般に、繊維基材に樹脂組成物を含浸してなる基板に導体パターンや導体ポストが形成されてなる。 Interposers used for new packages such as BGA and CSP are generally formed by forming a conductor pattern or a conductor post on a substrate obtained by impregnating a fiber base material with a resin composition.
 このようなインターポーザは、チップとの熱膨張係数差が大きい。また、インターポーザは、通常、チップよりも大面積となるため、チップと接触していない部分の面積が大きい。このようなチップと接触していない部分は、剛性が極めて低く、前述したようなチップとインターポーザの熱膨張差に起因して反りやすい。なお、本発明において熱膨張係数とは30~300℃の範囲において物体が1℃あたりに伸びる長さのことをいい、剛性とは板状物質の曲がりにくさのことをいう。 Such an interposer has a large difference in thermal expansion coefficient from the chip. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion that is not in contact with the tip is extremely low in rigidity, and tends to warp due to the difference in thermal expansion between the tip and the interposer as described above. In the present invention, the coefficient of thermal expansion means the length of the object extending per 1 ° C. in the range of 30 to 300 ° C., and the rigidity means the difficulty of bending the plate-like substance.
 ところで、インターポーザをそれぞれ備える2つのパッケージ(トップパッケージ、ボトムパッケージ)を重ねた構造、いわゆるPOP(Package On Package)構造の半導体パッケージが知られている。 By the way, there is known a semiconductor package having a so-called POP (Package On Package) structure in which two packages (top package and bottom package) each having an interposer are stacked.
 従来のPOP構造のパッケージでは、ボトムパッケージのインターポーザが前述したようなチップとの熱膨張差に起因して反りやすく、電気的接続信頼性を低下させるという問題があった。 In the conventional POP structure package, there is a problem that the interposer of the bottom package tends to warp due to the difference in thermal expansion from the chip as described above, and the electrical connection reliability is lowered.
 また、従来のPOP構造のパッケージにおいては、インターポーザ間に挟まれたチップの熱を効率よく逃すことができず、このようなことも前述したような問題を引き起こす要因となっていた。 Further, in the conventional POP structure package, the heat of the chip sandwiched between the interposers cannot be efficiently released, and this also causes the above-described problems.
特開2009-81261号公報JP 2009-81261 A
 本発明の目的は、熱による不具合の発生を防止することができる半導体パッケージおよび半導体装置を提供することである。 An object of the present invention is to provide a semiconductor package and a semiconductor device that can prevent the occurrence of defects due to heat.
 このような目的は、下記(1)~(25)の本発明により達成される。
 (1) 第1配線基板と、
 前記第1配線基板の一方の面に接合された第1半導体素子と、
 前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
 前記補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
 前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
 前記第1半導体素子は、前記第2配線基板に対して非接触であることを特徴とする半導体パッケージ。
Such an object is achieved by the present inventions (1) to (25) below.
(1) a first wiring board;
A first semiconductor element bonded to one surface of the first wiring board;
A reinforcing member bonded to a portion of the surface of the first wiring substrate on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring substrate;
A second wiring board provided on the side opposite to the first wiring board with respect to the reinforcing member and joined to the first wiring board via two or more metal bumps;
A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
 (2) 第1配線基板と、
 前記第1配線基板の一方の面に接合された第1半導体素子と、
 前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
 前記補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
 前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
 前記第1半導体素子は、前記第2配線基板に対して接触していることを特徴とする半導体パッケージ。
(2) a first wiring board;
A first semiconductor element bonded to one surface of the first wiring board;
A reinforcing member bonded to a portion of the surface of the first wiring substrate on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring substrate;
A second wiring board provided on the side opposite to the first wiring board with respect to the reinforcing member and joined to the first wiring board via two or more metal bumps;
A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
 (3) 第1配線基板と、
 前記第1配線基板の一方の面に接合された第1半導体素子と、
 前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
 前記第1半導体素子に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
 前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
 前記第1半導体素子は、前記第2配線基板に対して非接触であることを特徴とする半導体パッケージ。
(3) a first wiring board;
A first semiconductor element bonded to one surface of the first wiring board;
A reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
A second wiring board provided on the opposite side of the first wiring board with respect to the first semiconductor element and bonded to the first wiring board via two or more metal bumps;
A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
 (4) 第1配線基板と、
 前記第1配線基板の一方の面に接合された第1半導体素子と、
 前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
 前記第1半導体素子に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
 前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
 前記第1半導体素子は、前記第2配線基板に対して接触していることを特徴とする半導体パッケージ。
(4) a first wiring board;
A first semiconductor element bonded to one surface of the first wiring board;
A reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
A second wiring board provided on the opposite side of the first wiring board with respect to the first semiconductor element and bonded to the first wiring board via two or more metal bumps;
A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
 (5) 第1配線基板と、
 前記第1配線基板の一方の面に接合された第1半導体素子と、
 前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい第1補強部材と、
 前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい第2補強部材と、
 前記第1補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
 前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
 前記第1半導体素子は、前記第2配線基板に対して非接触であることを特徴とする半導体パッケージ。
(5) a first wiring board;
A first semiconductor element bonded to one surface of the first wiring board;
A first reinforcing member bonded to a portion of the surface of the first wiring board on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring board;
A second reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
A second wiring board provided on the opposite side of the first wiring board with respect to the first reinforcing member and joined to the first wiring board via two or more metal bumps;
A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
 (6) 第1配線基板と、
 前記第1配線基板の一方の面に接合された第1半導体素子と、
 前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい第1補強部材と、
 前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい第2補強部材と、
 前記第1補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
 前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
 前記第1半導体素子は、前記第2配線基板に対して接触していることを特徴とする半導体パッケージ。
(6) a first wiring board;
A first semiconductor element bonded to one surface of the first wiring board;
A first reinforcing member bonded to a portion of the surface of the first wiring board on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring board;
A second reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
A second wiring board provided on the opposite side of the first wiring board with respect to the first reinforcing member and joined to the first wiring board via two or more metal bumps;
A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
 (7) 前記第1補強部材は、前記第1半導体素子の周囲を囲むような形状をなす上記(5)または(6)に記載の半導体パッケージ。 (7) The semiconductor package according to (5) or (6), wherein the first reinforcing member has a shape surrounding the periphery of the first semiconductor element.
 (8) 前記第1半導体素子と前記第2配線基板との間の距離が0.01mm以上0.8mm以下である上記(1)、(3)、(5)および(7)のいずれかに記載の半導体パッケージ。 (8) In any one of (1), (3), (5) and (7) above, the distance between the first semiconductor element and the second wiring board is 0.01 mm or more and 0.8 mm or less. The semiconductor package described.
 (9) 前記第1補強部材は、前記第2配線基板に対して非接触である上記(5)ないし(8)のいずれかに記載の半導体パッケージ。 (9) The semiconductor package according to any one of (5) to (8), wherein the first reinforcing member is not in contact with the second wiring board.
 (10) 前記第1補強部材は、前記第2配線基板に対して接触している上記(6)または(7)に記載の半導体パッケージ。 (10) The semiconductor package according to (6) or (7), wherein the first reinforcing member is in contact with the second wiring board.
 (11) 前記第1補強部材と前記第2配線基板との間の距離は、前記前記第1半導体素子と前記第2配線基板との間の距離よりも大きい上記(9)に記載の半導体パッケージ。 (11) The semiconductor package according to (9), wherein a distance between the first reinforcing member and the second wiring board is larger than a distance between the first semiconductor element and the second wiring board. .
 (12) 前記第1補強部材は、前記各金属バンプに対して非接触で前記各金属バンプを囲むように形成された2つ以上の開口部を有する上記(5)ないし(11)のいずれかに記載の半導体パッケージ。 (12) Any of (5) to (11) above, wherein the first reinforcing member has two or more openings formed so as to surround the metal bumps in a non-contact manner with respect to the metal bumps. The semiconductor package described in 1.
 (13) 前記第1補強部材と前記各金属バンプとの間には、絶縁材が設けられている上記(5)ないし(12)のいずれかに記載の半導体パッケージ。 (13) The semiconductor package according to any one of (5) to (12), wherein an insulating material is provided between the first reinforcing member and each metal bump.
 (14) 前記第1補強部材および前記第2補強部材は、それぞれ、前記第1半導体素子との熱膨張係数差が7ppm/℃以下である上記(5)ないし(13)のいずれかに記載の半導体パッケージ。 (14) The first reinforcing member and the second reinforcing member according to any one of (5) to (13), wherein a difference in thermal expansion coefficient from the first semiconductor element is 7 ppm / ° C. or less. Semiconductor package.
 (15) 前記第1補強部材および前記第2補強部材は、それぞれ、板状をなす上記(5)ないし(14)のいずれかに記載の半導体パッケージ。 (15) The semiconductor package according to any one of (5) to (14), wherein each of the first reinforcing member and the second reinforcing member has a plate shape.
 (16) 前記第1補強部材および前記第2補強部材は、それぞれ、金属材料で構成されている上記(5)ないし(15)のいずれかに記載の半導体パッケージ。 (16) The semiconductor package according to any one of (5) to (15), wherein each of the first reinforcing member and the second reinforcing member is made of a metal material.
 (17) 前記金属材料は、Fe-Ni系合金である上記(16)に記載の半導体パッケージ。 (17) The semiconductor package according to (16), wherein the metal material is an Fe—Ni alloy.
 (18) 上記(1)ないし(17)のいずれかに記載の半導体パッケージを備えることを特徴とする半導体装置。 (18) A semiconductor device comprising the semiconductor package according to any one of (1) to (17).
 (19) 第1配線基板に第1補強部材を接合する工程と、
 前記第1配線基板に第1半導体素子を接合して、ボトムパッケージを形成する工程と、
 第2配線基板に第2半導体素子を接合して、トップパッケージを形成する工程と、
 2つ以上の金属バンプを介して、前記トップパッケージと前記ボトムパッケージとを接合する工程とを含む、
 上記(1)ないし(17)のいずれかに記載の半導体パッケージの製造方法。
(19) bonding the first reinforcing member to the first wiring board;
Bonding a first semiconductor element to the first wiring substrate to form a bottom package;
Bonding a second semiconductor element to a second wiring substrate to form a top package;
Joining the top package and the bottom package via two or more metal bumps,
The manufacturing method of the semiconductor package in any one of said (1) thru | or (17).
 (20) 第1配線基板に第2補強部材を接合する工程と、
 前記第1配線基板の前記第2補強部材とは反対側の面に、第1半導体素子を接合して、ボトムパッケージを形成する工程と、
 第2配線基板に第2半導体素子を接合して、トップパッケージを形成する工程と、
 2つ以上の金属バンプを介して、前記トップパッケージと前記ボトムパッケージとを接合する工程とを含む、
 上記(1)ないし(17)のいずれかに記載の半導体パッケージの製造方法。
(20) joining the second reinforcing member to the first wiring board;
Bonding a first semiconductor element to a surface of the first wiring board opposite to the second reinforcing member to form a bottom package;
Bonding a second semiconductor element to a second wiring substrate to form a top package;
Joining the top package and the bottom package via two or more metal bumps,
The manufacturing method of the semiconductor package in any one of said (1) thru | or (17).
 (21) 第1配線基板に第1補強部材を接合する工程と、
 前記第1配線基板に第2補強部材を接合する工程と、
 前記第1配線基板の前記第2補強部材とは反対側の面に、第1半導体素子を接合して、ボトムパッケージを形成する工程と、
 第2配線基板に第2半導体素子を接合して、トップパッケージを形成する工程と、
 2つ以上の金属バンプを介して、前記トップパッケージと前記ボトムパッケージとを接合する工程とを含む、
 上記(1)ないし(17)のいずれかに記載の半導体パッケージの製造方法。
(21) bonding the first reinforcing member to the first wiring board;
Bonding a second reinforcing member to the first wiring board;
Bonding a first semiconductor element to a surface of the first wiring board opposite to the second reinforcing member to form a bottom package;
Bonding a second semiconductor element to a second wiring substrate to form a top package;
Joining the top package and the bottom package via two or more metal bumps,
The manufacturing method of the semiconductor package in any one of said (1) thru | or (17).
 (22) 前記第1配線基板に第1補強部材を接合する工程が、
 金属層とプリプレグとの積層体を用意し、前記積層体のプリプレグ側の面に、第1補強部材を接合するサブ工程と、
 前記プリプレグに貫通孔を形成するサブ工程と、
 前記貫通孔に導体ポストを形成するサブ工程と、
 前記金属層をパターンニングすることにより、導体パターンを形成するサブ工程と、
 前記プリプレグを硬化させるサブ工程とを含む、
 上記(19)または(21)に記載の半導体パッケージの製造方法。
(22) The step of joining the first reinforcing member to the first wiring board includes:
Preparing a laminate of the metal layer and the prepreg, and joining the first reinforcing member to the prepreg side surface of the laminate;
A sub-process for forming a through hole in the prepreg;
A sub-step of forming a conductor post in the through hole;
A sub-process of forming a conductor pattern by patterning the metal layer;
A sub-step of curing the prepreg.
The manufacturing method of the semiconductor package as described in said (19) or (21).
 (23) 前記金属バンプの冷却に伴って、前記金属バンプが厚さ方向に膨張し、前記トップパッケージの第2配線基板と前記ボトムパッケージの第1半導体素子とが離間した状態となる、上記(19)ないし(22)のいずれかに記載の半導体パッケージの製造方法。 (23) With the cooling of the metal bumps, the metal bumps expand in the thickness direction, and the second wiring board of the top package and the first semiconductor element of the bottom package are separated from each other. 19) A method for manufacturing a semiconductor package according to any one of (22).
 (24) 前記トップパッケージと前記ボトムパッケージとの間にスペーサを配置し、前記トップパッケージと前記ボトムパッケージの接合後に、前記スペーサを取り除くことによって、前記トップパッケージの第2配線基板と前記ボトムパッケージの第1半導体素子とが離間した状態となる、上記(19)ないし(22)のいずれかに記載の半導体パッケージの製造方法。 (24) A spacer is disposed between the top package and the bottom package, and after the top package and the bottom package are joined, the spacer is removed, whereby the second wiring substrate of the top package and the bottom package are removed. The method for manufacturing a semiconductor package according to any one of (19) to (22), wherein the first semiconductor element is separated from the first semiconductor element.
 (25) 前記トップパッケージと前記ボトムパッケージとが互いに近づく方向にこれらを加圧して、前記トップパッケージの第2配線基板と前記ボトムパッケージの第1半導体素子とが接触した状態となる、上記(19)ないし(22)のいずれかに記載の半導体パッケージの製造方法。 (25) The top package and the bottom package are pressurized in a direction approaching each other, and the second wiring board of the top package and the first semiconductor element of the bottom package are in contact with each other (19 The manufacturing method of the semiconductor package in any one of (22) thru | or (22).
 本発明の半導体パッケージによれば、第1配線基板が補強部材により補強されるため(特に、補強部材が第1半導体素子と一体的となって第1配線基板を補強するため)、第1配線基板と第1半導体素子との熱膨張係数差に起因する反りを防止または抑制することができる。その結果、第2配線基板と第1配線基板を接続する金属バンプの接続信頼性、第1半導体素子と第1配線基板を接続する金属バンプの接続信頼性、配線基板内部の導体パターン・導体ポストの接続信頼性、および、第1配線基板とマザーボードを接続する金属バンプの接続信頼性が向上する。 According to the semiconductor package of the present invention, the first wiring board is reinforced by the reinforcing member (particularly, because the reinforcing member is integrated with the first semiconductor element to reinforce the first wiring board). Warpage due to a difference in thermal expansion coefficient between the substrate and the first semiconductor element can be prevented or suppressed. As a result, the connection reliability of the metal bumps connecting the second wiring board and the first wiring board, the connection reliability of the metal bumps connecting the first semiconductor element and the first wiring board, the conductor pattern / conductor post inside the wiring board And the connection reliability of the metal bumps connecting the first wiring board and the mother board are improved.
 また、本発明の半導体パッケージによれば、第1半導体素子と第2配線基板とが非接触である場合は、第1半導体素子と第2配線基板との間に形成された隙間を通じて通気を行い、第1半導体素子の熱を外方へ効率的に逃すことができる。一方、第1半導体素子と第2配線基板とが接触する場合は、第1半導体素子の熱を第2配線基板を通じて外方へ効率的に逃すことができる。また、第1配線基板が前述したように補強されていることから、第1配線基板自体の剛性を高める必要がなく、第1配線基板の厚さを薄くすることができる。そのため、第1配線基板の厚さ方向での熱伝導性を高め、第1半導体素子からの熱を第1配線基板を介して外方へ効率的に逃すこともできる。このようなことから、本発明の半導体パッケージは、放熱性に優れる。 According to the semiconductor package of the present invention, when the first semiconductor element and the second wiring board are not in contact with each other, ventilation is performed through a gap formed between the first semiconductor element and the second wiring board. The heat of the first semiconductor element can be efficiently released to the outside. On the other hand, when the first semiconductor element and the second wiring board are in contact, the heat of the first semiconductor element can be efficiently released to the outside through the second wiring board. Further, since the first wiring board is reinforced as described above, it is not necessary to increase the rigidity of the first wiring board itself, and the thickness of the first wiring board can be reduced. Therefore, the thermal conductivity in the thickness direction of the first wiring board can be increased, and the heat from the first semiconductor element can be efficiently released to the outside through the first wiring board. For these reasons, the semiconductor package of the present invention is excellent in heat dissipation.
 また、本発明の半導体装置によれば、前述したような半導体パッケージを備えるので、信頼性に優れる。 Moreover, according to the semiconductor device of the present invention, since the semiconductor package as described above is provided, the reliability is excellent.
本発明の第1実施形態に係る半導体パッケージを模式的に示す断面図である。1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention. 図1に示す半導体パッケージが備えるボトムパッケージを示す上面図である。It is a top view which shows the bottom package with which the semiconductor package shown in FIG. 1 is provided. 図1に示す半導体パッケージが備えるボトムパッケージを示す下面図である。It is a bottom view which shows the bottom package with which the semiconductor package shown in FIG. 1 is provided. 図1に示す半導体パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. 本発明の第2実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment of this invention. 本発明の第3実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 3rd Embodiment of this invention. 本発明の半導体装置の実施形態の一例を模式的に示す断面図である。It is sectional drawing which shows typically an example of embodiment of the semiconductor device of this invention. 本発明の第4実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 4th Embodiment of this invention. 図8に示す半導体パッケージが備えるボトムパッケージを示す上面図である。It is a top view which shows the bottom package with which the semiconductor package shown in FIG. 8 is provided. 図8に示す半導体パッケージが備えるボトムパッケージを示す下面図である。It is a bottom view which shows the bottom package with which the semiconductor package shown in FIG. 8 is provided. 図8に示す半導体パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. 本発明の第5実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 5th Embodiment of this invention. 本発明の第6実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 6th Embodiment of this invention. 本発明の半導体装置の実施形態の一例を模式的に示す断面図である。It is sectional drawing which shows typically an example of embodiment of the semiconductor device of this invention.
 以下、添付図面に基づき、本発明の半導体パッケージおよび半導体装置の好適な実施形態について説明するが、本発明はこれらの実施形態に限定されることはない。本発明の趣旨を逸脱しない範囲で、構成の付加、省略、置換、およびその他の変更が可能である。 Hereinafter, preferred embodiments of the semiconductor package and the semiconductor device of the present invention will be described with reference to the accompanying drawings, but the present invention is not limited to these embodiments. Additions, omissions, substitutions, and other modifications can be made without departing from the spirit of the present invention.
 <第1実施形態>
 (半導体パッケージ)
 まず、本発明の半導体パッケージを説明する。
<First Embodiment>
(Semiconductor package)
First, the semiconductor package of the present invention will be described.
 図1は、本発明の第1実施形態に係る半導体パッケージを模式的に示す断面図、図2は、図1に示す半導体パッケージを示す上面図、図3は、図1に示す半導体パッケージを示す下面図、図4は、図1に示す半導体パッケージの製造方法の一例を示す図である。なお、以下の説明では、説明の便宜上、図1中の上側を「上」、下側を「下」と言う。また、図1ないし4では、それぞれ、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a top view showing the semiconductor package shown in FIG. 1, and FIG. 3 shows the semiconductor package shown in FIG. FIG. 4 is a bottom view and FIG. 4 is a view showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIGS. 1 to 4, each part of the semiconductor package is exaggerated for convenience of explanation.
 図1に示すように、半導体パッケージ1は、配線基板2と、この配線基板2上に搭載された半導体素子3と、第1補強部材4と、第2補強部材5と、配線基板301と、この配線基板301上に搭載された半導体素子305と、配線基板2と配線基板301とを接続する複数の金属バンプ400とを有する。 As shown in FIG. 1, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member 4, a second reinforcing member 5, a wiring board 301, The semiconductor element 305 mounted on the wiring board 301 and a plurality of metal bumps 400 that connect the wiring board 2 and the wiring board 301 are provided.
 この半導体パッケージ1は、配線基板(第1配線基板)2に半導体素子(第1半導体素子)3を搭載したボトムパッケージ500と、配線基板(第2配線基板)301に半導体素子(第2半導体素子)305を搭載したトップパッケージ300とを重ねたPOP(Package On Package)構造を有する。 The semiconductor package 1 includes a bottom package 500 in which a semiconductor element (first semiconductor element) 3 is mounted on a wiring board (first wiring board) 2 and a semiconductor element (second semiconductor element) on a wiring board (second wiring board) 301. ) A POP (Package On Package) structure in which the top package 300 mounted with 305 is stacked.
 このような半導体パッケージ1によれば、半導体素子3と接合された部分以外の部分においても、配線基板2が第1補強部材4により補強されるため、ボトムパッケージ500全体の剛性が増す。特に、第1補強部材4の熱膨張係数が配線基板2(具体的には後述する基板21)よりも小さいため、半導体素子3が配線基板2の全面に亘って設けられているのと同様に、配線基板2と半導体素子3との熱膨張係数差に起因する配線基板2の反りを抑制または防止することができる。 According to such a semiconductor package 1, since the wiring board 2 is reinforced by the first reinforcing member 4 even in a portion other than the portion joined to the semiconductor element 3, the rigidity of the entire bottom package 500 is increased. In particular, since the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, a substrate 21 described later), the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. The warpage of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be suppressed or prevented.
 また、後述するように半導体素子3と配線基板301とが非接触であるため、半導体素子3と配線基板301との間に形成された隙間を通じて通気を行い、半導体素子3の熱を外方へ効率的に逃すことができる。また、配線基板2が前述したように補強されていることから、配線基板2自体の剛性を高める必要がなく、配線基板2の厚さを薄くすることができるので、配線基板2の厚さ方向での熱伝導性を高め、半導体素子3からの熱を配線基板2を介して逃すことができる。このようなことから、半導体パッケージ1は、放熱性に優れる。また、第1補強部材4および第2補強部材5の構成材料を適宜選択することにより、半導体パッケージ1の放熱性を高めることもできる。 Further, as will be described later, since the semiconductor element 3 and the wiring board 301 are not in contact with each other, air is ventilated through a gap formed between the semiconductor element 3 and the wiring board 301, and the heat of the semiconductor element 3 is moved outward. Can be missed efficiently. Further, since the wiring board 2 is reinforced as described above, it is not necessary to increase the rigidity of the wiring board 2 itself, and the thickness of the wiring board 2 can be reduced. Thus, the heat conductivity of the semiconductor element 3 can be increased and the heat from the semiconductor element 3 can be released through the wiring board 2. For this reason, the semiconductor package 1 is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
 このような半導体パッケージ1の優れた放熱性も相俟って、配線基板2と半導体素子3との熱膨張係数差に起因する配線基板2の反りを効果的に抑制または防止することができる。その結果、トップパッケージ300とボトムパッケージ500との間の電気的な接続信頼性を優れたものとすることができる。 Combined with such excellent heat dissipation of the semiconductor package 1, it is possible to effectively suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. As a result, the electrical connection reliability between the top package 300 and the bottom package 500 can be made excellent.
 また、半導体パッケージ1では、第2補強部材5を配線基板2の半導体素子3と反対側の面(下面)に接合することにより、配線基板2は半導体素子3と第2補強部材5とに挟持された状態となるため、配線基板2がより強固に補強されるとともに、配線基板2の両面の熱膨張差を抑制することができる。特に、第2補強部材は、後述する金属バンプ71間にも及ぶように設けられているので、配線基板2を強固に補強することができる。 Also, in the semiconductor package 1, the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5 by bonding the second reinforcing member 5 to the surface (lower surface) opposite to the semiconductor element 3 of the wiring board 2. Therefore, the wiring board 2 can be reinforced more strongly, and the difference in thermal expansion between both surfaces of the wiring board 2 can be suppressed. In particular, since the second reinforcing member is provided so as to extend between the metal bumps 71 described later, the wiring board 2 can be strongly reinforced.
 以下、半導体パッケージ1の各部を順次詳細に説明する。
 (ボトムパッケージ)
 ボトムパッケージ(第1パッケージ)500は、配線基板2と、半導体素子3と、第1補強部材4と、第2補強部材5とを有する。
Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
(Bottom package)
The bottom package (first package) 500 includes a wiring board 2, a semiconductor element 3, a first reinforcing member 4, and a second reinforcing member 5.
 [配線基板]
 配線基板2は、半導体素子3を支持する基板(第1配線基板)であり、例えば、その搭載した半導体素子3と後述するようなマザーボード200との電気的接続を中継する中継基板(インターポーザ)である。また、配線基板2は、その平面視形状は、通常、正方形、長方形等の四角形とされる。
[Wiring board]
The wiring board 2 is a board (first wiring board) that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later. is there. In addition, the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.
 配線基板2は、基板21と、導体パターン221、222、223、224と、導体ポスト231、232、233、234と、伝熱ポスト24とを有している。 The wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, 234, and heat transfer posts 24.
 なお、本実施形態では、導体パターン221は、基板21の一方の面側に設けられた第1導体パターンを構成し、導体パターン224は、基板21の他方の面側に設けられ、前記第1導体パターンと電気的に接続された第2導体パターンを構成する。 In this embodiment, the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21. A second conductor pattern electrically connected to the conductor pattern is formed.
 基板21は、複数(本実施形態では5層)の絶縁層211、212、213、214、215で構成されている。より具体的には、基板21は、絶縁層211、絶縁層212、絶縁層213、絶縁層214、絶縁層215がこの順で積層されて構成されている。なお、基板21を構成する絶縁層の数は、これに限定されず、1~4層であってもよいし、6層以上であってもよい。 The substrate 21 is composed of a plurality (five layers in this embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order. The number of insulating layers constituting the substrate 21 is not limited to this, and may be 1 to 4 layers or 6 or more layers.
 各絶縁層211、212、213、214、215は、絶縁性を有する材料で構成されている。 Each insulating layer 211, 212, 213, 214, 215 is made of an insulating material.
 具体的には、各絶縁層211、212、213、214、215は、基材(繊維基材)と、その基材に含浸された樹脂組成物とで構成されている。 Specifically, each insulating layer 211, 212, 213, 214, 215 is composed of a base material (fiber base material) and a resin composition impregnated in the base material.
 基材は、各絶縁層211、212、213、214、215の芯材として用いられる。このような基材を有することにより、基板21の剛性を高めることができる。 The base material is used as a core material of each insulating layer 211, 212, 213, 214, 215. By having such a base material, the rigidity of the substrate 21 can be increased.
 基材としては、例えば、ガラス織布、ガラス不織布等のガラス繊維で構成されたガラス繊維基材、ポリアミド樹脂繊維、芳香族ポリアミド樹脂繊維、全芳香族ポリアミド樹脂繊維等のポリアミド系樹脂繊維、ポリエステル樹脂繊維、芳香族ポリエステル樹脂繊維、全芳香族ポリエステル樹脂繊維等のポリエステル系樹脂繊維、ポリイミド樹脂繊維、フッ素樹脂繊維等を主成分とする織布または不織布で構成される合成繊維基材、クラフト紙、コットンリンター紙、リンターとクラフトパルプの混抄紙等を主成分とする紙基材等が挙げられる。これらの中でも、かかる基材としては、ガラス繊維基材が好ましい。これにより、基板21の剛性を高めるとともに、基板21の薄型化を図ることができる。さらに、基板2の熱膨張係数も小さくすることができる。 Examples of the base material include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthetic fiber base material, kraft paper composed of woven fabric or non-woven fabric mainly composed of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, etc. And paper base materials mainly composed of cotton linter paper, mixed paper of linter and kraft pulp, and the like. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Further, the thermal expansion coefficient of the substrate 2 can be reduced.
 このようなガラス繊維基材を構成するガラスとしては、例えば、Eガラス、Cガラス、Aガラス、Sガラス、Dガラス、NEガラス、Tガラス、Hガラス等が挙げられる。これらの中でもTガラスが好ましい。これにより、ガラス繊維基材の熱膨張係数を小さくすることができ、それによって基板21の熱膨張係数を小さくすることができる。 Examples of the glass constituting such a glass fiber substrate include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, and H glass. Among these, T glass is preferable. Thereby, the thermal expansion coefficient of a glass fiber base material can be made small, and, thereby, the thermal expansion coefficient of the board | substrate 21 can be made small.
 また、絶縁層211、212、213、214、215が基材を含む場合、絶縁層211、212、213、214、215における基材の含有率は、それぞれ、30~70wt%であることが好ましく、40~60wt%であることがより好ましい。これにより、これらの絶縁層のひび割れ等の破損を確実に防ぎつつ、各絶縁層の電気絶縁性および熱膨張係数を十分に低いものとすることができる。なお、絶縁層211、212、213、214、215のうちの少なくとも1層は、基材を含まずに樹脂組成物のみで構成されていてもよい。 When the insulating layers 211, 212, 213, 214, and 215 include a base material, the content of the base material in the insulating layers 211, 212, 213, 214, and 215 is preferably 30 to 70 wt%, respectively. 40 to 60 wt% is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers. Note that at least one of the insulating layers 211, 212, 213, 214, and 215 may be composed of only the resin composition without including the base material.
 このような基材に含浸される樹脂組成物は、樹脂材料が含まれている。かかる樹脂材料としては、熱硬化性樹脂が好適に用いられる。 The resin composition impregnated in such a base material contains a resin material. As such a resin material, a thermosetting resin is preferably used.
 前記熱硬化性樹脂としては、例えば、フェノールノボラック樹脂、クレゾールノボラック樹脂、ビスフェノールAノボラック樹脂等のノボラック型フェノール樹脂、未変性のレゾールフェノール樹脂、桐油、アマニ油、クルミ油等で変性した油変性レゾールフェノール樹脂等のレゾール型フェノール樹脂等のフェノール樹脂、ビスフェノールAエポキシ樹脂、ビスフェノールFエポキシ樹脂等のビスフェノール型エポキシ樹脂、ノボラックエポキシ樹脂、クレゾールノボラックエポキシ樹脂等のノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂等のエポキシ樹脂、シアネート樹脂、ユリア(尿素)樹脂、メラミン樹脂等のトリアジン環を有する樹脂、不飽和ポリエステル樹脂、ビスマレイミド樹脂、ポリウレタン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、ベンゾオキサジン環を有する樹脂、シアネートエステル樹脂等が挙げられる。 Examples of the thermosetting resin include novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like. Such as phenol resin, phenol resin such as resol type phenol resin, bisphenol type epoxy resin such as bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin such as novolac epoxy resin, cresol novolac epoxy resin, biphenyl type epoxy resin, etc. Epoxy resin, cyanate resin, urea (urea) resin, resin having triazine ring such as melamine resin, unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate Over preparative resin, silicone resin, resins having a benzoxazine ring, cyanate ester resins.
 これらの中でも、特に、シアネート樹脂が好ましい。これにより、基板21の熱膨張係数を十分に小さくすることができる。さらに、基板21の電気特性(低誘電率、低誘電正接等)を優れたものとすることができる。 Among these, cyanate resin is particularly preferable. Thereby, the thermal expansion coefficient of the board | substrate 21 can be made small enough. Furthermore, the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.
 また、前記樹脂組成物は、フィラーを含むのが好ましい。すなわち、絶縁層211、212、213、214、215は、それぞれ、フィラーを含むことが好ましい。これにより、絶縁層211、212、213、214、215の熱膨張係数を低くすることができる。なお、フィラーとは製造工程中および最終製品になった場合でも固形状態を保持する上記絶縁層を構成する物質である。 The resin composition preferably contains a filler. That is, each of the insulating layers 211, 212, 213, 214, and 215 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be lowered. The filler is a substance constituting the insulating layer that maintains a solid state even during the manufacturing process and when it becomes a final product.
 前記フィラーとしては、各種無機フィラーまたは有機フィラーが挙げられる。
 無機フィラー(無機充填材)としては、例えば、シリカ、アルミナ、ケイ藻土、酸化チタン、酸化鉄、酸化亜鉛、酸化マグネシウム、金属フェライト等の酸化物、水酸化アルミニウム、水酸化マグネシウム等の水酸化物、炭酸カルシウム(軽質、重質)、炭酸マグネシウム、ドロマイト、ドーソナイト等の炭酸塩、硫酸カルシウム、硫酸バリウム、硫酸アンモニウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、タルク、マイカ、クレー、ガラス繊維、ケイ酸カルシウム、モンモリロナイト、ベントナイト等のケイ酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、カーボンブラック、グラファイト、炭素繊維等の炭素、その他鉄粉、銅粉、アルミニウム粉、亜鉛華、硫化モリブデン、ボロン繊維、チタン酸カリウム、チタン酸ジルコン酸鉛が挙げられる。
Examples of the filler include various inorganic fillers or organic fillers.
Examples of the inorganic filler (inorganic filler) include oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, and hydroxide such as aluminum hydroxide and magnesium hydroxide. Products, calcium carbonate (light, heavy), carbonates such as magnesium carbonate, dolomite, dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber, silica Silicates such as calcium oxide, montmorillonite and bentonite, borate such as zinc borate, barium metaborate, aluminum borate, calcium borate and sodium borate, carbon such as carbon black, graphite and carbon fiber, other iron Powder, copper powder, aluminum powder, zinc white, sulfide Ribuden, boron fiber, potassium titanate, and a lead zirconate titanate.
 また、有機フィラーとしては、合成樹脂粉末が挙げられる。この合成樹脂粉末としては、例えば、アルキド樹脂、エポキシ樹脂、シリコーン樹脂、フェノール樹脂、ポリエステル、アクリル樹脂、アセタール樹脂、ポリエチレン、ポリエーテル、ポリカーボネート、ポリアミド、ポリスルホン、ポリスチレン、ポリ塩化ビニル、フッ素樹脂、ポリプロピレン、エチレン-酢酸ビニル共重合体等の各種熱硬化性樹脂または熱可塑性樹脂の粉末、またはこれらの樹脂の共重合体の粉末が挙げられる。また、有機フィラーの他の例としては、芳香族または脂肪族ポリアミド繊維、ポリプロピレン繊維、ポリエステル繊維、アラミド繊維等が挙げられる。 Further, as the organic filler, synthetic resin powder can be mentioned. Examples of the synthetic resin powder include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene. In addition, various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins may be mentioned. Other examples of organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.
 前述したようなフィラーの中でも、無機フィラーを用いるのが好ましい。これにより、絶縁層211、212、213、214、215の熱膨張係数を効果的に低めることができる。また、絶縁層211、212、213、214、215の伝熱性を高めることもできる。 Among the fillers as described above, it is preferable to use an inorganic filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be effectively reduced. In addition, the heat transfer properties of the insulating layers 211, 212, 213, 214, and 215 can be increased.
 特に、無機フィラーの中でも、シリカが好ましく、溶融シリカ(特に球状溶融シリカ)が低熱膨張性に優れる点で好ましい。 Particularly, among inorganic fillers, silica is preferable, and fused silica (especially spherical fused silica) is preferable in terms of excellent low thermal expansion.
 無機フィラーの平均粒子径は、特に限定されないが、0.05~2.0μmが好ましく、特に0.1~1.0μmが好ましい。これにより、絶縁層211、212、213、214、215中で、無機フィラーは、より均一に分散することができ、絶縁層211、212、213、214、215の物理的強度および絶縁性を特に優れたものとすることができる。 The average particle size of the inorganic filler is not particularly limited, but is preferably 0.05 to 2.0 μm, particularly preferably 0.1 to 1.0 μm. As a result, the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, 213, 214, and 215, and the physical strength and insulating properties of the insulating layers 211, 212, 213, 214, and 215 are particularly improved. It can be excellent.
 なお、上記無機フィラーの平均粒子径は、例えば、粒度分布計(HORIBA製、LA-500)により測定することができる。また、本明細書において、平均粒子径とは、体積基準での平均粒子径を指す。 The average particle size of the inorganic filler can be measured by, for example, a particle size distribution meter (manufactured by HORIBA, LA-500). Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.
 絶縁層211、212、213、214、215における無機充填材の含有量は、それぞれ、特に限定されないが、基材を除く樹脂組成物を100wt%としたときに、30~80wt%が好ましく、特に45~75wt%が好ましい。含有量が前記範囲内であると、絶縁層211、212、213、214、215は、熱膨張係数が十分に低く、吸湿性が特に低いものとなる。 The content of the inorganic filler in the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but is preferably 30 to 80 wt% when the resin composition excluding the base material is 100 wt%, particularly 45 to 75 wt% is preferable. When the content is within the above range, the insulating layers 211, 212, 213, 214, and 215 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.
 また、前記樹脂組成物は、前述した熱硬化性樹脂の他、フェノキシ樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ポリフェニレンオキサイド樹脂、ポリエーテルスルホン樹脂等の熱可塑性樹脂含んでいてもよい。 The resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin in addition to the thermosetting resin described above.
 また、前記樹脂組成物は、必要に応じて、顔料、酸化防止剤等の上記成分以外の添加物を含んでいてもよい。 The resin composition may contain additives other than the above components such as pigments and antioxidants as necessary.
 また、絶縁層211、212、213、214、215は、互いに同じ材料で構成されていてもよいし、互いに異なる材料で構成されていてもよい。 In addition, the insulating layers 211, 212, 213, 214, and 215 may be made of the same material as each other, or may be made of different materials.
 上述したような複数の層で構成された基板21の平均厚さは、特に限定されないが、30μm以上800μm以下であることが好ましく、30μm以上400μm以下であることがより好ましい。 The average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 μm or more and 800 μm or less, and more preferably 30 μm or more and 400 μm or less.
 このような基板21の絶縁層211と絶縁層212の間には、導体パターン221が介挿されている。また、絶縁層212と絶縁層213との間には、導体パターン222が介挿されている。また、絶縁層213と絶縁層214との間には、導体パターン223が介挿されている。また、絶縁層214と絶縁層215との間には、導体パターン224が介挿されている。また、絶縁層211の上面上には、導体パターン225が設けられている。 The conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21. In addition, a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213. A conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214. A conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215. A conductor pattern 225 is provided on the upper surface of the insulating layer 211.
 この導体パターン221、222、223、224、225は、それぞれ、複数の配線を有する回路として機能する。 The conductor patterns 221, 222, 223, 224, and 225 each function as a circuit having a plurality of wirings.
 導体パターン221、222、223、224、225の構成材料としては、導電性を有するものであれば、特に限定されず、例えば、銅、銅系合金、アルミ、アルミ系合金等の各種金属および各種合金が挙げられる。中でも、かかる構成材料としては、銅および銅系合金を用いるのが好ましい。銅および銅系合金は、電気伝導率が比較的高い。そのため、配線基板2の電気的特性を良好なものとすることができる。また、銅および銅系合金は熱伝導性にも優れるので、配線基板2の放熱性を向上させることもできる。 The constituent material of the conductor patterns 221, 222, 223, 224, 225 is not particularly limited as long as it has conductivity. For example, various metals such as copper, copper-based alloys, aluminum, aluminum-based alloys, and various types An alloy is mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have a relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
 また、導体パターン221、222、223、224、225の平均厚さは、特に限定されないが、5μm以上30μm以下であることが好ましい。 The average thickness of the conductor patterns 221, 222, 223, 224, and 225 is not particularly limited, but is preferably 5 μm or more and 30 μm or less.
 また、絶縁層211には、その厚さ方向に貫通するビアホールが形成され、そのビアホール内に導体ポスト(ビアポスト)231が設けられている。この導体ポスト231は、絶縁層211をその厚さ方向に貫通しており、上端部が半導体素子3に金属バンプ31を介して接続されるとともに、下端部が導体パターン221に接続されている。これにより、導体パターン221と半導体素子3とが導通している。なお、ビアホールとは絶縁層の上の回路と下の回路を導通させるための貫通もしくは有底の穴のことである。 Further, a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole. The conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected. A via hole is a through-hole or bottomed hole for conducting a circuit above an insulating layer and a circuit below.
 また、図示しないが、絶縁層211には、導体パターン221と導体パターン225とを導通させる導体ポスト(ビアポスト)が厚さ方向に貫通している。導体パターン225の基板21の上面上には、複数の金属バンプ400が接合されている。 Although not shown, the insulating layer 211 has a conductor post (via post) passing through the conductor pattern 221 and the conductor pattern 225 in the thickness direction. On the upper surface of the substrate 21 of the conductor pattern 225, a plurality of metal bumps 400 are bonded.
 この各金属バンプ400は、トップパッケージ300とボトムパッケージ500との電気的接続(より具体的には配線基板2と配線基板301との電気的接続)を行う。また、各金属バンプ400は、配線基板2と配線基板301との機械的接続(固定)を行う機能をも有する。 Each metal bump 400 makes electrical connection between the top package 300 and the bottom package 500 (more specifically, electrical connection between the wiring board 2 and the wiring board 301). Each metal bump 400 also has a function of performing mechanical connection (fixation) between the wiring board 2 and the wiring board 301.
 この複数の金属バンプ400は、配線基板2の外周部に沿って間隔を隔てて配置されている。 The plurality of metal bumps 400 are arranged along the outer peripheral portion of the wiring board 2 at intervals.
 本実施形態では、各金属バンプ400は、略球状をなしている。なお、各金属バンプ400の形状は、これに限定されない。また、各金属バンプ400の大きさ(直径)は、後述するように半導体素子3と配線基板301とが非接触となる程度に設定される。 In the present embodiment, each metal bump 400 has a substantially spherical shape. The shape of each metal bump 400 is not limited to this. In addition, the size (diameter) of each metal bump 400 is set to such an extent that the semiconductor element 3 and the wiring board 301 are not in contact with each other as will be described later.
 また、金属バンプ400の構成材料としては、特に限定されないが、例えば、錫-鉛系、錫-銀系、錫-亜鉛系、錫-ビスマス系、錫-アンチモン系、錫-銀-ビスマス系、錫-銅系、錫-銀-銅系等の各種ろう材(半田)を用いることができる。 Further, the constituent material of the metal bump 400 is not particularly limited. For example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, Various brazing materials (solder) such as tin-copper and tin-silver-copper can be used.
 また、絶縁層212には、その厚さ方向に貫通する導体ポスト(ビアポスト)232が設けられている。この導体ポスト232は、上端部が導体パターン221に接続されるとともに、下端部が導体パターン222に接続されている。これにより、導体パターン221と導体パターン222とが導通している。 The insulating layer 212 is provided with a conductor post (via post) 232 that penetrates in the thickness direction. The conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.
 また、絶縁層213には、その厚さ方向に貫通する導体ポスト(ビアポスト)233が設けられている。この導体ポスト233は、上端部が導体パターン222に接続されるとともに、下端部が導体パターン223に接続されている。これにより、導体パターン222と導体パターン223とが導通している。 The insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction. The conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.
 また、絶縁層214には、その厚さ方向に貫通する導体ポスト(ビアポスト)234が設けられている。この導体ポスト234は、上端部が導体パターン223に接続されるとともに、下端部が導体パターン224に接続されている。これにより、導体パターン223と導体パターン224とが導通している。 Also, the insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction. The conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.
 また、絶縁層215には、その厚さ方向に貫通する複数の開口部が設けられ、その各開口部から導体パターン224の一部(端子)が露出している。その導体パターン224の露出した各部分(端子)上には、金属バンプ71が接合されている。すなわち、第2導体パターンである導体パターン224の基板21と反対側の面には、複数の金属バンプ71が接合されている。 The insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening. Metal bumps 71 are bonded onto the exposed portions (terminals) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21.
 この金属バンプ71は、半導体パッケージ1を例えば後述するようなマザーボードに対して電気的に接続する。 The metal bump 71 electrically connects the semiconductor package 1 to, for example, a motherboard as described later.
 本実施形態では、金属バンプ71は、略球状をなしている。なお、金属バンプ71の形状は、これに限定されない。 In this embodiment, the metal bump 71 has a substantially spherical shape. The shape of the metal bump 71 is not limited to this.
 金属バンプ71の構成材料としては、特に限定されないが、例えば、錫-鉛系、錫-銀系、錫-亜鉛系、錫-ビスマス系、錫-アンチモン系、錫-銀-ビスマス系、錫-銅系、錫-銀-銅系等の各種ろう材(半田)を用いることができる。 The constituent material of the metal bump 71 is not particularly limited. For example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin-- Various brazing materials (solder) such as copper and tin-silver-copper can be used.
 また、基板21には、その厚さ方向に全域に亘って貫通する複数のビアホールが形成され、その各ビアホールに伝熱ポスト24が設けられている。 The substrate 21 is formed with a plurality of via holes penetrating over the entire area in the thickness direction, and a heat transfer post 24 is provided in each via hole.
 この各伝熱ポスト24は、基板21全体をその厚さ方向に貫通しており、上端が基板21の上面から露出するとともに、下端が基板21の下面から露出している。伝熱ポスト24は、上端が第1補強部材4に接触し、下端が第2補強部材5に接触している。これにより、各伝熱ポスト24は、第1補強部材4と第2補強部材5とを接続している。 Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the substrate 21 and its lower end is exposed from the lower surface of the substrate 21. The heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5. Thus, each heat transfer post 24 connects the first reinforcing member 4 and the second reinforcing member 5.
 この各伝熱ポスト(熱伝導部)24は、前述した基板21(絶縁層)よりも高い伝熱性を有する。これにより、第1補強部材4から伝熱ポスト24を介して第2補強部材5へ熱を効率的に伝達することができる。その結果、半導体パッケージ1の放熱性を向上させることができる。 Each of the heat transfer posts (heat conducting portions) 24 has higher heat transfer performance than the substrate 21 (insulating layer) described above. Thereby, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.
 また、この各伝熱ポスト24は、基板21をその厚さ方向に貫通するため、公知の導体ポストと同様に、簡単かつ高精度に形成することができる。 In addition, since each of the heat transfer posts 24 penetrates the substrate 21 in the thickness direction, the heat transfer posts 24 can be formed easily and with high accuracy in the same manner as known conductor posts.
 また、各伝熱ポスト24は、中空であってもよいし、中実であってもよい。また、各伝熱ポスト24の横断面形状としては、特に限定されず、例えば、円形、楕円形、多角形等が挙げられる。また、伝熱ポスト24の数は、特に限定されず、任意であるが、配線基板2の機械的強度を損ねない程度に、できるだけ多くするのが好ましい。 Further, each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post | mailbox 24, For example, circular, an ellipse, a polygon etc. are mentioned. Further, the number of heat transfer posts 24 is not particularly limited and is arbitrary, but is preferably as large as possible so as not to impair the mechanical strength of the wiring board 2.
 また、各伝熱ポスト24は、電気信号の伝送に寄与しない。これにより、第1補強部材4から伝熱ポスト24を介して第2補強部材5へ熱をより効率的に伝達することができる。 Also, each heat transfer post 24 does not contribute to the transmission of electrical signals. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 through the heat transfer post 24.
 本実施形態では、複数の伝熱ポスト24は、配線基板2を平面視したときに、配線基板2の外周部に沿って互いに間隔を隔てて並設されている。特に、複数の伝熱ポスト24は、配線基板2を平面視したときに、配線基板2の外周部に沿って周方向に等間隔で並設されているのが好ましい。これにより、配線基板2の温度分布を均一化することができる。 In the present embodiment, the plurality of heat transfer posts 24 are arranged in parallel along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan. In particular, the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.
 また、複数の伝熱ポスト24は、配線基板2を平面視したときに、前述した導体パターン221、222、223、224、225に重ならないように設けられている。これにより、伝熱ポスト24の形成が簡単となるとともに、伝熱ポスト24による導体パターン221、222、223、224、225の短絡を防止することができる。 Further, the plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, 224, 225 described above when the wiring board 2 is viewed in plan. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit of the conductor patterns 221, 222, 223, 224, and 225 by the heat transfer post 24 can be prevented.
 このような各伝熱ポスト24の構成材料としては、前述した基板21(絶縁層)よりも高い伝熱性を有するものであれば、特に限定されないが、金属材料を用いるのが好ましい。 The constituent material of each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.
 かかる金属材料としては、例えば、銅、銅系合金、アルミ、アルミ系合金等の各種金属および各種合金が挙げられる。中でも、かかる金属材料としては、伝熱性に優れるので、銅、銅系合金、アルミ、アルミ系合金を用いるのが好ましい。 Examples of such metal materials include various metals and various alloys such as copper, copper-based alloys, aluminum, and aluminum-based alloys. Among these, as such a metal material, it is preferable to use copper, a copper-based alloy, aluminum, or an aluminum-based alloy because of excellent heat conductivity.
 また、伝熱ポスト24の構成材料は、前述した導体ポスト231~234の構成材料と異なっていてもよいが、導体ポスト231~234の構成材料(特に導体ポスト234の構成材料)と同じであるのが好ましい。これにより、伝熱ポスト24を導体ポスト234の形成と同時に一括して形成することができる。そのため、半導体パッケージ1の製造が簡単化され、また、半導体パッケージ1を安価なものとすることができる。 The constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 234 described above, but is the same as the constituent material of the conductor posts 231 to 234 (particularly, the constituent material of the conductor posts 234). Is preferred. As a result, the heat transfer posts 24 can be formed simultaneously with the formation of the conductor posts 234. Therefore, the manufacturing of the semiconductor package 1 is simplified, and the semiconductor package 1 can be made inexpensive.
 [半導体素子]
 半導体素子(第1半導体素子)3は、例えば、集積回路素子(IC)であり、より具体的には、例えば、ロジックIC、メモリおよび受発光素子等である。
[Semiconductor element]
The semiconductor element (first semiconductor element) 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light emitting / receiving element.
 この半導体素子3は、前述した配線基板2の基板21の上面(一方の面)に接合され、第1導体パターンである導体パターン221に電気的に接続されている。 The semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
 具体的には、半導体素子3は、その下面に、図示しない複数の端子が設けられており、その各端子が金属バンプ31を介して、前述した配線基板2の導体ポスト231に電気的に接続されている。これにより、半導体素子3と配線基板2の導体パターン221とが電気的に接続されている。 Specifically, the semiconductor element 3 is provided with a plurality of terminals (not shown) on its lower surface, and each terminal is electrically connected to the conductor post 231 of the wiring board 2 described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2 are electrically connected.
 金属バンプ31の構成材料としては、特に限定されないが、前述した金属バンプ71と同様、例えば、錫-鉛系、錫-銀系、錫-亜鉛系、錫-ビスマス系、錫-アンチモン系、錫-銀-ビスマス系、錫-銅系、錫-銀-銅系等の各種ろう材(半田)を用いることができる。 The constituent material of the metal bump 31 is not particularly limited, but is similar to the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin Various brazing materials (solder) such as silver-bismuth, tin-copper, tin-silver-copper can be used.
 また、半導体素子3は、接着層32を介して、配線基板2の上面に接着(接合)されている。 Further, the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 through the adhesive layer 32.
 この接着層32は、接着性および絶縁性を有する材料で構成され、例えば、アンダーフィル材の硬化物で構成されている。 The adhesive layer 32 is made of a material having adhesiveness and insulating properties, for example, a cured product of an underfill material.
 アンダーフィル材としては、特に限定されず、公知のアンダーフィル材を用いることができるが、後述する絶縁材81を形成するための半田接合用レジストと同様のものを用いることもできる。 The underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.
 [第1補強部材]
 第1補強部材(スティフナー)4は、前述した配線基板2の基板21の上面(一方の面)の、半導体素子3が接合されていない部分に接合されている。
[First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.
 この第1補強部材4と基板21とは、例えば接着剤を介して接合することができる。これにより、第1補強部材4の設置が簡単となる。 The first reinforcing member 4 and the substrate 21 can be joined through an adhesive, for example. Thereby, installation of the 1st reinforcement member 4 becomes easy.
 かかる接着剤としては、接着機能を有するものであれば、特に限定されず、各種接着剤を用いることができるが、熱伝導性に優れたものが好ましく、後述する熱伝導性材料6と同様のものを用いることができる。 Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.
 この第1補強部材4は、基板21よりも熱膨張係数が小さい。これにより、基板21の熱膨張を抑えることができる。 The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.
 また、第1補強部材4は、板状をなしている。これにより、第1補強部材4の構成を簡単かつ小型なものとすることができる。 The first reinforcing member 4 has a plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.
 本実施形態では、第1補強部材4の基板21と反対側の面(すなわち上面)と、半導体素子3の基板21と反対側の面(すなわち上面)とが同一面上に位置している。これにより、半導体パッケージ1を薄型化しつつ、配線基板2の反りを効果的に抑制または防止することができる。また、第1補強部材4の上面上にトップパッケージ300の配線基板301を設置する際、その設置を安定的に行うことができる。また、半導体パッケージ1の製造に際し、第1補強部材4の設置後に半導体素子3を設置する場合、半導体素子3の設置が容易となる。 In the present embodiment, the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface. Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Further, when installing the wiring board 301 of the top package 300 on the upper surface of the first reinforcing member 4, the installation can be performed stably. Further, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the semiconductor element 3 can be easily installed.
 また、第1補強部材4は、半導体素子3の周囲を囲むような形状をなしている。本実施形態では、第1補強部材4は、半導体素子3を囲むように環状(より具体的には四角環状)をなしている。これにより、第1補強部材4と半導体素子3との一体性が増し、第1補強部材4による配線基板2の剛性を高める効果を優れたものとすることができる。 The first reinforcing member 4 has a shape surrounding the semiconductor element 3. In the present embodiment, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the effect which improves the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.
 また、図2に示すように、第1補強部材4には、その厚さ方向に貫通する複数の開口部42が形成されている。この各開口部42内には、前述した金属バンプ400が配置されている。 Further, as shown in FIG. 2, the first reinforcing member 4 is formed with a plurality of openings 42 penetrating in the thickness direction. In each opening 42, the metal bump 400 described above is arranged.
 本実施形態では、各開口部42は、それぞれ、各金属バンプ400に対して一対一で対応して設けられている。各開口部42は、各金属バンプ400に対して非接触で各金属バンプ400を囲むように形成されている。このように開口部42内に金属バンプ400を配置することにより、複数の金属バンプ400を介した配線基板2と配線基板301との接合を許容しつつ、第1補強部材4の平面視での面積を大きくすることができる。 In the present embodiment, each opening 42 is provided in one-to-one correspondence with each metal bump 400. Each opening 42 is formed so as to surround each metal bump 400 without contacting each metal bump 400. By disposing the metal bumps 400 in the openings 42 in this way, it is possible to join the wiring board 2 and the wiring board 301 via the plurality of metal bumps 400 while the first reinforcing member 4 is seen in a plan view. The area can be increased.
 また、図2に示すように、第1補強部材4と各金属バンプ400との間(開口部42の壁面と金属バンプ400との間)には、絶縁材401が設けられている。これにより、第1補強部材4が導電性を有する場合であっても、金属バンプ400同士の短絡を防止することができる。絶縁材401を第1補強部材4と各金属バンプ400との間に充填することにより、第1補強部材4と各金属バンプ400との一体性が増すとともに、第1補強部材4と各金属バンプ400との間の熱伝導性を高めることができる。 Further, as shown in FIG. 2, an insulating material 401 is provided between the first reinforcing member 4 and each metal bump 400 (between the wall surface of the opening 42 and the metal bump 400). Thereby, even if it is a case where the 1st reinforcement member 4 has electroconductivity, the short circuit between metal bumps 400 can be prevented. By filling the insulating material 401 between the first reinforcing member 4 and each metal bump 400, the integrity of the first reinforcing member 4 and each metal bump 400 is increased, and the first reinforcing member 4 and each metal bump 400 are increased. The thermal conductivity between 400 can be increased.
 また、絶縁材401は、金属バンプ400の基板21側の部分(下部)の周囲を囲むような形状をなし、かつ、各金属バンプ400に接合されている。これにより、絶縁材401は、金属バンプ400を補強している。 Further, the insulating material 401 is shaped to surround the periphery (lower part) of the metal bump 400 on the substrate 21 side, and is joined to each metal bump 400. Thereby, the insulating material 401 reinforces the metal bump 400.
 また、絶縁材401は、前述した配線基板2の基板21よりも高い熱伝導性を有するのが好ましい。これにより、金属バンプ400と第1補強部材4との間の熱伝導性を優れたものとし、半導体パッケージ1の放熱性を向上させることができる。 The insulating material 401 preferably has higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 400 and the first reinforcing member 4 is excellent, and the heat dissipation of the semiconductor package 1 can be improved.
 このような絶縁材401は、絶縁性を有し、樹脂材料を含んで構成され、特に限定されないが、後述する絶縁材81と同様、例えば、熱硬化性を有する半田接合用樹脂により形成されるのが好ましい。 Such an insulating material 401 has an insulating property and includes a resin material, and is not particularly limited. However, like the insulating material 81 described later, the insulating material 401 is formed of, for example, a thermosetting solder bonding resin. Is preferred.
 また、第1補強部材4は、各金属バンプ400との間の距離(平面視における開口部42の壁面と金属バンプ400の外周面との間の距離)が金属バンプ400の全周に亘って一定となるように形成されている。これにより、第1補強部材4および各金属バンプ400の一体性が増し、これらによる配線基板2の補強効果が好適に発揮される。 Further, the distance between the first reinforcing member 4 and each metal bump 400 (the distance between the wall surface of the opening 42 and the outer peripheral surface of the metal bump 400 in plan view) extends over the entire circumference of the metal bump 400. It is formed to be constant. Thereby, the integrity of the 1st reinforcement member 4 and each metal bump 400 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.
 また、第1補強部材4は、半導体素子3との間の距離(第1補強部材4の内周面41と半導体素子3の外周面33との間の距離)が半導体素子3の全周に亘って一定となるように形成されている。これにより、第1補強部材4および半導体素子3の一体性が増し、これらによる配線基板2の補強効果が好適に発揮される。また、後述する熱伝導性材料6を介した半導体素子3から第1補強部材への伝熱を効率的かつ均一に生じさせることができる。 Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.
 また、第1補強部材4は、半導体素子3との熱膨張係数差が7ppm/℃以下であるのが好ましい。これにより、半導体素子3および第1補強部材4が一体的に配線基板2を補強し、ボトムパッケージ500全体の熱膨張を抑えることができる。 Moreover, it is preferable that the first reinforcing member 4 has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the bottom package 500 whole.
 また、第1補強部材4の構成材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、例えば、金属材料、セラミックス材料等を用いることができるが、金属材料を用いるのが好ましい。第1補強部材4が金属材料で構成されていると、第1補強部材4の放熱性を高めることができる。その結果、ボトムパッケージ500の放熱性を向上させることができる。 In addition, the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above. For example, a metal material, a ceramic material, or the like can be used. It is preferable to use it. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the bottom package 500 can be improved.
 かかる金属材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、各種金属材料を用いることができるが、放熱性および低熱膨張を実現する観点から、Feを含む合金を用いるのが好ましい。 Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
 かかるFeを含む合金としては、例えば、Fe-Ni系合金、Fe-Co-Cr系合金、Fe-Co系合金、Fe-Pt系合金、Fe-Pd合金等が挙げられ、特に、Fe-Ni系合金を用いるのが好ましい。 Examples of such alloys containing Fe include Fe—Ni alloys, Fe—Co—Cr alloys, Fe—Co alloys, Fe—Pt alloys, Fe—Pd alloys, and the like. It is preferable to use a base alloy.
 このような金属材料は、放熱性に優れるだけでなく、熱膨張係数が低く、かつ、一般的な半導体素子3の熱膨張係数に近い熱膨張係数を有する。そのため、半導体素子3および第1補強部材4が一体的に配線基板2を補強することができる。 Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.
 Fe-Ni系合金としては、FeおよびNiを含むものであれは、特に限定されず、FeおよびNiの他に、残部(M)として、Co、Ti、Mo、Cr、Pd、Pt等の金属のうちの1種または2種以上の金属を含んでいてもよい。 The Fe—Ni alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.
 より具体的には、Fe-Ni系合金としては、例えば、Fe-36Ni合金(インバー)等のFe-Ni合金、Fe-32Ni-5Co合金(スーパーインバー)、Fe-29Ni-17Co合金(コバール)、Fe-36Ni-12Co合金(エリンバー)等のFe-Ni-Co合金、Fe-Ni-Cr-Ti合金、Ni-28Mo-2Fe合金等のNi-Mo-Fe合金等が挙げられる。また、Fe-Ni-Co合金は、例えば、KV-2、KV-4、KV-6、KV-15、KV-25等のKVシリーズ(NEOMAXマテリアル社製)、Nivarox等の商品名で市販されている。また、Fe-Ni合金は、例えば、NS-5、D-1(NEOMAXマテリアル社製)等の商品名で市販されている。また、Fe-Ni-Cr-Ti合金は、例えば、Ni-Span C-902(大同スペシャルメタル社製)、EL-3(NEOMAXマテリアル社製)等の商品名で市販されている。 More specifically, examples of Fe—Ni alloys include Fe—Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar). Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy. In addition, Fe—Ni—Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, KV-25, and Nivarox. ing. In addition, Fe—Ni alloys are commercially available under trade names such as NS-5 and D-1 (manufactured by NEOMAX Materials). Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal Co., Ltd.), EL-3 (manufactured by NEOMAX Material Co., Ltd.), and the like.
 また、Fe-Co-Cr系合金としては、Fe、CoおよびCrを含むものであれは、特に限定されないが、例えば、Fe-54Co-9.5Cr(ステンレスインバー)等のFe-Co-Cr合金が挙げられる。なお、Fe-Co-Cr系合金は、Fe、CoおよびCrの他に、Ni、Ti、Mo、Pd、Pt等の金属のうちの1種または2種以上の金属を含んでいてもよい。 Further, the Fe—Co—Cr-based alloy is not particularly limited as long as it contains Fe, Co, and Cr. For example, an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is available. Is mentioned. Note that the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.
 また、Fe-Co系合金としては、FeおよびCoを含むものであれは、特に限定されず、FeおよびCoの他に、Ni、Ti、Mo、Cr、Pd、Pt等の金属のうちの1種または2種以上の金属を含んでいてもよい。 Further, the Fe—Co alloy is not particularly limited as long as it contains Fe and Co, and in addition to Fe and Co, one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt. It may contain seeds or two or more metals.
 また、Fe-Pt系合金としては、FeおよびPtを含むものであれは、特に限定されず、FeおよびPtの他に、Co、Ni、Ti、Mo、Cr、Pd等の金属のうちの1種または2種以上の金属を含んでいてもよい。 Further, the Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt. In addition to Fe and Pt, one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. It may contain seeds or two or more metals.
 また、Fe-Pd系合金としては、FeおよびPdを含むものであれは、特に限定されず、FeおよびPdの他に、Co、Ni、Ti、Mo、Cr、Pt等の金属のうちの1種または2種以上の金属を含んでいてもよい。 Further, the Fe—Pd alloy is not particularly limited as long as it contains Fe and Pd. In addition to Fe and Pd, one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.
 特に、第1補強部材4の熱膨張係数は、0.5ppm/℃以上10ppm/℃以下であるのが好ましく、1ppm/℃以上7ppm/℃以下であるのがより好ましく、1ppm/℃以上5ppm/℃以下であるのがさらに好ましい。これにより、半導体素子3と第1補強部材4との熱膨張係数差を小さくし、これらが一体として配線基板2を補強することができる。そのため、配線基板2の反りを効果的に防止することができる。 In particular, the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
 また、第1補強部材4と半導体素子3との熱膨張係数差の絶対値は、7ppm/℃以下であるのが好ましく、5ppm/℃以下であるのがより好ましく、2ppm/℃以下であるのがさらに好ましい。これにより、半導体素子3と第1補強部材4との熱膨張係数差を小さくし、これらが一体として配線基板2を補強することができる。そのため、配線基板2の反りを効果的に防止することができる。 The absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
 上述したような熱膨張係数の観点から、第1補強部材4を構成する金属材料がFe-Ni系合金である場合、前記Fe-Ni系合金は、Niの含有量が30wt%以上50wt%以下であるのが好ましく、Niの含有量が35wt%以上45wt%以下であるのがより好ましい。これにより、第1補強部材4の熱膨張係数を半導体素子3の熱膨張係数に近づけることができる。この場合、前記Fe-Ni系合金は、Feの含有量が50wt%以上70wt%以下であるのが好ましく、Feの含有量が55wt%以上65wt%以下であるのがより好ましい。 From the viewpoint of the thermal expansion coefficient as described above, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
 また、第1補強部材4を構成する金属材料がFe-Ni系合金である場合、前記Fe-Ni系合金は、FeおよびNiの合計含有量が85wt%以上100wt%以下であるのが好ましく、FeおよびNiの合計含有量が90wt%以上100wt%以下であるのがより好ましい。すなわち、前記Fe-Ni系合金は、残部(M)の含有量が0wt%以上15wt%以下であるのが好ましく、残部(M)の含有量が0wt%以上10wt%以下であるのがより好ましい。これにより、第1補強部材4の熱膨張係数を半導体素子3の熱膨張係数に近づけることができる。 When the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
 また、第1補強部材4の平均厚さは、配線基板2の熱膨張係数、配線基板2の第1補強部材4および第2補強部材5の形状、大きさ、構成材料等に応じて決められるものであり、特に限定されないが、例えば、0.02mm以上0.8mm以下程度である。なお、本実施形態では第1補強部材4の厚さは均一であるが、厚さの異なる部分を有していてもよい。例えば、第1補強部材4の内側から外側に向けて厚さが連続的または段階的に減少または増加していてもよい。 The average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less. In addition, although the thickness of the 1st reinforcement member 4 is uniform in this embodiment, you may have a part from which thickness differs. For example, the thickness may decrease or increase continuously or stepwise from the inside to the outside of the first reinforcing member 4.
 また、本実施形態では、図1および図2に示すように、第1補強部材4と半導体素子3との間に、熱伝導性材料6が充填されている。これにより、半導体素子3から熱伝導性材料6を介して第1補強部材4へ効率的に熱を伝達することができる。その結果、半導体パッケージ1の放熱性を向上させることができる。 In this embodiment, as shown in FIGS. 1 and 2, a heat conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.
 このような熱伝導性材料6としては、特に限定されないが、無機フィラーおよび樹脂材料を含んで構成された樹脂組成物が挙げられる。 Such a heat conductive material 6 is not particularly limited, and examples thereof include a resin composition including an inorganic filler and a resin material.
 熱伝導性材料6(樹脂組成物)に用いる無機フィラー(無機充填材)としては、例えば、Au、Ag、Pt等の金属、シリカ、アルミナ、ケイ藻土、酸化チタン、酸化鉄、酸化亜鉛、酸化マグネシウム、金属フェライト等の酸化物、窒化ホウ素、窒化ケイ素、窒化ガリウム、窒化チタン等の窒化物、水酸化アルミニウム、水酸化マグネシウム等の水酸化物、炭酸カルシウム(軽質、重質)、炭酸マグネシウム、ドロマイト、ドーソナイト等の炭酸塩、硫酸カルシウム、硫酸バリウム、硫酸アンモニウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、タルク、マイカ、クレー、ガラス繊維、ケイ酸カルシウム、モンモリロナイト、ベントナイト等のケイ酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、カーボンブラック、グラファイト、炭素繊維等の炭素、その他鉄粉、銅粉、アルミニウム粉、亜鉛華、硫化モリブデン、ボロン繊維、チタン酸カリウム、チタン酸ジルコン酸鉛が挙げられる。なお、無機フィラーとして導電性を有するものを用いた場合、必要に応じて、熱伝導性材料6の接する部位に絶縁処理を施す。 Examples of the inorganic filler (inorganic filler) used in the heat conductive material 6 (resin composition) include metals such as Au, Ag, and Pt, silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, Oxides such as magnesium oxide and metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride, and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, calcium carbonate (light and heavy), magnesium carbonate Carbonates such as dolomite and dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate and calcium sulfite, talc, mica, clay, glass fiber, silicates such as calcium silicate, montmorillonite and bentonite, boron Zinc oxide, barium metaborate, aluminum borate, calcium borate, Borate such as sodium acid, carbon black, graphite, carbon such as carbon fiber, other iron powder, copper powder, aluminum powder, zinc white, molybdenum sulfide, boron fiber, potassium titanate, lead zirconate titanate . In addition, when what has electroconductivity as an inorganic filler is used, the insulation process is performed to the site | part which the heat conductive material 6 contacts as needed.
 中でも、前記無機フィラーとしては、絶縁性および熱伝導性に優れるという観点から、シリカ、アルミナ、ケイ藻土、酸化チタン、酸化鉄、酸化亜鉛、酸化マグネシウム、金属フェライト等の酸化物、窒化ホウ素、窒化ケイ素、窒化ガリウム、窒化チタン等の窒化物が好ましい。 Among these, as the inorganic filler, from the viewpoint of excellent insulation and thermal conductivity, oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite, boron nitride, Nitride such as silicon nitride, gallium nitride and titanium nitride is preferable.
 また、熱伝導性材料6(樹脂組成物)に用いる樹脂材料としては、各種熱可塑性樹脂、各種熱硬化性樹脂が挙げられる。 Also, examples of the resin material used for the heat conductive material 6 (resin composition) include various thermoplastic resins and various thermosetting resins.
 熱伝導性材料6(樹脂組成物)に用いる熱可塑性樹脂としては、例えば、ポリエチレン、ポリプロピレン、エチレン-酢酸ビニル共重合体等のポリオレフィン、変性ポリオレフィン、ポリアミド(例:ナイロン6、ナイロン46、ナイロン66、ナイロン610、ナイロン612、ナイロン11、ナイロン12、ナイロン6-12、ナイロン6-66)、熱可塑性ポリイミド、芳香族ポリエステル等の液晶ポリマー、ポリフェニレンオキシド、ポリフェニレンサルファイド、ポリカーボネート、ポリメチルメタクリレート、ポリエーテル、ポリエーテルエーテルケトン、ポリエーテルイミド、ポリアセタール、スチレン系、ポリオレフィン系、ポリ塩化ビニル系、ポリウレタン系、ポリエステル系、ポリアミド系、ポリブタジエン系、トランスポリイソプレン系、フッ素ゴム系、塩素化ポリエチレン系等の各種熱可塑性エラストマー等、またはこれらを主とする共重合体、ブレンド体、ポリマーアロイ等が挙げられ、これらのうちの1種または2種以上を混合して用いることができる。 Examples of the thermoplastic resin used for the thermally conductive material 6 (resin composition) include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66). , Nylon 610, Nylon 612, Nylon 11, Nylon 12, Nylon 6-12, Nylon 6-66), Thermoplastic polyimide, Liquid crystalline polymer such as aromatic polyester, Polyphenylene oxide, Polyphenylene sulfide, Polycarbonate, Polymethyl methacrylate, Polyether , Polyether ether ketone, polyether imide, polyacetal, styrene, polyolefin, polyvinyl chloride, polyurethane, polyester, polyamide, polybutadiene, Examples include various thermoplastic elastomers such as polyisoprene, fluororubber, and chlorinated polyethylene, and copolymers, blends, and polymer alloys mainly composed of these, one or two of these The above can be mixed and used.
 また、熱伝導性材料6(樹脂組成物)に用いる熱硬化性樹脂としては、例えば、エポキシ樹脂、フェノール樹脂、ユリア樹脂、メラミン樹脂、ポリエステル(不飽和ポリエステル)樹脂、ポリイミド樹脂、シリコーン樹脂、ポリウレタン樹脂等が挙げられ、これらのうちの1種または2種以上を混合して用いることができる。 Moreover, as a thermosetting resin used for the heat conductive material 6 (resin composition), for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, polyurethane Resins etc. are mentioned, 1 type or 2 types or more of these can be mixed and used.
 中でも、熱伝導性材料6(樹脂組成物)に用いる樹脂材料としては、熱硬化性樹脂(特に硬化前に液状をなすもの)を用いるのが好ましく、フェノール樹脂、エポキシ樹脂を用いるのがより好ましく、フェノール樹脂を用いるのが特に好ましい。これにより、熱伝導性材料6を第1補強部材4と半導体素子3との間に隙間なく充填できるとともに、熱伝導性材料6の熱膨張係数を効果的に抑えることができる。 Among these, as the resin material used for the heat conductive material 6 (resin composition), it is preferable to use a thermosetting resin (particularly, a liquid that forms a liquid before curing), more preferably a phenol resin or an epoxy resin. It is particularly preferable to use a phenol resin. Thereby, the thermal conductive material 6 can be filled between the first reinforcing member 4 and the semiconductor element 3 without a gap, and the thermal expansion coefficient of the thermal conductive material 6 can be effectively suppressed.
 かかるフェノール樹脂としては、フェノールノボラック樹脂、クレゾールノボラック樹脂、ビスフェノールAノボラック樹脂等のノボラック型フェノール樹脂、未変性のレゾールフェノール樹脂、桐油、アマニ油、クルミ油等で変性した油変性レゾールフェノール樹脂等のレゾール型フェノール樹脂等のフェノール樹脂等が挙げられる。 Examples of such phenolic resins include phenol novolac resins, cresol novolac resins, novolac type phenol resins such as bisphenol A novolac resins, unmodified resole phenol resins, oil-modified resole phenol resins modified with paulownia oil, linseed oil, walnut oil, etc. Examples thereof include phenolic resins such as resol type phenolic resins.
 また、この熱伝導性材料6は、前述した接着層32(アンダーフィル材)と同様のものを用いてもよく、また、熱伝導性材料6および接着層32を一括して形成することもできる。 In addition, the heat conductive material 6 may be the same as the adhesive layer 32 (underfill material) described above, and the heat conductive material 6 and the adhesive layer 32 may be formed in a lump. .
 [第2補強部材]
 第2補強部材(スティフナー)5は、配線基板2の基板21の下面(他方の面)に接合されている。
[Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.
 この第2補強部材5と基板21とは、接着剤を介して接合することができる。これにより、第2補強部材5の設置が簡単となる。 The second reinforcing member 5 and the substrate 21 can be joined via an adhesive. Thereby, installation of the 2nd reinforcement member 5 becomes easy.
 かかる接着剤としては、接着機能を有するものであれば、特に限定されず、各種接着剤を用いることができるが、熱伝導性に優れたものが好ましく、後述する熱伝導性材料6と同様のものを用いることができる。 Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.
 この第2補強部材5は、前述した第1補強部材4と同様、基板21よりも熱膨張係数が小さい。 The second reinforcing member 5 has a smaller thermal expansion coefficient than that of the substrate 21 as in the first reinforcing member 4 described above.
 第2補強部材5は、板状をなしている。これにより、第2補強部材5の構成を簡単かつ小型なものとすることができる。 The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.
 また、図3に示すように、第2補強部材5は、配線基板2(基板21)の外周部(導体パターン224よりも外側)に沿って設けられた部分(枠部)52と、金属バンプ71同士の間に設けられた部分53とを有している。第2補強部材5の部分52と配線基板2(基板21)との接合により、第2補強部材5が配線基板2を効果的に補強することができる。また、第2補強部材5の部分53と配線基板2との接合により、第2補強部材5の剛性が高められる。 Further, as shown in FIG. 3, the second reinforcing member 5 includes a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21), and metal bumps. And a portion 53 provided between 71. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the second reinforcing member 5 can effectively reinforce the wiring substrate 2. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.
 より具体的に説明すると、第2補強部材5は、前述した各金属バンプ71に非接触で各金属バンプ71を囲むように形成された複数の開口部51を有する。これにより、第2補強部材5が配線基板2の下面に占める面積の割合を大きくすることができる。その結果、第2補強部材5による配線基板2の剛性を高める効果を優れたものとすることができる。 More specifically, the second reinforcing member 5 has a plurality of openings 51 formed so as to surround each metal bump 71 in a non-contact manner with each metal bump 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.
 本実施形態では、各開口部51は、平面視にて、円形をなしている。なお、各開口部51の平面視形状は、これに限定されず、例えば、楕円形、多角形等であってもよい。 In the present embodiment, each opening 51 is circular in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
 また、各開口部51は、各金属バンプ71に対応して(一対一で対応して)設けられている。これにより、第2補強部材5の剛性の均一化を図ることができる。また、第2補強部材5の放熱性も向上させることができる。 Further, each opening 51 is provided corresponding to each metal bump 71 (corresponding one-to-one). Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.
 また、第2補強部材5は、各金属バンプ71との間の距離(平面視における開口部51の壁面と金属バンプ71の外周面との間の距離)が金属バンプ71の全周に亘って一定となるように形成されている。これにより、第2補強部材5および各金属バンプ71の一体性が増し、これらによる配線基板2の補強効果が好適に発揮される。 In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.
 本実施形態では、第2補強部材5の下面に、伝熱バンプ91が設けられている。
 この伝熱バンプ91は、配線基板2の基板21よりも高い熱伝導性を有し、例えば、後述する半導体装置100において、マザーボード200に接合される。これにより、第2補強部材5の熱を外部(例えばマザーボード200)に逃がすことができる。
In the present embodiment, the heat transfer bumps 91 are provided on the lower surface of the second reinforcing member 5.
The heat transfer bumps 91 have higher thermal conductivity than the substrate 21 of the wiring board 2 and are bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).
 伝熱バンプ91の構成材料としては、前述したような伝熱性を有するものであれば、特に限定されず、金属材料、樹脂材料を用いることができるが、特に、前述した金属バンプ71と同様の構成材料、無機フィラーおよび樹脂材料を含有する伝熱性接着剤等を用いるのが好ましい。 The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material.
 また、前述した第1補強部材4と同様、第2補強部材5は、半導体素子3との熱膨張係数差が7ppm/℃以下であるのが好ましい。これにより、第2補強部材5が効果的に配線基板2を補強し、半導体パッケージ1全体の熱膨張を抑えることができる。 Further, similarly to the first reinforcing member 4 described above, the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.
 また、第2補強部材5は、金属材料で構成されているのが好ましい。これにより、第2補強部材5の放熱性を高めることができる。その結果、半導体パッケージ1の放熱性を向上させることができる。 The second reinforcing member 5 is preferably made of a metal material. Thereby, the heat dissipation of the 2nd reinforcement member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
 かかる金属材料としては、特に限定されないが、放熱性および低熱膨張を実現する観点から、Fe-Ni系合金を用いるのが好ましい。 The metal material is not particularly limited, but it is preferable to use an Fe—Ni-based alloy from the viewpoint of realizing heat dissipation and low thermal expansion.
 Fe-Ni系合金としては、前述した第1補強部材4と同様のものを用いることができる。 As the Fe—Ni alloy, the same material as the first reinforcing member 4 described above can be used.
 特に、第2補強部材5の熱膨張係数は、0.5ppm/℃以上10ppm/℃以下であるのが好ましく、1ppm/℃以上7ppm/℃以下であるのがより好ましく、1ppm/℃以上5ppm/℃以下であるのがさらに好ましい。これにより、半導体素子3と第2補強部材5との熱膨張係数差を小さくし、第2補強部材5が配線基板2を効果的に補強することができる。そのため、配線基板2の反りを効果的に防止することができる。 In particular, the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
 また、第2補強部材5と半導体素子3との熱膨張係数差の絶対値は、7ppm/℃以下であるのが好ましく、5ppm/℃以下であるのがより好ましく、2ppm/℃以下であるのがさらに好ましい。これにより、半導体素子3と第2補強部材5との熱膨張係数差を小さくし、第2補強部材5が配線基板2を効果的に補強することができる。そのため、配線基板2の反りを効果的に防止することができる。 The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
 また、第2補強部材5と第1補強部材4との熱膨張係数差の絶対値は、2ppm/℃以下であるのが好ましく、1ppm/℃以下であるのがより好ましく、0ppm/℃であるのがさらに好ましい。これにより、第1補強部材4と第2補強部材5との熱膨張係数差を小さくし、これらの熱膨張差に起因する配線基板2の反りを防止することができる。 The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.
 このような観点から、第2補強部材5の構成材料は、第1補強部材4の構成材料と同種または同じであるのが好ましい。 From such a viewpoint, the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.
 また、第2補強部材5の平均厚さは、配線基板2の熱膨張係数、配線基板2の第1補強部材4および第2補強部材5の形状、大きさ、構成材料等に応じて決められるものであり、特に限定されないが、例えば、0.02mm以上0.8mm以下程度である。 The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.
 また、第2補強部材5と各金属バンプ71との間には、絶縁材81が設けられている(充填されている)。これにより、第2補強部材5と各金属バンプ71との接触を防止することができる。そのため、半導体パッケージ1の信頼性を優れたものとしつつ、第2補強部材5の剛性および放熱性を高めることができる。 Further, an insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be improved while improving the reliability of the semiconductor package 1.
 また、絶縁材81は、金属バンプ71の基板21側の部分(上部)の周囲を囲むような形状をなし、かつ、各金属バンプ71に接合されている。これにより、絶縁材81は、金属バンプ71を補強している。 Further, the insulating material 81 has a shape surrounding the periphery (upper part) of the metal bump 71 on the substrate 21 side, and is joined to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71.
 また、絶縁材81は、前述した配線基板2の基板21よりも高い熱伝導性を有するのが好ましい。これにより、金属バンプ71と第2補強部材5の間の熱伝導性を優れたものとし、半導体パッケージ1の放熱性を向上させることができる。
 このような絶縁材81は、絶縁性を有し、樹脂材料を含んで構成されている。
The insulating material 81 preferably has a higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 71 and the second reinforcing member 5 can be made excellent, and the heat dissipation of the semiconductor package 1 can be improved.
Such an insulating material 81 has an insulating property and includes a resin material.
 このような絶縁材81は、特に限定されないが、例えば、熱硬化性を有する半田接合用樹脂により形成されるのが好ましい。 Such an insulating material 81 is not particularly limited, but is preferably formed from, for example, a solder bonding resin having thermosetting properties.
 このような半田接合用樹脂(以下、「硬化性フラックス」とも言う)は、半田接合時にフラックスとして作用し、次いで加熱することにより、硬化して半田接合部の補強材として作用する。なお、フラックスとは半田接合時に半田より先に溶けて金属や半田表面の酸化物や汚れを除去する材料である。また、かかる半田接合用樹脂は、半田接合の際に、半田接合面および半田材料の酸化物などの有害物を除去し、半田接合面を保護するとともに、半田材料の精錬を行って、強度の大きい良好な接合を可能にする。さらに、半田接合用樹脂は、半田接合後に洗浄などにより除去する必要がなく、そのまま加熱することにより、三次元架橋した樹脂となり、半田接合部の補強材として作用する。 Such a solder bonding resin (hereinafter also referred to as “curing flux”) acts as a flux at the time of solder bonding, and then cures by heating to act as a reinforcing material for the solder bonding portion. The flux is a material that melts before the solder and removes oxides and dirt on the surface of the solder when soldering. In addition, the solder bonding resin removes harmful substances such as solder joint surfaces and oxides of the solder material at the time of solder joint, protects the solder joint surface, and refines the solder material to improve the strength. Allows large good joints. Furthermore, the solder bonding resin does not need to be removed by washing or the like after the solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.
 かかる半田接合用樹脂は、例えば、フェノール性ヒドロキシル基を有する樹脂(A)および前記樹脂の硬化剤(B)を含んで構成することができる。 Such a solder bonding resin can be configured to include, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.
 フェノール性ヒドロキシル基を有する樹脂(A)としては、特に制限はないが、例えば、フェノールノボラック樹脂、アルキルフェノールノボラック樹脂、多価フェノールノボラック樹脂、レゾール樹脂、ポリビニルフェノール樹脂などを挙げることができる。 The resin (A) having a phenolic hydroxyl group is not particularly limited, and examples thereof include a phenol novolak resin, an alkylphenol novolak resin, a polyhydric phenol novolak resin, a resole resin, and a polyvinyl phenol resin.
 また、硬化性フラックスにおいて、フェノール性ヒドロキシル基を有する樹脂(A)の含有量は、硬化性フラックス全体の20~80重量%であることが好ましく、25~60重量%であることがより好ましい。樹脂(A)の含有量が20重量%未満であると、半田および金属表面の酸化物などの汚れを除去する作用が低下し、半田接合性が不良となるおそれがある。樹脂(A)の含有量が80重量%を超えると、十分な物性を有する硬化物が得られず、接合強度と信頼性が低下するおそれがある。 Further, in the curable flux, the content of the resin (A) having a phenolic hydroxyl group is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened | cured material which has sufficient physical property cannot be obtained, and there exists a possibility that joining strength and reliability may fall.
 また、フェノール性ヒドロキシル基を有する樹脂(A)のフェノール性ヒドロキシル基は、その還元作用により、半田および金属表面の酸化物などの汚れを除去するので、半田接合のフラックスとして効果的に作用する。 In addition, the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as solder and oxide on the metal surface by its reducing action, and thus effectively acts as a solder joint flux.
 また、フェノール性ヒドロキシル基を有する樹脂(A)の硬化剤(B)としては、例えば、エポキシ化合物、イソシアネート化合物などを挙げることができる。エポキシ化合物およびイソシアネート化合物としては、例えば、ビスフェノール系、フェノールノボラック系、アルキルフェノールノボラック系、ビフェノール系、ナフトール系、レゾルシノール系などのフェノールベースのエポキシ化合物、イソシアネート化合物や、飽和脂肪族、環状脂肪族、不飽和脂肪族などの骨格をベースとして変性されたエポキシ化合物、イソシアネート化合物などを挙げることができる。 Further, examples of the curing agent (B) of the resin (A) having a phenolic hydroxyl group include an epoxy compound and an isocyanate compound. Examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.
 また、硬化剤(B)の配合量は、硬化剤のエポキシ基、イソシアネート基などの反応性の官能基が、樹脂(A)のフェノール性ヒドロキシル基の0.5~1.5当量倍であることが好ましく、0.8~1.2当量倍であることがより好ましい。硬化剤の反応性の官能基がヒドロキシル基の0.5当量倍未満であると、十分な物性を有する硬化物が得られず、補強効果が小さくなって、接合強度と信頼性が低下するおそれがある。硬化剤の反応性の官能基がヒドロキシル基の1.5当量倍を超えると、半田および金属表面の酸化物などの汚れを除去する作用が低下し、半田接合性が不良となるおそれがある。 The compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group or isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. If the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, resulting in a decrease in bonding strength and reliability. There is. If the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxide on the solder and metal surface may be reduced, and solder jointability may be deteriorated.
 このような半田接合用樹脂(硬化性フラックス)においては、フェノール性ヒドロキシル基を有する樹脂(A)と前記樹脂の硬化剤(B)の反応により、良好な物性を有する硬化物が形成される。そのため、半田接合後に洗浄によりフラックスを除去する必要がなく、硬化物により半田接合部が保護されて、高温、多湿雰囲気でも電気絶縁性を保持し、接合強度と信頼性の高い半田接合が可能となる。 In such a solder bonding resin (curable flux), a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. Therefore, it is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in high temperature and high humidity atmosphere, enabling soldering with high bonding strength and reliability. Become.
 なお、前述したような半田接合用樹脂は、フェノール性ヒドロキシル基を有する樹脂(A)と前記樹脂の硬化剤(B)の他に、硬化性酸化防止剤(C)、微結晶状態で分散するフェノール性ヒドロキシル基を有する化合物(D)および前記化合物の硬化剤(E)、溶剤(F)、硬化触媒、密着性や耐湿性を向上させるためのシランカップリング剤、ボイドを防止するための消泡剤、あるいは液状または粉末の難燃剤等を含んでいてもよい。 In addition to the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin, the solder bonding resin as described above is dispersed in a curable antioxidant (C) and in a microcrystalline state. Compound (D) having a phenolic hydroxyl group and curing agent (E), solvent (F), curing catalyst, silane coupling agent for improving adhesion and moisture resistance of the compound, and elimination for preventing voids It may contain a foaming agent or a liquid or powder flame retardant.
 (トップパッケージ)
 トップパッケージ(第2パッケージ)300は、配線基板301、半導体素子305とを有し、配線基板301の半導体素子305側の面上には、半導体素子305を覆う封止部307が設けられている。なお、図示のトップパッケージ300の構成は一例であり、本発明はこれに限定されるものではない。
(Top package)
The top package (second package) 300 includes a wiring substrate 301 and a semiconductor element 305, and a sealing portion 307 that covers the semiconductor element 305 is provided on the surface of the wiring substrate 301 on the semiconductor element 305 side. . The configuration of the illustrated top package 300 is an example, and the present invention is not limited to this.
 [配線基板]
 配線基板301は、半導体素子305を支持する基板(第2配線基板)であり、例えば、その搭載した半導体素子305と前述したボトムパッケージ500との電気的接続を中継する中継基板(インターポーザ)である。また、配線基板301は、その平面視形状は、通常、正方形、長方形等の四角形とされる。
[Wiring board]
The wiring board 301 is a board (second wiring board) that supports the semiconductor element 305. For example, the wiring board 301 is a relay board (interposer) that relays electrical connection between the mounted semiconductor element 305 and the bottom package 500 described above. . In addition, the wiring board 301 has a shape in plan view generally a quadrangle such as a square or a rectangle.
 配線基板301は、基板302を有する。この基板302は、絶縁性を有する材料で構成され、例えば、基材(繊維基材)と、その基材に含浸された樹脂組成物とで構成されている。この基材および樹脂組成物としては、前述したボトムパッケージ500の配線基板2の絶縁層と同様のものを用いることができる。なお、図示の例では、基板302は、一層の絶縁層で構成されているが、複数の絶縁層で構成されていてもよい。 The wiring substrate 301 has a substrate 302. The substrate 302 is composed of an insulating material, and is composed of, for example, a base material (fiber base material) and a resin composition impregnated in the base material. As this base material and resin composition, the same thing as the insulating layer of the wiring board 2 of the bottom package 500 mentioned above can be used. In the illustrated example, the substrate 302 is formed of a single insulating layer, but may be formed of a plurality of insulating layers.
 このような基板302の下面上には、導体パターン308が設けられている。この導体パターン308は、前述した各金属バンプ400を介してボトムパッケージ500の導体パターン225に接合されている。また、基板302の上面上には、図示しないが、基板302を貫通する導体ポストを介して導体パターン308に電気的に接続されるとともに、半導体素子305と電気的に接続される導体パターンが設けられている。 A conductor pattern 308 is provided on the lower surface of the substrate 302. The conductor pattern 308 is bonded to the conductor pattern 225 of the bottom package 500 through the metal bumps 400 described above. On the upper surface of the substrate 302, although not shown, a conductor pattern that is electrically connected to the conductor pattern 308 through a conductor post that penetrates the substrate 302 and electrically connected to the semiconductor element 305 is provided. It has been.
 これらの導体パターンおよび導体ポストは、前述した配線基板2の導体パターンおよび導体ポストと同様に構成することができる。 These conductor patterns and conductor posts can be configured similarly to the conductor patterns and conductor posts of the wiring board 2 described above.
 また、基板302の下面上には、導体パターン308を覆うように、絶縁層304が設けられている。同様に、基板302の上面上には、絶縁層303が設けられている。この絶縁層303、304は、それぞれ、例えば、公知のソルダーレジストにより形成することができる。
 このような配線基板301の上面上には、半導体素子305が接合されている。
An insulating layer 304 is provided on the lower surface of the substrate 302 so as to cover the conductor pattern 308. Similarly, an insulating layer 303 is provided on the top surface of the substrate 302. The insulating layers 303 and 304 can be formed by, for example, a known solder resist.
A semiconductor element 305 is bonded on the upper surface of the wiring substrate 301.
 [半導体素子]
 半導体素子(第2半導体素子)305は、例えば、集積回路素子(IC)であり、より具体的には、例えば、ロジックIC、メモリおよび受発光素子等である。なお、半導体素子305の構成および機能は、それぞれ、前述した半導体素子3の構成および機能を同じであっても異なっていてもよい。
[Semiconductor element]
The semiconductor element (second semiconductor element) 305 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light emitting / receiving element. The configuration and function of the semiconductor element 305 may be the same as or different from the configuration and function of the semiconductor element 3 described above.
 この半導体素子305は、前述した配線基板301の上面側に設けられた導体パターン(図示せず)に複数の金属ワイヤー306を介して電気的に接続されている。 The semiconductor element 305 is electrically connected via a plurality of metal wires 306 to a conductor pattern (not shown) provided on the upper surface side of the wiring board 301 described above.
 この各金属ワイヤー306は、例えば、公知のワイヤーボンディング技術により形成される。なお、この電気的な接続は、金属ワイヤーに代えて、前述したボトムパッケージ500と同様、フェイスダウンボンディングにより行ってもよい。
 このような半導体素子305は、封止部307により封止されている。
Each metal wire 306 is formed by, for example, a known wire bonding technique. This electrical connection may be performed by face-down bonding in the same manner as the bottom package 500 described above, instead of the metal wire.
Such a semiconductor element 305 is sealed by a sealing portion 307.
 この封止部307は、配線基板301の上面上に半導体素子305を覆うように設けられているので、トップパッケージ300の剛性を高めることができる。そのため、トップパッケージ300の反りを防止または抑制することができる。 Since the sealing portion 307 is provided on the upper surface of the wiring substrate 301 so as to cover the semiconductor element 305, the rigidity of the top package 300 can be increased. Therefore, warping of the top package 300 can be prevented or suppressed.
 この封止部307の構成材料としては、特に限定されないが、公知の封止樹脂を用いることができる。 Although it does not specifically limit as a constituent material of this sealing part 307, A well-known sealing resin can be used.
 このようなトップパッケージ300の配線基板301の下面は、前述したボトムパッケージ500の半導体素子3と非接触となっている(離間している)。本実施形態では、半導体素子3の上面の全域が配線基板301の下面に対して離間している。これにより、半導体素子3と配線基板301との間に形成された隙間S1を通じて通気を行い、半導体素子3の熱を外方へ効率的に逃すことができる。 The lower surface of the wiring substrate 301 of the top package 300 is not in contact with (separated from) the semiconductor element 3 of the bottom package 500 described above. In the present embodiment, the entire upper surface of the semiconductor element 3 is separated from the lower surface of the wiring substrate 301. Thereby, air can be ventilated through the gap S1 formed between the semiconductor element 3 and the wiring board 301, and the heat of the semiconductor element 3 can be efficiently released outward.
 半導体素子3の上面と配線基板301の下面との間の距離(すなわち隙間S1の厚さ方向での長さ)Lは、前述したような通気を確保する観点から、0.01mm以上0.8mm以下であるのが好ましい。Lは、より好ましくは、0.05mm以上0.5mm以下である。 The distance L between the upper surface of the semiconductor element 3 and the lower surface of the wiring board 301 (that is, the length of the gap S1 in the thickness direction) L is 0.01 mm or more and 0.8 mm from the viewpoint of ensuring the above-described ventilation. It is preferable that: L is more preferably 0.05 mm or more and 0.5 mm or less.
 また、本実施形態では、前述したように半導体素子3の上面と第1補強部材4の上面とが同一面上に位置しているので、配線基板301の下面は、前述したボトムパッケージ500の第1補強部材4の上面に対して離間している(非接触である)。本実施形態では、第1補強部材4の上面の全域が配線基板301の下面に対して非接触である。第1補強部材4と配線基板301との間に形成された隙間S2を通じて通気を行い、半導体素子3の熱を外方へ効率的に逃すことができる。そのため、半導体パッケージ1の放熱性を優れたものとすることができる。なお、第1補強部材4の上面のうちの一部が配線基板301の下面に接触していてもよい。 In the present embodiment, since the upper surface of the semiconductor element 3 and the upper surface of the first reinforcing member 4 are located on the same plane as described above, the lower surface of the wiring board 301 is the same as that of the bottom package 500 described above. 1 Separated from the upper surface of the reinforcing member 4 (non-contacting). In the present embodiment, the entire upper surface of the first reinforcing member 4 is not in contact with the lower surface of the wiring board 301. Air can be ventilated through the gap S2 formed between the first reinforcing member 4 and the wiring board 301, and the heat of the semiconductor element 3 can be efficiently released to the outside. Therefore, the heat dissipation of the semiconductor package 1 can be made excellent. A part of the upper surface of the first reinforcing member 4 may be in contact with the lower surface of the wiring board 301.
 以上説明したように構成された半導体パッケージ1によれば、半導体素子3と接合された部分以外の部分においても、配線基板2が第1補強部材4により補強されるため、ボトムパッケージ500全体の剛性が増す。特に、第1補強部材4の熱膨張係数が配線基板2(具体的には基板21)よりも小さいため、半導体素子3が配線基板2の全面に亘って設けられているのと同様に、配線基板2と半導体素子3との熱膨張係数差に起因する配線基板2の反りを抑制または防止することができる。 According to the semiconductor package 1 configured as described above, since the wiring board 2 is reinforced by the first reinforcing member 4 even in a portion other than the portion joined to the semiconductor element 3, the rigidity of the bottom package 500 as a whole. Increase. In particular, since the thermal expansion coefficient of the first reinforcing member 4 is smaller than that of the wiring substrate 2 (specifically, the substrate 21), the wiring is similar to the case where the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. It is possible to suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the substrate 2 and the semiconductor element 3.
 また、半導体素子3と配線基板301とが非接触であるため、半導体素子3と配線基板301との間に形成された隙間を通じて通気を行い、半導体素子3の熱を外方へ効率的に逃すことができる。また、配線基板2自体の剛性を高める必要がなく、配線基板2の厚さを薄くすることができるので、配線基板2の厚さ方向での熱伝導性を高め、半導体素子3からの熱を配線基板2を介して逃すことができる。このようなことから、半導体パッケージ1は、放熱性に優れる。また、第1補強部材4および第2補強部材5の構成材料を適宜選択することにより、半導体パッケージ1の放熱性を高めることもできる。 Further, since the semiconductor element 3 and the wiring board 301 are not in contact with each other, air is ventilated through a gap formed between the semiconductor element 3 and the wiring board 301 to efficiently release the heat of the semiconductor element 3 to the outside. be able to. In addition, since it is not necessary to increase the rigidity of the wiring board 2 and the thickness of the wiring board 2 can be reduced, the thermal conductivity in the thickness direction of the wiring board 2 is increased, and the heat from the semiconductor element 3 is increased. It can escape through the wiring board 2. For this reason, the semiconductor package 1 is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
 このような半導体パッケージ1の優れた放熱性も相俟って、配線基板2と半導体素子3との熱膨張係数差に起因する配線基板2の反りを効果的に抑制または防止することができる。その結果、トップパッケージ300とボトムパッケージ500との間の電気的な接続信頼性を優れたものとすることができる。 Combined with such excellent heat dissipation of the semiconductor package 1, it is possible to effectively suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3. As a result, the electrical connection reliability between the top package 300 and the bottom package 500 can be made excellent.
 また、半導体パッケージ1では、第2補強部材5を配線基板2の半導体素子3と反対側の面(下面)に接合することにより、配線基板2は半導体素子3と第2補強部材5とに挟持された状態となるため、配線基板2がより強固に補強されるとともに、配線基板2の両面の熱膨張差を抑制することができる。特に、第2補強部材5は、後述する金属バンプ71間にも及ぶように設けられているので、配線基板2を強固に補強することができる。 Also, in the semiconductor package 1, the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5 by bonding the second reinforcing member 5 to the surface (lower surface) opposite to the semiconductor element 3 of the wiring board 2. Therefore, the wiring board 2 can be reinforced more strongly, and the difference in thermal expansion between both surfaces of the wiring board 2 can be suppressed. In particular, since the second reinforcing member 5 is provided so as to extend between metal bumps 71 described later, the wiring board 2 can be strongly reinforced.
 (半導体パッケージの製造方法)
 以上説明したような半導体パッケージ1は、例えば、以下のようにして製造することができる。
(Semiconductor package manufacturing method)
The semiconductor package 1 as described above can be manufactured as follows, for example.
 以下、図4に基づき、半導体パッケージ1の製造方法の一例を簡単に説明する。なお、半導体パッケージ1の製造方法は、これに限定されるものではない。 Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIG. In addition, the manufacturing method of the semiconductor package 1 is not limited to this.
 [1]
 まず、図4(a)に示すように、金属層221Aとプリプレグ211Aとの積層体を用意し、その積層体のプリプレグ211A側の面に、第1補強部材4を貼り付ける。
[1]
First, as shown to Fig.4 (a), the laminated body of the metal layer 221A and the prepreg 211A is prepared, and the 1st reinforcement member 4 is affixed on the surface at the side of the prepreg 211A of the laminated body.
 ここで、プリプレグ211Aは、前述した絶縁層211の樹脂組成物の未硬化物(半硬化物)が基材に含浸してなり、前述した配線基板2の絶縁層211を形成する。 Here, the prepreg 211A is formed by impregnating the base material with the uncured material (semi-cured material) of the resin composition of the insulating layer 211 described above, and forms the insulating layer 211 of the wiring substrate 2 described above.
 また、金属層221Aは、前述した配線基板2の導体パターン221を形成するためのものであり、導体パターン221の構成材料と同様の材料で構成されている。 The metal layer 221A is for forming the conductor pattern 221 of the wiring board 2 described above, and is made of the same material as that of the conductor pattern 221.
 [2]
 次に、図4(b)に示すように、プリプレグ211Aに貫通孔2111(ビアホール)を形成する。
[2]
Next, as shown in FIG. 4B, a through hole 2111 (via hole) is formed in the prepreg 211A.
 貫通孔2111の形成方法としては、特に限定されないが、例えば、レーザーを照射することにより形成することができる。 The formation method of the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.
 ここで、レーザーとしては、例えばCOレーザー、UV-YAGレーザー等を用いることができる。 Here, as the laser, for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
 なお、貫通孔2111は、例えば、ドリル等の機械加工によって形成することもできる。 In addition, the through-hole 2111 can be formed by machining such as a drill, for example.
 [3]
 次に、図4(c)に示すように、貫通孔2111内に導体ポスト231および導体パターン225を形成する。
[3]
Next, as shown in FIG. 4C, conductor posts 231 and a conductor pattern 225 are formed in the through hole 2111.
 導体ポスト231の形成方法としては、特に限定されないが、例えば、導電性ペーストを充填する方法、無電解めっきにより埋め込む方法、電解めっきにより埋め込む方法等を用いることができる。 The method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.
 また、導体パターン225の形成方法としては、特に限定されないが、例えば、導電性ペーストを塗布する方法、無電解めっきにより成膜する方法等を用いることができる。 Further, the method for forming the conductor pattern 225 is not particularly limited, and for example, a method of applying a conductive paste, a method of forming a film by electroless plating, or the like can be used.
 [4]
 次に、図4(d)に示すように、金属層221Aをパターンニングすることにより、導体パターン221を形成する。
[4]
Next, as shown in FIG. 4D, the conductor layer 221 is formed by patterning the metal layer 221A.
 かかるパターンニングの方法としては、特に限定されないが、エッチングが好適に用いられる。 Such a patterning method is not particularly limited, but etching is preferably used.
 以上のようにして、絶縁層211、導体パターン221および導体ポスト231が形成される。 As described above, the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.
 [5]
 次に、上記工程[1]~[4]と同様にして、絶縁層212、213、214、215および導体パターン222、223、224を形成するためのプリプレグおよび金属層からなる積層体をそれぞれ用意し、導体パターン222、223、224および導体ポスト232、233、234、235を形成する。
[5]
Next, in the same manner as in the above steps [1] to [4], prepregs for forming the insulating layers 212, 213, 214, 215 and the conductor patterns 222, 223, 224 and laminates made of metal layers are respectively prepared. Then, conductor patterns 222, 223, 224 and conductor posts 232, 233, 234, 235 are formed.
 また、絶縁層211、212、213、214、215のためのプリプレグを積層した後、導体ポスト231、232、233、234、235と同様の方法を用いて、伝熱ポスト24を形成する。 Further, after the prepregs for the insulating layers 211, 212, 213, 214, and 215 are laminated, the heat transfer post 24 is formed using the same method as that for the conductor posts 231, 232, 233, 234, and 235.
 その後、絶縁層211、212、213、214、215のためのプリプレグを硬化(完全硬化)させて、図4(e)に示すように、配線基板2を得る。 Thereafter, the prepreg for the insulating layers 211, 212, 213, 214, and 215 is cured (completely cured) to obtain the wiring board 2 as shown in FIG.
 絶縁層211、212、213、214、215のためのプリプレグを積層する方法としては、例えば、真空プレス、ラミネート等が挙げられる。これらの中でも真空プレスによる接合方法が好ましい。これにより、絶縁層211、212、213、214、215のためのプリプレグの密着強度を向上することができる。 Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.
 絶縁層211、212、213、214、215のためのプリプレグを硬化させる方法としては、特に限定されないが、例えば、熱処理が好適に用いられる。 The method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but for example, heat treatment is preferably used.
 なお、伝熱ポスト24の形成は、各導体ポスト231、232、233、234、235と同時に、各絶縁層211、212、213、214、215のためのプリプレグに伝熱ポストを形成しておき、これらのプリプレグを積層することにより、これらの伝熱ポストを接続して形成してもよい。 The heat transfer post 24 is formed at the same time as the conductor posts 231, 232, 233, 234, and 235, and the heat transfer posts are formed on the prepregs for the insulating layers 211, 212, 213, 214, and 215. These heat transfer posts may be connected and formed by laminating these prepregs.
 [6]
 次に、配線基板2の下面に、絶縁材81Aを塗布した後、金属ボール(半田ボール)71Aを半田リフローにより半田接合する。これにより、金属バンプ71および絶縁材81が形成される。
[6]
Next, after applying an insulating material 81A to the lower surface of the wiring board 2, a metal ball (solder ball) 71A is soldered by solder reflow. Thereby, the metal bump 71 and the insulating material 81 are formed.
 かかる半田接合は、特に限定されないが、配線基板2の下面に各金属バンプ71が当接するように配置し、その状態で、例えば200~280℃×10~60秒間加熱することにより行うことができる。 Such solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. × 10 to 60 seconds. .
 また、絶縁材81Aは、前述した絶縁材81を形成し、例えば、加熱により硬化する。 Further, the insulating material 81A forms the above-described insulating material 81 and is cured by heating, for example.
 絶縁材81を形成するに際しては、例えば、図4(f)に示すように、絶縁材81Aを配線基板2の下面に塗布し、前述したような半田接合の後、加熱により絶縁材81Aを硬化させることにより、絶縁材81を得る。 When forming the insulating material 81, for example, as shown in FIG. 4F, the insulating material 81A is applied to the lower surface of the wiring board 2, and after the solder bonding as described above, the insulating material 81A is cured by heating. By doing so, the insulating material 81 is obtained.
 このようにして得られた絶縁材81は、前述したように金属バンプ71の周囲を囲むように形成される。 The insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
 このとき、絶縁材81Aは、半田接合時にフラックスとして機能し、且つ、金属ボール71Aとの界面張力により半田接合部周辺をリング状に補強する形状で硬化する。 At this time, the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.
 [7]
 次に、図4(g)に示すように、配線基板2の下面に、第2補強部材5を接合する。また、配線基板2の上面に、アンダーフィル材を塗布した後、半導体素子3を金属バンプ31を介して半田リフローにより接合する。なお、この場合、アンダーフィル材として前述した絶縁材81と同じようなフラックス活性のある樹脂を用いる。また、半導体素子3を搭載し、フラックスあるいは半田ペースト等を用いてリフローにより半導体素子3を配線基板2に接合させた後、通常のキャピラリーアンダーフィル材を配線基板2と半導体素子3との間に充填・硬化させることもできる。
[7]
Next, as shown in FIG. 4G, the second reinforcing member 5 is joined to the lower surface of the wiring board 2. In addition, after applying an underfill material to the upper surface of the wiring board 2, the semiconductor element 3 is joined by solder reflow through the metal bumps 31. In this case, a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material. Further, after mounting the semiconductor element 3 and joining the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.
 また、配線基板2の上面上に、前述した金属バンプ71および絶縁材81の形成と同様にして、金属バンプ400Aおよび絶縁材401を形成する。 Further, on the upper surface of the wiring board 2, the metal bumps 400A and the insulating material 401 are formed in the same manner as the formation of the metal bumps 71 and the insulating material 81 described above.
 その後、半導体素子3と第1補強部材4との間に、熱伝導性材料6を充填する。
 以上のようにしてボトムパッケージ500が得られる。
Thereafter, a thermally conductive material 6 is filled between the semiconductor element 3 and the first reinforcing member 4.
The bottom package 500 is obtained as described above.
 [8]
 次に、図4(h)に示すように、トップパッケージ300を用意し、金属バンプ400A(金属バンプ400)を介してトップパッケージ300とボトムパッケージ500とを半田接合により接合する。その際、無加圧状態で接合を行うと、接合後の金属バンプ400の冷却に伴って、金属バンプ400が厚さ方向に膨張し、前記接合後において、トップパッケージ300の配線基板301の下面とボトムパッケージ500の半導体素子3の上面とが離間した状態とすることができる。なお、接合時に、トップパッケージ300とボトムパッケージ500との間にスペーサを配置し、接合後に、そのスペーサを取り除くことによって、接合後において、トップパッケージ300の配線基板301の下面とボトムパッケージ500の半導体素子3の上面とが離間した状態とすることもできる。この場合、前述したようにスペーサを配置した状態で2つのパッケージが互いに近づく方向にこれらを加圧してもよい。
 以上のようにして、半導体パッケージ1が得られる。
[8]
Next, as shown in FIG. 4H, the top package 300 is prepared, and the top package 300 and the bottom package 500 are joined by solder bonding via the metal bump 400A (metal bump 400). At this time, if bonding is performed in a non-pressurized state, the metal bump 400 expands in the thickness direction with cooling of the metal bump 400 after bonding, and after the bonding, the lower surface of the wiring substrate 301 of the top package 300. And the upper surface of the semiconductor element 3 of the bottom package 500 can be separated from each other. Note that a spacer is disposed between the top package 300 and the bottom package 500 at the time of bonding, and the spacer is removed after the bonding, so that after bonding, the lower surface of the wiring substrate 301 of the top package 300 and the semiconductor of the bottom package 500 are bonded. A state in which the upper surface of the element 3 is separated can also be employed. In this case, as described above, the two packages may be pressed in the direction in which the two packages approach each other with the spacers arranged.
The semiconductor package 1 is obtained as described above.
 <第2実施形態>
 次に、本発明の第2実施形態を説明する。
Second Embodiment
Next, a second embodiment of the present invention will be described.
 図5は、本発明の第2実施形態に係る半導体パッケージを模式的に示す断面図である。なお、以下の説明では、説明の便宜上、図5中の上側を「上」、下側を「下」と言う。また、図5では、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 FIG. 5 is a cross-sectional view schematically showing a semiconductor package according to the second embodiment of the present invention. In the following description, for convenience of explanation, the upper side in FIG. 5 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 5, for convenience of explanation, each part of the semiconductor package is exaggerated.
 以下、第2実施形態の半導体パッケージについて、前述した実施形態との相違点を中心に説明し、同様の事項については、その説明を省略する。なお、図5において、前述した実施形態と同様の構成については、同一符号を付している。 Hereinafter, the semiconductor package of the second embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted. In FIG. 5, the same reference numerals are given to the same configurations as those in the above-described embodiment.
 第2実施形態の半導体パッケージは、補強部材(第1補強部材)の構成が異なる以外は、第1実施形態と同様である。 The semiconductor package of the second embodiment is the same as that of the first embodiment except that the configuration of the reinforcing member (first reinforcing member) is different.
 図5に示すように、半導体パッケージ1Aは、トップパッケージ300とボトムパッケージ500Aとが複数の金属バンプ400を介して接合されている。 As shown in FIG. 5, in the semiconductor package 1 </ b> A, the top package 300 and the bottom package 500 </ b> A are joined via a plurality of metal bumps 400.
 ボトムパッケージ500Aは、配線基板2の上面に第1補強部材4Aが接合されている。 In the bottom package 500A, the first reinforcing member 4A is joined to the upper surface of the wiring board 2.
 この第1補強部材4Aの基板21と反対側の面(すなわち上面)は、半導体素子3の基板21と反対側の面(すなわち上面)よりも基板21側(すなわち下側)に位置している。これにより、半導体パッケージ1の製造に際し、第1補強部材4Aの設置後に半導体素子3を設置する場合、半導体素子3の設置が容易となる。 The surface (that is, the upper surface) opposite to the substrate 21 of the first reinforcing member 4A is located on the substrate 21 side (that is, the lower side) than the surface (that is, the upper surface) opposite to the substrate 21 of the semiconductor element 3. . Accordingly, when the semiconductor element 3 is installed after the first reinforcing member 4 </ b> A is installed in manufacturing the semiconductor package 1, the semiconductor element 3 can be easily installed.
 本実施形態では、第1補強部材4Aの上面と配線基板301の下面との間の距離(すなわち隙間S2の厚さ方向での長さ)L2は、半導体素子3の上面と配線基板301の下面との間の距離(すなわち隙間S1の厚さ方向での長さ)L1よりも大きい。これにより、第1補強部材4Aと配線基板301との間に形成された隙間S2を通じて、効率的に通気を行うことができる。 In the present embodiment, the distance L2 between the upper surface of the first reinforcing member 4A and the lower surface of the wiring substrate 301 (that is, the length of the gap S2 in the thickness direction) L2 is the upper surface of the semiconductor element 3 and the lower surface of the wiring substrate 301. (Ie, the length of the gap S1 in the thickness direction) L1. Accordingly, it is possible to efficiently ventilate through the gap S2 formed between the first reinforcing member 4A and the wiring board 301.
 このような第1補強部材4Aの厚さと金属バンプ31の厚さとの合計厚さは、半導体素子3の厚さよりも薄い。これにより、前述したような隙間S2を簡単かつ確実に形成することができる。 The total thickness of the first reinforcing member 4A and the metal bump 31 is smaller than the thickness of the semiconductor element 3. Thereby, the gap S2 as described above can be easily and reliably formed.
 また、半導体素子3の厚さと金属バンプ31の厚さとの合計厚さをT1とし、第1補強部材4Aの厚さT2としたときに、T2/T1は、0.04以上0.96以下であるのが好ましく、0.1以上0.9以下であるのがより好ましい。半導体パッケージ1を製造する際に、配線基板2上に第1補強部材4Aを接合した状態で半導体素子3を設置する場合、その半導体素子3の設置(マウント作業)の作業性が優れたものとなる。また、第1補強部材4Aに必要な補強機能を確保することができる。 When the total thickness of the semiconductor element 3 and the metal bump 31 is T1, and the thickness T2 of the first reinforcing member 4A is T2 / T1, T2 / T1 is 0.04 or more and 0.96 or less. It is preferable that it is 0.1 or more and 0.9 or less. When the semiconductor element 3 is installed with the first reinforcing member 4A bonded on the wiring board 2 when the semiconductor package 1 is manufactured, the workability of the installation (mounting operation) of the semiconductor element 3 is excellent. Become. In addition, a reinforcing function necessary for the first reinforcing member 4A can be ensured.
 また、第1補強部材4Aと配線基板301との間の距離(すなわち隙間S2の厚さ方向での長さ)L2は、前述したような通気を確保する観点から、0.015mm以上0.8mm以下であるのが好ましい。L2は、より好ましくは、0.05mm以上0.5mm以下である。 In addition, the distance L2 between the first reinforcing member 4A and the wiring board 301 (that is, the length of the gap S2 in the thickness direction) L2 is 0.015 mm or more and 0.8 mm from the viewpoint of ensuring ventilation as described above. It is preferable that: L2 is more preferably 0.05 mm or more and 0.5 mm or less.
 以上説明したような第2実施形態の半導体パッケージ1Aによっても、配線基板2の反りを防止するとともに、放熱性を高めることができる。 The semiconductor package 1A of the second embodiment as described above can also prevent the wiring board 2 from warping and improve heat dissipation.
 <第3実施形態>
 次に、本発明の第3実施形態を説明する。
<Third Embodiment>
Next, a third embodiment of the present invention will be described.
 図6は、本発明の第3実施形態に係る半導体パッケージを模式的に示す断面図である。なお、以下の説明では、説明の便宜上、図6中の上側を「上」、下側を「下」と言う。また、図6では、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 FIG. 6 is a cross-sectional view schematically showing a semiconductor package according to the third embodiment of the present invention. In the following description, for convenience of description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 6, for convenience of explanation, each part of the semiconductor package is exaggerated.
 以下、第3実施形態の半導体パッケージについて、前述した実施形態との相違点を中心に説明し、同様の事項については、その説明を省略する。なお、図6において、前述した実施形態と同様の構成については、同一符号を付している。 Hereinafter, the semiconductor package of the third embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted. In FIG. 6, the same reference numerals are given to the same configurations as those in the above-described embodiment.
 第3実施形態の半導体パッケージは、第1補強部材、伝熱ポスト、熱伝導性材料および伝熱バンプを省略した以外は、第1実施形態と同様である。 The semiconductor package of the third embodiment is the same as that of the first embodiment except that the first reinforcing member, the heat transfer post, the heat conductive material, and the heat transfer bump are omitted.
 図6に示すように、半導体パッケージ1Bは、トップパッケージ300とボトムパッケージ500Bとが複数の金属バンプ400を介して接合されている。 As shown in FIG. 6, in the semiconductor package 1 </ b> B, the top package 300 and the bottom package 500 </ b> B are joined via a plurality of metal bumps 400.
 ボトムパッケージ500Bは、伝熱ポスト24を省略した以外は前述した第1実施形態の配線基板2と同様に構成された配線基板2Bを有している。その配線基板2Bの下面上には、前述した第1実施形態の第2補強部材5と同様に構成された補強部材5Bが接合されている。一方、配線基板2Bの上面上には、配線基板2Bの補強を目的とする補強部材は接合されていない。 The bottom package 500B has a wiring board 2B configured similarly to the wiring board 2 of the first embodiment described above except that the heat transfer post 24 is omitted. On the lower surface of the wiring board 2B, a reinforcing member 5B configured similarly to the second reinforcing member 5 of the first embodiment described above is joined. On the other hand, a reinforcing member intended to reinforce the wiring board 2B is not joined on the upper surface of the wiring board 2B.
 このようなボトムパッケージ500Bを有する半導体パッケージ1Bでは、配線基板2B上の半導体素子3の周囲において配線基板301と配線基板2Bとの間に形成される隙間を大きくすることができる。そのため、その隙間を通じた通気により半導体素子3を効率的に放熱するという効果をもたらす。 In the semiconductor package 1B having such a bottom package 500B, a gap formed between the wiring board 301 and the wiring board 2B around the semiconductor element 3 on the wiring board 2B can be increased. For this reason, the semiconductor element 3 is efficiently radiated by ventilation through the gap.
 以上説明したような第3実施形態の半導体パッケージ1Bによっても、配線基板2Bの反りを防止するとともに、放熱性を高めることができる。 The semiconductor package 1B according to the third embodiment as described above can also prevent the wiring board 2B from warping and improve heat dissipation.
(半導体装置)
 次に、半導体装置の製造方法および半導体装置について好適な実施形態に基づいて説明する。
(Semiconductor device)
Next, a method for manufacturing a semiconductor device and a semiconductor device will be described based on preferred embodiments.
 図7は、本発明の半導体装置の実施形態の一例を模式的に示す断面図である。
 図7に示すように、半導体装置100は、マザーボード(基板)200と、このマザーボード200に搭載された半導体パッケージ1とを有している。
FIG. 7 is a cross-sectional view schematically showing an example of the embodiment of the semiconductor device of the present invention.
As shown in FIG. 7, the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.
 このような半導体装置100においては、半導体パッケージ1の金属バンプ71がマザーボード200の端子201に接合されている。これにより、半導体パッケージ1とマザーボード200とが電気的に接続され、これらの間で電気的信号の伝送が行われる。また、この接合部を介して、半導体パッケージ1の熱をマザーボード200へ逃すことができる。 In such a semiconductor device 100, the metal bumps 71 of the semiconductor package 1 are joined to the terminals 201 of the motherboard 200. Thereby, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.
 また、半導体パッケージ1の伝熱バンプ91がマザーボード200の放熱用の端子202に接合されている。この接合部を介して、半導体パッケージ1の熱をマザーボード200へ効率的に逃すことができる。このような伝熱バンプ91は、前述した金属バンプ71と同様の構成材料で構成されている場合、金属バンプ71の接合と同時に一括してマザーボード200に対して接合を行うことができる。 Further, the heat transfer bumps 91 of the semiconductor package 1 are joined to the heat radiation terminals 202 of the motherboard 200. The heat of the semiconductor package 1 can be efficiently released to the mother board 200 through this joint. When such a heat transfer bump 91 is made of the same material as that of the metal bump 71 described above, the heat transfer bump 91 can be bonded to the mother board 200 at the same time as the metal bump 71 is bonded.
 以上説明したような半導体装置100によれば、前述したような放熱性および信頼性に優れた半導体パッケージ1を備えるので、信頼性に優れる。 According to the semiconductor device 100 as described above, since the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
 以上、本発明の半導体パッケージおよび半導体装置を、図示の実施形態に基づいて説明したが、本発明はこれらに限定されるものでない。 As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.
 例えば、前述した実施形態では、第1補強部材4が半導体素子3の全周に亘って囲むように設けられていたが、これに限定されず、例えば、半導体素子3の周囲の一部に欠損した部分(切り欠き)が形成されていてもよい。 For example, in the above-described embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.
 また、第1補強部材4の剛性や配線基板2の厚さ等によっては、第2補強部材5を省略してもよい。 Further, the second reinforcing member 5 may be omitted depending on the rigidity of the first reinforcing member 4 and the thickness of the wiring board 2.
 また、前述した実施形態では、第1補強部材4と第2補強部材5とを接続する熱伝導部として、基板21を貫通する伝熱ポスト24を用いたが、例えば、基板21の外側に設けた熱伝導部材(金属部材)を用いてもよい。この場合、伝熱性接着剤を用いて熱伝導部材を基板21、第1補強部材4および第2補強部材5に接着(接合)してもよいし、基板21の側面側から基板21、第1補強部材4および第2補強部材5を上下から銜えこむような形態としてもよい。 In the above-described embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below.
 また、第1補強部材4に形成される開口部は、各金属バンプ400と一対一で対応していなくてもよい。すなわち、第1補強部材4には、複数の金属バンプ400に対して1つが対応するように、開口部が形成されていてもよい。 Further, the opening formed in the first reinforcing member 4 may not correspond to each metal bump 400 on a one-to-one basis. That is, an opening may be formed in the first reinforcing member 4 so that one corresponds to the plurality of metal bumps 400.
 また、第2補強部材5に形成される開口部は、各金属バンプ71と一対一で対応していなくてもよい。すなわち、第2補強部材5には、複数の金属バンプ71に対して1つが対応するように、開口部が形成されていてもよい。 Further, the opening formed in the second reinforcing member 5 may not correspond to each metal bump 71 on a one-to-one basis. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.
 <第4実施形態>
 次に、本発明の第4実施形態を説明する。
<Fourth embodiment>
Next, a fourth embodiment of the present invention will be described.
 図8は、本発明の第4実施形態に係る半導体パッケージを模式的に示す断面図である。なお、以下の説明では、説明の便宜上、図8中の上側を「上」、下側を「下」と言う。また、図8では、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 FIG. 8 is a cross-sectional view schematically showing a semiconductor package according to the fourth embodiment of the present invention. In the following description, for convenience of explanation, the upper side in FIG. 8 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 8, for convenience of explanation, each part of the semiconductor package is exaggerated.
 以下、第4実施形態の半導体パッケージについて、前述した実施形態との相違点を中心に説明し、同様の事項については、その説明を省略する。なお、図8において、前述した実施形態と同様の構成については、同一符号を付している。
 第4実施形態の半導体パッケージは、第1半導体素子と第2配線基板とが接触する以外は、第1実施形態と同様である。
Hereinafter, the semiconductor package of the fourth embodiment will be described focusing on differences from the above-described embodiment, and description of similar matters will be omitted. In FIG. 8, the same reference numerals are given to the same configurations as those in the above-described embodiment.
The semiconductor package of the fourth embodiment is the same as that of the first embodiment except that the first semiconductor element and the second wiring board are in contact with each other.
 (半導体パッケージ)
 図8に示すように、半導体素子3と配線基板301とが接触しているため、半導体素子3の熱を配線基板301を通じて外方へ効率的に逃すことができる。
(Semiconductor package)
As shown in FIG. 8, since the semiconductor element 3 and the wiring board 301 are in contact, the heat of the semiconductor element 3 can be efficiently released to the outside through the wiring board 301.
 また、各金属バンプ400の大きさ(直径)は、半導体素子3と配線基板301とが接触する程度に設定される。 Further, the size (diameter) of each metal bump 400 is set to such an extent that the semiconductor element 3 and the wiring board 301 are in contact with each other.
[半導体素子]
 トップパッケージ300の配線基板301の下面は、前述したボトムパッケージ500の半導体素子3と接触している。本実施形態では、半導体素子3の上面のほぼ全域が配線基板301の下面に接触している。これにより、半導体素子3の熱を配線基板301を通じて外方へ効率的に逃すことができる。なお、半導体素子3の上面のうちの一部が配線基板301の下面に接触していなくてもよい。
[Semiconductor element]
The lower surface of the wiring substrate 301 of the top package 300 is in contact with the semiconductor element 3 of the bottom package 500 described above. In the present embodiment, almost the entire upper surface of the semiconductor element 3 is in contact with the lower surface of the wiring substrate 301. Thereby, the heat of the semiconductor element 3 can be efficiently released to the outside through the wiring board 301. A part of the upper surface of the semiconductor element 3 may not be in contact with the lower surface of the wiring substrate 301.
 半導体素子3と配線基板301との間に隙間が形成される場合、その隙間には、前述した熱伝導性材料6と同様の熱伝導性材料(熱伝導性接着剤)を充填するのが好ましい。この場合、例えば、半導体素子3と配線基板301とを熱伝導性材料を介して接着するのが好ましい。これにより、簡単かつ確実に、半導体素子3と配線基板301との間の熱伝導性を優れたものとすることができる。また、半導体素子3と配線基板301とを接着することにより、配線基板301が補強され、半導体パッケージ1全体の剛性が増す。 When a gap is formed between the semiconductor element 3 and the wiring substrate 301, it is preferable to fill the gap with a heat conductive material (thermal conductive adhesive) similar to the above-described heat conductive material 6. . In this case, for example, it is preferable to bond the semiconductor element 3 and the wiring substrate 301 via a heat conductive material. Thereby, the thermal conductivity between the semiconductor element 3 and the wiring substrate 301 can be made excellent and easy and reliable. Further, by bonding the semiconductor element 3 and the wiring board 301, the wiring board 301 is reinforced and the rigidity of the entire semiconductor package 1 is increased.
 また、本実施形態では、前述したように半導体素子3の上面と第1補強部材4の上面とが同一面上に位置しているので、配線基板301の下面は、前述したボトムパッケージ500の第1補強部材4の上面に接触(面接触)している。本実施形態では、第1補強部材4の上面のほぼ全域が配線基板301の下面に接触している。このように第1補強部材4が配線基板301に対して接触していることにより、配線基板2と配線基板301との間の伝熱を第1補強部材4を介して行うことができる。そのため、半導体パッケージ1の放熱性を優れたものとすることができる。なお、第1補強部材4の上面のうちの一部が配線基板301の下面に接触していなくてもよい。 In the present embodiment, since the upper surface of the semiconductor element 3 and the upper surface of the first reinforcing member 4 are located on the same plane as described above, the lower surface of the wiring board 301 is the same as that of the bottom package 500 described above. 1 The top surface of the reinforcing member 4 is in contact (surface contact). In the present embodiment, almost the entire upper surface of the first reinforcing member 4 is in contact with the lower surface of the wiring board 301. Since the first reinforcing member 4 is in contact with the wiring board 301 in this manner, heat transfer between the wiring board 2 and the wiring board 301 can be performed via the first reinforcing member 4. Therefore, the heat dissipation of the semiconductor package 1 can be made excellent. A part of the upper surface of the first reinforcing member 4 may not be in contact with the lower surface of the wiring board 301.
 第1補強部材4と配線基板301との間に隙間が形成される場合、その隙間には、前述した熱伝導性材料6と同様の熱伝導性材料(熱伝導性接着剤)を充填するのが好ましい。この場合、例えば、第1補強部材4と配線基板301とを熱伝導性材料を介して接着するのが好ましい。これにより、簡単かつ確実に、第1補強部材4と配線基板301との間の熱伝導性を優れたものとすることができる。また、第1補強部材4と配線基板301とを接着することにより、配線基板301も第1補強部材4により補強され、半導体パッケージ1全体の剛性が増す。 When a gap is formed between the first reinforcing member 4 and the wiring board 301, the gap is filled with the same heat conductive material (heat conductive adhesive) as the heat conductive material 6 described above. Is preferred. In this case, for example, it is preferable that the first reinforcing member 4 and the wiring board 301 are bonded via a heat conductive material. Thereby, the heat conductivity between the 1st reinforcement member 4 and the wiring board 301 can be made excellent easily and reliably. Further, by bonding the first reinforcing member 4 and the wiring board 301, the wiring board 301 is also reinforced by the first reinforcing member 4, and the rigidity of the entire semiconductor package 1 is increased.
 また、半導体素子3と配線基板301とが接触しているため、半導体素子3の熱を配線基板301を通じて外方へ効率的に逃すことができる。 Further, since the semiconductor element 3 and the wiring board 301 are in contact, the heat of the semiconductor element 3 can be efficiently released to the outside through the wiring board 301.
(半導体パッケージの製造方法)
 図11(h)に示すように、トップパッケージ300を用意し、金属バンプ400A(金属バンプ400)を介してトップパッケージ300とボトムパッケージ500とを半田接合により接合する。その際、トップパッケージ300とボトムパッケージ500とが互いに近づく方向にこれらを加圧する。これにより前記接合後において、トップパッケージ300の配線基板301の下面とボトムパッケージ500の半導体素子3の上面とが接触した状態とすることができる。
 以上のようにして、半導体パッケージ1が得られる。
(Semiconductor package manufacturing method)
As shown in FIG. 11 (h), the top package 300 is prepared, and the top package 300 and the bottom package 500 are joined to each other by solder bonding via the metal bump 400A (metal bump 400). At that time, the top package 300 and the bottom package 500 are pressurized in a direction approaching each other. Thereby, after the joining, the lower surface of the wiring substrate 301 of the top package 300 and the upper surface of the semiconductor element 3 of the bottom package 500 can be brought into contact with each other.
The semiconductor package 1 is obtained as described above.
 <第5実施形態>
 次に、本発明の第5実施形態を説明する。
<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described.
 図12は、本発明の第5実施形態に係る半導体パッケージを模式的に示す断面図である。また、図12では、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 FIG. 12 is a cross-sectional view schematically showing a semiconductor package according to the fifth embodiment of the present invention. Also, in FIG. 12, for convenience of explanation, each part of the semiconductor package is exaggerated.
 以下、第5実施形態の半導体パッケージについて、前述した実施形態との相違点を中心に説明し、同様の事項については、その説明を省略する。なお、図12において、前述した実施形態と同様の構成については、同一符号を付している。
 第5実施形態の半導体パッケージは、第1半導体素子と第2配線基板とが接触する以外は、第2実施形態と同様である。
Hereinafter, the semiconductor package of the fifth embodiment will be described focusing on differences from the above-described embodiment, and description of similar matters will be omitted. In FIG. 12, the same components as those in the above-described embodiment are denoted by the same reference numerals.
The semiconductor package of the fifth embodiment is the same as that of the second embodiment except that the first semiconductor element and the second wiring board are in contact with each other.
 図12に示すように、第1補強部材4Aは、配線基板301に対して非接触である。これにより、第1補強部材4Aと配線基板301との間に形成された隙間Sを通じて、通気を行うことができる。そのため、半導体パッケージ1Aの放熱性を優れたものとすることができる。なお第1補強部材4Aは、配線基板301に対して接触した部分を部分的に有していてもよい。このような場合においても、第1補強部材4Aと配線基板301との間に通気のための隙間を形成することができる。 As shown in FIG. 12, the first reinforcing member 4 </ b> A is not in contact with the wiring board 301. Thereby, ventilation can be performed through the gap S formed between the first reinforcing member 4 </ b> A and the wiring board 301. Therefore, the heat dissipation of the semiconductor package 1A can be made excellent. Note that the first reinforcing member 4 </ b> A may partially have a portion in contact with the wiring substrate 301. Even in such a case, a gap for ventilation can be formed between the first reinforcing member 4 </ b> A and the wiring board 301.
 このような第1補強部材4Aの厚さは、半導体素子3の厚さと金属バンプ31の厚さとの合計厚さよりも薄い。これにより、前述したような隙間Sを簡単かつ確実に形成することができる。 The thickness of the first reinforcing member 4A is smaller than the total thickness of the semiconductor element 3 and the metal bump 31. Thereby, the gap S as described above can be easily and reliably formed.
 また、第1補強部材4Aと配線基板301との間の距離(すなわち隙間Sの厚さ方向での長さ)Lは、前述したような通気を確保する観点から、0.02mm以上0.5mm以下程度であるのが好ましい。 In addition, the distance L between the first reinforcing member 4A and the wiring board 301 (that is, the length of the gap S in the thickness direction) L is 0.02 mm or more and 0.5 mm from the viewpoint of ensuring ventilation as described above. It is preferable that it is about the following.
 <第6実施形態>
 次に、本発明の第6実施形態を説明する。
<Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described.
 図13は、本発明の第6実施形態に係る半導体パッケージを模式的に示す断面図である。また、図13では、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 FIG. 13 is a cross-sectional view schematically showing a semiconductor package according to the sixth embodiment of the present invention. In FIG. 13, for convenience of explanation, each part of the semiconductor package is exaggerated.
 以下、第6実施形態の半導体パッケージについて、前述した実施形態との相違点を中心に説明し、同様の事項については、その説明を省略する。なお、図13において、前述した実施形態と同様の構成については、同一符号を付している。
 第6実施形態の半導体パッケージは、第1半導体素子と第2配線基板とが接触する以外は、第3実施形態と同様である。
Hereinafter, the semiconductor package of the sixth embodiment will be described focusing on the differences from the above-described embodiment, and description of similar matters will be omitted. In FIG. 13, the same reference numerals are given to the same configurations as those in the above-described embodiment.
The semiconductor package of the sixth embodiment is the same as that of the third embodiment except that the first semiconductor element and the second wiring board are in contact with each other.
(半導体装置)
 図14は、本発明の半導体装置の実施形態の一例を模式的に示す断面図である。
 図14に示すように、半導体装置100は、マザーボード(基板)200と、このマザーボード200に搭載された半導体パーケージ1とを有している。
(Semiconductor device)
FIG. 14 is a cross-sectional view schematically showing an example of an embodiment of a semiconductor device of the present invention.
As shown in FIG. 14, the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.
 熱による不具合の発生を防止することができる半導体パッケージおよび半導体装置を提供することができる。 It is possible to provide a semiconductor package and a semiconductor device that can prevent the occurrence of defects due to heat.
1    半導体パッケージ
1A   半導体パッケージ
1B   半導体パッケージ
2    配線基板
3    半導体素子
4A   第1補強部材
4    第1補強部材
5    第2補強部材
5B   補強部材
6    熱伝導性材料
21    基板
24    伝熱ポスト
31    金属バンプ
32    接着層
33    外周面
41    内周面
42    開口部
51    開口部
52    部分
53    部分
71    金属バンプ
71A    金属ボール
81    絶縁材
81A    絶縁材
91    伝熱バンプ
100    半導体装置
200    マザーボード
201    端子
202    端子
211    絶縁層
211A    プリプレグ
212    絶縁層
213    絶縁層
214    絶縁層
215    絶縁層
221    導体パターン
221A    金属層
222    導体パターン
222A    金属層
223    導体パターン
224    導体パターン
225    導体パターン
231    導体ポスト
232    導体ポスト
233    導体ポスト
234    導体ポスト
300    トップパッケージ
301    配線基板
302    基板
303    絶縁層
304    絶縁層
305    半導体素子
306    金属ワイヤー
307    封止部
308    導体パターン
400    金属バンプ
400A   金属バンプ
500    ボトムパッケージ
500A   ボトムパッケージ
500B   ボトムパッケージ
600    トップパッケージ
401    絶縁材
2111   貫通孔
S      隙間
S1     隙間
S2     隙間
T2     厚さ
DESCRIPTION OF SYMBOLS 1 Semiconductor package 1A Semiconductor package 1B Semiconductor package 2 Wiring board 3 Semiconductor element 4A 1st reinforcement member 4 1st reinforcement member 5 2nd reinforcement member 5B Reinforcement member 6 Thermally conductive material 21 Substrate 24 Heat transfer post 31 Metal bump 32 Adhesive layer 33 outer peripheral surface 41 inner peripheral surface 42 opening 51 opening 52 part 53 part 71 metal bump 71A metal ball 81 insulating material 81A insulating material 91 heat transfer bump 100 semiconductor device 200 motherboard 201 terminal 202 terminal 211 insulating layer 211A prepreg 212 insulating layer 213 Insulating layer 214 Insulating layer 215 Insulating layer 221 Conductor pattern 221A Metal layer 222 Conductor pattern 222A Metal layer 223 Conductor pattern 224 Conductor pattern 225 Body pattern 231 Conductor post 232 Conductor post 233 Conductor post 234 Conductor post 300 Top package 301 Wiring substrate 302 Substrate 303 Insulating layer 304 Insulating layer 305 Semiconductor element 306 Metal wire 307 Sealing portion 308 Conductor pattern 400 Metal bump 400A Metal bump 500 Bottom package 500A Bottom package 500B Bottom package 600 Top package 401 Insulating material 2111 Through hole S Gap S1 Gap S2 Gap T2 Thickness

Claims (25)

  1.  第1配線基板と、
     前記第1配線基板の一方の面に接合された第1半導体素子と、
     前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
     前記補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
     前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
     前記第1半導体素子は、前記第2配線基板に対して非接触であることを特徴とする半導体パッケージ。
    A first wiring board;
    A first semiconductor element bonded to one surface of the first wiring board;
    A reinforcing member bonded to a portion of the surface of the first wiring substrate on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring substrate;
    A second wiring board provided on the side opposite to the first wiring board with respect to the reinforcing member and joined to the first wiring board via two or more metal bumps;
    A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
    The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
  2.  第1配線基板と、
     前記第1配線基板の一方の面に接合された第1半導体素子と、
     前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
     前記補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
     前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
     前記第1半導体素子は、前記第2配線基板に対して接触していることを特徴とする半導体パッケージ。
    A first wiring board;
    A first semiconductor element bonded to one surface of the first wiring board;
    A reinforcing member bonded to a portion of the surface of the first wiring substrate on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring substrate;
    A second wiring board provided on the side opposite to the first wiring board with respect to the reinforcing member and joined to the first wiring board via two or more metal bumps;
    A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
    The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
  3.  第1配線基板と、
     前記第1配線基板の一方の面に接合された第1半導体素子と、
     前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
     前記第1半導体素子に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
     前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
     前記第1半導体素子は、前記第2配線基板に対して非接触であることを特徴とする半導体パッケージ。
    A first wiring board;
    A first semiconductor element bonded to one surface of the first wiring board;
    A reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
    A second wiring board provided on the opposite side of the first wiring board with respect to the first semiconductor element and bonded to the first wiring board via two or more metal bumps;
    A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
    The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
  4.  第1配線基板と、
     前記第1配線基板の一方の面に接合された第1半導体素子と、
     前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい補強部材と、
     前記第1半導体素子に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
     前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
     前記第1半導体素子は、前記第2配線基板に対して接触していることを特徴とする半導体パッケージ。
    A first wiring board;
    A first semiconductor element bonded to one surface of the first wiring board;
    A reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
    A second wiring board provided on the opposite side of the first wiring board with respect to the first semiconductor element and bonded to the first wiring board via two or more metal bumps;
    A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
    The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
  5.  第1配線基板と、
     前記第1配線基板の一方の面に接合された第1半導体素子と、
     前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい第1補強部材と、
     前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい第2補強部材と、
     前記第1補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
     前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
     前記第1半導体素子は、前記第2配線基板に対して非接触であることを特徴とする半導体パッケージ。
    A first wiring board;
    A first semiconductor element bonded to one surface of the first wiring board;
    A first reinforcing member bonded to a portion of the surface of the first wiring board on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring board;
    A second reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
    A second wiring board provided on the opposite side of the first wiring board with respect to the first reinforcing member and joined to the first wiring board via two or more metal bumps;
    A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
    The semiconductor package according to claim 1, wherein the first semiconductor element is not in contact with the second wiring board.
  6.  第1配線基板と、
     前記第1配線基板の一方の面に接合された第1半導体素子と、
     前記第1配線基板の前記第1半導体素子側の面の、前記第1半導体素子が接合されていない部分に接合され、前記第1配線基板よりも熱膨張係数が小さい第1補強部材と、
     前記第1配線基板の前記第1半導体素子とは反対側の面に接合され、前記第1配線基板よりも熱膨張係数が小さい第2補強部材と、
     前記第1補強部材に対して前記第1配線基板とは反対側に設けられ、2つ以上の金属バンプを介して前記第1配線基板に接合された第2配線基板と、
     前記第2配線基板の前記第1配線基板とは反対側の面に接合された第2半導体素子とを有し、
     前記第1半導体素子は、前記第2配線基板に対して接触していることを特徴とする半導体パッケージ。
    A first wiring board;
    A first semiconductor element bonded to one surface of the first wiring board;
    A first reinforcing member bonded to a portion of the surface of the first wiring board on the first semiconductor element side where the first semiconductor element is not bonded, and having a smaller thermal expansion coefficient than the first wiring board;
    A second reinforcing member bonded to a surface of the first wiring board opposite to the first semiconductor element and having a smaller coefficient of thermal expansion than the first wiring board;
    A second wiring board provided on the opposite side of the first wiring board with respect to the first reinforcing member and joined to the first wiring board via two or more metal bumps;
    A second semiconductor element bonded to a surface of the second wiring board opposite to the first wiring board;
    The semiconductor package, wherein the first semiconductor element is in contact with the second wiring board.
  7.  前記第1補強部材は、前記第1半導体素子の周囲を囲むような形状をなす請求項5または6に記載の半導体パッケージ。 The semiconductor package according to claim 5 or 6, wherein the first reinforcing member has a shape surrounding the periphery of the first semiconductor element.
  8.  前記第1半導体素子と前記第2配線基板との間の距離が0.01mm以上0.8mm以下である請求項1、3、5および7のいずれかに記載の半導体パッケージ。 The semiconductor package according to any one of claims 1, 3, 5, and 7, wherein a distance between the first semiconductor element and the second wiring board is 0.01 mm or more and 0.8 mm or less.
  9.  前記第1補強部材は、前記第2配線基板に対して非接触である請求項5ないし8のいずれかに記載の半導体パッケージ。 9. The semiconductor package according to claim 5, wherein the first reinforcing member is not in contact with the second wiring board.
  10.  前記第1補強部材は、前記第2配線基板に対して接触している請求項6または7に記載の半導体パッケージ。 The semiconductor package according to claim 6 or 7, wherein the first reinforcing member is in contact with the second wiring board.
  11.  前記第1補強部材と前記第2配線基板との間の距離は、前記第1半導体素子と前記第2配線基板との間の距離よりも大きい請求項9に記載の半導体パッケージ。 10. The semiconductor package according to claim 9, wherein a distance between the first reinforcing member and the second wiring board is larger than a distance between the first semiconductor element and the second wiring board.
  12.  前記第1補強部材は、前記各金属バンプに対して非接触で前記各金属バンプを囲むように形成された2つ以上の開口部を有する請求項5ないし11のいずれかに記載の半導体パッケージ。 12. The semiconductor package according to claim 5, wherein the first reinforcing member has two or more openings formed so as to surround the metal bumps in a non-contact manner with respect to the metal bumps.
  13.  前記第1補強部材と前記各金属バンプとの間には、絶縁材が設けられている請求項5ないし12のいずれかに記載の半導体パッケージ。 13. The semiconductor package according to claim 5, wherein an insulating material is provided between the first reinforcing member and each of the metal bumps.
  14.  前記第1補強部材および前記第2補強部材は、それぞれ、前記第1半導体素子との熱膨張係数差が7ppm/℃以下である請求項5ないし13のいずれかに記載の半導体パッケージ。 14. The semiconductor package according to claim 5, wherein each of the first reinforcing member and the second reinforcing member has a thermal expansion coefficient difference of 7 ppm / ° C. or less with respect to the first semiconductor element.
  15.  前記第1補強部材および前記第2補強部材は、それぞれ、板状をなす請求項5ないし14のいずれかに記載の半導体パッケージ。 15. The semiconductor package according to claim 5, wherein each of the first reinforcing member and the second reinforcing member has a plate shape.
  16.  前記第1補強部材および前記第2補強部材は、それぞれ、金属材料で構成されている請求項5ないし15のいずれかに記載の半導体パッケージ。 16. The semiconductor package according to claim 5, wherein each of the first reinforcing member and the second reinforcing member is made of a metal material.
  17.  前記金属材料は、Fe-Ni系合金である請求項16に記載の半導体パッケージ。 The semiconductor package according to claim 16, wherein the metal material is an Fe-Ni alloy.
  18.  請求項1ないし17のいずれかに記載の半導体パッケージを備えることを特徴とする半導体装置。 A semiconductor device comprising the semiconductor package according to claim 1.
  19.  第1配線基板に第1補強部材を接合する工程と、
     前記第1配線基板に第1半導体素子を接合して、ボトムパッケージを形成する工程と、
     第2配線基板に第2半導体素子を接合して、トップパッケージを形成する工程と、
     2つ以上の金属バンプを介して、前記トップパッケージと前記ボトムパッケージとを接合する工程とを含む、
     請求項1ないし17のいずれかに記載の半導体パッケージの製造方法。
    Joining the first reinforcing member to the first wiring board;
    Bonding a first semiconductor element to the first wiring substrate to form a bottom package;
    Bonding a second semiconductor element to a second wiring substrate to form a top package;
    Joining the top package and the bottom package via two or more metal bumps,
    A method for manufacturing a semiconductor package according to claim 1.
  20.  第1配線基板に第2補強部材を接合する工程と、
     前記第1配線基板の前記第2補強部材とは反対側の面に、第1半導体素子を接合して、ボトムパッケージを形成する工程と、
     第2配線基板に第2半導体素子を接合して、トップパッケージを形成する工程と、
     2つ以上の金属バンプを介して、前記トップパッケージと前記ボトムパッケージとを接合する工程とを含む、
     請求項1ないし17のいずれかに記載の半導体パッケージの製造方法。
    Bonding the second reinforcing member to the first wiring board;
    Bonding a first semiconductor element to a surface of the first wiring board opposite to the second reinforcing member to form a bottom package;
    Bonding a second semiconductor element to a second wiring substrate to form a top package;
    Joining the top package and the bottom package via two or more metal bumps,
    A method for manufacturing a semiconductor package according to claim 1.
  21.  第1配線基板に第1補強部材を接合する工程と、
     前記第1配線基板に第2補強部材を接合する工程と、
     前記第1配線基板の前記第2補強部材とは反対側の面に、第1半導体素子を接合して、ボトムパッケージを形成する工程と、
     第2配線基板に第2半導体素子を接合して、トップパッケージを形成する工程と、
     2つ以上の金属バンプを介して、前記トップパッケージと前記ボトムパッケージとを接合する工程とを含む、
     請求項1ないし17のいずれかに記載の半導体パッケージの製造方法。
    Joining the first reinforcing member to the first wiring board;
    Bonding a second reinforcing member to the first wiring board;
    Bonding a first semiconductor element to a surface of the first wiring board opposite to the second reinforcing member to form a bottom package;
    Bonding a second semiconductor element to a second wiring substrate to form a top package;
    Joining the top package and the bottom package via two or more metal bumps,
    A method for manufacturing a semiconductor package according to claim 1.
  22.  前記第1配線基板に第1補強部材を接合する工程が、
     金属層とプリプレグとの積層体を用意し、前記積層体のプリプレグ側の面に、第1補強部材を接合するサブ工程と、
     前記プリプレグに貫通孔を形成するサブ工程と、
     前記貫通孔に導体ポストを形成するサブ工程と、
     前記金属層をパターンニングすることにより、導体パターンを形成するサブ工程と、
     前記プリプレグを硬化させるサブ工程とを含む、
     請求項19または21に記載の半導体パッケージの製造方法。
    Joining the first reinforcing member to the first wiring board;
    Preparing a laminate of the metal layer and the prepreg, and joining the first reinforcing member to the prepreg side surface of the laminate;
    A sub-process for forming a through hole in the prepreg;
    A sub-step of forming a conductor post in the through hole;
    A sub-process of forming a conductor pattern by patterning the metal layer;
    A sub-step of curing the prepreg.
    The method of manufacturing a semiconductor package according to claim 19 or 21.
  23.  前記金属バンプの冷却に伴って、前記金属バンプが厚さ方向に膨張し、前記トップパッケージの第2配線基板と前記ボトムパッケージの第1半導体素子とが離間した状態となる、請求項19ないし22のいずれかに記載の半導体パッケージの製造方法。 23. The metal bumps expand in the thickness direction as the metal bumps are cooled, and the second wiring board of the top package and the first semiconductor element of the bottom package are separated from each other. The manufacturing method of the semiconductor package in any one of.
  24.  前記トップパッケージと前記ボトムパッケージとの間にスペーサを配置し、前記トップパッケージと前記ボトムパッケージの接合後に、前記スペーサを取り除くことによって、前記トップパッケージの第2配線基板と前記ボトムパッケージの第1半導体素子とが離間した状態となる、請求項19ないし22のいずれかに記載の半導体パッケージの製造方法。 A spacer is disposed between the top package and the bottom package, and after the top package and the bottom package are joined, the spacer is removed, whereby the second wiring substrate of the top package and the first semiconductor of the bottom package The method for manufacturing a semiconductor package according to claim 19, wherein the device is in a state of being separated from the device.
  25.  前記トップパッケージと前記ボトムパッケージとが互いに近づく方向にこれらを加圧して、前記トップパッケージの第2配線基板と前記ボトムパッケージの第1半導体素子とが接触した状態となる、請求項19ないし22のいずれかに記載の半導体パッケージの製造方法。 The top package and the bottom package are pressed in a direction approaching each other, and the second wiring board of the top package and the first semiconductor element of the bottom package are in contact with each other. The manufacturing method of the semiconductor package in any one.
PCT/JP2011/069641 2010-09-17 2011-08-30 Semiconductor package and semiconductor device WO2012035972A1 (en)

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