WO2012029579A1 - Semiconductor package and semiconductor device - Google Patents

Semiconductor package and semiconductor device Download PDF

Info

Publication number
WO2012029579A1
WO2012029579A1 PCT/JP2011/068881 JP2011068881W WO2012029579A1 WO 2012029579 A1 WO2012029579 A1 WO 2012029579A1 JP 2011068881 W JP2011068881 W JP 2011068881W WO 2012029579 A1 WO2012029579 A1 WO 2012029579A1
Authority
WO
WIPO (PCT)
Prior art keywords
reinforcing member
substrate
semiconductor package
conductor pattern
wiring board
Prior art date
Application number
PCT/JP2011/068881
Other languages
French (fr)
Japanese (ja)
Inventor
岡田　亮一
賢也 橘
猛 八月朔日
Original Assignee
住友ベークライト株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友ベークライト株式会社 filed Critical 住友ベークライト株式会社
Priority to JP2012531805A priority Critical patent/JPWO2012029579A1/en
Publication of WO2012029579A1 publication Critical patent/WO2012029579A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present invention relates to a semiconductor package and a semiconductor device.
  • This application is based on Japanese Patent Application Nos. 2010-192904 and 2010-192905 filed in Japan on August 30, 2010, and Japanese Patent Application No. 2010-210158 filed in Japan on September 17, 2010. Claim priority and incorporate the contents here.
  • BGA Bit Grid
  • CSP Chip Scale Package
  • Interposers used for new packages such as BGA and CSP are generally formed by forming a conductor pattern or a conductor post on a substrate obtained by impregnating a fiber base material with a resin composition.
  • Such an interposer has a large difference in thermal expansion coefficient from the chip. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion that is not in contact with the chip has a very low rigidity, and thus tends to warp due to the difference in thermal expansion between the chip and the interposer as described above, resulting in a problem that reliability of electrical connection is lowered. Moreover, since the chip generates heat, the interposer is required to have excellent heat dissipation.
  • An object of the present invention is to provide a semiconductor package and a semiconductor device that can prevent the occurrence of defects due to heat.
  • Another object of the present invention is to provide a semiconductor package and a semiconductor device that can be thinned.
  • a substrate a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • a wiring board comprising: A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern; A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate; A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate, The said reinforcement member has a part located between the said metal bumps in non-contact with each said metal bump,
  • the semiconductor package characterized by the above-mentioned.
  • the reinforcing member has a plurality of openings, The semiconductor package according to (1), wherein a portion between the openings of the reinforcing member is positioned between the metal bumps without contacting the metal bumps.
  • a substrate a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • a wiring board comprising: A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern; A second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate; A semiconductor package comprising heat transfer bumps provided on a surface of the second reinforcing member opposite to the substrate and having higher thermal conductivity than the substrate.
  • a plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate, Said 2nd reinforcement member is a semiconductor package in any one of said (6) thru
  • each of the first reinforcing member and the second reinforcing member has a plate shape.
  • each of the first reinforcing member and the second reinforcing member is made of a metal material.
  • a substrate a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • a wiring board comprising: A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern; A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate; When the area of the semiconductor element in plan view is S1, and the area in the region surrounded by the outer periphery of the reinforcing member in plan view is S2, S2 / S1 is 0.64 or more and 2.25 or less, The semiconductor package characterized by the above-mentioned.
  • a plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate, and the reinforcing member is a portion located between the metal bumps in a non-contact manner with the metal bumps.
  • a semiconductor device comprising the semiconductor package according to any one of (1) to (25).
  • the wiring board is sandwiched between the semiconductor element and the reinforcing member by bonding the reinforcing member having a thermal expansion coefficient smaller than that of the board to the surface of the wiring board opposite to the semiconductor element. Therefore, the rigidity of the entire semiconductor package can be increased, and the difference in thermal expansion between both surfaces of the wiring board can be prevented or suppressed.
  • the reinforcing member is provided so as to extend between the metal bumps, the wiring board can be strongly reinforced.
  • the semiconductor package of the present invention can release heat from the semiconductor element through the wiring board, and is excellent in heat dissipation.
  • the semiconductor package provided with the heat transfer bump the heat from the semiconductor element can be released through the heat transfer bump, and the heat dissipation is more excellent. Since the heat dissipation is excellent in this manner, the temperature rise of the semiconductor element and the wiring board can be suppressed, so that the wiring board warpage caused by the difference in thermal expansion coefficient between the wiring board and the semiconductor element can be reduced. It can be suppressed or prevented.
  • the semiconductor device of the present invention since the semiconductor package as described above is provided, the reliability is excellent.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention. It is a top view which shows the semiconductor package shown in FIG. It is a bottom view which shows the semiconductor package shown in FIG. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor device which concerns on 4th Embodiment of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows typically the semiconductor package which concerns on 3rd Embodiment of this invention.
  • FIG. 8 is a top view showing the semiconductor package shown in FIG. 7.
  • FIG. 8 is a bottom view showing the semiconductor package shown in FIG. 7.
  • FIG. 12 is a bottom view showing the semiconductor package shown in FIG. 11. It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. It is sectional drawing which shows typically the semiconductor device which concerns on 6th Embodiment of this invention.
  • FIG. 1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention
  • FIG. 2 is a top view showing the semiconductor package shown in FIG. 1
  • FIG. 3 shows the semiconductor package shown in FIG.
  • FIG. 4 is a bottom view
  • FIG. 4 is a view showing an example of a method for manufacturing the semiconductor package shown in FIG.
  • the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”.
  • each part of the semiconductor package is exaggerated for convenience of explanation.
  • the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member 4, and a second reinforcing member 5.
  • both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Increases overall rigidity.
  • the thermal expansion coefficient of the first reinforcing member 4 and the second reinforcing member 5 is smaller than that of the wiring substrate 2 (specifically, a substrate 21 described later), the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. In the same manner, warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be suppressed or prevented.
  • the semiconductor package 1 can release the heat from the semiconductor element 3 through the wiring board 2 and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
  • the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5 by bonding the second reinforcing member 5 to the surface (lower surface) opposite to the semiconductor element 3 of the wiring board 2. Therefore, the difference in thermal expansion between both surfaces of the wiring board 2 can be prevented or suppressed.
  • the second reinforcing member 5 is provided so as to extend between metal bumps 71 described later, the wiring board 2 can be strongly reinforced.
  • the wiring board 2 is a board that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later.
  • the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.
  • the wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, 234, and heat transfer posts 24.
  • the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21.
  • a second conductor pattern electrically connected to the conductor pattern is formed. By being electrically connected, an electric signal can be transmitted between the first conductor pattern and the second conductor pattern.
  • the substrate 21 is composed of a plurality (five layers in this embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order.
  • the number of insulating layers constituting the substrate 21 is not limited to this, and may be 1 to 4 layers or 6 or more layers.
  • Each insulating layer 211, 212, 213, 214, 215 is made of an insulating material.
  • each insulating layer 211, 212, 213, 214, 215 is composed of a base material (fiber base material) and a resin composition impregnated in the base material.
  • the base material is used as a core material of the insulating layers 211, 212, 213, 214, and 215. By having such a base material, the rigidity of the substrate 21 can be increased.
  • the base material examples include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthetic fiber base material, kraft paper composed of woven fabric or non-woven fabric mainly composed of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, etc. And paper base materials mainly composed of cotton linter paper, mixed paper of linter and kraft pulp, and the like. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Furthermore, the thermal expansion coefficient of the substrate 21 can be reduced.
  • Examples of the glass constituting such a glass fiber substrate include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, and H glass.
  • T glass is preferable.
  • the thermal expansion coefficient of a glass fiber base material can be made small, and, thereby, the thermal expansion coefficient of the board
  • substrate 21 can be made small.
  • the content of the base material in the insulating layers 211, 212, 213, 214, and 215 is preferably 30 to 70 wt%, respectively. 40 to 60 wt% is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers.
  • at least one of the insulating layers 211, 212, 213, 214, and 215 may be composed of only the resin composition without including the base material.
  • the resin composition impregnated in such a base material contains a resin material.
  • a resin material a thermosetting resin is preferably used.
  • thermosetting resin examples include novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like.
  • novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like.
  • phenol resin such as resol type phenol resin
  • bisphenol type epoxy resin such as bisphenol A epoxy resin
  • bisphenol F epoxy resin novolac epoxy resin
  • novolac epoxy resin such as novolac epoxy resin, cresol novolac epoxy resin, biphenyl type epoxy resin, etc.
  • resin having triazine ring such as melamine resin, unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate Over preparative resin, silicone resin, resins having a benzoxazine ring, cyanate ester resins.
  • cyanate resin is particularly preferable.
  • substrate 21 can be made small enough.
  • the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.
  • the resin composition preferably contains a filler. That is, each of the insulating layers 211, 212, 213, 214, and 215 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be lowered.
  • Examples of the filler include various inorganic fillers or organic fillers.
  • Examples of the inorganic filler include oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, and hydroxide such as aluminum hydroxide and magnesium hydroxide.
  • organic filler synthetic resin powder
  • synthetic resin powder examples include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene.
  • various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins may be mentioned.
  • organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.
  • the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be effectively reduced.
  • the heat transfer properties of the insulating layers 211, 212, 213, 214, and 215 can be increased.
  • silica is preferable, and fused silica (especially spherical fused silica) is preferable in terms of excellent low thermal expansion.
  • the average particle size of the inorganic filler is not particularly limited, but is preferably 0.05 to 2.0 ⁇ m, particularly preferably 0.1 to 1.0 ⁇ m.
  • the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, 213, 214, and 215, and the physical strength and insulating properties of the insulating layers 211, 212, 213, 214, and 215 are particularly improved. It can be excellent.
  • the average particle size of the inorganic filler can be measured by, for example, a particle size distribution meter (manufactured by HORIBA, LA-500). Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.
  • the content of the inorganic filler in the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but is preferably 30 to 80 wt% when the resin composition excluding the base material is 100 wt%, particularly 45 to 75 wt% is preferable.
  • the insulating layers 211, 212, 213, 214, and 215 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.
  • the resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin in addition to the thermosetting resin described above.
  • a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin in addition to the thermosetting resin described above.
  • the resin composition may contain additives other than the above components such as pigments and antioxidants as necessary.
  • the insulating layers 211, 212, 213, 214, and 215 may be made of the same material as each other, or may be made of different materials.
  • the average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 ⁇ m or more and 800 ⁇ m or less, and more preferably 30 ⁇ m or more and 400 ⁇ m or less.
  • the conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21.
  • a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213.
  • a conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214.
  • a conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215.
  • the conductor patterns 221, 222, 223, and 224 each function as a circuit having a plurality of wirings.
  • the constituent material of the conductor patterns 221, 222, 223, and 224 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
  • the average thickness of the conductor patterns 221, 222, 223, and 224 is not particularly limited, but is preferably 5 ⁇ m or more and 30 ⁇ m or less.
  • a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole.
  • the conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected.
  • the insulating layer 212 is provided with a conductor post (via post) 232 penetrating in the thickness direction.
  • the conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.
  • the insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction.
  • the conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.
  • the insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction.
  • the conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.
  • the constituent material of the conductor posts 231, 232, 233, 234 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
  • the insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening.
  • a metal bump 71 is bonded onto each exposed portion (terminal) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21.
  • the metal bumps 71 are for electrically connecting the semiconductor package 1 to, for example, a mother board as will be described later. By being electrically connected, an electric signal can be transmitted between the semiconductor package 1 and the mother board.
  • the metal bump 71 has a substantially spherical shape.
  • the shape of the metal bump 71 is not limited to this.
  • the constituent material of the metal bump 71 is not particularly limited.
  • tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin-- Various brazing materials (solder) such as copper and tin-silver-copper can be used.
  • a plurality of via holes penetrating in the thickness direction are formed in the substrate 21, and a heat transfer post 24 is provided in each via hole.
  • Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the substrate 21 and its lower end is exposed from the lower surface of the substrate 21.
  • the heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5.
  • each heat transfer post 24 connects the first reinforcing member 4 and the second reinforcing member 5.
  • Each of the heat transfer posts (heat conducting portions) 24 has higher heat transfer performance than the substrate 21 (insulating layer) described above. Thereby, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • each heat transfer post 24 penetrates the substrate 21 in the thickness direction, it can be formed easily and with high accuracy in the same manner as a known conductor post.
  • each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post
  • Each heat transfer post 24 does not contribute to the transmission of electrical signals. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 through the heat transfer post 24.
  • the plurality of heat transfer posts 24 are arranged in parallel along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan.
  • the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.
  • the plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, and 224 described above when the wiring board 2 is viewed in plan view. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit between the heat transfer post 24 and the conductor patterns 221, 222, 223, and 224 can be prevented.
  • each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.
  • Such metal materials include various metals and various alloys such as copper, copper-based alloys, aluminum, and aluminum-based alloys.
  • a metal material it is preferable to use copper, a copper-based alloy, aluminum, or an aluminum-based alloy because of excellent heat conductivity. Since copper and a copper-based alloy are excellent in thermal conductivity, the heat dissipation of the wiring board 2 can also be improved.
  • the constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 234 described above, but is the same as the constituent material of the conductor posts 231 to 234 (particularly, the constituent material of the conductor posts 234). Is preferred. As a result, the heat transfer posts 24 can be formed simultaneously with the formation of the conductor posts 234. Therefore, the manufacturing of the semiconductor package 1 is simplified, and the semiconductor package 1 can be made inexpensive.
  • the semiconductor element 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light receiving / emitting element.
  • IC integrated circuit element
  • the semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
  • the semiconductor element 3 is provided with a plurality of terminals (not shown) on its lower surface, and each terminal is electrically connected to the conductor post 231 of the wiring board 2 described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2 are electrically connected, and an electric signal can be transmitted between the semiconductor element 3 and the conductor pattern 221.
  • the constituent material of the metal bump 31 is not particularly limited, but is similar to the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin Various brazing materials (solder) such as silver-bismuth, tin-copper, tin-silver-copper can be used.
  • the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 through the adhesive layer 32.
  • the adhesive layer 32 is made of a material having adhesiveness and insulating properties, for example, a cured product of an underfill material.
  • the underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.
  • the first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.
  • the first reinforcing member 4 and the substrate 21 can be joined via an adhesive. Thereby, installation of the 1st reinforcement member 4 becomes easy.
  • Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used.
  • an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.
  • the first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.
  • the first reinforcing member 4 has a plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.
  • the surface of the first reinforcing member 4 opposite to the substrate 21 is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that) It is preferably located on the lower side.
  • the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface.
  • the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned.
  • another structure for example, a board
  • the first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.
  • the first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3.
  • the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3.
  • the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.
  • the first reinforcing member 4 has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less.
  • the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.
  • the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above.
  • a metal material, a ceramic material, or the like can be used. It is preferable to use it.
  • the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
  • Such alloys containing Fe include Fe—Ni alloys, Fe—Co—Cr alloys, Fe—Co alloys, Fe—Pt alloys, Fe—Pd alloys, and the like. It is preferable to use a base alloy.
  • Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.
  • the Fe—Ni alloy is not particularly limited as long as it contains Fe and Ni.
  • the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.
  • Fe—Ni alloys include Fe—Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar).
  • Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy.
  • Fe—Ni—Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, KV-25, and Nivarox. ing.
  • Fe—Ni alloys are commercially available under trade names such as NS-5 and D-1 (manufactured by NEOMAX Materials).
  • Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal Co., Ltd.), EL-3 (manufactured by NEOMAX Material Co., Ltd.), and the like.
  • the Fe—Co—Cr alloy is not particularly limited as long as it contains Fe, Co, and Cr.
  • an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is used. Is mentioned.
  • the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.
  • the Fe—Co alloy is not particularly limited as long as it contains Fe and Co.
  • one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt is used. It may contain seeds or two or more metals.
  • the Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt.
  • one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. It may contain seeds or two or more metals.
  • the Fe—Pd alloy is not particularly limited as long as it contains Fe and Pd.
  • one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.
  • the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy
  • the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less.
  • the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
  • the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.
  • the surface of the first reinforcing member 4 may be roughened. If the surface of the first reinforcing member 4 is roughened, the surface area increases and the efficiency of heat dissipation increases.
  • the method for roughening the surface of the first reinforcing member 4 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.
  • the magnitude of the surface roughness of the first reinforcing member 4 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the first reinforcing member 4, and the like.
  • the surface roughness expressed by arithmetic mean is about 0.1 ⁇ m or more and 100 ⁇ m or less.
  • the surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.
  • a copper film may be formed on the surface of the first reinforcing member 4 from the viewpoint of improving the adhesion with the resin material.
  • the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the first reinforcing member 4. Can be selected and implemented.
  • the method for forming the copper film is not particularly limited, and can be performed by, for example, plating treatment such as electrolytic plating or electroless plating, sputtering treatment, or the like.
  • the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the first reinforcing member 4 and capable of surface treatment for improving adhesion.
  • a heat conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3.
  • heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6.
  • the heat dissipation of the semiconductor package 1 can be improved.
  • Such a heat conductive material 6 is not particularly limited, and examples thereof include a resin composition including an inorganic filler and a resin material.
  • Examples of the inorganic filler (inorganic filler) used in the heat conductive material 6 (resin composition) include metals such as Au, Ag, and Pt, silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, Oxides such as magnesium oxide and metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride, and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, calcium carbonate (light and heavy), magnesium carbonate Carbonates such as dolomite and dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate and calcium sulfite, talc, mica, clay, glass fiber, silicates such as calcium silicate, montmorillonite and bentonite, boron Zinc oxide, barium metaborate, aluminum borate, calcium borate, Borate
  • oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite, boron nitride, Nitride such as silicon nitride, gallium nitride and titanium nitride is preferable.
  • examples of the resin material used for the heat conductive material 6 include various thermoplastic resins and various thermosetting resins.
  • thermoplastic resin used for the thermally conductive material 6 examples include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66).
  • thermoplastic elastomers such as polyisoprene, fluororubber, and chlorinated polyethylene, and copolymers, blends, and polymer alloys mainly composed of these, one or two of these The above can
  • thermosetting resin used for the heat conductive material 6 for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, polyurethane Resins etc. are mentioned, 1 type or 2 types or more of these can be mixed and used.
  • the resin material used for the heat conductive material 6 (resin composition)
  • a thermosetting resin particularly, a liquid that forms a liquid before curing
  • a phenol resin or an epoxy resin is particularly preferable to use a phenol resin.
  • the thermal conductive material 6 can be filled between the first reinforcing member 4 and the semiconductor element 3 without a gap, and the thermal expansion coefficient of the thermal conductive material 6 can be effectively suppressed.
  • phenolic resins examples include phenol novolac resins, cresol novolac resins, novolac type phenol resins such as bisphenol A novolac resins, unmodified resole phenol resins, oil-modified resole phenol resins modified with paulownia oil, linseed oil, walnut oil, etc.
  • phenolic resins such as resol type phenolic resins.
  • the heat conductive material 6 may be the same as the adhesive layer 32 (underfill material) described above, and the heat conductive material 6 and the adhesive layer 32 may be formed in a lump. .
  • the second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.
  • the second reinforcing member 5 is bonded to the lower surface of the substrate 21 through an adhesive, for example. Thereby, installation of the 2nd reinforcement member 5 becomes easy.
  • Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used.
  • an adhesive excellent in thermal conductivity is preferable, and is the same as the above-described thermal conductive material 6. Things can be used.
  • the second reinforcing member 5 has a smaller thermal expansion coefficient than that of the substrate 21 as in the first reinforcing member 4 described above.
  • the second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.
  • the second reinforcing member 5 includes a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21). And a portion 53 provided between the metal bumps 71.
  • the second reinforcing member 5 has a plurality of openings 51 formed so as to surround each metal bump 71 in a non-contact manner with each metal bump 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.
  • each opening 51 is circular in plan view.
  • the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
  • each opening 51 is provided corresponding to each metal bump 71 (corresponding one-to-one) in the formation region (region surrounded by the outer peripheral edge) of the second reinforcing member 5.
  • the rigidity of the second reinforcing member 5 can be made uniform.
  • the heat dissipation of the 2nd reinforcement member 5 can also be improved.
  • the distance between the second reinforcing member 5 and each metal bump 71 extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.
  • heat transfer bumps 91 may be provided on the lower surface of the second reinforcing member 5.
  • the heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).
  • the constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material. Thereby, the heat transfer bump 91 can exhibit excellent heat transfer properties, and the heat transfer bump 91 can be effectively used as an adhesive for fixing the wiring board 2 to the mother board 200.
  • the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less.
  • the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.
  • the constituent material of the second reinforcing member 5 is not particularly limited as long as it has a thermal expansion coefficient as described above, and the same constituent material as that of the first reinforcing member 4 described above may be used.
  • a metal material, a ceramic material, etc. can be used, it is preferable to be comprised with the metal material.
  • the heat dissipation of the 2nd reinforcement member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
  • Such a metal material is not particularly limited, but from the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe, for example, an Fe—Ni alloy, Fe—Co—, in the same manner as the first reinforcing member 4 described above. It is preferable to use a Cr alloy, a Fe—Co alloy, a Fe—Pt alloy, a Fe—Pd alloy, or the like, and it is more preferable to use a Fe—Ni alloy.
  • the same material as the first reinforcing member 4 described above can be used.
  • the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable.
  • the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.
  • the average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.
  • the surface of the second reinforcing member 5 may be roughened. If the surface of the second reinforcing member 5 is roughened, the surface area increases and the efficiency of heat dissipation increases.
  • the method for roughening the surface of the second reinforcing member 5 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.
  • the magnitude of the surface roughness of the second reinforcing member 5 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the second reinforcing member 5, and the like.
  • the surface roughness expressed by arithmetic mean is about 0.1 ⁇ m or more and 100 ⁇ m or less.
  • the surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.
  • a copper film may be formed on the surface of the second reinforcing member 5 from the viewpoint of improving the adhesion with the resin material.
  • the surface treatment is appropriately selected according to the shape and size of the reinforcing member, the type of the resin material, etc. Can be implemented.
  • the method for forming the copper film is not particularly limited, and can be performed by, for example, plating treatment such as electrolytic plating or electroless plating, sputtering treatment, or the like.
  • the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the second reinforcing member 5 and allowing surface treatment for improving adhesion.
  • an insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be improved while improving the reliability of the semiconductor package 1.
  • the insulating material 81 has a shape surrounding the periphery (upper part) of the metal bump 71 on the substrate 21 side, and is joined to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71.
  • the insulating material 81 preferably has higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 71 and the second reinforcing member 5 can be made excellent, and the heat dissipation of the semiconductor package 1 can be improved.
  • Such an insulating material 81 has an insulating property and includes a resin material.
  • Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a solder bonding resin having thermosetting properties.
  • solder bonding resin acts as a flux at the time of solder bonding, and then is cured by heating to act as a reinforcing material for the solder bonding portion.
  • Solder bonding resin removes harmful substances such as solder joint surfaces and oxides of solder materials during solder joining, protects the solder joint surfaces, and refines the solder materials to provide good strength and good strength.
  • the solder bonding resin does not need to be removed by washing after solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.
  • Such a solder bonding resin can be configured to include, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.
  • the resin (A) having a phenolic hydroxyl group is not particularly limited, and examples thereof include a phenol novolak resin, an alkylphenol novolak resin, a polyhydric phenol novolak resin, a resole resin, and a polyvinyl phenol resin.
  • the content of the resin (A) having a phenolic hydroxyl group is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened
  • the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as solder and oxide on the metal surface by its reducing action, and thus effectively acts as a solder joint flux.
  • examples of the curing agent (B) of the resin (A) having a phenolic hydroxyl group include an epoxy compound and an isocyanate compound.
  • examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.
  • the compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group or isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. If the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, resulting in a decrease in bonding strength and reliability. There is. If the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxide on the solder and metal surface may be reduced, and solder jointability may be deteriorated.
  • Such a solder bonding resin (curable flux) is formed because a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. It is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in a high temperature and high humidity atmosphere, and soldering with high joining strength and reliability is possible. .
  • the solder bonding resin as described above is dispersed in a microcrystalline state as a curable antioxidant (C).
  • the solder bonding resin may contain a thermally conductive filler as long as the insulating property is not impaired in order to improve heat dissipation.
  • the heat conductive filler is not particularly limited.
  • zinc oxide at least one selected from aluminum nitride, aluminum oxide, and boron nitride is preferable from the viewpoints of dispersibility, insulation, and thermal conductivity.
  • both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased.
  • the semiconductor device 3 is provided over the entire surface of the wiring substrate 2 in the same manner as the wiring substrate 2. It is possible to suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the semiconductor element 3 and the semiconductor element 3.
  • the semiconductor package 1 can release the heat from the semiconductor element 3 through the wiring board 2 and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
  • the semiconductor package 1 as described above can be manufactured as follows, for example.
  • the laminated body of the metal layer 221A and the prepreg 211A is prepared, and the 1st reinforcement member 4 is affixed on the surface at the side of the prepreg 211A of the laminated body.
  • the prepreg 211A is for forming the insulating layer 211 of the wiring board 2 described above, and the base material is impregnated with an uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. It will be.
  • the metal layer 221A is for forming the conductor pattern 221 of the wiring board 2 described above, and is made of the same material as that of the conductor pattern 221.
  • a through hole 2111 (via hole) is formed in the prepreg 211A.
  • the formation method of the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.
  • the laser for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
  • the through-hole 2111 can be formed by machining such as a drill, for example.
  • the method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.
  • the conductor layer 221 is formed by patterning the metal layer 221A.
  • Such a patterning method is not particularly limited, but etching is preferably used.
  • the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.
  • Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.
  • the method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but for example, heat treatment is preferably used.
  • the heat transfer posts 24 are formed at the same time as the conductor posts 231, 232, 233, 234, and the heat transfer posts are formed on the prepregs for the insulating layers 211, 212, 213, 214, 215. These heat transfer posts may be connected and formed by laminating prepregs.
  • solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. ⁇ 10 to 60 seconds. .
  • the insulating material 81A is for forming the above-described insulating material 81, and is cured by heating, for example.
  • the insulating material 81A When forming the insulating material 81, for example, as shown in FIG. 4F, the insulating material 81A is applied to the lower surface of the wiring board 2, and after the solder bonding as described above, the insulating material 81A is cured by heating. By doing so, the insulating material 81 is obtained.
  • the insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
  • the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.
  • the second reinforcing member 5 is joined to the lower surface of the wiring board 2.
  • the semiconductor element 3 is joined by solder reflow through the metal bumps 31.
  • the adhesive layer 32 is formed using a resin having the same flux activity as the insulating material 81 described above as the underfill material.
  • a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.
  • the semiconductor package 1 is obtained as described above.
  • the semiconductor package of the second embodiment is A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • a plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate, The reinforcing member has a portion located between the metal bumps without contacting the metal bumps.
  • FIG. 6 is a cross-sectional view schematically showing a semiconductor package 1A according to the second embodiment of the present invention.
  • the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 6, for convenience of explanation, each part of the semiconductor package is exaggerated.
  • the semiconductor package 1A of the second embodiment will be described focusing on the differences from the first embodiment described above, and the description of the same matters will be omitted.
  • FIG. 6 the same reference numerals are given to the same configurations as those in the above-described embodiment.
  • the semiconductor package 1A shown in FIG. 6 is substantially the same as the first embodiment except that the first reinforcing member, the heat transfer post, and the heat conductive material are omitted.
  • the semiconductor package 1A includes a wiring board 2A, a semiconductor element 3A mounted on the wiring board 2A, and a reinforcement bonded to the lower surface (the other surface) of the substrate 21A of the wiring board 2A. 5A.
  • the semiconductor package 1A has a wiring board 2A configured similarly to the wiring board 2 of the first embodiment described above except that the heat transfer post 24 is omitted.
  • the reinforcement member 5A comprised similarly to the 2nd reinforcement member 5 of 1st Embodiment mentioned above is joined on the lower surface of the wiring board 2A.
  • a reinforcing member intended to reinforce the wiring board 2A is not joined on the upper surface of the wiring board 2A.
  • the reinforcing member 5A is bonded to the mounting surface of the semiconductor element 3A and the other surface, the symmetry of the structure of the semiconductor package 1A increases, and as a result, the difference in thermal expansion coefficient between the wiring board 2A and the semiconductor element 3A. It is possible to suppress or prevent the warping of the wiring board 2A due to the above.
  • the size of the reinforcing member 5A is determined according to the size / thickness of the semiconductor element 3A, the configuration / thickness of the wiring board 2A, the material type, thickness, opening state, etc. of the reinforcing member 5A.
  • the size is not particularly limited as long as the size is equal to or smaller than that of the wiring board 2A.
  • the heat transfer post 24 in the first embodiment is omitted, but the heat generated by the semiconductor element 3A is generated by the metal bump 31, the conductor pattern and the conductor post of the wiring board 2A, the metal bump 71, Since the insulating material 81 and the reinforcing member 5A are transmitted and diffused in this order, the semiconductor package 1A has high heat dissipation.
  • the semiconductor package 1A of the second embodiment as described above can also prevent the wiring board 2A from warping and improve heat dissipation.
  • the semiconductor package of the third embodiment is A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • the semiconductor package 1B of the third embodiment will be described with a focus on differences from the above-described embodiments, and the same components will be denoted by the same reference numerals and description thereof will be omitted.
  • FIG. 7 is a sectional view schematically showing a semiconductor package 1B according to the third embodiment of the present invention
  • FIG. 8 is a top view showing the semiconductor package 1B shown in FIG. 7
  • FIG. 9 is a plan view showing the semiconductor package 1B shown in FIG.
  • FIG. 10 is a view showing an example of a method for manufacturing the semiconductor package 1B shown in FIG.
  • the upper side in FIG. 7 is referred to as “upper” and the lower side is referred to as “lower”.
  • the plurality of heat transfer bumps 91 are provided on the frame portion 52 of the second reinforcing member 5. That is, the plurality of heat transfer bumps 91 are provided so as not to overlap the conductor patterns 221, 222, 223, 224 when the wiring substrate 2 is viewed in plan. Thereby, formation of the heat transfer bump 91 is simplified, and a short circuit between the heat transfer bump 91 and the conductor patterns 221, 222, 223, and 224 can be prevented.
  • the plurality of heat transfer bumps 91 are spaced from each other along the frame portion 52, that is, along the outer peripheral portion of the wiring substrate 2 (second reinforcing member 5) when the wiring substrate 2 is viewed in plan. They are arranged side by side.
  • the plurality of heat transfer bumps 91 are preferably arranged in parallel at equal intervals along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.
  • each heat transfer bump 91 is provided so as to face one heat transfer post 24 with the second reinforcing member 5 interposed therebetween. That is, it is preferable that one heat transfer bump 91 is provided corresponding to one heat transfer post 24. Thereby, the temperature distribution of the wiring board 2 can be made more effective.
  • the arrangement of the metal bumps 91 is not limited to this. For example, when the wiring board 2 is viewed in plan, a plurality of heat transfer bumps 91 are provided so as to be positioned between one adjacent heat transfer post 24. May be. Further, the heat transfer bump 91 may be provided on the portion 53 of the second reinforcing member 5 as long as a short circuit with the conductor patterns 221, 222, 223, and 224 can be prevented.
  • the lowest point (the point farthest from the second reinforcing member 5) P1 of each heat transfer bump 91 in FIG. 7 and the lowest point (the point farthest from the second reinforcing member 5) of FIG. ) P2 is located on the same plane.
  • the heat transfer bump 91 can be brought into contact with the motherboard 200 more reliably.
  • excessive deformation of the heat transfer bump 91 in a state where the metal bump 71 is bonded to the terminal of the mother board 200 can be prevented, and a short circuit between the heat transfer bump 71 and the conductor patterns 221, 222, 223, 224 can be prevented. It can prevent more reliably.
  • each heat transfer bump 91 is plated. That is, a metal film is preferably formed on the surface of the heat transfer bump 91. Thereby, the heat transfer property of the heat transfer bump 91 can be further improved.
  • the metal material used for the plating process is not particularly limited, and various metal materials such as gold, silver, and copper can be used. Among these, gold is preferably used. By using gold, that is, by applying gold plating to the heat transfer bump 91, the above effect becomes more remarkable.
  • the heat transfer bump 91 can be formed by soldering a metal ball 91A to the lower surface of the second reinforcing member 5 by solder reflow.
  • the heat transfer bump 91 is preferably formed after the semiconductor element 3 is bonded to the upper surface of the wiring board 2 via the metal bump 31. Further, it is preferable that the heat conductive material 6 is filled between the semiconductor element 3 and the first reinforcing member 4 after the heat transfer bump 91 is formed.
  • the manufacturing process of the other configuration of the semiconductor package 1B of the third embodiment shown in FIGS. 10A to 10G is the same as that of the first embodiment shown in FIGS. 4A to 4G. Since it is the same as the manufacturing process of the semiconductor package 1, its detailed description is omitted.
  • heat from the semiconductor element can be released even through the heat transfer bump, so that heat dissipation can be further improved.
  • semiconductor device 100 semiconductor device 100 Next, a method for manufacturing the semiconductor device 100 and the semiconductor device 100 will be described based on preferred embodiments.
  • FIG. 5 is a cross-sectional view schematically showing a semiconductor device 100 according to the fourth embodiment of the present invention.
  • the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.
  • the metal bumps 71 of the semiconductor package 1 are joined to the terminals (not shown) of the mother board 200. Thereby, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.
  • the heat transfer bumps 91 of the semiconductor package 1 are joined to terminals for heat dissipation (not shown) of the mother board 200.
  • the heat of the semiconductor package 1 can be efficiently released to the mother board 200 through this joint.
  • a heat transfer bump 91 is made of the same material as that of the metal bump 71 described above, the heat transfer bump 91 can be bonded to the mother board 200 at the same time as the metal bump 71 is bonded.
  • the semiconductor package 1 having excellent heat dissipation and reliability as described above since the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
  • the semiconductor package 1 mounted on the semiconductor device 100 can be changed to the semiconductor package 1A or 1B.
  • the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3.
  • the present invention is not limited to this.
  • a cut-out portion (notch) may be formed.
  • the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5.
  • a heat conductive member metal member
  • the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21.
  • the reinforcing member 4 and the second reinforcing member 5 may be held from above and below.
  • the opening formed in the second reinforcing member 5 may not correspond to each metal bump 71 on a one-to-one basis. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.
  • the semiconductor package 1C of the fifth embodiment is A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern.
  • a wiring board A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern; A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
  • S1 the area of the semiconductor element in plan view
  • S2 / S1 is 0.64 or more and 2.25 or less.
  • FIG. 11 is a cross-sectional view schematically showing the semiconductor package 1C
  • FIG. 12 is a bottom view showing the semiconductor package 1C
  • FIG. 13 is a view showing an example of a manufacturing method of the semiconductor package 1C.
  • the upper side in FIG. 11 is referred to as “upper” and the lower side is referred to as “lower”.
  • 11 and 12 each part of the semiconductor package is exaggerated for convenience of explanation. Further, a part of the detailed description of the same configuration as that of the semiconductor package in the first to third embodiments described above is omitted.
  • a semiconductor package 1C shown in FIG. 11 includes a wiring board 2C, a semiconductor element 3 mounted on the wiring board 2C, and a reinforcing member 5C.
  • the rigidity of the entire semiconductor package 1C is increased.
  • the thermal expansion coefficient of the reinforcing member 5C is smaller than that of the wiring substrate 2C (specifically, the substrate 21C)
  • the semiconductor device 3 is provided over the entire surface of the wiring substrate 2C, similarly to the wiring substrate 2C. It is possible to suppress or prevent warping of the wiring board 2C due to the difference in thermal expansion coefficient between the semiconductor element 3 and the semiconductor element 3.
  • the wiring board 2C is sandwiched between the semiconductor element 3 and the reinforcing member 5C, the wiring board 2C is more strongly reinforced and the thermal expansion difference between both surfaces of the wiring board 2C is increased. Can be suppressed.
  • the area of the reinforcing member 5C is optimized as will be described later, it is possible to effectively warp the wiring board 2A without further providing a reinforcing member (stiffener) on the surface of the wiring board 2A on the semiconductor element 3 side. Can be prevented. Therefore, the configuration of the semiconductor package 1C becomes simpler.
  • the semiconductor package 1C can release heat from the semiconductor element 3 through the wiring board 2C, and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1C can be improved by appropriately selecting the constituent material of the reinforcing member 5C.
  • the wiring board 2C is a board that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later.
  • the wiring substrate 2C has a plan view shape that is usually a square such as a square or a rectangle.
  • the wiring board 2C includes a board 21C, conductor patterns 221, 222, 223, and 224, and conductor posts 231, 232, 233, and 234.
  • the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21C, and the conductor pattern 224 is provided on the other surface side of the substrate 21C.
  • a second conductor pattern electrically connected to the conductor pattern is formed.
  • the substrate 21 ⁇ / b> C includes a plurality (five layers in this embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21C is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order.
  • the number of insulating layers constituting the substrate 21C is not limited to this, and may be 1 to 4 layers, or 6 or more layers.
  • the insulating layers 211, 212, 213, 214, and 215 are configured in the same manner as the insulating layers 211, 212, 213, 214, and 215 in the second embodiment described above, and detailed description thereof is omitted.
  • the average thickness of the substrate 21C composed of a plurality of layers as described above is not particularly limited, but is preferably 30 ⁇ m or more and 800 ⁇ m or less, and more preferably 30 ⁇ m or more and 400 ⁇ m or less.
  • a conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21C.
  • a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213.
  • a conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214.
  • a conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215.
  • the conductor patterns 221, 222, 223, and 224 are configured in the same manner as the conductor patterns 221, 222, 223, and 224 in the second embodiment described above, and a detailed description thereof is omitted.
  • a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole.
  • the conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected.
  • the insulating layer 212 is provided with a conductor post (via post) 232 penetrating in the thickness direction.
  • the conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.
  • the insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction.
  • the conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.
  • the insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction.
  • the conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.
  • the insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening.
  • a metal bump 71 is bonded onto each exposed portion (terminal) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21C.
  • the metal bumps 71 are for electrically connecting the semiconductor package 1C to a mother board as will be described later, for example.
  • the metal bump 71 is configured in the same manner as the metal bump 71 in the second embodiment described above, and detailed description thereof is omitted.
  • the semiconductor element 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light receiving / emitting element.
  • the semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21C of the wiring substrate 2C described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
  • the semiconductor element 3 is provided with a plurality of terminals (not shown) on the lower surface thereof, and each terminal is electrically connected to the conductor post 231 of the wiring board 2C described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2C are electrically connected.
  • the configuration of the metal bump 31 is the same as that of the metal bump 31 in the second embodiment described above, and a detailed description thereof is omitted.
  • the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 ⁇ / b> C via the adhesive layer 32.
  • the adhesive layer 32 is configured in the same manner as the adhesive layer 32 in the second embodiment described above, and detailed description thereof is omitted.
  • the reinforcing member (stiffener) 5C is joined to the lower surface (the other surface) of the substrate 21C of the wiring substrate 2C.
  • the reinforcing member 5C and the substrate 21C can be bonded via an adhesive. Thereby, installation of the reinforcing member 5C becomes easy.
  • Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used, but those having excellent thermal conductivity are preferable, and the thermal conductivity in the first embodiment described above.
  • the same material 6 can be used.
  • the reinforcing member 5C has a smaller thermal expansion coefficient than the substrate 21C.
  • the reinforcing member 5C has a plate shape. Thereby, the structure of 5 C of reinforcement members can be made simple and small.
  • the reinforcing member 5 ⁇ / b> C includes a portion (frame portion) 52 ⁇ / b> C provided along the outer peripheral portion of the wiring substrate 2 ⁇ / b> C (substrate 21 ⁇ / b> C) and a portion 53 ⁇ / b> C provided between the metal bumps 71. And have.
  • the reinforcing member 5C can effectively reinforce the wiring substrate 2C.
  • the rigidity of the reinforcing member 5C is increased by joining the portion 53C of the reinforcing member 5C and the wiring board 2C.
  • the reinforcing member 5C has a plurality of openings 51C formed so as to surround each metal bump 71 in a non-contact manner with each metal bump 71 described above. Thereby, the ratio of the area which the reinforcing member 5C occupies in the lower surface of the wiring board 2C can be increased. As a result, the effect of increasing the rigidity of the wiring board 2C by the reinforcing member 5C can be made excellent.
  • each opening 51C has a circular shape in plan view.
  • the planar view shape of each opening part 51C is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
  • each opening 51C is provided corresponding to each metal bump 71 (corresponding one-to-one) in the region where the reinforcing member 5C is formed (the region surrounded by the outer peripheral edge 5c).
  • the rigidity of the reinforcing member 5C can be made uniform.
  • the heat dissipation of the reinforcing member 5C can be improved.
  • the distance between the reinforcing member 5C and each metal bump 71 is constant over the entire circumference of the metal bump 71. It is formed to become. Thereby, the integrity of the reinforcing member 5C and each metal bump 71 is increased, and the reinforcing effect of the wiring board 2C by these is suitably exhibited.
  • the area of the semiconductor element 3 in plan view (the area in the region surrounded by the outer peripheral edge 3c) is S1
  • the region surrounded by the outer peripheral edge 5c of the reinforcing member 5C in plan view S2 / S1 is configured to be 0.64 or more and 2.25 or less when the inner area is S2.
  • the semiconductor element 3 can be easily installed when the semiconductor package 1C is manufactured.
  • the area S2 is a total area of the above-described portions (frame portions) 52C, the portions 53C, and the plurality of openings 51C in plan view.
  • the area ratio S2 / S1 is preferably such that S2 / S1 is 0.81 or more and 1.44 or less.
  • the outer peripheral edge 5c of the reinforcing member 5C is located outside the outer peripheral edge 3c of the semiconductor element in a plan view.
  • the curvature of the wiring board 2C can be effectively prevented easily and reliably.
  • the same effect can be obtained even when the outer peripheral edge 5c of the reinforcing member 5C coincides with the outer peripheral edge 3c of the semiconductor element in plan view.
  • a part of the outer peripheral edge 5c of the reinforcing member 5C may be located inside the outer peripheral edge 3c of the semiconductor element.
  • the entire periphery of the outer peripheral edge 5c of the reinforcing member 5C may be located inside the outer peripheral edge 3c of the semiconductor element in a plan view.
  • the reinforcing member 5C preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the reinforcing member 5C can effectively reinforce the wiring board 2C and suppress the thermal expansion of the entire semiconductor package 1C.
  • the constituent material of the reinforcing member 5C is not particularly limited as long as it has a thermal expansion coefficient as described above.
  • a metal material, a ceramic material, or the like can be used, but a metal material is used. Is preferred.
  • the reinforcing member 5C is made of a metal material, the heat dissipation of the reinforcing member 5C can be improved. As a result, the heat dissipation of the semiconductor package 1C can be improved.
  • Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
  • Fe-containing alloys examples include Fe—Ni alloys, Fe—Co—Cr alloys, Fe—Co alloys, Fe—Pt alloys, Fe—Pd alloys and the like used in the first embodiment described above. In particular, it is preferable to use an Fe—Ni alloy.
  • Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the difference in thermal expansion between both surfaces of the wiring board 2C can be suppressed.
  • the thermal expansion coefficient of the reinforcing member 5C is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and more preferably 1 ppm / ° C. or more and 5 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 5C can be reduced, and the warp of the wiring board 2C can be effectively prevented.
  • the absolute value of the difference in thermal expansion coefficient between the reinforcing member 5C and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and further preferably 2 ppm / ° C. or less. preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 5C can be reduced, and the warp of the wiring board 2C can be effectively prevented.
  • the Fe—Ni alloy when the metal material constituting the reinforcing member 5C is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the reinforcing member 5 ⁇ / b> C can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
  • the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less. It is more preferable that the total content of Ni is 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. .
  • the thermal expansion coefficient of the reinforcing member 5 ⁇ / b> C can be brought close to the thermal expansion coefficient of the semiconductor element 3.
  • the average thickness of the reinforcing member 5C is determined according to the thermal expansion coefficient of the wiring board 2C, the shape, size, constituent material, etc. of the reinforcing member 5C, and is not particularly limited. It is about 0.8 mm or less.
  • the surface of the reinforcing member 5C may be roughened from the viewpoint of heat dissipation. If the surface of the reinforcing member 5C is roughened, the surface area increases and the efficiency of heat dissipation increases.
  • the method for roughening the surface of the reinforcing member 5C is not particularly limited, and can be carried out by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.
  • the magnitude of the surface roughness of the reinforcing member 5C is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the wiring substrate 21C, the shape and size of the reinforcing member 5C, and the like.
  • the surface roughness expressed by arithmetic mean is about 0.1 ⁇ m or more and 100 ⁇ m or less.
  • the surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.
  • a copper film may be formed on the surface of the reinforcing member 5C.
  • the surface treatment is appropriately selected according to the shape, size, type of resin material, etc. of the reinforcing member 5C. Can be implemented.
  • the method for forming the copper film is not particularly limited, and can be performed by, for example, plating treatment such as electrolytic plating or electroless plating, sputtering treatment, or the like.
  • the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the reinforcing member 5C and capable of surface treatment for improving adhesion.
  • an insulating material 81 is provided (filled) between the reinforcing member 5C and each metal bump 71. Thereby, contact with 5 C of reinforcement members and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the reinforcing member 5C can be enhanced while improving the reliability of the semiconductor package 1C.
  • the insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.
  • Such an insulating material 81 has an insulating property and includes a resin material.
  • Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a thermosetting solder bonding resin, and has the same configuration as the insulating material 81 in the first embodiment described above. it can.
  • the wiring substrate 2 ⁇ / b> C is reinforced by the reinforcing member 5 ⁇ / b> C at portions other than the portion joined to the semiconductor element 3, so that the rigidity of the entire semiconductor package 1 ⁇ / b> C is increased. .
  • the wiring board 2C is sandwiched between the semiconductor element 3 and the reinforcing member 5C, the wiring board 2C is more strongly reinforced and the thermal expansion difference between both surfaces of the wiring board 2C is increased. Can be suppressed.
  • the area of the reinforcing member 5C is optimized, warping of the wiring board 2C can be effectively prevented without further providing a reinforcing member (stiffener) on the surface of the wiring board 2C on the semiconductor element 3 side. be able to. Therefore, the configuration of the semiconductor package 1C is simplified.
  • the semiconductor package 1C can release heat from the semiconductor element 3 through the wiring board 2C, and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1C can be improved by appropriately selecting the constituent material of the reinforcing member 5C.
  • the semiconductor package 1C as described above can be manufactured, for example, as follows.
  • FIG. 13A a laminate of a metal layer 221A and a prepreg 211A is prepared.
  • the prepreg 211A is for forming the insulating layer 211 of the wiring board 2C described above, and the base material is impregnated with the uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. It will be.
  • the metal layer 221A is for forming the conductor pattern 221 of the wiring board 2C described above, and is made of the same material as the constituent material of the conductor pattern 221.
  • a through hole 2111 (via hole) is formed in the prepreg 211A.
  • the formation method of the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.
  • the laser for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
  • the through-hole 2111 can be formed by machining such as a drill, for example.
  • the method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.
  • the conductor layer 221 is formed by patterning the metal layer 221A.
  • Such a patterning method is not particularly limited, but etching is preferably used.
  • the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.
  • Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.
  • the method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but for example, heat treatment is preferably used.
  • a metal ball (solder ball) 71A is soldered by solder reflow. Thereby, the metal bump 71 and the insulating material 81 are formed.
  • solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2C and heating in that state, for example, 200 to 280 ° C. ⁇ 10 to 60 seconds. .
  • the insulating material 81A is for forming the above-described insulating material 81, and is cured by heating, for example.
  • the insulating material 81A When forming the insulating material 81, for example, as shown in FIG. 13F, the insulating material 81A is applied to the lower surface of the wiring board 2C, and after the solder bonding as described above, the insulating material 81A is cured by heating. By doing so, the insulating material 81 is obtained.
  • the insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
  • the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.
  • the reinforcing member 5C is joined to the lower surface of the wiring board 2C.
  • the semiconductor element 3 is joined by solder reflow through the metal bumps 31.
  • a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material.
  • a normal capillary underfill material is placed between the wiring board 2C and the semiconductor element 3. It can also be filled and cured.
  • the semiconductor package 1C is obtained as described above.
  • FIG. 14 is a cross-sectional view schematically showing a semiconductor device 100C according to the fifth embodiment of the present invention.
  • the semiconductor device 100 ⁇ / b> C includes a mother board (substrate) 200 and a semiconductor package 1 ⁇ / b> C mounted on the mother board 200.
  • the metal bumps 71 of the semiconductor package 1C are joined to terminals (not shown) of the mother board 200. Thereby, the semiconductor package 1C and the mother board 200 are electrically connected, and electrical signals are transmitted between them. Further, the heat of the semiconductor package 1 ⁇ / b> C can be released to the mother board 200 through this joint.
  • the semiconductor package 1C having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
  • the opening formed in the reinforcing member 5C may not correspond to each metal bump 71 on a one-to-one basis. That is, openings may be formed in the reinforcing member 5 ⁇ / b> C so that one corresponds to the plurality of metal bumps 71.
  • the shape of the outer peripheral edge 5c of the reinforcing member 5C in a plan view is a square shape.
  • the shape is not limited to this.
  • the metal bump 71 positioned outside the reinforcing member 5C A shape along the shape or arrangement may be formed.
  • the wiring board is sandwiched between the semiconductor element and the reinforcing member by bonding the reinforcing member to the surface of the wiring board opposite to the semiconductor element.
  • the difference in thermal expansion can be prevented or suppressed.
  • the reinforcing member is provided so as to extend between the metal bumps, the wiring board can be strongly reinforced.
  • the thermal conductivity in the thickness direction of the wiring board can be increased. Therefore, the semiconductor package of the present invention can release heat from the semiconductor element through the wiring board, and is excellent in heat dissipation. Thereby, since the temperature rise of the semiconductor element and the wiring board can be suppressed, the warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element can also be suppressed or prevented.
  • the semiconductor device of the present invention since the semiconductor package as described above is provided, the reliability is excellent.

Abstract

This semiconductor package (1) has: a wiring board (2), which is provided with a substrate (21), a conductor pattern (221) that is provided on one surface of the substrate (21), and a conductor pattern (224) that is provided on the other surface of the substrate (21) and is electrically connected to the conductor pattern (221); a semiconductor element (3), which is bonded to the one surface of the substrate (21), and which is electrically connected to the conductor pattern (221); and a second reinforcing member (5), which is bonded to the other surface of the substrate (21), and which has a thermal expansion coefficient smaller than that of the substrate (21). On the surface of the conductor pattern (224), said surface being on the reverse side of the substrate (21), a plurality of metal bumps (71) are bonded, and the second reinforcing member (5) has a plurality of openings (51), which are formed to surround each of the metal bumps (71) without contact with each of the metal bumps (71).

Description

半導体パッケージおよび半導体装置Semiconductor package and semiconductor device
　本発明は、半導体パッケージおよび半導体装置に関する。
　本願は、２０１０年８月３０日に日本に出願された特願２０１０－１９２９０４号および特願２０１０－１９２９０５号と、２０１０年９月１７日に日本に出願された特願２０１０－２１０１５８号に基づき優先権を主張し、その内容をここに援用する。 The present invention relates to a semiconductor package and a semiconductor device.
This application is based on Japanese Patent Application Nos. 2010-192904 and 2010-192905 filed in Japan on August 30, 2010, and Japanese Patent Application No. 2010-210158 filed in Japan on September 17, 2010. Claim priority and incorporate the contents here.
　近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできており、これらの電子機器に使用される半導体パッケージは、従来にも増して益々小型化かつ多ピン化が進んできている。 In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and further high-density mounting of electronic components have progressed. Semiconductor packages used in these electronic devices have been In addition, the size and number of pins are increasing.
　半導体パッケージはその小型化に伴って、従来のようなリードフレームを使用した形態のパッケージでは、小型化に限界がきているため、最近では回路基板上にチップを実装したものとして、ＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）や、ＣＳＰ（Ｃｈｉｐ　Ｓｃａｌｅ　Ｐａｃｋａｇｅ）と言った、エリア実装型の新しいパッケージ方式が提案されている。 With the downsizing of semiconductor packages, there is a limit to miniaturization of packages using a conventional lead frame, and recently, BGA (Ball Grid) is assumed as a chip mounted on a circuit board. Array) and a new area mounting type package method such as CSP (Chip Scale Package) have been proposed.
　ＢＧＡやＣＳＰ等の新しいパッケージに用いられるインターポーザは、一般に、繊維基材に樹脂組成物を含浸してなる基板に導体パターンや導体ポストが形成されてなる。 Interposers used for new packages such as BGA and CSP are generally formed by forming a conductor pattern or a conductor post on a substrate obtained by impregnating a fiber base material with a resin composition.
　このようなインターポーザは、チップとの熱膨張係数差が大きい。また、インターポーザは、通常、チップよりも大面積となるため、チップと接触していない部分の面積が大きい。このようなチップと接触していない部分は、剛性が極めて低く、前述したようなチップとインターポーザの熱膨張差に起因して反りやすく、電気的接続の信頼性を低下させるという問題があった。
　また、チップは発熱するため、インターポーザには優れた放熱性が要求されている。 Such an interposer has a large difference in thermal expansion coefficient from the chip. Further, since the interposer usually has a larger area than the chip, the area of the portion not in contact with the chip is large. Such a portion that is not in contact with the chip has a very low rigidity, and thus tends to warp due to the difference in thermal expansion between the chip and the interposer as described above, resulting in a problem that reliability of electrical connection is lowered.
Moreover, since the chip generates heat, the interposer is required to have excellent heat dissipation.
特開２００２－２７０７１６号公報JP 2002-270716 A
　本発明の目的は、熱による不具合の発生を防止することができる半導体パッケージおよび半導体装置を提供することである。 An object of the present invention is to provide a semiconductor package and a semiconductor device that can prevent the occurrence of defects due to heat.
　また、本発明の目的は、薄型化し得る半導体パッケージおよび半導体装置を提供することである。 Another object of the present invention is to provide a semiconductor package and a semiconductor device that can be thinned.
　このような目的は、下記（１）～（２６）の本発明により達成される。
　（１）　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい補強部材とを有し、
　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、
　前記補強部材は、前記各金属バンプに非接触で前記金属バンプ同士の間に位置する部分を有することを特徴とする半導体パッケージ。 Such an object is achieved by the present inventions (1) to (26) below.
(1) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate,
The said reinforcement member has a part located between the said metal bumps in non-contact with each said metal bump, The semiconductor package characterized by the above-mentioned.
　（２）　前記補強部材は、複数の開口部を有し、
　前記補強部材の前記開口部同士の間の部分が前記各金属バンプに非接触で前記金属バンプ同士の間に位置する上記（１）に記載の半導体パッケージ。 (2) The reinforcing member has a plurality of openings,
The semiconductor package according to (1), wherein a portion between the openings of the reinforcing member is positioned between the metal bumps without contacting the metal bumps.
　（３）　前記補強部材は、前記半導体素子との熱膨張係数差が７ｐｐｍ／℃以下である上記（１）または（２）に記載の半導体パッケージ。 (3) The semiconductor package according to (1) or (2), wherein the reinforcing member has a difference in thermal expansion coefficient from the semiconductor element of 7 ppm / ° C. or less.
　（４）　前記補強部材は、金属材料で構成されている上記（１）ないし（３）のいずれかに記載の半導体パッケージ。 (4) The semiconductor package according to any one of (1) to (3), wherein the reinforcing member is made of a metal material.
　（５）　前記金属材料は、Ｆｅ－Ｎｉ系合金である上記（４）に記載の半導体パッケージ。 (5) The semiconductor package according to (4), wherein the metal material is an Fe—Ni alloy.
　（６）　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい第２補強部材と、
　前記第２補強部材の前記基板と反対側の面に設けられ、前記基板よりも高い熱伝導性を有する伝熱バンプとを有することを特徴とする半導体パッケージ。 (6) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
A semiconductor package comprising heat transfer bumps provided on a surface of the second reinforcing member opposite to the substrate and having higher thermal conductivity than the substrate.
（７）　前記伝熱バンプは、金属材料で構成されている上記（６）に記載の半導体パッケージ。 (7) The semiconductor package according to (6), wherein the heat transfer bump is made of a metal material.
（８）　前記伝熱バンプは、その表面にメッキ処理が施されている上記（６）または（７）に記載の半導体パッケージ。 (8) The semiconductor package according to (6) or (7), wherein a surface of the heat transfer bump is plated.
（９）　前記伝熱バンプは、複数設けられている上記（６）ないし（８）のいずれかに記載の半導体パッケージ。 (9) The semiconductor package according to any one of (6) to (8), wherein a plurality of the heat transfer bumps are provided.
（１０）　前記複数の伝熱バンプは、前記第２補強部材の縁部に沿って互いに離間して設けられている上記（９）に記載の半導体パッケージ。 (10) The semiconductor package according to (9), wherein the plurality of heat transfer bumps are provided apart from each other along an edge portion of the second reinforcing member.
（１１）　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、
　前記第２補強部材は、前記各金属バンプに非接触で前記各金属バンプを囲むように形成された複数の開口部を有する上記（６）ないし（１０）のいずれかに記載の半導体パッケージ。 (11) A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate,
Said 2nd reinforcement member is a semiconductor package in any one of said (6) thru | or (10) which has several opening part formed so that each said metal bump might be surrounded without contacting said each metal bump.
（１２）　前記基板の前記一方の面の、前記半導体素子が接合されていない部分に接合され、前記基板よりも熱膨張係数の小さい第１補強部材を更に有している上記（６）ないし（１１）のいずれかに記載の半導体パッケージ。 (12) The above (6) to (6) further including a first reinforcing member bonded to a portion of the one surface of the substrate where the semiconductor element is not bonded and having a smaller coefficient of thermal expansion than the substrate. The semiconductor package according to any one of 11).
（１３）　前記第１補強部材と前記第２補強部材とを接続し、前記基板よりも熱伝導性の高い熱伝導部を更に有する上記（１２）に記載の半導体パッケージ。 (13) The semiconductor package according to (12), further including a heat conduction portion that connects the first reinforcement member and the second reinforcement member and has higher heat conductivity than the substrate.
（１４）　前記熱伝導部は、前記基板をその厚さ方向に貫通するものである上記（１３）に記載の半導体パッケージ。 (14) The semiconductor package according to (13), wherein the heat conducting portion penetrates the substrate in the thickness direction.
（１５）　前記第１補強部材および前記第２補強部材は、それぞれ、板状をなしている上記（１３）または（１４）に記載の半導体パッケージ。 (15) The semiconductor package according to (13) or (14), wherein each of the first reinforcing member and the second reinforcing member has a plate shape.
（１６）　前記第１補強部材および前記第２補強部材は、それぞれ、前記半導体素子との熱膨張係数差が７ｐｐｍ／℃以下である上記（１２）ないし（１５）のいずれかに記載の半導体パッケージ。 (16) The semiconductor package according to any one of (12) to (15), wherein the first reinforcing member and the second reinforcing member each have a difference in coefficient of thermal expansion of 7 ppm / ° C. or less from the semiconductor element. .
（１７）　前記第１補強部材および前記第２補強部材は、それぞれ、金属材料で構成されている上記（１２）ないし（１６）のいずれかに記載の半導体パッケージ。 (17) The semiconductor package according to any one of (12) to (16), wherein each of the first reinforcing member and the second reinforcing member is made of a metal material.
（１８）　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい補強部材とを有し、
　前記半導体素子の平面視での面積をＳ１とし、前記補強部材の平面視での外周縁で囲まれた領域内の面積をＳ２としたときに、
　Ｓ２／Ｓ１が０．６４以上２．２５以下であることを特徴とする半導体パッケージ。 (18) A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board comprising:
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
When the area of the semiconductor element in plan view is S1, and the area in the region surrounded by the outer periphery of the reinforcing member in plan view is S2,
S2 / S1 is 0.64 or more and 2.25 or less, The semiconductor package characterized by the above-mentioned.
（１９）　平面視にて、前記補強部材の外周縁は、前記半導体素子の外周縁と一致またはそれよりも外側に位置している上記（１８）に記載の半導体パッケージ。 (19) The semiconductor package according to (18), wherein the outer peripheral edge of the reinforcing member coincides with or is located outside the outer peripheral edge of the semiconductor element in a plan view.
（２０）　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、前記補強部材は、前記各金属バンプに非接触で前記金属バンプ同士の間に位置する部分を有する上記（１８）または（１９）に記載の半導体パッケージ。 (20) A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate, and the reinforcing member is a portion located between the metal bumps in a non-contact manner with the metal bumps. The semiconductor package according to (18) or (19), wherein
（２１）　前記補強部材は、複数の開口部を有し、前記補強部材の前記開口部同士の間の部分が前記金属バンプ同士の間に位置する上記（２０）に記載の半導体パッケージ。 (21) The semiconductor package according to (20), wherein the reinforcing member has a plurality of openings, and a portion between the openings of the reinforcing member is located between the metal bumps.
（２２）　前記補強部材は、前記基板よりも熱膨張係数が小さい上記（１８）ないし（２１）のいずれかに記載の半導体パッケージ。 (22) The semiconductor package according to any one of (18) to (21), wherein the reinforcing member has a thermal expansion coefficient smaller than that of the substrate.
（２３）　前記補強部材の熱膨張係数は、３ｐｐｍ／℃以上１０ｐｐｍ／℃以下である上記（２２）に記載の半導体パッケージ。 (23) The semiconductor package according to (22), wherein the reinforcing member has a thermal expansion coefficient of 3 ppm / ° C. or more and 10 ppm / ° C. or less.
（２４）　前記補強部材は、前記半導体素子との熱膨張係数差が７ｐｐｍ／℃以下である上記（１８）ないし（２３）のいずれかに記載の半導体パッケージ。 (24) The semiconductor package according to any one of (18) to (23), wherein the reinforcing member has a difference in thermal expansion coefficient from the semiconductor element of 7 ppm / ° C. or less.
（２５）　前記補強部材は、板状をなしている上記（１８）ないし（２４）のいずれかに記載の半導体パッケージ。 (25) The semiconductor package according to any one of (18) to (24), wherein the reinforcing member has a plate shape.
（２６）　上記（１）ないし（２５）のいずれかに記載の半導体パッケージを備えることを特徴とする半導体装置。 (26) A semiconductor device comprising the semiconductor package according to any one of (1) to (25).
　本発明の半導体パッケージによれば、熱膨張係数が基板よりも小さい補強部材を配線基板の半導体素子と反対側の面に接合することにより、配線基板は半導体素子と補強部材とに挟持された状態となるため、半導体パッケージ全体の剛性を高めることができ、配線基板の両面の熱膨張差を防止または抑制することができる。特に、補強部材は、金属バンプ間にも及ぶように設けられているので、配線基板を強固に補強することができる。 According to the semiconductor package of the present invention, the wiring board is sandwiched between the semiconductor element and the reinforcing member by bonding the reinforcing member having a thermal expansion coefficient smaller than that of the board to the surface of the wiring board opposite to the semiconductor element. Therefore, the rigidity of the entire semiconductor package can be increased, and the difference in thermal expansion between both surfaces of the wiring board can be prevented or suppressed. In particular, since the reinforcing member is provided so as to extend between the metal bumps, the wiring board can be strongly reinforced.
　このようなことから、配線基板と半導体素子との熱膨張係数差に起因する配線基板の反りを抑制または防止することができる。その結果、半導体素子と基板を接続する金属バンプの接続信頼性、基板内部の導体パターン・導体ポストの接続信頼性および基板とマザーボードを接続する金属バンプの接続信頼性を向上させることができる。 For this reason, it is possible to suppress or prevent the warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element. As a result, it is possible to improve the connection reliability of the metal bumps connecting the semiconductor element and the substrate, the connection reliability of the conductor pattern / conductor post inside the substrate, and the connection reliability of the metal bumps connecting the substrate and the motherboard.
　また、配線基板自体の剛性を高める必要がなく、配線基板の厚さを薄くすることができるので、配線基板の厚さ方向での熱伝導性を高めることができる。そのため、本発明の半導体パッケージは、半導体素子からの熱を配線基板を介して逃すことができ、放熱性に優れる。
　また、伝熱バンプを備えた半導体パッケージにあっては、半導体素子からの熱を伝熱バンプを介して逃すことができ、放熱性がより優れたものとなる。
　このように放熱性に優れていることにより、半導体素子および配線基板の昇温を抑えることができるので、この点でも、配線基板と半導体素子との熱膨張係数差に起因する配線基板の反りを抑制または防止することができる。 Further, it is not necessary to increase the rigidity of the wiring board itself, and the thickness of the wiring board can be reduced, so that the thermal conductivity in the thickness direction of the wiring board can be increased. Therefore, the semiconductor package of the present invention can release heat from the semiconductor element through the wiring board, and is excellent in heat dissipation.
Moreover, in the semiconductor package provided with the heat transfer bump, the heat from the semiconductor element can be released through the heat transfer bump, and the heat dissipation is more excellent.
Since the heat dissipation is excellent in this manner, the temperature rise of the semiconductor element and the wiring board can be suppressed, so that the wiring board warpage caused by the difference in thermal expansion coefficient between the wiring board and the semiconductor element can be reduced. It can be suppressed or prevented.
　また、本発明の半導体装置によれば、前述したような半導体パッケージを備えるので、信頼性に優れる。 Moreover, according to the semiconductor device of the present invention, since the semiconductor package as described above is provided, the reliability is excellent.
本発明の第１実施形態に係る半導体パッケージを模式的に示す断面図である。1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention. 図１に示す半導体パッケージを示す上面図である。It is a top view which shows the semiconductor package shown in FIG. 図１に示す半導体パッケージを示す下面図である。It is a bottom view which shows the semiconductor package shown in FIG. 図１に示す半導体パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. 本発明の第４実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on 4th Embodiment of this invention. 本発明の第２実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 3rd Embodiment of this invention. 図７に示す半導体パッケージを示す上面図である。FIG. 8 is a top view showing the semiconductor package shown in FIG. 7. 図７に示す半導体パッケージを示す下面図である。FIG. 8 is a bottom view showing the semiconductor package shown in FIG. 7. 図７に示す半導体パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. 本発明の第５実施形態に係る半導体パッケージを模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor package which concerns on 5th Embodiment of this invention. 図１１に示す半導体パッケージを示す下面図である。FIG. 12 is a bottom view showing the semiconductor package shown in FIG. 11. 図１１に示す半導体パッケージの製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor package shown in FIG. 本発明の第６実施形態に係る半導体装置を模式的に示す断面図である。It is sectional drawing which shows typically the semiconductor device which concerns on 6th Embodiment of this invention.
　以下、添付図面に基づき、本発明の半導体パッケージおよび半導体装置の好適な実施形態について説明する。 Hereinafter, preferred embodiments of a semiconductor package and a semiconductor device of the present invention will be described with reference to the accompanying drawings.
　（半導体パッケージ）
　まず、本発明の第１実施形態～第３実施形態の半導体パッケージを説明する。 (Semiconductor package)
First, the semiconductor packages of the first to third embodiments of the present invention will be described.
　＜第１実施形態＞
　図１は、本発明の第１実施形態に係る半導体パッケージを模式的に示す断面図、図２は、図１に示す半導体パッケージを示す上面図、図３は、図１に示す半導体パッケージを示す下面図、図４は、図１に示す半導体パッケージの製造方法の一例を示す図である。なお、以下の説明では、説明の便宜上、図１中の上側を「上」、下側を「下」と言う。また、図１ないし４では、それぞれ、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 <First Embodiment>
1 is a cross-sectional view schematically showing a semiconductor package according to a first embodiment of the present invention, FIG. 2 is a top view showing the semiconductor package shown in FIG. 1, and FIG. 3 shows the semiconductor package shown in FIG. FIG. 4 is a bottom view and FIG. 4 is a view showing an example of a method for manufacturing the semiconductor package shown in FIG. In the following description, for convenience of description, the upper side in FIG. 1 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIGS. 1 to 4, each part of the semiconductor package is exaggerated for convenience of explanation.
　図１に示すように、半導体パッケージ１は、配線基板２と、この配線基板２上に搭載された半導体素子３と、第１補強部材４と、第２補強部材５とを有する。 As shown in FIG. 1, the semiconductor package 1 includes a wiring board 2, a semiconductor element 3 mounted on the wiring board 2, a first reinforcing member 4, and a second reinforcing member 5.
　このような半導体パッケージ１によれば、半導体素子３と接合された部分以外の部分においても、配線基板２の両面が第１補強部材４および第２補強部材５により補強されるため、半導体パッケージ１全体の剛性が増す。特に、第１補強部材４および第２補強部材５の熱膨張係数が配線基板２（具体的には後述する基板２１）よりも小さいため、半導体素子３が配線基板２の全面に亘って設けられているのと同様に、配線基板２と半導体素子３との熱膨張係数差に起因する配線基板２の反りを抑制または防止することができる。 According to such a semiconductor package 1, both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Increases overall rigidity. In particular, since the thermal expansion coefficient of the first reinforcing member 4 and the second reinforcing member 5 is smaller than that of the wiring substrate 2 (specifically, a substrate 21 described later), the semiconductor element 3 is provided over the entire surface of the wiring substrate 2. In the same manner, warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 can be suppressed or prevented.
　また、配線基板２自体の剛性を高める必要がなく、配線基板２の厚さを薄くすることができるので、配線基板２の厚さ方向での熱伝導性を高めることができる。そのため、半導体パッケージ１は、半導体素子３からの熱を配線基板２を介して逃すことができ、放熱性に優れる。また、第１補強部材４および第２補強部材５の構成材料を適宜選択することにより、半導体パッケージ１の放熱性を高めることもできる。 Further, it is not necessary to increase the rigidity of the wiring board 2 itself, and the thickness of the wiring board 2 can be reduced, so that the thermal conductivity in the thickness direction of the wiring board 2 can be increased. Therefore, the semiconductor package 1 can release the heat from the semiconductor element 3 through the wiring board 2 and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
　このようなことから、半導体素子３および配線基板２の昇温を抑えることができるので、この点でも、配線基板２と半導体素子３との熱膨張係数差に起因する配線基板２の反りを抑制または防止することができる。 For this reason, since the temperature rise of the semiconductor element 3 and the wiring board 2 can be suppressed, the warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is also suppressed in this respect. Or it can be prevented.
　特に、半導体パッケージ１では、第２補強部材５を配線基板２の半導体素子３と反対側の面（下面）に接合することにより、配線基板２は半導体素子３と第２補強部材５とに挟持された状態となるため、配線基板２の両面の熱膨張差を防止または抑制することができる。特に、第２補強部材５は、後述する金属バンプ７１間にも及ぶように設けられているので、配線基板２を強固に補強することができる。 In particular, in the semiconductor package 1, the wiring board 2 is sandwiched between the semiconductor element 3 and the second reinforcing member 5 by bonding the second reinforcing member 5 to the surface (lower surface) opposite to the semiconductor element 3 of the wiring board 2. Therefore, the difference in thermal expansion between both surfaces of the wiring board 2 can be prevented or suppressed. In particular, since the second reinforcing member 5 is provided so as to extend between metal bumps 71 described later, the wiring board 2 can be strongly reinforced.
　以下、半導体パッケージ１の各部を順次詳細に説明する。
　［配線基板］
　配線基板２は、半導体素子３を支持する基板であり、例えば、その搭載した半導体素子３と後述するようなマザーボード２００との電気的接続を中継する中継基板（インターポーザ）である。また、配線基板２は、その平面視形状は、通常、正方形、長方形等の四角形とされる。 Hereinafter, each part of the semiconductor package 1 will be sequentially described in detail.
[Wiring board]
The wiring board 2 is a board that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later. In addition, the wiring substrate 2 is usually a quadrangle such as a square or a rectangle in plan view.
　配線基板２は、基板２１と、導体パターン２２１、２２２、２２３、２２４と、導体ポスト２３１、２３２、２３３、２３４と、伝熱ポスト２４とを有している。 The wiring board 2 includes a substrate 21, conductor patterns 221, 222, 223, 224, conductor posts 231, 232, 233, 234, and heat transfer posts 24.
　なお、本実施形態では、導体パターン２２１は、基板２１の一方の面側に設けられた第１導体パターンを構成し、導体パターン２２４は、基板２１の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンを構成する。電気的に接続されていることにより、第１導体パターンと第２導体パターンとの間で電気信号の伝送が可能となる。 In this embodiment, the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21, and the conductor pattern 224 is provided on the other surface side of the substrate 21. A second conductor pattern electrically connected to the conductor pattern is formed. By being electrically connected, an electric signal can be transmitted between the first conductor pattern and the second conductor pattern.
　基板２１は、複数（本実施形態では５層）の絶縁層２１１、２１２、２１３、２１４、２１５で構成されている。より具体的には、基板２１は、絶縁層２１１、絶縁層２１２、絶縁層２１３、絶縁層２１４、絶縁層２１５がこの順で積層されて構成されている。なお、基板２１を構成する絶縁層の数は、これに限定されず、１～４層であってもよいし、６層以上であってもよい。 The substrate 21 is composed of a plurality (five layers in this embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21 is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order. The number of insulating layers constituting the substrate 21 is not limited to this, and may be 1 to 4 layers or 6 or more layers.
　各絶縁層２１１、２１２、２１３、２１４、２１５は、絶縁性を有する材料で構成されている。 Each insulating layer 211, 212, 213, 214, 215 is made of an insulating material.
　具体的には、各絶縁層２１１、２１２、２１３、２１４、２１５は、基材（繊維基材）と、その基材に含浸された樹脂組成物とで構成されている。 Specifically, each insulating layer 211, 212, 213, 214, 215 is composed of a base material (fiber base material) and a resin composition impregnated in the base material.
　基材は、各絶縁層２１１、２１２、２１３、２１４、２１５の芯材として用いられるものである。このような基材を有することにより、基板２１の剛性を高めることができる。 The base material is used as a core material of the insulating layers 211, 212, 213, 214, and 215. By having such a base material, the rigidity of the substrate 21 can be increased.
　基材としては、例えば、ガラス織布、ガラス不織布等のガラス繊維で構成されたガラス繊維基材、ポリアミド樹脂繊維、芳香族ポリアミド樹脂繊維、全芳香族ポリアミド樹脂繊維等のポリアミド系樹脂繊維、ポリエステル樹脂繊維、芳香族ポリエステル樹脂繊維、全芳香族ポリエステル樹脂繊維等のポリエステル系樹脂繊維、ポリイミド樹脂繊維、フッ素樹脂繊維等を主成分とする織布または不織布で構成される合成繊維基材、クラフト紙、コットンリンター紙、リンターとクラフトパルプの混抄紙等を主成分とする紙基材等が挙げられる。これらの中でも、かかる基材としては、ガラス繊維基材が好ましい。これにより、基板２１の剛性を高めるとともに、基板２１の薄型化を図ることができる。さらに、基板２１の熱膨張係数も小さくすることができる。 Examples of the base material include glass fiber base materials composed of glass fibers such as glass woven fabrics and glass nonwoven fabrics, polyamide resin fibers such as polyamide resin fibers, aromatic polyamide resin fibers, wholly aromatic polyamide resin fibers, and polyesters. Synthetic fiber base material, kraft paper composed of woven fabric or non-woven fabric mainly composed of resin fiber, aromatic polyester resin fiber, polyester resin fiber such as wholly aromatic polyester resin fiber, polyimide resin fiber, fluororesin fiber, etc. And paper base materials mainly composed of cotton linter paper, mixed paper of linter and kraft pulp, and the like. Among these, as such a base material, a glass fiber base material is preferable. Thereby, the rigidity of the substrate 21 can be increased and the substrate 21 can be thinned. Furthermore, the thermal expansion coefficient of the substrate 21 can be reduced.
　このようなガラス繊維基材を構成するガラスとしては、例えば、Ｅガラス、Ｃガラス、Ａガラス、Ｓガラス、Ｄガラス、ＮＥガラス、Ｔガラス、Ｈガラス等が挙げられる。これらの中でもＴガラスが好ましい。これにより、ガラス繊維基材の熱膨張係数を小さくすることができ、それによって基板２１の熱膨張係数を小さくすることができる。 Examples of the glass constituting such a glass fiber substrate include E glass, C glass, A glass, S glass, D glass, NE glass, T glass, and H glass. Among these, T glass is preferable. Thereby, the thermal expansion coefficient of a glass fiber base material can be made small, and, thereby, the thermal expansion coefficient of the board | substrate 21 can be made small.
　また、絶縁層２１１、２１２、２１３、２１４、２１５が基材を含む場合、絶縁層２１１、２１２、２１３、２１４、２１５における基材の含有率は、それぞれ、３０～７０ｗｔ％であることが好ましく、４０～６０ｗｔ％であることがより好ましい。これにより、これらの絶縁層のひび割れ等の破損を確実に防ぎつつ、各絶縁層の電気絶縁性および熱膨張係数を十分に低いものとすることができる。なお、絶縁層２１１、２１２、２１３、２１４、２１５のうちの少なくとも１層は、基材を含まずに樹脂組成物のみで構成されていてもよい。 When the insulating layers 211, 212, 213, 214, and 215 include a base material, the content of the base material in the insulating layers 211, 212, 213, 214, and 215 is preferably 30 to 70 wt%, respectively. 40 to 60 wt% is more preferable. Thereby, the electric insulation and thermal expansion coefficient of each insulating layer can be made sufficiently low while reliably preventing damage such as cracks of these insulating layers. Note that at least one of the insulating layers 211, 212, 213, 214, and 215 may be composed of only the resin composition without including the base material.
　このような基材に含浸される樹脂組成物は、樹脂材料が含まれている。かかる樹脂材料としては、熱硬化性樹脂が好適に用いられる。 The resin composition impregnated in such a base material contains a resin material. As such a resin material, a thermosetting resin is preferably used.
　前記熱硬化性樹脂としては、例えば、フェノールノボラック樹脂、クレゾールノボラック樹脂、ビスフェノールＡノボラック樹脂等のノボラック型フェノール樹脂、未変性のレゾールフェノール樹脂、桐油、アマニ油、クルミ油等で変性した油変性レゾールフェノール樹脂等のレゾール型フェノール樹脂等のフェノール樹脂、ビスフェノールＡエポキシ樹脂、ビスフェノールＦエポキシ樹脂等のビスフェノール型エポキシ樹脂、ノボラックエポキシ樹脂、クレゾールノボラックエポキシ樹脂等のノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂等のエポキシ樹脂、シアネート樹脂、ユリア（尿素）樹脂、メラミン樹脂等のトリアジン環を有する樹脂、不飽和ポリエステル樹脂、ビスマレイミド樹脂、ポリウレタン樹脂、ジアリルフタレート樹脂、シリコーン樹脂、ベンゾオキサジン環を有する樹脂、シアネートエステル樹脂等が挙げられる。 Examples of the thermosetting resin include novolak type phenol resins such as phenol novolak resin, cresol novolak resin, bisphenol A novolak resin, unmodified resole phenol resin, oil-modified resole modified with tung oil, linseed oil, walnut oil, and the like. Such as phenol resin, phenol resin such as resol type phenol resin, bisphenol type epoxy resin such as bisphenol A epoxy resin, bisphenol F epoxy resin, novolac epoxy resin such as novolac epoxy resin, cresol novolac epoxy resin, biphenyl type epoxy resin, etc. Epoxy resin, cyanate resin, urea (urea) resin, resin having triazine ring such as melamine resin, unsaturated polyester resin, bismaleimide resin, polyurethane resin, diallyl phthalate Over preparative resin, silicone resin, resins having a benzoxazine ring, cyanate ester resins.
　これらの中でも、特に、シアネート樹脂が好ましい。これにより、基板２１の熱膨張係数を十分に小さくすることができる。さらに、基板２１の電気特性（低誘電率、低誘電正接等）を優れたものとすることができる。 Among these, cyanate resin is particularly preferable. Thereby, the thermal expansion coefficient of the board | substrate 21 can be made small enough. Furthermore, the electrical characteristics (low dielectric constant, low dielectric loss tangent, etc.) of the substrate 21 can be made excellent.
　また、前記樹脂組成物は、フィラーを含むのが好ましい。すなわち、絶縁層２１１、２１２、２１３、２１４、２１５は、それぞれ、フィラーを含むことが好ましい。これにより、絶縁層２１１、２１２、２１３、２１４、２１５の熱膨張係数を低くすることができる。 The resin composition preferably contains a filler. That is, each of the insulating layers 211, 212, 213, 214, and 215 preferably contains a filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be lowered.
　前記フィラーとしては、各種無機フィラーまたは有機フィラーが挙げられる。
　無機フィラー（無機充填材）としては、例えば、シリカ、アルミナ、ケイ藻土、酸化チタン、酸化鉄、酸化亜鉛、酸化マグネシウム、金属フェライト等の酸化物、水酸化アルミニウム、水酸化マグネシウム等の水酸化物、炭酸カルシウム（軽質、重質）、炭酸マグネシウム、ドロマイト、ドーソナイト等の炭酸塩、硫酸カルシウム、硫酸バリウム、硫酸アンモニウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、タルク、マイカ、クレー、ガラス繊維、ケイ酸カルシウム、モンモリロナイト、ベントナイト等のケイ酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、カーボンブラック、グラファイト、炭素繊維等の炭素、その他鉄粉、銅粉、アルミニウム粉、亜鉛華、硫化モリブデン、ボロン繊維、チタン酸カリウム、チタン酸ジルコン酸鉛が挙げられる。 Examples of the filler include various inorganic fillers or organic fillers.
Examples of the inorganic filler (inorganic filler) include oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide and metal ferrite, and hydroxide such as aluminum hydroxide and magnesium hydroxide. Products, calcium carbonate (light, heavy), carbonates such as magnesium carbonate, dolomite, dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate, calcium sulfite, talc, mica, clay, glass fiber, silica Silicates such as calcium oxide, montmorillonite and bentonite, borate such as zinc borate, barium metaborate, aluminum borate, calcium borate and sodium borate, carbon such as carbon black, graphite and carbon fiber, other iron Powder, copper powder, aluminum powder, zinc white, sulfide Ribuden, boron fiber, potassium titanate, and a lead zirconate titanate.
　また、有機フィラーとしては、合成樹脂粉末が挙げられる。この合成樹脂粉末としては、例えば、アルキド樹脂、エポキシ樹脂、シリコーン樹脂、フェノール樹脂、ポリエステル、アクリル樹脂、アセタール樹脂、ポリエチレン、ポリエーテル、ポリカーボネート、ポリアミド、ポリスルホン、ポリスチレン、ポリ塩化ビニル、フッ素樹脂、ポリプロピレン、エチレン－酢酸ビニル共重合体等の各種熱硬化性樹脂または熱可塑性樹脂の粉末、またはこれらの樹脂の共重合体の粉末が挙げられる。また、有機フィラーの他の例としては、芳香族または脂肪族ポリアミド繊維、ポリプロピレン繊維、ポリエステル繊維、アラミド繊維等が挙げられる。 Further, as the organic filler, synthetic resin powder can be mentioned. Examples of the synthetic resin powder include alkyd resin, epoxy resin, silicone resin, phenol resin, polyester, acrylic resin, acetal resin, polyethylene, polyether, polycarbonate, polyamide, polysulfone, polystyrene, polyvinyl chloride, fluororesin, and polypropylene. In addition, various thermosetting resins such as ethylene-vinyl acetate copolymers or powders of thermoplastic resins, or powders of copolymers of these resins may be mentioned. Other examples of organic fillers include aromatic or aliphatic polyamide fibers, polypropylene fibers, polyester fibers, and aramid fibers.
　前述したようなフィラーの中でも、無機フィラーを用いるのが好ましい。これにより、絶縁層２１１、２１２、２１３、２１４、２１５の熱膨張係数を効果的に低めることができる。また、絶縁層２１１、２１２、２１３、２１４、２１５の伝熱性を高めることもできる。 Among the fillers as described above, it is preferable to use an inorganic filler. Thereby, the thermal expansion coefficient of the insulating layers 211, 212, 213, 214, and 215 can be effectively reduced. In addition, the heat transfer properties of the insulating layers 211, 212, 213, 214, and 215 can be increased.
　特に、無機フィラーの中でも、シリカが好ましく、溶融シリカ（特に球状溶融シリカ）が低熱膨張性に優れる点で好ましい。 Particularly, among inorganic fillers, silica is preferable, and fused silica (especially spherical fused silica) is preferable in terms of excellent low thermal expansion.
　無機フィラーの平均粒子径は、特に限定されないが、０．０５～２．０μｍが好ましく、特に０．１～１．０μｍが好ましい。これにより、絶縁層２１１、２１２、２１３、２１４、２１５中で、無機フィラーは、より均一に分散することができ、絶縁層２１１、２１２、２１３、２１４、２１５の物理的強度および絶縁性を特に優れたものとすることができる。 The average particle size of the inorganic filler is not particularly limited, but is preferably 0.05 to 2.0 μm, particularly preferably 0.1 to 1.0 μm. As a result, the inorganic filler can be more uniformly dispersed in the insulating layers 211, 212, 213, 214, and 215, and the physical strength and insulating properties of the insulating layers 211, 212, 213, 214, and 215 are particularly improved. It can be excellent.
　なお、上記無機フィラーの平均粒子径は、例えば、粒度分布計（ＨＯＲＩＢＡ製、ＬＡ－５００）により測定することができる。また、本明細書において、平均粒子径とは、体積基準での平均粒子径を指す。 The average particle size of the inorganic filler can be measured by, for example, a particle size distribution meter (manufactured by HORIBA, LA-500). Moreover, in this specification, an average particle diameter refers to the average particle diameter on a volume basis.
　絶縁層２１１、２１２、２１３、２１４、２１５における無機充填材の含有量は、それぞれ、特に限定されないが、基材を除く樹脂組成物を１００ｗｔ％としたときに、３０～８０ｗｔ％が好ましく、特に４５～７５ｗｔ％が好ましい。含有量が前記範囲内であると、絶縁層２１１、２１２、２１３、２１４、２１５は、熱膨張係数が十分に低く、吸湿性が特に低いものとなる。 The content of the inorganic filler in the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but is preferably 30 to 80 wt% when the resin composition excluding the base material is 100 wt%, particularly 45 to 75 wt% is preferable. When the content is within the above range, the insulating layers 211, 212, 213, 214, and 215 have sufficiently low thermal expansion coefficients and particularly low hygroscopicity.
　また、前記樹脂組成物は、前述した熱硬化性樹脂の他、フェノキシ樹脂、ポリイミド樹脂、ポリアミドイミド樹脂、ポリフェニレンオキサイド樹脂、ポリエーテルスルホン樹脂等の熱可塑性樹脂含んでいてもよい。 The resin composition may contain a thermoplastic resin such as a phenoxy resin, a polyimide resin, a polyamideimide resin, a polyphenylene oxide resin, or a polyethersulfone resin in addition to the thermosetting resin described above.
　また、前記樹脂組成物は、必要に応じて、顔料、酸化防止剤等の上記成分以外の添加物を含んでいてもよい。 The resin composition may contain additives other than the above components such as pigments and antioxidants as necessary.
　また、絶縁層２１１、２１２、２１３、２１４、２１５は、互いに同じ材料で構成されていてもよいし、互いに異なる材料で構成されていてもよい。 In addition, the insulating layers 211, 212, 213, 214, and 215 may be made of the same material as each other, or may be made of different materials.
　上述したような複数の層で構成された基板２１の平均厚さは、特に限定されないが、３０μｍ以上８００μｍ以下であることが好ましく、３０μｍ以上４００μｍ以下であることがより好ましい。 The average thickness of the substrate 21 composed of a plurality of layers as described above is not particularly limited, but is preferably 30 μm or more and 800 μm or less, and more preferably 30 μm or more and 400 μm or less.
　このような基板２１の絶縁層２１１と絶縁層２１２の間には、導体パターン２２１が介挿されている。また、絶縁層２１２と絶縁層２１３との間には、導体パターン２２２が介挿されている。また、絶縁層２１３と絶縁層２１４との間には、導体パターン２２３が介挿されている。また、絶縁層２１４と絶縁層２１５との間には、導体パターン２２４が介挿されている。 The conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21. In addition, a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213. A conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214. A conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215.
　この導体パターン２２１、２２２、２２３、２２４は、それぞれ、複数の配線を有する回路として機能するものである。 The conductor patterns 221, 222, 223, and 224 each function as a circuit having a plurality of wirings.
　導体パターン２２１、２２２、２２３、２２４の構成材料としては、導電性を有するものであれば、特に限定されず、例えば、銅、銅系合金、アルミ、アルミ系合金等の各種金属および各種合金が挙げられる。中でも、かかる構成材料としては、銅および銅系合金を用いるのが好ましい。銅および銅系合金は、電気伝導率が比較的高いものである。そのため、配線基板２の電気的特性を良好なものとすることができる。また、銅および銅系合金は熱伝導性にも優れるので、配線基板２の放熱性を向上させることもできる。 The constituent material of the conductor patterns 221, 222, 223, and 224 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
　また、導体パターン２２１、２２２、２２３、２２４の平均厚さは、特に限定されないが、５μｍ以上３０μｍ以下であることが好ましい。 The average thickness of the conductor patterns 221, 222, 223, and 224 is not particularly limited, but is preferably 5 μm or more and 30 μm or less.
　また、絶縁層２１１には、その厚さ方向に貫通するビアホールが形成され、そのビアホール内に導体ポスト（ビアポスト）２３１が設けられている。この導体ポスト２３１は、絶縁層２１１をその厚さ方向に貫通しており、上端部が半導体素子３に金属バンプ３１を介して接続されるとともに、下端部が導体パターン２２１に接続されている。これにより、導体パターン２２１と半導体素子３とが導通している。 Further, a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole. The conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected.
　同様に、絶縁層２１２には、その厚さ方向に貫通する導体ポスト（ビアポスト）２３２が設けられている。この導体ポスト２３２は、上端部が導体パターン２２１に接続されるとともに、下端部が導体パターン２２２に接続されている。これにより、導体パターン２２１と導体パターン２２２とが導通している。 Similarly, the insulating layer 212 is provided with a conductor post (via post) 232 penetrating in the thickness direction. The conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.
　また、絶縁層２１３には、その厚さ方向に貫通する導体ポスト（ビアポスト）２３３が設けられている。この導体ポスト２３３は、上端部が導体パターン２２２に接続されるとともに、下端部が導体パターン２２３に接続されている。これにより、導体パターン２２２と導体パターン２２３とが導通している。 The insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction. The conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.
　また、絶縁層２１４には、その厚さ方向に貫通する導体ポスト（ビアポスト）２３４が設けられている。この導体ポスト２３４は、上端部が導体パターン２２３に接続されるとともに、下端部が導体パターン２２４に接続されている。これにより、導体パターン２２３と導体パターン２２４とが導通している。 Also, the insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction. The conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.
　導体ポスト２３１、２３２、２３３、２３４の構成材料としては、導電性を有するものであれば、特に限定されず、例えば、銅、銅系合金、アルミ、アルミ系合金等の各種金属および各種合金が挙げられる。中でも、かかる構成材料としては、銅および銅系合金を用いるのが好ましい。銅および銅系合金は、電気伝導率が比較的高いものである。そのため、配線基板２の電気的特性を良好なものとすることができる。また、銅および銅系合金は熱伝導性にも優れるので、配線基板２の放熱性を向上させることもできる。 The constituent material of the conductor posts 231, 232, 233, 234 is not particularly limited as long as it has conductivity, and examples thereof include various metals and various alloys such as copper, a copper-based alloy, aluminum, and an aluminum-based alloy. Can be mentioned. Among these, it is preferable to use copper and a copper-based alloy as the constituent material. Copper and copper-based alloys have relatively high electrical conductivity. Therefore, the electrical characteristics of the wiring board 2 can be improved. Moreover, since copper and a copper-type alloy are excellent also in heat conductivity, the heat dissipation of the wiring board 2 can also be improved.
　また、絶縁層２１５には、その厚さ方向に貫通する複数の開口部が設けられ、その各開口部から導体パターン２２４の一部（端子）が露出している。そして、その導体パターン２２４の露出した各部分（端子）上には、金属バンプ７１が接合されている。すなわち、第２導体パターンである導体パターン２２４の基板２１と反対側の面には、複数の金属バンプ７１が接合されている。 The insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening. A metal bump 71 is bonded onto each exposed portion (terminal) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21.
　この金属バンプ７１は、半導体パッケージ１を例えば後述するようなマザーボードに対して電気的に接続するためのものである。電気的に接続されることにより、半導体パッケージ１とマザーボードとの間で電気信号の伝送が可能となる。 The metal bumps 71 are for electrically connecting the semiconductor package 1 to, for example, a mother board as will be described later. By being electrically connected, an electric signal can be transmitted between the semiconductor package 1 and the mother board.
　本実施形態では、金属バンプ７１は、略球状をなしている。なお、金属バンプ７１の形状は、これに限定されない。 In this embodiment, the metal bump 71 has a substantially spherical shape. The shape of the metal bump 71 is not limited to this.
　金属バンプ７１の構成材料としては、特に限定されないが、例えば、錫－鉛系、錫－銀系、錫－亜鉛系、錫－ビスマス系、錫－アンチモン系、錫－銀－ビスマス系、錫－銅系、錫－銀－銅系等の各種ろう材（半田）を用いることができる。 The constituent material of the metal bump 71 is not particularly limited. For example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, tin-- Various brazing materials (solder) such as copper and tin-silver-copper can be used.
　また、基板２１には、その厚さ方向に貫通する複数のビアホールが形成され、その各ビアホールに伝熱ポスト２４が設けられている。 In addition, a plurality of via holes penetrating in the thickness direction are formed in the substrate 21, and a heat transfer post 24 is provided in each via hole.
　この各伝熱ポスト２４は、基板２１全体をその厚さ方向に貫通しており、上端が基板２１の上面から露出するとともに、下端が基板２１の下面から露出している。そして、伝熱ポスト２４は、上端が第１補強部材４に接触し、下端が第２補強部材５に接触している。これにより、各伝熱ポスト２４は、第１補強部材４と第２補強部材５とを接続している。 Each heat transfer post 24 penetrates the entire substrate 21 in the thickness direction, and its upper end is exposed from the upper surface of the substrate 21 and its lower end is exposed from the lower surface of the substrate 21. The heat transfer post 24 has an upper end in contact with the first reinforcing member 4 and a lower end in contact with the second reinforcing member 5. Thus, each heat transfer post 24 connects the first reinforcing member 4 and the second reinforcing member 5.
　この各伝熱ポスト（熱伝導部）２４は、前述した基板２１（絶縁層）よりも高い伝熱性を有する。これにより、第１補強部材４から伝熱ポスト２４を介して第２補強部材５へ熱を効率的に伝達することができる。その結果、半導体パッケージ１の放熱性を向上させることができる。 Each of the heat transfer posts (heat conducting portions) 24 has higher heat transfer performance than the substrate 21 (insulating layer) described above. Thereby, heat can be efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 via the heat transfer post 24. As a result, the heat dissipation of the semiconductor package 1 can be improved.
　また、この各伝熱ポスト２４は、基板２１をその厚さ方向に貫通するものであるため、公知の導体ポストと同様に、簡単かつ高精度に形成することができる。 Further, since each heat transfer post 24 penetrates the substrate 21 in the thickness direction, it can be formed easily and with high accuracy in the same manner as a known conductor post.
　また、各伝熱ポスト２４は、中空であってもよいし、中実であってもよい。また、各伝熱ポスト２４の横断面形状としては、特に限定されず、例えば、円形、楕円形、多角形等が挙げられる。また、伝熱ポスト２４の数は、特に限定されず、任意であるが、配線基板２の機械的強度を損ねない程度に、できるだけ多くするのが好ましい。 Further, each heat transfer post 24 may be hollow or solid. Moreover, it does not specifically limit as a cross-sectional shape of each heat-transfer post | mailbox 24, For example, circular, an ellipse, a polygon etc. are mentioned. Further, the number of heat transfer posts 24 is not particularly limited and is arbitrary, but is preferably as large as possible so as not to impair the mechanical strength of the wiring board 2.
　各伝熱ポスト２４は、電気信号の伝送に寄与しないものである。これにより、第１補強部材４から伝熱ポスト２４を介して第２補強部材５へ熱をより効率的に伝達することができる。 Each heat transfer post 24 does not contribute to the transmission of electrical signals. Thereby, heat can be more efficiently transferred from the first reinforcing member 4 to the second reinforcing member 5 through the heat transfer post 24.
　本実施形態では、複数の伝熱ポスト２４は、配線基板２を平面視したときに、配線基板２の外周部に沿って互いに間隔を隔てて並設されている。特に、複数の伝熱ポスト２４は、配線基板２を平面視したときに、配線基板２の外周部に沿って周方向に等間隔で並設されているのが好ましい。これにより、配線基板２の温度分布を均一化することができる。 In the present embodiment, the plurality of heat transfer posts 24 are arranged in parallel along the outer peripheral portion of the wiring board 2 at intervals when the wiring board 2 is viewed in plan. In particular, the plurality of heat transfer posts 24 are preferably arranged side by side at equal intervals in the circumferential direction along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.
　また、複数の伝熱ポスト２４は、配線基板２を平面視したときに、前述した導体パターン２２１、２２２、２２３、２２４に重ならないように設けられている。これにより、伝熱ポスト２４の形成が簡単となるとともに、伝熱ポスト２４と導体パターン２２１、２２２、２２３、２２４との短絡を防止することができる。 Further, the plurality of heat transfer posts 24 are provided so as not to overlap the conductor patterns 221, 222, 223, and 224 described above when the wiring board 2 is viewed in plan view. Thereby, formation of the heat transfer post 24 is simplified, and a short circuit between the heat transfer post 24 and the conductor patterns 221, 222, 223, and 224 can be prevented.
　このような各伝熱ポスト２４の構成材料としては、前述した基板２１（絶縁層）よりも高い伝熱性を有するものであれば、特に限定されないが、金属材料を用いるのが好ましい。 The constituent material of each heat transfer post 24 is not particularly limited as long as it has a higher heat transfer property than the substrate 21 (insulating layer) described above, but a metal material is preferably used.
　かかる金属材料としては、例えば、銅、銅系合金、アルミ、アルミ系合金等の各種金属および各種合金が挙げられる。中でも、かかる金属材料としては、伝熱性に優れるので、銅、銅系合金、アルミ、アルミ系合金を用いるのが好ましい。銅および銅系合金は、熱伝導性に優れるので、配線基板２の放熱性を向上させることもできる。 Examples of such metal materials include various metals and various alloys such as copper, copper-based alloys, aluminum, and aluminum-based alloys. Among these, as such a metal material, it is preferable to use copper, a copper-based alloy, aluminum, or an aluminum-based alloy because of excellent heat conductivity. Since copper and a copper-based alloy are excellent in thermal conductivity, the heat dissipation of the wiring board 2 can also be improved.
　また、伝熱ポスト２４の構成材料は、前述した導体ポスト２３１～２３４の構成材料と異なっていてもよいが、導体ポスト２３１～２３４の構成材料（特に導体ポスト２３４の構成材料）と同じであるのが好ましい。これにより、伝熱ポスト２４を導体ポスト２３４の形成と同時に一括して形成することができる。そのため、半導体パッケージ１の製造が簡単化され、また、半導体パッケージ１を安価なものとすることができる。 The constituent material of the heat transfer post 24 may be different from the constituent material of the conductor posts 231 to 234 described above, but is the same as the constituent material of the conductor posts 231 to 234 (particularly, the constituent material of the conductor posts 234). Is preferred. As a result, the heat transfer posts 24 can be formed simultaneously with the formation of the conductor posts 234. Therefore, the manufacturing of the semiconductor package 1 is simplified, and the semiconductor package 1 can be made inexpensive.
　［半導体素子］
　半導体素子３は、例えば、集積回路素子（ＩＣ）であり、より具体的には、例えば、ロジックＩＣ、メモリおよび受発光素子等である。 [Semiconductor element]
The semiconductor element 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light receiving / emitting element.
　この半導体素子３は、前述した配線基板２の基板２１の上面（一方の面）に接合され、第１導体パターンである導体パターン２２１に電気的に接続されている。 The semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
　具体的には、半導体素子３は、その下面に、図示しない複数の端子が設けられており、その各端子が金属バンプ３１を介して、前述した配線基板２の導体ポスト２３１に電気的に接続されている。これにより、半導体素子３と配線基板２の導体パターン２２１とが電気的に接続され、半導体素子３と導体パターン２２１との間で電気信号の伝送が可能となっている。 Specifically, the semiconductor element 3 is provided with a plurality of terminals (not shown) on its lower surface, and each terminal is electrically connected to the conductor post 231 of the wiring board 2 described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2 are electrically connected, and an electric signal can be transmitted between the semiconductor element 3 and the conductor pattern 221.
　金属バンプ３１の構成材料としては、特に限定されないが、前述した金属バンプ７１と同様、例えば、錫－鉛系、錫－銀系、錫－亜鉛系、錫－ビスマス系、錫－アンチモン系、錫－銀－ビスマス系、錫－銅系、錫－銀－銅系等の各種ろう材（半田）を用いることができる。 The constituent material of the metal bump 31 is not particularly limited, but is similar to the metal bump 71 described above, for example, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin Various brazing materials (solder) such as silver-bismuth, tin-copper, tin-silver-copper can be used.
　また、半導体素子３は、接着層３２を介して、配線基板２の上面に接着（接合）されている。 Further, the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 through the adhesive layer 32.
　この接着層３２は、接着性および絶縁性を有する材料で構成され、例えば、アンダーフィル材の硬化物で構成されている。 The adhesive layer 32 is made of a material having adhesiveness and insulating properties, for example, a cured product of an underfill material.
　アンダーフィル材としては、特に限定されず、公知のアンダーフィル材を用いることができるが、後述する絶縁材８１を形成するための半田接合用レジストと同様のものを用いることもできる。 The underfill material is not particularly limited, and a known underfill material can be used, but the same solder bonding resist as that for forming an insulating material 81 described later can also be used.
　［第１補強部材］
　第１補強部材（スティフナー）４は、前述した配線基板２の基板２１の上面（一方の面）の、半導体素子３が接合されていない部分に接合されている。 [First reinforcing member]
The first reinforcing member (stiffener) 4 is bonded to a portion of the upper surface (one surface) of the substrate 21 of the wiring substrate 2 described above where the semiconductor element 3 is not bonded.
　この第１補強部材４と基板２１とは、接着剤を介して接合することができる。これにより、第１補強部材４の設置が簡単となる。 The first reinforcing member 4 and the substrate 21 can be joined via an adhesive. Thereby, installation of the 1st reinforcement member 4 becomes easy.
　かかる接着剤としては、接着機能を有するものであれば、特に限定されず、各種接着剤を用いることができるが、熱伝導性に優れたものが好ましく、後述する熱伝導性材料６と同様のものを用いることができる。 Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the thermal conductive material 6 described later. Things can be used.
　この第１補強部材４は、基板２１よりも熱膨張係数が小さい。これにより、基板２１の熱膨張を抑えることができる。 The first reinforcing member 4 has a smaller thermal expansion coefficient than the substrate 21. Thereby, the thermal expansion of the substrate 21 can be suppressed.
　また、第１補強部材４は、板状をなしている。これにより、第１補強部材４の構成を簡単かつ小型なものとすることができる。 The first reinforcing member 4 has a plate shape. Thereby, the structure of the 1st reinforcement member 4 can be made simple and small.
　このような第１補強部材４の基板２１と反対側の面（すなわち上面）は、半導体素子３の基板２１と反対側の面（すなわち上面）と同一面上またはそれよりも基板２１側（すなわち下側）に位置しているのが好ましい。これにより、半導体パッケージ１の製造に際し、第１補強部材４の設置後に半導体素子３を設置する場合、半導体素子３の設置が容易となる。 The surface of the first reinforcing member 4 opposite to the substrate 21 (that is, the upper surface) is the same surface as the surface of the semiconductor element 3 opposite to the substrate 21 (that is, the upper surface) or the substrate 21 side (that is, more than that) It is preferably located on the lower side. Thereby, when the semiconductor element 3 is installed after the first reinforcing member 4 is installed in manufacturing the semiconductor package 1, the installation of the semiconductor element 3 is facilitated.
　本実施形態では、第１補強部材４の基板２１と反対側の面（すなわち上面）と、半導体素子３の基板２１と反対側の面（すなわち上面）とが同一面上に位置している。これにより、半導体パッケージ１を薄型化しつつ、配線基板２の反りを効果的に抑制または防止することができる。また、第１補強部材４の上面上に他の構造体（例えば、基板、半導体素子、ヒートシンク等）を設ける場合、その構造体の設置を安定的に行うことができる。
　なお、第１補強部材４および半導体素子３を封止樹脂でモールドしてもよい。 In the present embodiment, the surface of the first reinforcing member 4 opposite to the substrate 21 (ie, the upper surface) and the surface of the semiconductor element 3 opposite to the substrate 21 (ie, the upper surface) are located on the same surface. Thereby, the curvature of the wiring board 2 can be effectively suppressed or prevented while the semiconductor package 1 is thinned. Moreover, when providing another structure (for example, a board | substrate, a semiconductor element, a heat sink, etc.) on the upper surface of the 1st reinforcement member 4, the installation of the structure can be performed stably.
The first reinforcing member 4 and the semiconductor element 3 may be molded with a sealing resin.
　また、第１補強部材４は、半導体素子３の周囲を囲むように設けられている。本実施形態では、図２に示すように、第１補強部材４は、半導体素子３を囲むように環状（より具体的には四角環状）をなしている。これにより、第１補強部材４による配線基板２の剛性を高める効果を優れたものとすることができる。 The first reinforcing member 4 is provided so as to surround the periphery of the semiconductor element 3. In the present embodiment, as shown in FIG. 2, the first reinforcing member 4 has an annular shape (more specifically, a rectangular annular shape) so as to surround the semiconductor element 3. Thereby, the effect which raises the rigidity of the wiring board 2 by the 1st reinforcement member 4 can be made excellent.
　また、第１補強部材４は、半導体素子３との間の距離（第１補強部材４の内周面４１と半導体素子３の外周面３３との間の距離）が半導体素子３の全周に亘って一定となるように形成されている。これにより、第１補強部材４および半導体素子３の一体性が増し、これらによる配線基板２の補強効果が好適に発揮される。また、後述する熱伝導性材料６を介した半導体素子３から第１補強部材への伝熱を効率的かつ均一に生じさせることができる。 Further, the distance between the first reinforcing member 4 and the semiconductor element 3 (the distance between the inner peripheral surface 41 of the first reinforcing member 4 and the outer peripheral surface 33 of the semiconductor element 3) is on the entire circumference of the semiconductor element 3. It is formed so as to be constant throughout. Thereby, the integrity of the 1st reinforcement member 4 and the semiconductor element 3 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably. In addition, heat transfer from the semiconductor element 3 to the first reinforcing member via the heat conductive material 6 described later can be generated efficiently and uniformly.
　また、第１補強部材４は、半導体素子３との熱膨張係数差が７ｐｐｍ／℃以下であるのが好ましい。これにより、半導体素子３および第１補強部材４が一体的に配線基板２を補強し、半導体パッケージ１全体の熱膨張を抑えることができる。 Moreover, it is preferable that the first reinforcing member 4 has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the semiconductor element 3 and the 1st reinforcement member 4 can reinforce the wiring board 2 integrally, and can suppress the thermal expansion of the semiconductor package 1 whole.
　また、第１補強部材４の構成材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、例えば、金属材料、セラミックス材料等を用いることができるが、金属材料を用いるのが好ましい。第１補強部材４が金属材料で構成されていると、第１補強部材４の放熱性を高めることができる。その結果、半導体パッケージ１の放熱性を向上させることができる。 In addition, the constituent material of the first reinforcing member 4 is not particularly limited as long as it has a thermal expansion coefficient as described above. For example, a metal material, a ceramic material, or the like can be used. It is preferable to use it. When the 1st reinforcement member 4 is comprised with the metal material, the heat dissipation of the 1st reinforcement member 4 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
　かかる金属材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、各種金属材料を用いることができるが、放熱性および低熱膨張を実現する観点から、Ｆｅを含む合金を用いるのが好ましい。 Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
　かかるＦｅを含む合金としては、例えば、Ｆｅ－Ｎｉ系合金、Ｆｅ－Ｃｏ－Ｃｒ系合金、Ｆｅ－Ｃｏ系合金、Ｆｅ－Ｐｔ系合金、Ｆｅ－Ｐｄ合金等が挙げられ、特に、Ｆｅ－Ｎｉ系合金を用いるのが好ましい。 Examples of such alloys containing Fe include Fe—Ni alloys, Fe—Co—Cr alloys, Fe—Co alloys, Fe—Pt alloys, Fe—Pd alloys, and the like. It is preferable to use a base alloy.
　このような金属材料は、放熱性に優れるだけでなく、熱膨張係数が低く、かつ、一般的な半導体素子３の熱膨張係数に近い熱膨張係数を有する。そのため、半導体素子３および第１補強部材４が一体的に配線基板２を補強することができる。 Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the semiconductor element 3 and the first reinforcing member 4 can integrally reinforce the wiring board 2.
　Ｆｅ－Ｎｉ系合金としては、ＦｅおよびＮｉを含むものであれば、特に限定されず、ＦｅおよびＮｉの他に、残部（Ｍ）として、Ｃｏ、Ｔｉ、Ｍｏ、Ｃｒ、Ｐｄ、Ｐｔ等の金属のうちの１種または２種以上の金属を含んでいてもよい。 The Fe—Ni alloy is not particularly limited as long as it contains Fe and Ni. In addition to Fe and Ni, the balance (M) is a metal such as Co, Ti, Mo, Cr, Pd, and Pt. Of these, one or more metals may be included.
　より具体的には、Ｆｅ－Ｎｉ系合金としては、例えば、Ｆｅ－３６Ｎｉ合金（インバー）等のＦｅ－Ｎｉ合金、Ｆｅ－３２Ｎｉ－５Ｃｏ合金（スーパーインバー）、Ｆｅ－２９Ｎｉ－１７Ｃｏ合金（コバール）、Ｆｅ－３６Ｎｉ－１２Ｃｏ合金（エリンバー）等のＦｅ－Ｎｉ－Ｃｏ合金、Ｆｅ－Ｎｉ－Ｃｒ－Ｔｉ合金、Ｎｉ－２８Ｍｏ－２Ｆｅ合金等のＮｉ－Ｍｏ－Ｆｅ合金等が挙げられる。また、Ｆｅ－Ｎｉ－Ｃｏ合金は、例えば、ＫＶ－２、ＫＶ－４、ＫＶ－６、ＫＶ－１５、ＫＶ－２５等のＫＶシリーズ（ＮＥＯＭＡＸマテリアル社製）、Ｎｉｖａｒｏｘ等の商品名で市販されている。また、Ｆｅ－Ｎｉ合金は、例えば、ＮＳ－５、Ｄ－１（ＮＥＯＭＡＸマテリアル社製）等の商品名で市販されている。また、Ｆｅ－Ｎｉ－Ｃｒ－Ｔｉ合金は、例えば、Ｎｉ－Ｓｐａｎ　Ｃ－９０２(大同スペシャルメタル社製)、ＥＬ－３(ＮＥＯＭＡＸマテリアル社製)等の商品名で市販されている。 More specifically, examples of Fe—Ni alloys include Fe—Ni alloys such as Fe-36Ni alloy (Invar), Fe-32Ni-5Co alloy (Super Invar), and Fe-29Ni-17Co alloy (Kovar). Fe-Ni-Co alloys such as Fe-36Ni-12Co alloy (Erin bar), Ni-Mo-Fe alloys such as Fe-Ni-Cr-Ti alloy and Ni-28Mo-2Fe alloy. In addition, Fe—Ni—Co alloys are commercially available under trade names such as KV series (manufactured by NEOMAX Materials) such as KV-2, KV-4, KV-6, KV-15, KV-25, and Nivarox. ing. In addition, Fe—Ni alloys are commercially available under trade names such as NS-5 and D-1 (manufactured by NEOMAX Materials). Fe-Ni-Cr-Ti alloys are commercially available under trade names such as Ni-Span C-902 (manufactured by Daido Special Metal Co., Ltd.), EL-3 (manufactured by NEOMAX Material Co., Ltd.), and the like.
　また、Ｆｅ－Ｃｏ－Ｃｒ系合金としては、Ｆｅ、ＣｏおよびＣｒを含むものであれば、特に限定されないが、例えば、Ｆｅ－５４Ｃｏ－９．５Ｃｒ（ステンレスインバー）等のＦｅ－Ｃｏ－Ｃｒ合金が挙げられる。なお、Ｆｅ－Ｃｏ－Ｃｒ系合金は、Ｆｅ、ＣｏおよびＣｒの他に、Ｎｉ、Ｔｉ、Ｍｏ、Ｐｄ、Ｐｔ等の金属のうちの１種または２種以上の金属を含んでいてもよい。 The Fe—Co—Cr alloy is not particularly limited as long as it contains Fe, Co, and Cr. For example, an Fe—Co—Cr alloy such as Fe-54Co-9.5Cr (stainless invar) is used. Is mentioned. Note that the Fe—Co—Cr-based alloy may contain one or more metals of metals such as Ni, Ti, Mo, Pd, and Pt in addition to Fe, Co, and Cr.
　また、Ｆｅ－Ｃｏ系合金としては、ＦｅおよびＣｏを含むものであれば、特に限定されず、ＦｅおよびＣｏの他に、Ｎｉ、Ｔｉ、Ｍｏ、Ｃｒ、Ｐｄ、Ｐｔ等の金属のうちの１種または２種以上の金属を含んでいてもよい。 The Fe—Co alloy is not particularly limited as long as it contains Fe and Co. In addition to Fe and Co, one of metals such as Ni, Ti, Mo, Cr, Pd, and Pt is used. It may contain seeds or two or more metals.
　また、Ｆｅ－Ｐｔ系合金としては、ＦｅおよびＰｔを含むものであれば、特に限定されず、ＦｅおよびＰｔの他に、Ｃｏ、Ｎｉ、Ｔｉ、Ｍｏ、Ｃｒ、Ｐｄ等の金属のうちの１種または２種以上の金属を含んでいてもよい。 The Fe—Pt alloy is not particularly limited as long as it contains Fe and Pt. In addition to Fe and Pt, one of metals such as Co, Ni, Ti, Mo, Cr, and Pd is used. It may contain seeds or two or more metals.
　また、Ｆｅ－Ｐｄ系合金としては、ＦｅおよびＰｄを含むものであれば、特に限定されず、ＦｅおよびＰｄの他に、Ｃｏ、Ｎｉ、Ｔｉ、Ｍｏ、Ｃｒ、Ｐｔ等の金属のうちの１種または２種以上の金属を含んでいてもよい。 The Fe—Pd alloy is not particularly limited as long as it contains Fe and Pd. In addition to Fe and Pd, one of metals such as Co, Ni, Ti, Mo, Cr, and Pt is used. It may contain seeds or two or more metals.
　特に、第１補強部材４の熱膨張係数は、０．５ｐｐｍ／℃以上１０ｐｐｍ／℃以下であるのが好ましく、１ｐｐｍ／℃以上７ｐｐｍ／℃以下であるのがより好ましく、１ｐｐｍ／℃以上５ｐｐｍ／℃以下であるのがさらに好ましい。これにより、半導体素子３と第１補強部材４との熱膨張係数差を小さくし、これらが一体として配線基板２を補強することができる。そのため、配線基板２の反りを効果的に防止することができる。 In particular, the thermal expansion coefficient of the first reinforcing member 4 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
　また、第１補強部材４と半導体素子３との熱膨張係数差の絶対値は、７ｐｐｍ／℃以下であるのが好ましく、５ｐｐｍ／℃以下であるのがより好ましく、２ｐｐｍ／℃以下であるのがさらに好ましい。これにより、半導体素子３と第１補強部材４との熱膨張係数差を小さくし、これらが一体として配線基板２を補強することができる。そのため、配線基板２の反りを効果的に防止することができる。 The absolute value of the difference in thermal expansion coefficient between the first reinforcing member 4 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the first reinforcing member 4 can be reduced, and these can integrally reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
　上述したような熱膨張係数の観点から、第１補強部材４を構成する金属材料がＦｅ－Ｎｉ系合金である場合、前記Ｆｅ－Ｎｉ系合金は、Ｎｉの含有量が３０ｗｔ％以上５０ｗｔ％以下であるのが好ましく、Ｎｉの含有量が３５ｗｔ％以上４５ｗｔ％以下であるのがより好ましい。これにより、第１補強部材４の熱膨張係数を半導体素子３の熱膨張係数に近づけることができる。この場合、前記Ｆｅ－Ｎｉ系合金は、Ｆｅの含有量が５０ｗｔ％以上７０ｗｔ％以下であるのが好ましく、Ｆｅの含有量が５５ｗｔ％以上６５ｗｔ％以下であるのがより好ましい。 From the viewpoint of the thermal expansion coefficient as described above, when the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
　また、第１補強部材４を構成する金属材料がＦｅ－Ｎｉ系合金である場合、前記Ｆｅ－Ｎｉ系合金は、ＦｅおよびＮｉの合計含有量が８５ｗｔ％以上１００ｗｔ％以下であるのが好ましく、ＦｅおよびＮｉの合計含有量が９０ｗｔ％以上１００ｗｔ％以下であるのがより好ましい。すなわち、前記Ｆｅ－Ｎｉ系合金は、残部（Ｍ）の含有量が０ｗｔ％以上１５ｗｔ％以下であるのが好ましく、残部（Ｍ）の含有量が０ｗｔ％以上１０ｗｔ％以下であるのがより好ましい。これにより、第１補強部材４の熱膨張係数を半導体素子３の熱膨張係数に近づけることができる。 When the metal material constituting the first reinforcing member 4 is an Fe—Ni alloy, the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less, The total content of Fe and Ni is more preferably 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the first reinforcing member 4 can be brought close to the thermal expansion coefficient of the semiconductor element 3.
　また、第１補強部材４の平均厚さは、配線基板２の熱膨張係数、配線基板２の第１補強部材４および第２補強部材５の形状、大きさ、構成材料等に応じて決められるものであり、特に限定されないが、例えば、０．０２ｍｍ以上０．８ｍｍ以下程度である。 The average thickness of the first reinforcing member 4 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.
　また、熱放散性の観点から、第１補強部材４の表面が粗化されていてもよい。第１補強部材４表面が粗化されていれば、表面積が増大し熱放散の効率が上がる。第１補強部材４表面の粗化方法は、特に限定されず、例えば化学的な薬液処理、機械的なサンドブラスト処理などにより実施することができる。 Moreover, from the viewpoint of heat dissipation, the surface of the first reinforcing member 4 may be roughened. If the surface of the first reinforcing member 4 is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the first reinforcing member 4 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.
　第１補強部材４の表面粗度の大きさは、半導体素子３の発熱量、樹脂材料の構成、基板２１の構成、第１補強部材４の形状、大きさ等に応じて決められるものであり、特に限定されないが、例えば、算術平均で表される表面粗度が０．１μｍ以上１００μｍ以下程度である。前記算術平均で表される表面粗度は、例えばＪＩＳ　Ｂ　０６０１に準じて測定することができる。 The magnitude of the surface roughness of the first reinforcing member 4 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the first reinforcing member 4, and the like. Although not particularly limited, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.
　また、樹脂材料との密着性向上の観点から、第１補強部材４表面に銅皮膜が形成されていてもよい。銅については、樹脂材料との密着強度を向上させるための表面処理技術が数多く知られているため、第１補強部材４の形状、大きさ、樹脂材料の種類等に応じてその表面処理を適宜選択し、実施することができる。 In addition, a copper film may be formed on the surface of the first reinforcing member 4 from the viewpoint of improving the adhesion with the resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately performed according to the shape, size, type of the resin material, and the like of the first reinforcing member 4. Can be selected and implemented.
　銅皮膜の形成方法は、特に限定されないが、例えば、電解めっき、無電解めっき等のめっき処理、スパッタ処理等により実施することができる。 The method for forming the copper film is not particularly limited, and can be performed by, for example, plating treatment such as electrolytic plating or electroless plating, sputtering treatment, or the like.
　また、銅皮膜の平均厚さは、第１補強部材４の熱膨張係数に影響を及ぼさず、密着性向上の表面処理が可能な範囲で薄い方が好ましい。 Further, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the first reinforcing member 4 and capable of surface treatment for improving adhesion.
　また、本実施形態では、図１および図２に示すように、第１補強部材４と半導体素子３との間に、熱伝導性材料６が充填されている。これにより、半導体素子３から熱伝導性材料６を介して第１補強部材４へ効率的に熱を伝達することができる。その結果、半導体パッケージ１の放熱性を向上させることができる。 In this embodiment, as shown in FIGS. 1 and 2, a heat conductive material 6 is filled between the first reinforcing member 4 and the semiconductor element 3. Thereby, heat can be efficiently transferred from the semiconductor element 3 to the first reinforcing member 4 through the heat conductive material 6. As a result, the heat dissipation of the semiconductor package 1 can be improved.
　このような熱伝導性材料６としては、特に限定されないが、無機フィラーおよび樹脂材料を含んで構成された樹脂組成物が挙げられる。 Such a heat conductive material 6 is not particularly limited, and examples thereof include a resin composition including an inorganic filler and a resin material.
　熱伝導性材料６（樹脂組成物）に用いる無機フィラー（無機充填材）としては、例えば、Ａｕ、Ａｇ、Ｐｔ等の金属、シリカ、アルミナ、ケイ藻土、酸化チタン、酸化鉄、酸化亜鉛、酸化マグネシウム、金属フェライト等の酸化物、窒化ホウ素、窒化ケイ素、窒化ガリウム、窒化チタン等の窒化物、水酸化アルミニウム、水酸化マグネシウム等の水酸化物、炭酸カルシウム（軽質、重質）、炭酸マグネシウム、ドロマイト、ドーソナイト等の炭酸塩、硫酸カルシウム、硫酸バリウム、硫酸アンモニウム、亜硫酸カルシウム等の硫酸塩または亜硫酸塩、タルク、マイカ、クレー、ガラス繊維、ケイ酸カルシウム、モンモリロナイト、ベントナイト等のケイ酸塩、ホウ酸亜鉛、メタホウ酸バリウム、ホウ酸アルミニウム、ホウ酸カルシウム、ホウ酸ナトリウム等のホウ酸塩、カーボンブラック、グラファイト、炭素繊維等の炭素、その他鉄粉、銅粉、アルミニウム粉、亜鉛華、硫化モリブデン、ボロン繊維、チタン酸カリウム、チタン酸ジルコン酸鉛が挙げられる。なお、無機フィラーとして導電性を有するものを用いた場合、必要に応じて、熱伝導性材料６の接する部位に絶縁処理を施す。 Examples of the inorganic filler (inorganic filler) used in the heat conductive material 6 (resin composition) include metals such as Au, Ag, and Pt, silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, Oxides such as magnesium oxide and metal ferrite, nitrides such as boron nitride, silicon nitride, gallium nitride, and titanium nitride, hydroxides such as aluminum hydroxide and magnesium hydroxide, calcium carbonate (light and heavy), magnesium carbonate Carbonates such as dolomite and dosonite, sulfates or sulfites such as calcium sulfate, barium sulfate, ammonium sulfate and calcium sulfite, talc, mica, clay, glass fiber, silicates such as calcium silicate, montmorillonite and bentonite, boron Zinc oxide, barium metaborate, aluminum borate, calcium borate, Borate such as sodium acid, carbon black, graphite, carbon such as carbon fiber, other iron powder, copper powder, aluminum powder, zinc white, molybdenum sulfide, boron fiber, potassium titanate, lead zirconate titanate . In addition, when what has electroconductivity as an inorganic filler is used, the insulation process is performed to the site | part which the heat conductive material 6 contacts as needed.
　中でも、前記無機フィラーとしては、絶縁性および熱伝導性に優れるという観点から、シリカ、アルミナ、ケイ藻土、酸化チタン、酸化鉄、酸化亜鉛、酸化マグネシウム、金属フェライト等の酸化物、窒化ホウ素、窒化ケイ素、窒化ガリウム、窒化チタン等の窒化物が好ましい。 Among these, as the inorganic filler, from the viewpoint of excellent insulation and thermal conductivity, oxides such as silica, alumina, diatomaceous earth, titanium oxide, iron oxide, zinc oxide, magnesium oxide, metal ferrite, boron nitride, Nitride such as silicon nitride, gallium nitride and titanium nitride is preferable.
　また、熱伝導性材料６（樹脂組成物）に用いる樹脂材料としては、各種熱可塑性樹脂、各種熱硬化性樹脂が挙げられる。 Also, examples of the resin material used for the heat conductive material 6 (resin composition) include various thermoplastic resins and various thermosetting resins.
　熱伝導性材料６（樹脂組成物）に用いる熱可塑性樹脂としては、例えば、ポリエチレン、ポリプロピレン、エチレン－酢酸ビニル共重合体等のポリオレフィン、変性ポリオレフィン、ポリアミド（例：ナイロン６、ナイロン４６、ナイロン６６、ナイロン６１０、ナイロン６１２、ナイロン１１、ナイロン１２、ナイロン６－１２、ナイロン６－６６）、熱可塑性ポリイミド、芳香族ポリエステル等の液晶ポリマー、ポリフェニレンオキシド、ポリフェニレンサルファイド、ポリカーボネート、ポリメチルメタクリレート、ポリエーテル、ポリエーテルエーテルケトン、ポリエーテルイミド、ポリアセタール、スチレン系、ポリオレフィン系、ポリ塩化ビニル系、ポリウレタン系、ポリエステル系、ポリアミド系、ポリブタジエン系、トランスポリイソプレン系、フッ素ゴム系、塩素化ポリエチレン系等の各種熱可塑性エラストマー等、またはこれらを主とする共重合体、ブレンド体、ポリマーアロイ等が挙げられ、これらのうちの１種または２種以上を混合して用いることができる。 Examples of the thermoplastic resin used for the thermally conductive material 6 (resin composition) include polyolefins such as polyethylene, polypropylene, and ethylene-vinyl acetate copolymer, modified polyolefins, polyamides (eg, nylon 6, nylon 46, nylon 66). , Nylon 610, Nylon 612, Nylon 11, Nylon 12, Nylon 6-12, Nylon 6-66), Thermoplastic polyimide, Liquid crystalline polymer such as aromatic polyester, Polyphenylene oxide, Polyphenylene sulfide, Polycarbonate, Polymethyl methacrylate, Polyether , Polyether ether ketone, polyether imide, polyacetal, styrene, polyolefin, polyvinyl chloride, polyurethane, polyester, polyamide, polybutadiene, Examples include various thermoplastic elastomers such as polyisoprene, fluororubber, and chlorinated polyethylene, and copolymers, blends, and polymer alloys mainly composed of these, one or two of these The above can be mixed and used.
　また、熱伝導性材料６（樹脂組成物）に用いる熱硬化性樹脂としては、例えば、エポキシ樹脂、フェノール樹脂、ユリア樹脂、メラミン樹脂、ポリエステル（不飽和ポリエステル）樹脂、ポリイミド樹脂、シリコーン樹脂、ポリウレタン樹脂等が挙げられ、これらのうちの１種または２種以上を混合して用いることができる。 Moreover, as a thermosetting resin used for the heat conductive material 6 (resin composition), for example, epoxy resin, phenol resin, urea resin, melamine resin, polyester (unsaturated polyester) resin, polyimide resin, silicone resin, polyurethane Resins etc. are mentioned, 1 type or 2 types or more of these can be mixed and used.
　中でも、熱伝導性材料６（樹脂組成物）に用いる樹脂材料としては、熱硬化性樹脂（特に硬化前に液状をなすもの）を用いるのが好ましく、フェノール樹脂、エポキシ樹脂を用いるのがより好ましく、フェノール樹脂を用いるのが特に好ましい。これにより、熱伝導性材料６を第１補強部材４と半導体素子３との間に隙間なく充填できるとともに、熱伝導性材料６の熱膨張係数を効果的に抑えることができる。 Among these, as the resin material used for the heat conductive material 6 (resin composition), it is preferable to use a thermosetting resin (particularly, a liquid that forms a liquid before curing), more preferably a phenol resin or an epoxy resin. It is particularly preferable to use a phenol resin. Thereby, the thermal conductive material 6 can be filled between the first reinforcing member 4 and the semiconductor element 3 without a gap, and the thermal expansion coefficient of the thermal conductive material 6 can be effectively suppressed.
　かかるフェノール樹脂としては、フェノールノボラック樹脂、クレゾールノボラック樹脂、ビスフェノールＡノボラック樹脂等のノボラック型フェノール樹脂、未変性のレゾールフェノール樹脂、桐油、アマニ油、クルミ油等で変性した油変性レゾールフェノール樹脂等のレゾール型フェノール樹脂等のフェノール樹脂等が挙げられる。 Examples of such phenolic resins include phenol novolac resins, cresol novolac resins, novolac type phenol resins such as bisphenol A novolac resins, unmodified resole phenol resins, oil-modified resole phenol resins modified with paulownia oil, linseed oil, walnut oil, etc. Examples thereof include phenolic resins such as resol type phenolic resins.
　また、この熱伝導性材料６は、前述した接着層３２（アンダーフィル材）と同様のものを用いてもよく、また、熱伝導性材料６および接着層３２を一括して形成することもできる。 In addition, the heat conductive material 6 may be the same as the adhesive layer 32 (underfill material) described above, and the heat conductive material 6 and the adhesive layer 32 may be formed in a lump. .
　［第２補強部材］
　第２補強部材（スティフナー）５は、配線基板２の基板２１の下面（他方の面）に接合されている。 [Second reinforcing member]
The second reinforcing member (stiffener) 5 is joined to the lower surface (the other surface) of the substrate 21 of the wiring substrate 2.
　この第２補強部材５は、例えば、接着剤を介して基板２１の下面に接合されている。これにより、第２補強部材５の設置が簡単となる。 The second reinforcing member 5 is bonded to the lower surface of the substrate 21 through an adhesive, for example. Thereby, installation of the 2nd reinforcement member 5 becomes easy.
　かかる接着剤としては、接着機能を有するものであれば、特に限定されず、各種接着剤を用いることができるが、熱伝導性に優れたものが好ましく、前述した熱伝導性材料６と同様のものを用いることができる。 Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used. However, an adhesive excellent in thermal conductivity is preferable, and is the same as the above-described thermal conductive material 6. Things can be used.
　この第２補強部材５は、前述した第１補強部材４と同様、基板２１よりも熱膨張係数が小さい。 The second reinforcing member 5 has a smaller thermal expansion coefficient than that of the substrate 21 as in the first reinforcing member 4 described above.
　第２補強部材５は、板状をなしている。これにより、第２補強部材５の構成を簡単かつ小型なものとすることができる。 The second reinforcing member 5 has a plate shape. Thereby, the structure of the 2nd reinforcement member 5 can be made simple and small.
　また、第２補強部材５は、図１および３に示されるように、配線基板２（基板２１）の外周部（導体パターン２２４よりも外側）に沿って設けられた部分（枠部）５２と、金属バンプ７１同士の間に設けられた部分５３とを有している。第２補強部材５の部分５２と配線基板２（基板２１）との接合により、第２補強部材５が配線基板２を効果的に補強することができる。また、第２補強部材５の部分５３と配線基板２との接合により、第２補強部材５の剛性が高められる。 Further, as shown in FIGS. 1 and 3, the second reinforcing member 5 includes a portion (frame portion) 52 provided along the outer peripheral portion (outside the conductor pattern 224) of the wiring substrate 2 (substrate 21). And a portion 53 provided between the metal bumps 71. By joining the portion 52 of the second reinforcing member 5 and the wiring substrate 2 (substrate 21), the second reinforcing member 5 can effectively reinforce the wiring substrate 2. Further, the rigidity of the second reinforcing member 5 is increased by joining the portion 53 of the second reinforcing member 5 and the wiring board 2.
　より具体的に説明すると、第２補強部材５は、前述した各金属バンプ７１に非接触で各金属バンプ７１を囲むように形成された複数の開口部５１を有する。これにより、第２補強部材５が配線基板２の下面に占める面積の割合を大きくすることができる。その結果、第２補強部材５による配線基板２の剛性を高める効果を優れたものとすることができる。 More specifically, the second reinforcing member 5 has a plurality of openings 51 formed so as to surround each metal bump 71 in a non-contact manner with each metal bump 71 described above. Thereby, the ratio of the area which the 2nd reinforcement member 5 occupies for the lower surface of the wiring board 2 can be enlarged. As a result, the effect of increasing the rigidity of the wiring board 2 by the second reinforcing member 5 can be made excellent.
　本実施形態では、各開口部５１は、平面視にて、円形をなしている。なお、各開口部５１の平面視形状は、これに限定されず、例えば、楕円形、多角形等であってもよい。 In the present embodiment, each opening 51 is circular in plan view. In addition, the planar view shape of each opening part 51 is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
　また、各開口部５１は、第２補強部材５の形成領域（外周縁で囲まれた領域）内において、各金属バンプ７１に対応して（一対一で対応して）設けられている。これにより、第２補強部材５の剛性の均一化を図ることができる。また、第２補強部材５の放熱性も向上させることができる。 Further, each opening 51 is provided corresponding to each metal bump 71 (corresponding one-to-one) in the formation region (region surrounded by the outer peripheral edge) of the second reinforcing member 5. Thereby, the rigidity of the second reinforcing member 5 can be made uniform. Moreover, the heat dissipation of the 2nd reinforcement member 5 can also be improved.
　また、第２補強部材５は、各金属バンプ７１との間の距離（平面視における開口部５１の壁面と金属バンプ７１の外周面との間の距離）が金属バンプ７１の全周に亘って一定となるように形成されている。これにより、第２補強部材５および各金属バンプ７１の一体性が増し、これらによる配線基板２の補強効果が好適に発揮される。 In addition, the distance between the second reinforcing member 5 and each metal bump 71 (distance between the wall surface of the opening 51 and the outer peripheral surface of the metal bump 71 in plan view) extends over the entire circumference of the metal bump 71. It is formed to be constant. Thereby, the integrity of the 2nd reinforcement member 5 and each metal bump 71 increases, and the reinforcement effect of the wiring board 2 by these is exhibited suitably.
　本実施形態では、第２補強部材５の下面に、伝熱バンプ９１が設けられていてもよい。
　この伝熱バンプ９１は、配線基板２の基板２１よりも高い熱伝導性を有し、例えば、後述する半導体装置１００において、マザーボード２００に接合されるものである。これにより、第２補強部材５の熱を外部（例えばマザーボード２００）に逃がすことができる。 In the present embodiment, heat transfer bumps 91 may be provided on the lower surface of the second reinforcing member 5.
The heat transfer bump 91 has higher thermal conductivity than the substrate 21 of the wiring board 2 and is bonded to the mother board 200 in the semiconductor device 100 described later, for example. Thereby, the heat of the 2nd reinforcement member 5 can be escaped outside (for example, motherboard 200).
　伝熱バンプ９１の構成材料としては、前述したような伝熱性を有するものであれば、特に限定されず、金属材料、樹脂材料を用いることができるが、特に、前述した金属バンプ７１と同様の構成材料、無機フィラーおよび樹脂材料を含有する伝熱性接着剤等を用いるのが好ましい。これにより、伝熱バンプ９１が優れた伝熱性を発揮することができるとともに、伝熱バンプ９１を配線基板２をマザーボード２００に固定する接着剤としても有効活用することができる。 The constituent material of the heat transfer bump 91 is not particularly limited as long as it has the heat transfer property as described above, and a metal material or a resin material can be used. It is preferable to use a heat conductive adhesive containing a constituent material, an inorganic filler, and a resin material. Thereby, the heat transfer bump 91 can exhibit excellent heat transfer properties, and the heat transfer bump 91 can be effectively used as an adhesive for fixing the wiring board 2 to the mother board 200.
　また、前述した第１補強部材４と同様、第２補強部材５は、半導体素子３との熱膨張係数差が７ｐｐｍ／℃以下であるのが好ましい。これにより、第２補強部材５が効果的に配線基板２を補強し、半導体パッケージ１全体の熱膨張を抑えることができる。 Further, similarly to the first reinforcing member 4 described above, the second reinforcing member 5 preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the 2nd reinforcement member 5 can reinforce the wiring board 2 effectively, and can suppress the thermal expansion of the semiconductor package 1 whole.
　また、第２補強部材５の構成材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、前述した第１補強部材４の構成材料と同様のものを用いることができ、例えば、金属材料、セラミックス材料等を用いることができるが、金属材料で構成されているのが好ましい。第２補強部材５が金属材料で構成されていると、第２補強部材５の放熱性を高めることができる。その結果、半導体パッケージ１の放熱性を向上させることができる。 The constituent material of the second reinforcing member 5 is not particularly limited as long as it has a thermal expansion coefficient as described above, and the same constituent material as that of the first reinforcing member 4 described above may be used. For example, although a metal material, a ceramic material, etc. can be used, it is preferable to be comprised with the metal material. When the 2nd reinforcement member 5 is comprised with the metal material, the heat dissipation of the 2nd reinforcement member 5 can be improved. As a result, the heat dissipation of the semiconductor package 1 can be improved.
　かかる金属材料としては、特に限定されないが、放熱性および低熱膨張を実現する観点から、前述した第１補強部材４と同様に、Ｆｅを含む合金、例えば、Ｆｅ－Ｎｉ系合金、Ｆｅ－Ｃｏ－Ｃｒ系合金、Ｆｅ－Ｃｏ系合金、Ｆｅ－Ｐｔ系合金、Ｆｅ－Ｐｄ合金等を用いるのが好ましく、Ｆｅ－Ｎｉ系合金を用いるのがより好ましい。 Such a metal material is not particularly limited, but from the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe, for example, an Fe—Ni alloy, Fe—Co—, in the same manner as the first reinforcing member 4 described above. It is preferable to use a Cr alloy, a Fe—Co alloy, a Fe—Pt alloy, a Fe—Pd alloy, or the like, and it is more preferable to use a Fe—Ni alloy.
　Ｆｅ－Ｎｉ系合金としては、前述した第１補強部材４と同様のものを用いることができる。 As the Fe—Ni alloy, the same material as the first reinforcing member 4 described above can be used.
　特に、第２補強部材５の熱膨張係数は、０．５ｐｐｍ／℃以上１０ｐｐｍ／℃以下であるのが好ましく、１ｐｐｍ／℃以上７ｐｐｍ／℃以下であるのがより好ましく、１ｐｐｍ／℃以上５ｐｐｍ／℃以下であるのがさらに好ましい。これにより、半導体素子３と第２補強部材５との熱膨張係数差を小さくし、第２補強部材５が配線基板２を効果的に補強することができる。そのため、配線基板２の反りを効果的に防止することができる。 In particular, the thermal expansion coefficient of the second reinforcing member 5 is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and 1 ppm / ° C. or more and 5 ppm / ° C. or less. More preferably, it is not higher than ° C. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
　また、第２補強部材５と半導体素子３との熱膨張係数差の絶対値は、７ｐｐｍ／℃以下であるのが好ましく、５ｐｐｍ／℃以下であるのがより好ましく、２ｐｐｍ／℃以下であるのがさらに好ましい。これにより、半導体素子３と第２補強部材５との熱膨張係数差を小さくし、第２補強部材５が配線基板２を効果的に補強することができる。そのため、配線基板２の反りを効果的に防止することができる。 The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and 2 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the second reinforcing member 5 can be reduced, and the second reinforcing member 5 can effectively reinforce the wiring board 2. Therefore, warping of the wiring board 2 can be effectively prevented.
　また、第２補強部材５と第１補強部材４との熱膨張係数差の絶対値は、２ｐｐｍ／℃以下であるのが好ましく、１ｐｐｍ／℃以下であるのがより好ましく、０ｐｐｍ／℃であるのがさらに好ましい。これにより、第１補強部材４と第２補強部材５との熱膨張係数差を小さくし、これらの熱膨張差に起因する配線基板２の反りを防止することができる。 The absolute value of the difference in thermal expansion coefficient between the second reinforcing member 5 and the first reinforcing member 4 is preferably 2 ppm / ° C. or less, more preferably 1 ppm / ° C. or less, and 0 ppm / ° C. Is more preferable. Thereby, the thermal expansion coefficient difference of the 1st reinforcement member 4 and the 2nd reinforcement member 5 can be made small, and the curvature of the wiring board 2 resulting from these thermal expansion differences can be prevented.
　このような観点から、第２補強部材５の構成材料は、第１補強部材４の構成材料と同種または同じであるのが好ましい。 From such a viewpoint, the constituent material of the second reinforcing member 5 is preferably the same or the same as the constituent material of the first reinforcing member 4.
　また、第２補強部材５の平均厚さは、配線基板２の熱膨張係数、配線基板２の第１補強部材４および第２補強部材５の形状、大きさ、構成材料等に応じて決められるものであり、特に限定されないが、例えば、０．０２ｍｍ以上０．８ｍｍ以下程度である。 The average thickness of the second reinforcing member 5 is determined according to the thermal expansion coefficient of the wiring board 2, the shape, size, constituent material, and the like of the first reinforcing member 4 and the second reinforcing member 5 of the wiring board 2. Although it is a thing and is not specifically limited, For example, it is about 0.02 mm or more and 0.8 mm or less.
　また、熱放散性の観点から、第２補強部材５の表面が粗化されていてもよい。第２補強部材５表面が粗化されていれば、表面積が増大し熱放散の効率が上がる。第２補強部材５表面の粗化方法は、特に限定されず、例えば化学的な薬液処理、機械的なサンドブラスト処理などにより実施することができる。 Further, from the viewpoint of heat dissipation, the surface of the second reinforcing member 5 may be roughened. If the surface of the second reinforcing member 5 is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the second reinforcing member 5 is not particularly limited, and can be performed by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.
　第２補強部材５の表面粗度の大きさは、半導体素子３の発熱量、樹脂材料の構成、基板２１の構成、第２補強部材５の形状、大きさ等に応じて決められるものであり、特に限定されないが、例えば、算術平均で表される表面粗度が０．１μｍ以上１００μｍ以下程度である。前記算術平均で表される表面粗度は、例えばＪＩＳ　Ｂ　０６０１に準じて測定することができる。 The magnitude of the surface roughness of the second reinforcing member 5 is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the substrate 21, the shape and size of the second reinforcing member 5, and the like. Although not particularly limited, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.
　また、樹脂材料との密着性向上の観点から、第２補強部材５表面に銅皮膜が形成されていてもよい。銅については、樹脂材料との密着強度を向上させるための表面処理技術が数多く知られているため、補強部材の形状、大きさ、樹脂材料の種類等に応じてその表面処理を適宜選択し、実施することができる。 Moreover, a copper film may be formed on the surface of the second reinforcing member 5 from the viewpoint of improving the adhesion with the resin material. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately selected according to the shape and size of the reinforcing member, the type of the resin material, etc. Can be implemented.
　銅皮膜の形成方法は、特に限定されないが、例えば、電解めっき、無電解めっき等のめっき処理、スパッタ処理等により実施することができる。 The method for forming the copper film is not particularly limited, and can be performed by, for example, plating treatment such as electrolytic plating or electroless plating, sputtering treatment, or the like.
　また、銅皮膜の平均厚さは、第２補強部材５の熱膨張係数に影響を及ぼさず、密着性向上の表面処理が可能な範囲で薄い方が好ましい。 Also, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the second reinforcing member 5 and allowing surface treatment for improving adhesion.
　また、第２補強部材５と各金属バンプ７１との間には、絶縁材８１が設けられている（充填されている）。これにより、第２補強部材５と各金属バンプ７１との接触を防止することができる。そのため、半導体パッケージ１の信頼性を優れたものとしつつ、第２補強部材５の剛性および放熱性を高めることができる。 Further, an insulating material 81 is provided (filled) between the second reinforcing member 5 and each metal bump 71. Thereby, the contact with the 2nd reinforcement member 5 and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the second reinforcing member 5 can be improved while improving the reliability of the semiconductor package 1.
　また、絶縁材８１は、金属バンプ７１の基板２１側の部分（上部）の周囲を囲むような形状をなし、かつ、各金属バンプ７１に接合されている。これにより、絶縁材８１は、金属バンプ７１を補強している。 Further, the insulating material 81 has a shape surrounding the periphery (upper part) of the metal bump 71 on the substrate 21 side, and is joined to each metal bump 71. Thereby, the insulating material 81 reinforces the metal bump 71.
　また、絶縁材８１は、前述した配線基板２の基板２１よりも高い熱伝導性を有するのが好ましい。これにより、金属バンプ７１と第２補強部材５の間の熱伝導性を優れたものとし、半導体パッケージ１の放熱性を向上させることができる。 The insulating material 81 preferably has higher thermal conductivity than the substrate 21 of the wiring board 2 described above. Thereby, the thermal conductivity between the metal bump 71 and the second reinforcing member 5 can be made excellent, and the heat dissipation of the semiconductor package 1 can be improved.
　このような絶縁材８１は、絶縁性を有し、樹脂材料を含んで構成されている。
　このような絶縁材８１は、特に限定されないが、例えば、熱硬化性を有する半田接合用樹脂により形成されるのが好ましい。 Such an insulating material 81 has an insulating property and includes a resin material.
Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a solder bonding resin having thermosetting properties.
　このような半田接合用樹脂（以下、「硬化性フラックス）とも言う）は、半田接合時にフラックスとして作用し、次いで加熱することにより、硬化して半田接合部の補強材として作用する。また、かかる半田接合用樹脂は、半田接合の際に、半田接合面および半田材料の酸化物などの有害物を除去し、半田接合面を保護するとともに、半田材料の精錬を行って、強度の大きい良好な接合を可能にする。さらに、半田接合用樹脂は、半田接合後に洗浄などにより除去する必要がなく、そのまま加熱することにより、三次元架橋した樹脂となり、半田接合部の補強材として作用する。 Such a solder bonding resin (hereinafter also referred to as “curing flux”) acts as a flux at the time of solder bonding, and then is cured by heating to act as a reinforcing material for the solder bonding portion. Solder bonding resin removes harmful substances such as solder joint surfaces and oxides of solder materials during solder joining, protects the solder joint surfaces, and refines the solder materials to provide good strength and good strength. In addition, the solder bonding resin does not need to be removed by washing after solder bonding, and is heated as it is to become a three-dimensionally crosslinked resin, which acts as a reinforcing material for the solder bonding portion.
　かかる半田接合用樹脂は、例えば、フェノール性ヒドロキシル基を有する樹脂（Ａ）および該樹脂の硬化剤（Ｂ）を含んで構成することができる。 Such a solder bonding resin can be configured to include, for example, a resin (A) having a phenolic hydroxyl group and a curing agent (B) of the resin.
　フェノール性ヒドロキシル基を有する樹脂（Ａ）としては、特に制限はないが、例えば、フェノールノボラック樹脂、アルキルフェノールノボラック樹脂、多価フェノールノボラック樹脂、レゾール樹脂、ポリビニルフェノール樹脂などを挙げることができる。 The resin (A) having a phenolic hydroxyl group is not particularly limited, and examples thereof include a phenol novolak resin, an alkylphenol novolak resin, a polyhydric phenol novolak resin, a resole resin, and a polyvinyl phenol resin.
　また、硬化性フラックスにおいて、フェノール性ヒドロキシル基を有する樹脂（Ａ）の含有量は、硬化性フラックス全体の２０～８０重量％であることが好ましく、２５～６０重量％であることがより好ましい。樹脂（Ａ）の含有量が２０重量％未満であると、半田および金属表面の酸化物などの汚れを除去する作用が低下し、半田接合性が不良となるおそれがある。樹脂（Ａ）の含有量が８０重量％を超えると、十分な物性を有する硬化物が得られず、接合強度と信頼性が低下するおそれがある。 Further, in the curable flux, the content of the resin (A) having a phenolic hydroxyl group is preferably 20 to 80% by weight, and more preferably 25 to 60% by weight of the entire curable flux. If the content of the resin (A) is less than 20% by weight, the effect of removing dirt such as solder and oxides on the metal surface may be reduced, and solder jointability may be deteriorated. When content of resin (A) exceeds 80 weight%, the hardened | cured material which has sufficient physical property cannot be obtained, and there exists a possibility that joining strength and reliability may fall.
　また、フェノール性ヒドロキシル基を有する樹脂（Ａ）のフェノール性ヒドロキシル基は、その還元作用により、半田および金属表面の酸化物などの汚れを除去するので、半田接合のフラックスとして効果的に作用する。 In addition, the phenolic hydroxyl group of the resin (A) having a phenolic hydroxyl group effectively removes dirt such as solder and oxide on the metal surface by its reducing action, and thus effectively acts as a solder joint flux.
　また、フェノール性ヒドロキシル基を有する樹脂（Ａ）の硬化剤（Ｂ）としては、例えば、エポキシ化合物、イソシアネート化合物などを挙げることができる。エポキシ化合物およびイソシアネート化合物としては、例えば、ビスフェノール系、フェノールノボラック系、アルキルフェノールノボラック系、ビフェノール系、ナフトール系、レゾルシノール系などのフェノールベースのエポキシ化合物、イソシアネート化合物や、飽和脂肪族、環状脂肪族、不飽和脂肪族などの骨格をベースとして変性されたエポキシ化合物、イソシアネート化合物などを挙げることができる。 Further, examples of the curing agent (B) of the resin (A) having a phenolic hydroxyl group include an epoxy compound and an isocyanate compound. Examples of the epoxy compound and isocyanate compound include phenol-based epoxy compounds such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, and resorcinol, isocyanate compounds, saturated aliphatic, cycloaliphatic, Examples thereof include an epoxy compound and an isocyanate compound modified based on a skeleton such as a saturated aliphatic group.
　また、硬化剤（Ｂ）の配合量は、硬化剤のエポキシ基、イソシアネート基などの反応性の官能基が、樹脂（Ａ）のフェノール性ヒドロキシル基の０．５～１．５当量倍であることが好ましく、０．８～１．２当量倍であることがより好ましい。硬化剤の反応性の官能基がヒドロキシル基の０．５当量倍未満であると、十分な物性を有する硬化物が得られず、補強効果が小さくなって、接合強度と信頼性が低下するおそれがある。硬化剤の反応性の官能基がヒドロキシル基の１．５当量倍を超えると、半田および金属表面の酸化物などの汚れを除去する作用が低下し、半田接合性が不良となるおそれがある。 The compounding amount of the curing agent (B) is such that the reactive functional group such as epoxy group or isocyanate group of the curing agent is 0.5 to 1.5 equivalent times the phenolic hydroxyl group of the resin (A). It is preferably 0.8 to 1.2 equivalent times. If the reactive functional group of the curing agent is less than 0.5 equivalents of the hydroxyl group, a cured product having sufficient physical properties cannot be obtained, and the reinforcing effect may be reduced, resulting in a decrease in bonding strength and reliability. There is. If the reactive functional group of the curing agent exceeds 1.5 equivalents of the hydroxyl group, the action of removing dirt such as oxide on the solder and metal surface may be reduced, and solder jointability may be deteriorated.
　このような半田接合用樹脂（硬化性フラックス）は、フェノール性ヒドロキシル基を有する樹脂（Ａ）と該樹脂の硬化剤（Ｂ）の反応により、良好な物性を有する硬化物が形成されるために、半田接合後に洗浄によりフラックスを除去するが必要なく、硬化物により半田接合部が保護されて、高温、多湿雰囲気でも電気絶縁性を保持し、接合強度と信頼性の高い半田接合が可能となる。 Such a solder bonding resin (curable flux) is formed because a cured product having good physical properties is formed by the reaction of the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin. It is not necessary to remove the flux by washing after soldering, the soldered part is protected by the cured product, and electrical insulation is maintained even in a high temperature and high humidity atmosphere, and soldering with high joining strength and reliability is possible. .
　なお、前述したような半田接合用樹脂は、フェノール性ヒドロキシル基を有する樹脂（Ａ）と該樹脂の硬化剤（Ｂ）の他に、硬化性酸化防止剤（Ｃ）、微結晶状態で分散するフェノール性ヒドロキシル基を有する化合物（Ｄ）および該化合物の硬化剤（Ｅ）、溶剤（Ｆ）、硬化触媒、密着性や耐湿性を向上させるためのシランカップリング剤、ボイドを防止するための消泡剤、あるいは液状または粉末の難燃剤等を含んでいてもよい。 In addition to the resin (A) having a phenolic hydroxyl group and the curing agent (B) of the resin, the solder bonding resin as described above is dispersed in a microcrystalline state as a curable antioxidant (C). Compound (D) having phenolic hydroxyl group, curing agent (E), solvent (F), curing catalyst, silane coupling agent for improving adhesion and moisture resistance, and elimination for preventing voids It may contain a foaming agent or a liquid or powder flame retardant.
　また、半田接合用樹脂は、放熱性を向上させるために、絶縁性を損なわない範囲で熱伝導性フィラーを含んでいてもよい。熱伝導性フィラーとしては、特に制限はないが、例えば、酸化チタン、アルミナ、無水炭酸マグネシウム、酸化マグネシウム、ベリリア、炭化ケイ素、窒化アルミニウム、酸化アルミニウム、チタン酸バリウム、酸化ベリリウム、窒化ホウ素、炭化ケイ素、酸化亜鉛等が挙げられる。これらの中でも分散性、絶縁性、熱伝導性の観点から窒化アルミニウム、酸化アルミニウム、および窒化ホウ素より選ばれる１種以上が好ましい。 Also, the solder bonding resin may contain a thermally conductive filler as long as the insulating property is not impaired in order to improve heat dissipation. The heat conductive filler is not particularly limited. For example, titanium oxide, alumina, anhydrous magnesium carbonate, magnesium oxide, beryllia, silicon carbide, aluminum nitride, aluminum oxide, barium titanate, beryllium oxide, boron nitride, silicon carbide. And zinc oxide. Among these, at least one selected from aluminum nitride, aluminum oxide, and boron nitride is preferable from the viewpoints of dispersibility, insulation, and thermal conductivity.
　以上説明したように構成された半導体パッケージ１によれば、半導体素子３と接合された部分以外の部分においても、配線基板２の両面が第１補強部材４および第２補強部材５により補強されるため、半導体パッケージ１全体の剛性が増す。特に、第１補強部材４および第２補強部材５の熱膨張係数が配線基板２よりも小さいため、半導体素子３が配線基板２の全面に亘って設けられているのと同様に、配線基板２と半導体素子３との熱膨張係数差に起因する配線基板２の反りを抑制または防止することができる。 According to the semiconductor package 1 configured as described above, both surfaces of the wiring board 2 are reinforced by the first reinforcing member 4 and the second reinforcing member 5 even in a portion other than the portion joined to the semiconductor element 3. Therefore, the rigidity of the entire semiconductor package 1 is increased. In particular, since the coefficient of thermal expansion of the first reinforcing member 4 and the second reinforcing member 5 is smaller than that of the wiring substrate 2, the semiconductor device 3 is provided over the entire surface of the wiring substrate 2 in the same manner as the wiring substrate 2. It is possible to suppress or prevent warping of the wiring board 2 due to a difference in thermal expansion coefficient between the semiconductor element 3 and the semiconductor element 3.
　また、配線基板２の厚さを薄くすることができるので、配線基板２の厚さ方向での熱伝導性を高めることができる。そのため、半導体パッケージ１は、半導体素子３からの熱を配線基板２を介して逃すことができ、放熱性に優れる。また、第１補強部材４および第２補強部材５の構成材料を適宜選択することにより、半導体パッケージ１の放熱性を高めることもできる。 Moreover, since the thickness of the wiring board 2 can be reduced, the thermal conductivity in the thickness direction of the wiring board 2 can be increased. Therefore, the semiconductor package 1 can release the heat from the semiconductor element 3 through the wiring board 2 and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1 can be enhanced by appropriately selecting the constituent materials of the first reinforcing member 4 and the second reinforcing member 5.
　このようなことから、半導体素子３および配線基板２の昇温を抑えることができるので、この点でも、配線基板２と半導体素子３との熱膨張係数差に起因する配線基板２の反りを抑制または防止することができる。 For this reason, since the temperature rise of the semiconductor element 3 and the wiring board 2 can be suppressed, the warping of the wiring board 2 due to the difference in thermal expansion coefficient between the wiring board 2 and the semiconductor element 3 is also suppressed in this respect. Or it can be prevented.
　（半導体パッケージ１の製造方法）
　以上説明したような半導体パッケージ１は、例えば、以下のようにして製造することができる。 (Method for manufacturing semiconductor package 1)
The semiconductor package 1 as described above can be manufactured as follows, for example.
　以下、図４に基づき、半導体パッケージ１の製造方法の一例を簡単に説明する。
　［１］
　まず、図４（ａ）に示すように、金属層２２１Ａとプリプレグ２１１Ａとの積層体を用意し、その積層体のプリプレグ２１１Ａ側の面に、第１補強部材４を貼り付ける。 Hereinafter, an example of a method for manufacturing the semiconductor package 1 will be briefly described with reference to FIG.
[1]
First, as shown to Fig.4 (a), the laminated body of the metal layer 221A and the prepreg 211A is prepared, and the 1st reinforcement member 4 is affixed on the surface at the side of the prepreg 211A of the laminated body.
　ここで、プリプレグ２１１Ａは、前述した配線基板２の絶縁層２１１を形成するためのものであり、前述した絶縁層２１１の樹脂組成物の未硬化物（半硬化物）が基材に含浸してなるものである。 Here, the prepreg 211A is for forming the insulating layer 211 of the wiring board 2 described above, and the base material is impregnated with an uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. It will be.
　また、金属層２２１Ａは、前述した配線基板２の導体パターン２２１を形成するためのものであり、導体パターン２２１の構成材料と同様の材料で構成されている。 The metal layer 221A is for forming the conductor pattern 221 of the wiring board 2 described above, and is made of the same material as that of the conductor pattern 221.
　［２］
　次に、図４（ｂ）に示すように、プリプレグ２１１Ａに貫通孔２１１１（ビアホール）を形成する。 [2]
Next, as shown in FIG. 4B, a through hole 2111 (via hole) is formed in the prepreg 211A.
　貫通孔２１１１の形成方法としては、特に限定されないが、例えば、レーザーを照射することにより形成することができる。 The formation method of the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.
　ここで、レーザーとしては、例えばＣＯ２レーザー、ＵＶ－ＹＡＧレーザー等を用いることができる。 Here, as the laser, for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
　なお、貫通孔２１１１は、例えば、ドリル等の機械加工によって形成することもできる。 In addition, the through-hole 2111 can be formed by machining such as a drill, for example.
　［３］
　次に、図４（ｃ）に示すように、貫通孔２１１１内に導体ポスト２３１を形成する。 [3]
Next, as shown in FIG. 4C, a conductor post 231 is formed in the through hole 2111.
　導体ポスト２３１の形成方法としては、特に限定されないが、例えば、導電性ペーストを充填する方法、無電解めっきにより埋め込む方法、電解めっきにより埋め込む方法等を用いることができる。 The method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.
　［４］
　次に、図４（ｄ）に示すように、金属層２２１Ａをパターンニングすることにより、導体パターン２２１を形成する。 [4]
Next, as shown in FIG. 4D, the conductor layer 221 is formed by patterning the metal layer 221A.
　かかるパターンニングの方法としては、特に限定されないが、エッチングが好適に用いられる。 Such a patterning method is not particularly limited, but etching is preferably used.
　以上のようにして、絶縁層２１１、導体パターン２２１および導体ポスト２３１が形成される。 As described above, the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.
　［５］
　次に、上記工程［１］～［４］と同様にして、絶縁層２１２、２１３、２１４、２１５および導体パターン２２２、２２３、２２４を形成するためのプリプレグおよび金属層からなる積層体をそれぞれ用意し、導体パターン２２２、２２３、２２４および導体ポスト２３２、２３３、２３４を形成する。また、絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを積層した後、導体ポスト２３１、２３２、２３３、２３４と同様の方法を用いて、伝熱ポスト２４を形成する。その後、絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを硬化（完全硬化）させて、図４（ｅ）に示すように、配線基板２を得る。 [5]
Next, in the same manner as in the above steps [1] to [4], prepregs for forming the insulating layers 212, 213, 214, 215 and the conductor patterns 222, 223, 224 and laminates made of metal layers are respectively prepared. Then, conductor patterns 222, 223, and 224 and conductor posts 232, 233, and 234 are formed. Further, after the prepregs for the insulating layers 211, 212, 213, 214, and 215 are laminated, the heat transfer post 24 is formed using the same method as that for the conductor posts 231, 232, 233, and 234. Thereafter, the prepregs for the insulating layers 211, 212, 213, 214, and 215 are cured (completely cured) to obtain the wiring board 2 as shown in FIG.
　絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを積層する方法としては、例えば、真空プレス、ラミネート等が挙げられる。これらの中でも真空プレスによる接合方法が好ましい。これにより、絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグの密着強度を向上することができる。 Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.
　絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを硬化させる方法としては、特に限定されないが、例えば、熱処理が好適に用いられる。 The method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but for example, heat treatment is preferably used.
　なお、伝熱ポスト２４の形成は、各導体ポスト２３１、２３２、２３３、２３４と同時に、各絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグに伝熱ポストを形成しておき、これらのプリプレグを積層することにより、これらの伝熱ポストを接続して形成してもよい。 The heat transfer posts 24 are formed at the same time as the conductor posts 231, 232, 233, 234, and the heat transfer posts are formed on the prepregs for the insulating layers 211, 212, 213, 214, 215. These heat transfer posts may be connected and formed by laminating prepregs.
　［６］
　次に、配線基板２の下面に、絶縁材８１Ａを塗布した後、金属ボール（半田ボール）７１Ａを半田リフローにより半田接合する。これにより、金属バンプ７１および絶縁材８１が形成される。 [6]
Next, after applying an insulating material 81A to the lower surface of the wiring board 2, a metal ball (solder ball) 71A is soldered by solder reflow. Thereby, the metal bump 71 and the insulating material 81 are formed.
　かかる半田接合は、特に限定されないが、配線基板２の下面に各金属バンプ７１が当接するように配置し、その状態で、例えば２００～２８０℃×１０～６０秒間加熱することにより行うことができる。 Such solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2 and heating in that state, for example, 200 to 280 ° C. × 10 to 60 seconds. .
　また、絶縁材８１Ａは、前述した絶縁材８１を形成するためのものであり、例えば、加熱により硬化するものである。 Also, the insulating material 81A is for forming the above-described insulating material 81, and is cured by heating, for example.
　絶縁材８１を形成するに際しては、例えば、図４（ｆ）に示すように、絶縁材８１Ａを配線基板２の下面に塗布し、前述したような半田接合の後、加熱により絶縁材８１Ａを硬化させることにより、絶縁材８１を得る。 When forming the insulating material 81, for example, as shown in FIG. 4F, the insulating material 81A is applied to the lower surface of the wiring board 2, and after the solder bonding as described above, the insulating material 81A is cured by heating. By doing so, the insulating material 81 is obtained.
　このようにして得られた絶縁材８１は、前述したように金属バンプ７１の周囲を囲むように形成される。 The insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
　このとき、絶縁材８１Ａは、半田接合時にフラックスとして機能し、且つ、金属ボール７１Ａとの界面張力により半田接合部周辺をリング状に補強する形状で硬化する。 At this time, the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.
　［７］
　次に、図４（ｇ）に示すように、配線基板２の下面に、第２補強部材５を接合する。また、配線基板２の上面に、アンダーフィル材を塗布した後、半導体素子３を金属バンプ３１を介して半田リフローにより接合する。なお、この場合、アンダーフィル材として前述した絶縁材８１と同じようなフラックス活性のある樹脂を用いて接着層３２を形成させる。また、半導体素子３を搭載し、フラックスあるいは半田ペースト等を用いてリフローにより半導体素子３を配線基板２に接合させた後、通常のキャピラリーアンダーフィル材を配線基板２と半導体素子３との間に充填・硬化させることもできる。 [7]
Next, as shown in FIG. 4G, the second reinforcing member 5 is joined to the lower surface of the wiring board 2. In addition, after applying an underfill material to the upper surface of the wiring board 2, the semiconductor element 3 is joined by solder reflow through the metal bumps 31. In this case, the adhesive layer 32 is formed using a resin having the same flux activity as the insulating material 81 described above as the underfill material. Further, after mounting the semiconductor element 3 and joining the semiconductor element 3 to the wiring board 2 by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2 and the semiconductor element 3. It can also be filled and cured.
　その後、半導体素子３と第１補強部材４との間に、熱伝導性材料６を充填する。
　以上のようにして、半導体パッケージ１が得られる。 Thereafter, a thermally conductive material 6 is filled between the semiconductor element 3 and the first reinforcing member 4.
The semiconductor package 1 is obtained as described above.
　＜第２実施形態＞
　次に、本発明の第２実施形態を説明する。
　第２実施形態の半導体パッケージは、
　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい補強部材とを有し、
　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、
　前記補強部材は、前記各金属バンプに非接触で前記金属バンプ同士の間に位置する部分を有することを特徴とする。 Second Embodiment
Next, a second embodiment of the present invention will be described.
The semiconductor package of the second embodiment is
A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate,
The reinforcing member has a portion located between the metal bumps without contacting the metal bumps.
　図６は、本発明の第２実施形態に係る半導体パッケージ１Ａを模式的に示す断面図である。なお、以下の説明では、説明の便宜上、図６中の上側を「上」、下側を「下」と言う。また、図６では、説明の便宜上、半導体パッケージの各部が誇張して描かれている。 FIG. 6 is a cross-sectional view schematically showing a semiconductor package 1A according to the second embodiment of the present invention. In the following description, for convenience of description, the upper side in FIG. 6 is referred to as “upper” and the lower side is referred to as “lower”. Further, in FIG. 6, for convenience of explanation, each part of the semiconductor package is exaggerated.
　以下、第２実施形態の半導体パッケージ１Ａについて、前述した第１実施形態との相違点を中心に説明し、同様の事項については、その説明を省略する。なお、図６において、前述した実施形態と同様の構成については、同一符号を付している。 Hereinafter, the semiconductor package 1A of the second embodiment will be described focusing on the differences from the first embodiment described above, and the description of the same matters will be omitted. In FIG. 6, the same reference numerals are given to the same configurations as those in the above-described embodiment.
　図６に示す半導体パッケージ１Ａは、第１補強部材、伝熱ポスト、熱伝導性材料を省略した以外は、第１実施形態とほぼ同様である。
　図６に示すように、半導体パッケージ１Ａは、配線基板２Ａと、この配線基板２Ａ上に搭載された半導体素子３Ａと、配線基板２Ａの基板２１Ａの下面（他方の面）に接合されている補強部材５Ａとを有する。 The semiconductor package 1A shown in FIG. 6 is substantially the same as the first embodiment except that the first reinforcing member, the heat transfer post, and the heat conductive material are omitted.
As shown in FIG. 6, the semiconductor package 1A includes a wiring board 2A, a semiconductor element 3A mounted on the wiring board 2A, and a reinforcement bonded to the lower surface (the other surface) of the substrate 21A of the wiring board 2A. 5A.
　半導体パッケージ１Ａは、伝熱ポスト２４を省略した以外は前述した第１実施形態の配線基板２と同様に構成された配線基板２Ａを有している。そして、その配線基板２Ａの下面上には、前述した第１実施形態の第２補強部材５と同様に構成された補強部材５Ａが接合されている。一方、配線基板２Ａの上面上には、配線基板２Ａの補強を目的とする補強部材は接合されていない。 The semiconductor package 1A has a wiring board 2A configured similarly to the wiring board 2 of the first embodiment described above except that the heat transfer post 24 is omitted. And the reinforcement member 5A comprised similarly to the 2nd reinforcement member 5 of 1st Embodiment mentioned above is joined on the lower surface of the wiring board 2A. On the other hand, a reinforcing member intended to reinforce the wiring board 2A is not joined on the upper surface of the wiring board 2A.
　補強部材５Ａが、半導体素子３Ａの搭載面と他方面上に接合されていることにより、半導体パッケージ１Ａの構造の対称性が増し、その結果、配線基板２Ａと半導体素子３Ａとの熱膨張係数差に起因する配線基板２Ａの反りを抑制または防止することができる。 Since the reinforcing member 5A is bonded to the mounting surface of the semiconductor element 3A and the other surface, the symmetry of the structure of the semiconductor package 1A increases, and as a result, the difference in thermal expansion coefficient between the wiring board 2A and the semiconductor element 3A. It is possible to suppress or prevent the warping of the wiring board 2A due to the above.
　また、補強部材５Ａの大きさは、半導体素子３Ａの大きさ・厚さ、配線基板２Ａの構成・厚さ、補強部材５Ａの材料種、厚さ、開口状態等に応じて決められるものであり、配線基板２Ａと同等以下の大きさであれば特に限定されない。 The size of the reinforcing member 5A is determined according to the size / thickness of the semiconductor element 3A, the configuration / thickness of the wiring board 2A, the material type, thickness, opening state, etc. of the reinforcing member 5A. The size is not particularly limited as long as the size is equal to or smaller than that of the wiring board 2A.
　また、第２実施形態では第１実施形態における伝熱ポスト２４が省略されているが、半導体素子３Ａが発生した熱は、金属バンプ３１、配線基板２Ａの導体パターンおよび導体ポスト、金属バンプ７１、絶縁材８１、補強部材５Ａの順で伝えられ放散されるため、半導体パッケージ１Ａは、高い放熱性を有する。 Further, in the second embodiment, the heat transfer post 24 in the first embodiment is omitted, but the heat generated by the semiconductor element 3A is generated by the metal bump 31, the conductor pattern and the conductor post of the wiring board 2A, the metal bump 71, Since the insulating material 81 and the reinforcing member 5A are transmitted and diffused in this order, the semiconductor package 1A has high heat dissipation.
　以上説明したような第２実施形態の半導体パッケージ１Ａによっても、配線基板２Ａの反りを防止するとともに、放熱性を高めることができる。 The semiconductor package 1A of the second embodiment as described above can also prevent the wiring board 2A from warping and improve heat dissipation.
　＜第３実施形態＞
　次に、本発明の第３実施形態を説明する。
　第３実施形態の半導体パッケージは、
　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい第２補強部材と、
　前記第２補強部材の前記基板と反対側の面に設けられ、前記基板よりも高い熱伝導性を有する伝熱バンプとを有することを特徴とする。 <Third Embodiment>
Next, a third embodiment of the present invention will be described.
The semiconductor package of the third embodiment is
A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
A heat transfer bump is provided on a surface of the second reinforcing member opposite to the substrate and has higher thermal conductivity than the substrate.
　以下、第３実施形態の半導体パッケージ１Ｂについて、前述した実施形態との相違点を中心に説明し、同様の構成については、同一符号を付し、その説明を省略する。 Hereinafter, the semiconductor package 1B of the third embodiment will be described with a focus on differences from the above-described embodiments, and the same components will be denoted by the same reference numerals and description thereof will be omitted.
　図７は、本発明の第３実施形態に係る半導体パッケージ１Ｂを模式的に示す断面図、図８は図７に示す半導体パッケージ１Ｂを示す上面図、図９は図７に示す半導体パッケージ１Ｂを示す下面図、図１０は図７に示す半導体パッケージ１Ｂの製造方法の一例を示す図である。
　以下の説明においても、図７中の上側を「上」、下側を「下」と言う。 7 is a sectional view schematically showing a semiconductor package 1B according to the third embodiment of the present invention, FIG. 8 is a top view showing the semiconductor package 1B shown in FIG. 7, and FIG. 9 is a plan view showing the semiconductor package 1B shown in FIG. FIG. 10 is a view showing an example of a method for manufacturing the semiconductor package 1B shown in FIG.
In the following description, the upper side in FIG. 7 is referred to as “upper” and the lower side is referred to as “lower”.
　図９に示す半導体パッケージ１Ｂにおいて、複数の伝熱バンプ９１は、第２補強部材５の枠部５２に設けられている。すなわち、複数の伝熱バンプ９１は、配線基板２を平面視したときに、導体パターン２２１、２２２、２２３、２２４に重ならないように設けられている。これにより、伝熱バンプ９１の形成が簡単となるとともに、伝熱バンプ９１と導体パターン２２１、２２２、２２３、２２４との短絡を防止することができる。 In the semiconductor package 1 </ b> B shown in FIG. 9, the plurality of heat transfer bumps 91 are provided on the frame portion 52 of the second reinforcing member 5. That is, the plurality of heat transfer bumps 91 are provided so as not to overlap the conductor patterns 221, 222, 223, 224 when the wiring substrate 2 is viewed in plan. Thereby, formation of the heat transfer bump 91 is simplified, and a short circuit between the heat transfer bump 91 and the conductor patterns 221, 222, 223, and 224 can be prevented.
　本実施形態では、複数の伝熱バンプ９１は、配線基板２を平面視したときに、枠部５２に沿って、すなわち配線基板２（第２補強部材５）の外周部に沿って互いに間隔を隔てて並設されている。特に、複数の伝熱バンプ９１は、配線基板２を平面視したときに、配線基板２の外周部に沿って周方向に等間隔で並設されているのが好ましい。これにより、配線基板２の温度分布を均一化することができる。 In the present embodiment, the plurality of heat transfer bumps 91 are spaced from each other along the frame portion 52, that is, along the outer peripheral portion of the wiring substrate 2 (second reinforcing member 5) when the wiring substrate 2 is viewed in plan. They are arranged side by side. In particular, the plurality of heat transfer bumps 91 are preferably arranged in parallel at equal intervals along the outer peripheral portion of the wiring board 2 when the wiring board 2 is viewed in plan. Thereby, the temperature distribution of the wiring board 2 can be made uniform.
　さらには、各伝熱バンプ９１は、第２補強部材５を介して１つの伝熱ポスト２４と対向するように設けられているのが好ましい。すなわち、１つの伝熱ポスト２４に対応して１つの伝熱バンプ９１が設けられているのが好ましい。これにより、より効果的に、配線基板２の温度分布を均一化することができる。なお、金属バンプ９１の配置は、これに限定されず、例えば、配線基板２を平面視したときに、隣り合う１つの伝熱ポスト２４の間に位置するように複数の伝熱バンプ９１が設けられてもよい。また、導体パターン２２１、２２２、２２３、２２４との短絡を防止することができれば、伝熱バンプ９１を第２補強部材５の部分５３に設けてもよい。 Furthermore, it is preferable that each heat transfer bump 91 is provided so as to face one heat transfer post 24 with the second reinforcing member 5 interposed therebetween. That is, it is preferable that one heat transfer bump 91 is provided corresponding to one heat transfer post 24. Thereby, the temperature distribution of the wiring board 2 can be made more effective. The arrangement of the metal bumps 91 is not limited to this. For example, when the wiring board 2 is viewed in plan, a plurality of heat transfer bumps 91 are provided so as to be positioned between one adjacent heat transfer post 24. May be. Further, the heat transfer bump 91 may be provided on the portion 53 of the second reinforcing member 5 as long as a short circuit with the conductor patterns 221, 222, 223, and 224 can be prevented.
　また、各伝熱バンプ９１の図７中最下点（第２補強部材５から最も離間した点）Ｐ１と各金属バンプ７１の図７中最下点（第２補強部材５から最も離間した点）Ｐ２とが同一面上に位置している。これにより、金属バンプ７１をマザーボード２００の端子に接合した際に、より確実に、伝熱バンプ９１をマザーボード２００に接触させることができる。さらに、金属バンプ７１をマザーボード２００の端子に接合した状態での、伝熱バンプ９１の過度な変形を防止することができ、伝熱バンプ７１と導体パターン２２１、２２２、２２３、２２４との短絡をより確実に防止することができる。 Further, the lowest point (the point farthest from the second reinforcing member 5) P1 of each heat transfer bump 91 in FIG. 7 and the lowest point (the point farthest from the second reinforcing member 5) of FIG. ) P2 is located on the same plane. Thereby, when the metal bump 71 is joined to the terminal of the motherboard 200, the heat transfer bump 91 can be brought into contact with the motherboard 200 more reliably. Furthermore, excessive deformation of the heat transfer bump 91 in a state where the metal bump 71 is bonded to the terminal of the mother board 200 can be prevented, and a short circuit between the heat transfer bump 71 and the conductor patterns 221, 222, 223, 224 can be prevented. It can prevent more reliably.
　さらに、各伝熱バンプ９１は、その表面にメッキ処理が施されているのが好ましい。すなわち、伝熱バンプ９１の表面に金属被膜が形成されているのが好ましい。これにより、伝熱バンプ９１の伝熱性をより高めることができる。前記メッキ処理に用いる金属材料としては、特に限定されず、金、銀、銅等の各種金属材料を用いることができるが、これらの中でも、金を用いることが好ましい。金を用いることにより、すなわち伝熱バンプ９１に金メッキを施すことにより、上記効果がより顕著となる。 Furthermore, it is preferable that the surface of each heat transfer bump 91 is plated. That is, a metal film is preferably formed on the surface of the heat transfer bump 91. Thereby, the heat transfer property of the heat transfer bump 91 can be further improved. The metal material used for the plating process is not particularly limited, and various metal materials such as gold, silver, and copper can be used. Among these, gold is preferably used. By using gold, that is, by applying gold plating to the heat transfer bump 91, the above effect becomes more remarkable.
　伝熱バンプ９１は、図１０（ｆ）～（ｇ）に示されるように、金属ボール９１Ａを半田リフローにより第２補強部材５の下面に半田接合することにより、形成することができる。
　なお、伝熱バンプ９１は、配線基板２の上面に金属バンプ３１を介して半導体素子３を接合した後に形成されることが好ましい。また、伝熱バンプ９１が形成された後に、半導体素子３と第１補強部材４との間に、熱伝導性材料６が充填されることが好ましい。
　なお、図１０（ａ）～（ｇ）に示される第３の実施形態の半導体パッケージ１Ｂのその他の構成の製造工程は、図４（ａ）～（ｇ）に示される第１の実施形態の半導体パッケージ１の製造工程と同様であるため、その詳細な説明を省略する。 As shown in FIGS. 10F to 10G, the heat transfer bump 91 can be formed by soldering a metal ball 91A to the lower surface of the second reinforcing member 5 by solder reflow.
The heat transfer bump 91 is preferably formed after the semiconductor element 3 is bonded to the upper surface of the wiring board 2 via the metal bump 31. Further, it is preferable that the heat conductive material 6 is filled between the semiconductor element 3 and the first reinforcing member 4 after the heat transfer bump 91 is formed.
The manufacturing process of the other configuration of the semiconductor package 1B of the third embodiment shown in FIGS. 10A to 10G is the same as that of the first embodiment shown in FIGS. 4A to 4G. Since it is the same as the manufacturing process of the semiconductor package 1, its detailed description is omitted.
　以上説明したような第３実施形態の半導体パッケージによれば、半導体素子からの熱を伝熱バンプを介しても逃すことができるため、放熱性をより高めることができる。 According to the semiconductor package of the third embodiment as described above, heat from the semiconductor element can be released even through the heat transfer bump, so that heat dissipation can be further improved.
（半導体装置１００）
　次に、半導体装置１００の製造方法および半導体装置１００について好適な実施形態に基づいて説明する。 (Semiconductor device 100)
Next, a method for manufacturing the semiconductor device 100 and the semiconductor device 100 will be described based on preferred embodiments.
　図５は、本発明の第４実施形態に係る半導体装置１００を模式的に示す断面図である。
　図５に示すように、半導体装置１００は、マザーボード（基板）２００と、このマザーボード２００に搭載された半導体パッケージ１とを有している。 FIG. 5 is a cross-sectional view schematically showing a semiconductor device 100 according to the fourth embodiment of the present invention.
As shown in FIG. 5, the semiconductor device 100 includes a mother board (substrate) 200 and a semiconductor package 1 mounted on the mother board 200.
　このような半導体装置１００においては、半導体パッケージ１の金属バンプ７１がマザーボード２００の端子（図示せず）に接合されている。これにより、半導体パッケージ１とマザーボード２００とが電気的に接続され、これらの間で電気的信号の伝送が行われる。また、この接合部を介して、半導体パッケージ１の熱をマザーボード２００へ逃すことができる。 In such a semiconductor device 100, the metal bumps 71 of the semiconductor package 1 are joined to the terminals (not shown) of the mother board 200. Thereby, the semiconductor package 1 and the mother board 200 are electrically connected, and electrical signals are transmitted between them. In addition, the heat of the semiconductor package 1 can be released to the mother board 200 through this joint.
　また、半導体パッケージ１の伝熱バンプ９１がマザーボード２００の放熱用の端子（図示せず）に接合されている。この接合部を介して、半導体パッケージ１の熱をマザーボード２００へ効率的に逃すことができる。このような伝熱バンプ９１は、前述した金属バンプ７１と同様の構成材料で構成されている場合、金属バンプ７１の接合と同時に一括してマザーボード２００に対して接合を行うことができる。 In addition, the heat transfer bumps 91 of the semiconductor package 1 are joined to terminals for heat dissipation (not shown) of the mother board 200. The heat of the semiconductor package 1 can be efficiently released to the mother board 200 through this joint. When such a heat transfer bump 91 is made of the same material as that of the metal bump 71 described above, the heat transfer bump 91 can be bonded to the mother board 200 at the same time as the metal bump 71 is bonded.
　以上説明したような半導体装置１００によれば、前述したような放熱性および信頼性に優れた半導体パッケージ１を備えるので、信頼性に優れる。
　なお、半導体装置１００に搭載される半導体パッケージ１は、半導体パッケージ１Ａまたは１Ｂに変えることができる。 According to the semiconductor device 100 as described above, since the semiconductor package 1 having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
The semiconductor package 1 mounted on the semiconductor device 100 can be changed to the semiconductor package 1A or 1B.
　以上、本発明の半導体パッケージおよび半導体装置を、図示の実施形態に基づいて説明したが、本発明はこれらに限定されるものでない。 As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.
　例えば、前述した実施形態では、第１補強部材４が半導体素子３の全周に亘って囲むように設けられていたが、これに限定されず、例えば、半導体素子３の周囲の一部に欠損した部分（切り欠き）が形成されていてもよい。 For example, in the above-described embodiment, the first reinforcing member 4 is provided so as to surround the entire circumference of the semiconductor element 3. However, the present invention is not limited to this. A cut-out portion (notch) may be formed.
　また、前述した実施形態では、第１補強部材４と第２補強部材５とを接続する熱伝導部として、基板２１を貫通する伝熱ポスト２４を用いたが、例えば、基板２１の外側に設けた熱伝導部材（金属部材）を用いてもよい。この場合、伝熱性接着剤を用いて熱伝導部材を基板２１、第１補強部材４および第２補強部材５に接着（接合）してもよいし、基板２１の側面側から基板２１、第１補強部材４および第２補強部材５を上下から銜えこむような形態としてもよい。 In the above-described embodiment, the heat transfer post 24 penetrating the substrate 21 is used as the heat conducting portion for connecting the first reinforcing member 4 and the second reinforcing member 5. Alternatively, a heat conductive member (metal member) may be used. In this case, the heat conducting member may be bonded (bonded) to the substrate 21, the first reinforcing member 4, and the second reinforcing member 5 using a heat transfer adhesive, or the substrate 21, the first reinforcing member may be bonded from the side surface side of the substrate 21. The reinforcing member 4 and the second reinforcing member 5 may be held from above and below.
　また、第２補強部材５に形成される開口部は、各金属バンプ７１と一対一で対応していなくてもよい。すなわち、第２補強部材５には、複数の金属バンプ７１に対して１つが対応するように、開口部が形成されていてもよい。 Further, the opening formed in the second reinforcing member 5 may not correspond to each metal bump 71 on a one-to-one basis. That is, an opening may be formed in the second reinforcing member 5 so that one corresponds to the plurality of metal bumps 71.
　（半導体パッケージ）
　次に、本発明の第５実施形態の半導体パッケージ１Ｃを説明する。
　第５実施形態の半導体パッケージ１Ｃは、
　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい補強部材とを有し、
　前記半導体素子の平面視での面積をＳ１とし、前記補強部材の平面視での外周縁で囲まれた領域内の面積をＳ２としたときに、
　Ｓ２／Ｓ１が０．６４以上２．２５以下であることを特徴とする。 (Semiconductor package)
Next, a semiconductor package 1C according to a fifth embodiment of the present invention will be described.
The semiconductor package 1C of the fifth embodiment is
A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
When the area of the semiconductor element in plan view is S1, and the area in the region surrounded by the outer periphery of the reinforcing member in plan view is S2,
S2 / S1 is 0.64 or more and 2.25 or less.
　図１１は、半導体パッケージ１Ｃを模式的に示す断面図、図１２は半導体パッケージ１Ｃを示す下面図、図１３は半導体パッケージ１Ｃの製造方法の一例を示す図である。なお、以下の説明では、説明の便宜上、図１１中の上側を「上」、下側を「下」と言う。また、図１１および１２では、それぞれ、説明の便宜上、半導体パッケージの各部が誇張して描かれている。また、上述した第１実施態様~第３実施態様における半導体パッケージと同様の構成については、その詳細な説明を一部省略する。 FIG. 11 is a cross-sectional view schematically showing the semiconductor package 1C, FIG. 12 is a bottom view showing the semiconductor package 1C, and FIG. 13 is a view showing an example of a manufacturing method of the semiconductor package 1C. In the following description, for convenience of explanation, the upper side in FIG. 11 is referred to as “upper” and the lower side is referred to as “lower”. 11 and 12, each part of the semiconductor package is exaggerated for convenience of explanation. Further, a part of the detailed description of the same configuration as that of the semiconductor package in the first to third embodiments described above is omitted.
　図１１に示す半導体パッケージ１Ｃは、配線基板２Ｃと、この配線基板２Ｃ上に搭載された半導体素子３と、補強部材５Ｃとを有する。 A semiconductor package 1C shown in FIG. 11 includes a wiring board 2C, a semiconductor element 3 mounted on the wiring board 2C, and a reinforcing member 5C.
　このような半導体パッケージ１Ｃによれば、半導体素子３と接合された部分以外の部分においても、配線基板２Ｃが補強部材５Ｃにより補強されるため、半導体パッケージ１Ｃ全体の剛性が増す。特に、補強部材５Ｃの熱膨張係数が配線基板２Ｃ（具体的には基板２１Ｃ）よりも小さいため、半導体素子３が配線基板２Ｃの全面に亘って設けられているのと同様に、配線基板２Ｃと半導体素子３との熱膨張係数差に起因する配線基板２Ｃの反りを抑制または防止することができる。 According to such a semiconductor package 1C, since the wiring board 2C is reinforced by the reinforcing member 5C in the portion other than the portion joined to the semiconductor element 3, the rigidity of the entire semiconductor package 1C is increased. In particular, since the thermal expansion coefficient of the reinforcing member 5C is smaller than that of the wiring substrate 2C (specifically, the substrate 21C), the semiconductor device 3 is provided over the entire surface of the wiring substrate 2C, similarly to the wiring substrate 2C. It is possible to suppress or prevent warping of the wiring board 2C due to the difference in thermal expansion coefficient between the semiconductor element 3 and the semiconductor element 3.
　また、半導体パッケージ１Ｃでは、配線基板２Ｃは半導体素子３と補強部材５Ｃとに挟持された状態となるため、配線基板２Ｃがより強固に補強されるとともに、配線基板２Ｃの両面の熱膨張差を抑制することができる。特に、後述するように補強部材５Ｃの面積が最適化されているので、配線基板２Ａの半導体素子３側の面上に補強部材（スティフナー）をさらに設けなくても、配線基板２Ａの反りを効果的に防止することができる。そのため、半導体パッケージ１Ｃの構成がより簡単となる。 In the semiconductor package 1C, since the wiring board 2C is sandwiched between the semiconductor element 3 and the reinforcing member 5C, the wiring board 2C is more strongly reinforced and the thermal expansion difference between both surfaces of the wiring board 2C is increased. Can be suppressed. In particular, since the area of the reinforcing member 5C is optimized as will be described later, it is possible to effectively warp the wiring board 2A without further providing a reinforcing member (stiffener) on the surface of the wiring board 2A on the semiconductor element 3 side. Can be prevented. Therefore, the configuration of the semiconductor package 1C becomes simpler.
　また、配線基板２Ｃ自体の剛性を高める必要がなく、配線基板２Ｃの厚さを薄くすることができるので、配線基板２Ｃの厚さ方向での熱伝導性を高めることができる。そのため、半導体パッケージ１Ｃは、半導体素子３からの熱を配線基板２Ｃを介して逃すことができ、放熱性に優れる。また、補強部材５Ｃの構成材料を適宜選択することにより、半導体パッケージ１Ｃの放熱性を高めることもできる。 Further, it is not necessary to increase the rigidity of the wiring board 2C itself, and the thickness of the wiring board 2C can be reduced, so that the thermal conductivity in the thickness direction of the wiring board 2C can be increased. Therefore, the semiconductor package 1C can release heat from the semiconductor element 3 through the wiring board 2C, and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1C can be improved by appropriately selecting the constituent material of the reinforcing member 5C.
　このような半導体パッケージ１Ｃの優れた放熱性も相俟って、配線基板２Ｃと半導体素子３との熱膨張係数差に起因する配線基板２Ｃの反りを効果的に抑制または防止することができる。その結果、半導体パッケージ１Ｃの電気的な接続信頼性を優れたものとすることができる。 Combined with such excellent heat dissipation of the semiconductor package 1C, it is possible to effectively suppress or prevent the warpage of the wiring board 2C due to the difference in thermal expansion coefficient between the wiring board 2C and the semiconductor element 3. As a result, the electrical connection reliability of the semiconductor package 1C can be improved.
　以下、半導体パッケージ１Ｃの各部を順次詳細に説明する。
　［配線基板］
　配線基板２Ｃは、半導体素子３を支持する基板であり、例えば、その搭載した半導体素子３と後述するようなマザーボード２００との電気的接続を中継する中継基板（インターポーザ）である。また、配線基板２Ｃは、その平面視形状は、通常、正方形、長方形等の四角形とされる。 Hereinafter, each part of the semiconductor package 1C will be sequentially described in detail.
[Wiring board]
The wiring board 2C is a board that supports the semiconductor element 3, and is, for example, a relay board (interposer) that relays electrical connection between the mounted semiconductor element 3 and a mother board 200 as will be described later. In addition, the wiring substrate 2C has a plan view shape that is usually a square such as a square or a rectangle.
　配線基板２Ｃは、基板２１Ｃと、導体パターン２２１、２２２、２２３、２２４と、導体ポスト２３１、２３２、２３３、２３４とを有している。 The wiring board 2C includes a board 21C, conductor patterns 221, 222, 223, and 224, and conductor posts 231, 232, 233, and 234.
　なお、本実施形態では、導体パターン２２１は、基板２１Ｃの一方の面側に設けられた第１導体パターンを構成し、導体パターン２２４は、基板２１Ｃの他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンを構成する。 In the present embodiment, the conductor pattern 221 constitutes a first conductor pattern provided on one surface side of the substrate 21C, and the conductor pattern 224 is provided on the other surface side of the substrate 21C. A second conductor pattern electrically connected to the conductor pattern is formed.
　基板２１Ｃは、複数（本実施形態では５層）の絶縁層２１１、２１２、２１３、２１４、２１５で構成されている。より具体的には、基板２１Ｃは、絶縁層２１１、絶縁層２１２、絶縁層２１３、絶縁層２１４、絶縁層２１５がこの順で積層されて構成されている。なお、基板２１Ｃを構成する絶縁層の数は、これに限定されず、１～４層であってもよいし、６層以上であってもよい。 The substrate 21 </ b> C includes a plurality (five layers in this embodiment) of insulating layers 211, 212, 213, 214, and 215. More specifically, the substrate 21C is configured by laminating an insulating layer 211, an insulating layer 212, an insulating layer 213, an insulating layer 214, and an insulating layer 215 in this order. The number of insulating layers constituting the substrate 21C is not limited to this, and may be 1 to 4 layers, or 6 or more layers.
　各絶縁層２１１、２１２、２１３、２１４、２１５は、上述した第２実施態様における絶縁層２１１、２１２、２１３、２１４、２１５と同様に構成されており、その詳細な説明を省略する。 The insulating layers 211, 212, 213, 214, and 215 are configured in the same manner as the insulating layers 211, 212, 213, 214, and 215 in the second embodiment described above, and detailed description thereof is omitted.
　上述したような複数の層で構成された基板２１Ｃの平均厚さは、特に限定されないが、３０μｍ以上８００μｍ以下であることが好ましく、３０μｍ以上４００μｍ以下であることがより好ましい。 The average thickness of the substrate 21C composed of a plurality of layers as described above is not particularly limited, but is preferably 30 μm or more and 800 μm or less, and more preferably 30 μm or more and 400 μm or less.
　このような基板２１Ｃの絶縁層２１１と絶縁層２１２の間には、導体パターン２２１が介挿されている。また、絶縁層２１２と絶縁層２１３との間には、導体パターン２２２が介挿されている。また、絶縁層２１３と絶縁層２１４との間には、導体パターン２２３が介挿されている。また、絶縁層２１４と絶縁層２１５との間には、導体パターン２２４が介挿されている。
　この導体パターン２２１、２２２、２２３、２２４は、上述した第２実施態様における導体パターン２２１、２２２、２２３、２２４と同様に構成されており、その詳細な説明を省略する。 A conductor pattern 221 is interposed between the insulating layer 211 and the insulating layer 212 of the substrate 21C. In addition, a conductive pattern 222 is interposed between the insulating layer 212 and the insulating layer 213. A conductor pattern 223 is interposed between the insulating layer 213 and the insulating layer 214. A conductor pattern 224 is interposed between the insulating layer 214 and the insulating layer 215.
The conductor patterns 221, 222, 223, and 224 are configured in the same manner as the conductor patterns 221, 222, 223, and 224 in the second embodiment described above, and a detailed description thereof is omitted.
　また、絶縁層２１１には、その厚さ方向に貫通するビアホールが形成され、そのビアホール内に導体ポスト（ビアポスト）２３１が設けられている。この導体ポスト２３１は、絶縁層２１１をその厚さ方向に貫通しており、上端部が半導体素子３に金属バンプ３１を介して接続されるとともに、下端部が導体パターン２２１に接続されている。これにより、導体パターン２２１と半導体素子３とが導通している。 Further, a via hole penetrating in the thickness direction is formed in the insulating layer 211, and a conductor post (via post) 231 is provided in the via hole. The conductor post 231 passes through the insulating layer 211 in the thickness direction, and has an upper end connected to the semiconductor element 3 via the metal bump 31 and a lower end connected to the conductor pattern 221. Thereby, the conductor pattern 221 and the semiconductor element 3 are electrically connected.
　同様に、絶縁層２１２には、その厚さ方向に貫通する導体ポスト（ビアポスト）２３２が設けられている。この導体ポスト２３２は、上端部が導体パターン２２１に接続されるとともに、下端部が導体パターン２２２に接続されている。これにより、導体パターン２２１と導体パターン２２２とが導通している。 Similarly, the insulating layer 212 is provided with a conductor post (via post) 232 penetrating in the thickness direction. The conductor post 232 has an upper end connected to the conductor pattern 221 and a lower end connected to the conductor pattern 222. Thereby, the conductor pattern 221 and the conductor pattern 222 are electrically connected.
　また、絶縁層２１３には、その厚さ方向に貫通する導体ポスト（ビアポスト）２３３が設けられている。この導体ポスト２３３は、上端部が導体パターン２２２に接続されるとともに、下端部が導体パターン２２３に接続されている。これにより、導体パターン２２２と導体パターン２２３とが導通している。 The insulating layer 213 is provided with a conductor post (via post) 233 that penetrates in the thickness direction. The conductor post 233 has an upper end connected to the conductor pattern 222 and a lower end connected to the conductor pattern 223. Thereby, the conductor pattern 222 and the conductor pattern 223 are electrically connected.
　また、絶縁層２１４には、その厚さ方向に貫通する導体ポスト（ビアポスト）２３４が設けられている。この導体ポスト２３４は、上端部が導体パターン２２３に接続されるとともに、下端部が導体パターン２２４に接続されている。これにより、導体パターン２２３と導体パターン２２４とが導通している。 Also, the insulating layer 214 is provided with a conductor post (via post) 234 that penetrates in the thickness direction. The conductor post 234 has an upper end connected to the conductor pattern 223 and a lower end connected to the conductor pattern 224. Thereby, the conductor pattern 223 and the conductor pattern 224 are electrically connected.
　また、絶縁層２１５には、その厚さ方向に貫通する複数の開口部が設けられ、その各開口部から導体パターン２２４の一部（端子）が露出している。そして、その導体パターン２２４の露出した各部分（端子）上には、金属バンプ７１が接合されている。すなわち、第２導体パターンである導体パターン２２４の基板２１Ｃと反対側の面には、複数の金属バンプ７１が接合されている。 The insulating layer 215 is provided with a plurality of openings penetrating in the thickness direction, and a part (terminal) of the conductor pattern 224 is exposed from each opening. A metal bump 71 is bonded onto each exposed portion (terminal) of the conductor pattern 224. That is, a plurality of metal bumps 71 are bonded to the surface of the conductor pattern 224 that is the second conductor pattern on the side opposite to the substrate 21C.
　金属バンプ７１は、半導体パッケージ１Ｃを例えば後述するようなマザーボードに対して電気的に接続するためのものである。
　この金属バンプ７１は、上述した第２実施態様における金属バンプ７１と同様に構成されており、その詳細な説明を省略する。 The metal bumps 71 are for electrically connecting the semiconductor package 1C to a mother board as will be described later, for example.
The metal bump 71 is configured in the same manner as the metal bump 71 in the second embodiment described above, and detailed description thereof is omitted.
　［半導体素子］
　半導体素子３は、例えば、集積回路素子（ＩＣ）であり、より具体的には、例えば、ロジックＩＣ、メモリおよび受発光素子等である。
　この半導体素子３は、前述した配線基板２Ｃの基板２１Ｃの上面（一方の面）に接合され、第１導体パターンである導体パターン２２１に電気的に接続されている。 [Semiconductor element]
The semiconductor element 3 is, for example, an integrated circuit element (IC), and more specifically, for example, a logic IC, a memory, and a light receiving / emitting element.
The semiconductor element 3 is bonded to the upper surface (one surface) of the substrate 21C of the wiring substrate 2C described above, and is electrically connected to the conductor pattern 221 that is the first conductor pattern.
　具体的には、半導体素子３は、その下面に、図示しない複数の端子が設けられており、その各端子が金属バンプ３１を介して、前述した配線基板２Ｃの導体ポスト２３１に電気的に接続されている。これにより、半導体素子３と配線基板２Ｃの導体パターン２２１とが電気的に接続されている。
　金属バンプ３１の構成は、上述した第２実施態様における金属バンプ３１と同様に構成されており、その詳細な説明を省略する。 Specifically, the semiconductor element 3 is provided with a plurality of terminals (not shown) on the lower surface thereof, and each terminal is electrically connected to the conductor post 231 of the wiring board 2C described above via the metal bump 31. Has been. Thereby, the semiconductor element 3 and the conductor pattern 221 of the wiring board 2C are electrically connected.
The configuration of the metal bump 31 is the same as that of the metal bump 31 in the second embodiment described above, and a detailed description thereof is omitted.
　また、半導体素子３は、接着層３２を介して、配線基板２Ｃの上面に接着（接合）されている。
　この接着層３２は、上述した第２実施態様における接着層３２と同様に構成されており、その詳細な説明を省略する。 In addition, the semiconductor element 3 is bonded (bonded) to the upper surface of the wiring board 2 </ b> C via the adhesive layer 32.
The adhesive layer 32 is configured in the same manner as the adhesive layer 32 in the second embodiment described above, and detailed description thereof is omitted.
　［補強部材］
　補強部材（スティフナー）５Ｃは、配線基板２Ｃの基板２１Ｃの下面（他方の面）に接合されている。
　この補強部材５Ｃと基板２１Ｃとは、接着剤を介して接合することができる。これにより、補強部材５Ｃの設置が簡単となる。
　かかる接着剤としては、接着機能を有するものであれば、特に限定されず、各種接着剤を用いることができるが、熱伝導性に優れたものが好ましく、前述した第１実施態様における熱伝導性材料６と同様のものを用いることができる。
　この補強部材５Ｃは、基板２１Ｃよりも熱膨張係数が小さい。 [Reinforcing member]
The reinforcing member (stiffener) 5C is joined to the lower surface (the other surface) of the substrate 21C of the wiring substrate 2C.
The reinforcing member 5C and the substrate 21C can be bonded via an adhesive. Thereby, installation of the reinforcing member 5C becomes easy.
Such an adhesive is not particularly limited as long as it has an adhesive function, and various adhesives can be used, but those having excellent thermal conductivity are preferable, and the thermal conductivity in the first embodiment described above. The same material 6 can be used.
The reinforcing member 5C has a smaller thermal expansion coefficient than the substrate 21C.
　補強部材５Ｃは、板状をなしている。これにより、補強部材５Ｃの構成を簡単かつ小型なものとすることができる。 The reinforcing member 5C has a plate shape. Thereby, the structure of 5 C of reinforcement members can be made simple and small.
　また、図１３に示すように、補強部材５Ｃは、配線基板２Ｃ（基板２１Ｃ）の外周部に沿って設けられた部分（枠部）５２Ｃと、金属バンプ７１同士の間に設けられた部分５３Ｃとを有している。補強部材５Ｃの部分５２Ｃと配線基板２Ｃ（基板２１Ｃ）との接合により、補強部材５Ｃが配線基板２Ｃを効果的に補強することができる。また、補強部材５Ｃの部分５３Ｃと配線基板２Ｃとの接合により、補強部材５Ｃの剛性が高められる。 Further, as shown in FIG. 13, the reinforcing member 5 </ b> C includes a portion (frame portion) 52 </ b> C provided along the outer peripheral portion of the wiring substrate 2 </ b> C (substrate 21 </ b> C) and a portion 53 </ b> C provided between the metal bumps 71. And have. By joining the portion 52C of the reinforcing member 5C and the wiring substrate 2C (substrate 21C), the reinforcing member 5C can effectively reinforce the wiring substrate 2C. Further, the rigidity of the reinforcing member 5C is increased by joining the portion 53C of the reinforcing member 5C and the wiring board 2C.
　より具体的に説明すると、補強部材５Ｃは、前述した各金属バンプ７１に非接触で各金属バンプ７１を囲むように形成された複数の開口部５１Ｃを有する。これにより、補強部材５Ｃが配線基板２Ｃの下面に占める面積の割合を大きくすることができる。その結果、補強部材５Ｃによる配線基板２Ｃの剛性を高める効果を優れたものとすることができる。 More specifically, the reinforcing member 5C has a plurality of openings 51C formed so as to surround each metal bump 71 in a non-contact manner with each metal bump 71 described above. Thereby, the ratio of the area which the reinforcing member 5C occupies in the lower surface of the wiring board 2C can be increased. As a result, the effect of increasing the rigidity of the wiring board 2C by the reinforcing member 5C can be made excellent.
　本実施形態では、各開口部５１Ｃは、平面視にて、円形をなしている。なお、各開口部５１Ｃの平面視形状は、これに限定されず、例えば、楕円形、多角形等であってもよい。 In the present embodiment, each opening 51C has a circular shape in plan view. In addition, the planar view shape of each opening part 51C is not limited to this, For example, an ellipse, a polygon, etc. may be sufficient.
　また、各開口部５１Ｃは、補強部材５Ｃの形成領域（外周縁５ｃで囲まれた領域）内において、各金属バンプ７１に対応して（一対一で対応して）設けられている。これにより、補強部材５Ｃの剛性の均一化を図ることができる。また、補強部材５Ｃの放熱性も向上させることができる。 Further, each opening 51C is provided corresponding to each metal bump 71 (corresponding one-to-one) in the region where the reinforcing member 5C is formed (the region surrounded by the outer peripheral edge 5c). Thereby, the rigidity of the reinforcing member 5C can be made uniform. Moreover, the heat dissipation of the reinforcing member 5C can be improved.
　また、補強部材５Ｃは、各金属バンプ７１との間の距離（平面視における開口部５１Ｃの壁面と金属バンプ７１の外周面との間の距離）が金属バンプ７１の全周に亘って一定となるように形成されている。これにより、補強部材５Ｃおよび各金属バンプ７１の一体性が増し、これらによる配線基板２Ｃの補強効果が好適に発揮される。 In addition, the distance between the reinforcing member 5C and each metal bump 71 (distance between the wall surface of the opening 51C and the outer peripheral surface of the metal bump 71 in plan view) is constant over the entire circumference of the metal bump 71. It is formed to become. Thereby, the integrity of the reinforcing member 5C and each metal bump 71 is increased, and the reinforcing effect of the wiring board 2C by these is suitably exhibited.
　このような補強部材５Ｃは、半導体素子３の平面視での面積（外周縁３ｃで囲まれた領域内の面積）をＳ１とし、補強部材５Ｃの平面視での外周縁５ｃで囲まれた領域内の面積をＳ２としたときに、Ｓ２／Ｓ１が０．６４以上２．２５以下となるように構成されている。これにより、配線基板２Ｃの半導体素子３側の面上に補強部材（スティフナー）をさらに設けなくても、配線基板２Ｃの反りを効果的に防止することができる。そのため、半導体パッケージ１Ｃの構成が簡単となる。また、配線基板２Ｃの上面上に補強部材を設けなくてよいため、半導体パッケージ１Ｃの製造の際に、半導体素子３の設置が容易となる。なお、ここで、面積Ｓ２は、平面視において、前述した部分（枠部）５２Ｃと部分５３Ｃの面積と複数の開口部５１Ｃとの合計面積である。 In such a reinforcing member 5C, the area of the semiconductor element 3 in plan view (the area in the region surrounded by the outer peripheral edge 3c) is S1, and the region surrounded by the outer peripheral edge 5c of the reinforcing member 5C in plan view S2 / S1 is configured to be 0.64 or more and 2.25 or less when the inner area is S2. Thereby, even if a reinforcing member (stiffener) is not further provided on the surface of the wiring board 2C on the semiconductor element 3 side, the warping of the wiring board 2C can be effectively prevented. Therefore, the configuration of the semiconductor package 1C is simplified. In addition, since it is not necessary to provide a reinforcing member on the upper surface of the wiring board 2C, the semiconductor element 3 can be easily installed when the semiconductor package 1C is manufactured. Here, the area S2 is a total area of the above-described portions (frame portions) 52C, the portions 53C, and the plurality of openings 51C in plan view.
　また、配線基板２Ｃの反りをより効果的に防止する観点から、上記面積比Ｓ２／Ｓ１は、Ｓ２／Ｓ１が０．８１以上１．４４以下であるのが好ましい。 Also, from the viewpoint of more effectively preventing the warping of the wiring board 2C, the area ratio S2 / S1 is preferably such that S2 / S1 is 0.81 or more and 1.44 or less.
　また、図１２に示すように、平面視にて、補強部材５Ｃの外周縁５ｃは、半導体素子の外周縁３ｃよりも外側に位置している。これにより、簡単かつ確実に、配線基板２Ｃの反りを効果的に防止することができる。なお、平面視にて、補強部材５Ｃの外周縁５ｃは、半導体素子の外周縁３ｃに一致していても同様の効果を奏することができる。また、平面視にて、補強部材５Ｃの外周縁５ｃの一部が半導体素子の外周縁３ｃよりも内側に位置していてもよい。また、補強部材５Ｃの構成材料、厚さ、形状等によっては、平面視にて、補強部材５Ｃの外周縁５ｃの全周が半導体素子の外周縁３ｃよりも内側に位置していてもよい。 Further, as shown in FIG. 12, the outer peripheral edge 5c of the reinforcing member 5C is located outside the outer peripheral edge 3c of the semiconductor element in a plan view. Thereby, the curvature of the wiring board 2C can be effectively prevented easily and reliably. Note that the same effect can be obtained even when the outer peripheral edge 5c of the reinforcing member 5C coincides with the outer peripheral edge 3c of the semiconductor element in plan view. Further, in plan view, a part of the outer peripheral edge 5c of the reinforcing member 5C may be located inside the outer peripheral edge 3c of the semiconductor element. Further, depending on the constituent material, thickness, shape, and the like of the reinforcing member 5C, the entire periphery of the outer peripheral edge 5c of the reinforcing member 5C may be located inside the outer peripheral edge 3c of the semiconductor element in a plan view.
　また、補強部材５Ｃは、半導体素子３との熱膨張係数差が７ｐｐｍ／℃以下であるのが好ましい。これにより、補強部材５Ｃが効果的に配線基板２Ｃを補強し、半導体パッケージ１Ｃ全体の熱膨張を抑えることができる。 Further, the reinforcing member 5C preferably has a difference in thermal expansion coefficient from the semiconductor element 3 of 7 ppm / ° C. or less. Thereby, the reinforcing member 5C can effectively reinforce the wiring board 2C and suppress the thermal expansion of the entire semiconductor package 1C.
　また、補強部材５Ｃの構成材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、例えば、金属材料、セラミックス材料等を用いることができるが、金属材料を用いるのが好ましい。補強部材５Ｃが金属材料で構成されていると、補強部材５Ｃの放熱性を高めることができる。その結果、半導体パッケージ１Ｃの放熱性を向上させることができる。 The constituent material of the reinforcing member 5C is not particularly limited as long as it has a thermal expansion coefficient as described above. For example, a metal material, a ceramic material, or the like can be used, but a metal material is used. Is preferred. When the reinforcing member 5C is made of a metal material, the heat dissipation of the reinforcing member 5C can be improved. As a result, the heat dissipation of the semiconductor package 1C can be improved.
　かかる金属材料としては、前述したような熱膨張係数を有するものであれば、特に限定されず、各種金属材料を用いることができるが、放熱性および低熱膨張を実現する観点から、Ｆｅを含む合金を用いるのが好ましい。 Such a metal material is not particularly limited as long as it has a thermal expansion coefficient as described above, and various metal materials can be used. From the viewpoint of realizing heat dissipation and low thermal expansion, an alloy containing Fe is used. Is preferably used.
　かかるＦｅを含む合金としては、例えば、上述した第１実施形態で用いられるＦｅ－Ｎｉ系合金、Ｆｅ－Ｃｏ－Ｃｒ系合金、Ｆｅ－Ｃｏ系合金、Ｆｅ－Ｐｔ系合金、Ｆｅ－Ｐｄ合金等が挙げられ、特に、Ｆｅ－Ｎｉ系合金を用いるのが好ましい。 Examples of such Fe-containing alloys include Fe—Ni alloys, Fe—Co—Cr alloys, Fe—Co alloys, Fe—Pt alloys, Fe—Pd alloys and the like used in the first embodiment described above. In particular, it is preferable to use an Fe—Ni alloy.
　このような金属材料は、放熱性に優れるだけでなく、熱膨張係数が低く、かつ、一般的な半導体素子３の熱膨張係数に近い熱膨張係数を有する。そのため、配線基板２Ｃの両面の熱膨張差を抑えることができる。 Such a metal material not only has excellent heat dissipation, but also has a low thermal expansion coefficient and a thermal expansion coefficient close to that of a general semiconductor element 3. Therefore, the difference in thermal expansion between both surfaces of the wiring board 2C can be suppressed.
　補強部材５Ｃの熱膨張係数は、０．５ｐｐｍ／℃以上１０ｐｐｍ／℃以下であるのが好ましく、１ｐｐｍ／℃以上７ｐｐｍ／℃以下であるのがより好ましく、１ｐｐｍ／℃以上５ｐｐｍ／℃以下であるのがさらに好ましい。これにより、半導体素子３と補強部材５Ｃとの熱膨張係数差を小さくし、配線基板２Ｃの反りを効果的に防止することができる。 The thermal expansion coefficient of the reinforcing member 5C is preferably 0.5 ppm / ° C. or more and 10 ppm / ° C. or less, more preferably 1 ppm / ° C. or more and 7 ppm / ° C. or less, and more preferably 1 ppm / ° C. or more and 5 ppm / ° C. or less. Is more preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 5C can be reduced, and the warp of the wiring board 2C can be effectively prevented.
　また、補強部材５Ｃと半導体素子３との熱膨張係数差の絶対値は、７ｐｐｍ／℃以下であるのが好ましく、５ｐｐｍ／℃以下であるのがより好ましく、２ｐｐｍ／℃以下であるのがさらに好ましい。これにより、半導体素子３と補強部材５Ｃとの熱膨張係数差を小さくし、配線基板２Ｃの反りを効果的に防止することができる。 Further, the absolute value of the difference in thermal expansion coefficient between the reinforcing member 5C and the semiconductor element 3 is preferably 7 ppm / ° C. or less, more preferably 5 ppm / ° C. or less, and further preferably 2 ppm / ° C. or less. preferable. Thereby, the difference in thermal expansion coefficient between the semiconductor element 3 and the reinforcing member 5C can be reduced, and the warp of the wiring board 2C can be effectively prevented.
　上述したような熱膨張係数の観点から、補強部材５Ｃを構成する金属材料がＦｅ－Ｎｉ系合金である場合、前記Ｆｅ－Ｎｉ系合金は、Ｎｉの含有量が３０ｗｔ％以上５０ｗｔ％以下であるのが好ましく、Ｎｉの含有量が３５ｗｔ％以上４５ｗｔ％以下であるのがより好ましい。これにより、補強部材５Ｃの熱膨張係数を半導体素子３の熱膨張係数に近づけることができる。この場合、前記Ｆｅ－Ｎｉ系合金は、Ｆｅの含有量が５０ｗｔ％以上７０ｗｔ％以下であるのが好ましく、Ｆｅの含有量が５５ｗｔ％以上６５ｗｔ％以下であるのがより好ましい。 From the viewpoint of the thermal expansion coefficient as described above, when the metal material constituting the reinforcing member 5C is an Fe—Ni alloy, the Fe—Ni alloy has a Ni content of 30 wt% or more and 50 wt% or less. It is preferable that the Ni content is 35 wt% or more and 45 wt% or less. Thereby, the thermal expansion coefficient of the reinforcing member 5 </ b> C can be brought close to the thermal expansion coefficient of the semiconductor element 3. In this case, the Fe—Ni-based alloy preferably has an Fe content of 50 wt% or more and 70 wt% or less, and more preferably an Fe content of 55 wt% or more and 65 wt% or less.
　また、補強部材５Ｃを構成する金属材料がＦｅ－Ｎｉ系合金である場合、前記Ｆｅ－Ｎｉ系合金は、ＦｅおよびＮｉの合計含有量が８５ｗｔ％以上１００ｗｔ％以下であるのが好ましく、ＦｅおよびＮｉの合計含有量が９０ｗｔ％以上１００ｗｔ％以下であるのがより好ましい。すなわち、前記Ｆｅ－Ｎｉ系合金は、残部（Ｍ）の含有量が０ｗｔ％以上１５ｗｔ％以下であるのが好ましく、残部（Ｍ）の含有量が０ｗｔ％以上１０ｗｔ％以下であるのがより好ましい。これにより、補強部材５Ｃの熱膨張係数を半導体素子３の熱膨張係数に近づけることができる。 When the metal material constituting the reinforcing member 5C is an Fe—Ni alloy, the Fe—Ni alloy preferably has a total content of Fe and Ni of 85 wt% or more and 100 wt% or less. It is more preferable that the total content of Ni is 90 wt% or more and 100 wt% or less. That is, in the Fe—Ni-based alloy, the content of the balance (M) is preferably 0 wt% or more and 15 wt% or less, and the content of the balance (M) is more preferably 0 wt% or more and 10 wt% or less. . Thereby, the thermal expansion coefficient of the reinforcing member 5 </ b> C can be brought close to the thermal expansion coefficient of the semiconductor element 3.
　また、補強部材５Ｃの平均厚さは、配線基板２Ｃの熱膨張係数、補強部材５Ｃの形状、大きさ、構成材料等に応じて決められるものであり、特に限定されないが、例えば、０．０２ｍｍ以上０．８ｍｍ以下程度である。 The average thickness of the reinforcing member 5C is determined according to the thermal expansion coefficient of the wiring board 2C, the shape, size, constituent material, etc. of the reinforcing member 5C, and is not particularly limited. It is about 0.8 mm or less.
　また、熱放散性の観点から、補強部材５Ｃの表面が粗化されていてもよい。補強部材５Ｃ表面が粗化されていれば、表面積が増大し熱放散の効率が上がる。補強部材５Ｃ表面の粗化方法は、特に限定されず、例えば化学的な薬液処理、機械的なサンドブラスト処理などにより実施することができる。 Moreover, the surface of the reinforcing member 5C may be roughened from the viewpoint of heat dissipation. If the surface of the reinforcing member 5C is roughened, the surface area increases and the efficiency of heat dissipation increases. The method for roughening the surface of the reinforcing member 5C is not particularly limited, and can be carried out by, for example, chemical chemical treatment, mechanical sandblast treatment, or the like.
　補強部材５Ｃの表面粗度の大きさは、半導体素子３の発熱量、樹脂材料の構成、配線基板２１Ｃの構成、補強部材５Ｃの形状、大きさ等に応じて決められるものであり、特に限定されないが、例えば、算術平均で表される表面粗度が０．１μｍ以上１００μｍ以下程度である。前記算術平均で表される表面粗度は、例えばＪＩＳ　Ｂ　０６０１に準じて測定することができる。 The magnitude of the surface roughness of the reinforcing member 5C is determined according to the amount of heat generated by the semiconductor element 3, the configuration of the resin material, the configuration of the wiring substrate 21C, the shape and size of the reinforcing member 5C, and the like. However, for example, the surface roughness expressed by arithmetic mean is about 0.1 μm or more and 100 μm or less. The surface roughness represented by the arithmetic average can be measured according to, for example, JIS B 0601.
　また、樹脂材料との密着性向上の観点から、補強部材５Ｃ表面に銅皮膜が形成されていてもよい。銅については、樹脂材料との密着強度を向上させるための表面処理技術が数多く知られているため、補強部材５Ｃの形状、大きさ、樹脂材料の種類等に応じてその表面処理を適宜選択し、実施することができる。 Further, from the viewpoint of improving the adhesion with the resin material, a copper film may be formed on the surface of the reinforcing member 5C. For copper, since many surface treatment techniques for improving the adhesion strength with the resin material are known, the surface treatment is appropriately selected according to the shape, size, type of resin material, etc. of the reinforcing member 5C. Can be implemented.
　銅皮膜の形成方法は、特に限定されないが、例えば、電解めっき、無電解めっき等のめっき処理、スパッタ処理等により実施することができる。 The method for forming the copper film is not particularly limited, and can be performed by, for example, plating treatment such as electrolytic plating or electroless plating, sputtering treatment, or the like.
　また、銅皮膜の平均厚さは、補強部材５Ｃの熱膨張係数に影響を及ぼさず、密着性向上の表面処理が可能な範囲で薄い方が好ましい。 Also, the average thickness of the copper film is preferably as thin as possible without affecting the thermal expansion coefficient of the reinforcing member 5C and capable of surface treatment for improving adhesion.
　また、補強部材５Ｃと各金属バンプ７１との間には、絶縁材８１が設けられている（充填されている）。これにより、補強部材５Ｃと各金属バンプ７１との接触を防止することができる。そのため、半導体パッケージ１Ｃの信頼性を優れたものとしつつ、補強部材５Ｃの剛性および放熱性を高めることができる。 Further, an insulating material 81 is provided (filled) between the reinforcing member 5C and each metal bump 71. Thereby, contact with 5 C of reinforcement members and each metal bump 71 can be prevented. Therefore, the rigidity and heat dissipation of the reinforcing member 5C can be enhanced while improving the reliability of the semiconductor package 1C.
　また、絶縁材８１は、金属バンプ７１の周囲を囲むように形成され、かつ、各半田バンプに接合されている。これにより、絶縁材８１は、金属バンプ７１を補強している。
　このような絶縁材８１は、絶縁性を有し、樹脂材料を含んで構成されている。 The insulating material 81 is formed so as to surround the metal bump 71 and is bonded to each solder bump. Thereby, the insulating material 81 reinforces the metal bump 71.
Such an insulating material 81 has an insulating property and includes a resin material.
　このような絶縁材８１は、特に限定されないが、例えば、熱硬化性を有する半田接合用樹脂により形成されるのが好ましく、上述した第１実施形態における絶縁材８１と同様の構成とすることができる。 Such an insulating material 81 is not particularly limited, but is preferably formed of, for example, a thermosetting solder bonding resin, and has the same configuration as the insulating material 81 in the first embodiment described above. it can.
　以上説明したように構成された半導体パッケージ１Ｃによれば、半導体素子３と接合された部分以外の部分においても、配線基板２Ｃが補強部材５Ｃにより補強されるため、半導体パッケージ１Ｃ全体の剛性が増す。 According to the semiconductor package 1 </ b> C configured as described above, the wiring substrate 2 </ b> C is reinforced by the reinforcing member 5 </ b> C at portions other than the portion joined to the semiconductor element 3, so that the rigidity of the entire semiconductor package 1 </ b> C is increased. .
　また、半導体パッケージ１Ｃでは、配線基板２Ｃは半導体素子３と補強部材５Ｃとに挟持された状態となるため、配線基板２Ｃがより強固に補強されるとともに、配線基板２Ｃの両面の熱膨張差を抑制することができる。特に、補強部材５Ｃの面積が最適化されているので、配線基板２Ｃの半導体素子３側の面上に補強部材（スティフナー）をさらに設けなくても、配線基板２Ｃの反りを効果的に防止することができる。そのため、半導体パッケージ１Ｃの構成が簡単となる。 In the semiconductor package 1C, since the wiring board 2C is sandwiched between the semiconductor element 3 and the reinforcing member 5C, the wiring board 2C is more strongly reinforced and the thermal expansion difference between both surfaces of the wiring board 2C is increased. Can be suppressed. In particular, since the area of the reinforcing member 5C is optimized, warping of the wiring board 2C can be effectively prevented without further providing a reinforcing member (stiffener) on the surface of the wiring board 2C on the semiconductor element 3 side. be able to. Therefore, the configuration of the semiconductor package 1C is simplified.
　また、配線基板２Ｃ自体の剛性を高める必要がなく、配線基板２Ｃの厚さを薄くすることができるので、配線基板２Ｃの厚さ方向での熱伝導性を高めることができる。そのため、半導体パッケージ１Ｃは、半導体素子３からの熱を配線基板２Ｃを介して逃すことができ、放熱性に優れる。また、補強部材５Ｃの構成材料を適宜選択することにより、半導体パッケージ１Ｃの放熱性を高めることもできる。 Further, it is not necessary to increase the rigidity of the wiring board 2C itself, and the thickness of the wiring board 2C can be reduced, so that the thermal conductivity in the thickness direction of the wiring board 2C can be increased. Therefore, the semiconductor package 1C can release heat from the semiconductor element 3 through the wiring board 2C, and is excellent in heat dissipation. Moreover, the heat dissipation of the semiconductor package 1C can be improved by appropriately selecting the constituent material of the reinforcing member 5C.
　このような半導体パッケージ１Ｃの優れた放熱性も相俟って、配線基板２Ｃと半導体素子３との熱膨張係数差に起因する配線基板２Ｃの反りを効果的に抑制または防止することができる。その結果、半導体パッケージ１Ｃの電気的な接続信頼性を優れたものとすることができる。 Combined with such excellent heat dissipation of the semiconductor package 1C, it is possible to effectively suppress or prevent the warpage of the wiring board 2C due to the difference in thermal expansion coefficient between the wiring board 2C and the semiconductor element 3. As a result, the electrical connection reliability of the semiconductor package 1C can be improved.
　（半導体パッケージ１Ｃの製造方法）
　以上説明したような半導体パッケージ１Ｃは、例えば、以下のようにして製造することができる。 (Manufacturing method of semiconductor package 1C)
The semiconductor package 1C as described above can be manufactured, for example, as follows.
　以下、図１３に基づき、半導体パッケージ１Ｃの製造方法の一例を簡単に説明する。
　［１］
　まず、図１３（ａ）に示すように、金属層２２１Ａとプリプレグ２１１Ａとの積層体を用意する。 Hereinafter, an example of a method of manufacturing the semiconductor package 1C will be briefly described with reference to FIG.
[1]
First, as shown in FIG. 13A, a laminate of a metal layer 221A and a prepreg 211A is prepared.
　ここで、プリプレグ２１１Ａは、前述した配線基板２Ｃの絶縁層２１１を形成するためのものであり、前述した絶縁層２１１の樹脂組成物の未硬化物（半硬化物）が基材に含浸してなるものである。 Here, the prepreg 211A is for forming the insulating layer 211 of the wiring board 2C described above, and the base material is impregnated with the uncured product (semi-cured product) of the resin composition of the insulating layer 211 described above. It will be.
　また、金属層２２１Ａは、前述した配線基板２Ｃの導体パターン２２１を形成するためのものであり、導体パターン２２１の構成材料と同様の材料で構成されている。 The metal layer 221A is for forming the conductor pattern 221 of the wiring board 2C described above, and is made of the same material as the constituent material of the conductor pattern 221.
　［２］
　次に、図１３（ｂ）に示すように、プリプレグ２１１Ａに貫通孔２１１１（ビアホール）を形成する。 [2]
Next, as shown in FIG. 13B, a through hole 2111 (via hole) is formed in the prepreg 211A.
　貫通孔２１１１の形成方法としては、特に限定されないが、例えば、レーザーを照射することにより形成することができる。 The formation method of the through-hole 2111 is not particularly limited, but can be formed by, for example, laser irradiation.
　ここで、レーザーとしては、例えばＣＯ２レーザー、ＵＶ－ＹＡＧレーザー等を用いることができる。 Here, as the laser, for example, a CO 2 laser, a UV-YAG laser, or the like can be used.
　なお、貫通孔２１１１は、例えば、ドリル等の機械加工によって形成することもできる。 In addition, the through-hole 2111 can be formed by machining such as a drill, for example.
　［３］
　次に、図１３（ｃ）に示すように、貫通孔２１１１内に導体ポスト２３１を形成する。 [3]
Next, as shown in FIG. 13C, a conductor post 231 is formed in the through hole 2111.
　導体ポスト２３１の形成方法としては、特に限定されないが、例えば、導電性ペーストを充填する方法、無電解めっきにより埋め込む方法、電解めっきにより埋め込む方法等を用いることができる。 The method for forming the conductor post 231 is not particularly limited. For example, a method of filling a conductive paste, a method of embedding by electroless plating, a method of embedding by electrolytic plating, or the like can be used.
　［４］
　次に、図１３（ｄ）に示すように、金属層２２１Ａをパターンニングすることにより、導体パターン２２１を形成する。 [4]
Next, as shown in FIG. 13D, the conductor layer 221 is formed by patterning the metal layer 221A.
　かかるパターンニングの方法としては、特に限定されないが、エッチングが好適に用いられる。 Such a patterning method is not particularly limited, but etching is preferably used.
　以上のようにして、絶縁層２１１、導体パターン２２１および導体ポスト２３１が形成される。 As described above, the insulating layer 211, the conductor pattern 221 and the conductor post 231 are formed.
　［５］
　次に、上記工程［１］～［４］と同様にして、絶縁層２１２、２１３、２１４、２１５および導体パターン２２２、２２３、２２４を形成するためのプリプレグおよび金属層からなる積層体をそれぞれ用意し、導体パターン２２２、２２３、２２４および導体ポスト２３２、２３３、２３４を形成する。その後、絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを硬化（完全硬化）させて、図１４（ｅ）に示すように、配線基板２Ｃを得る。 [5]
Next, in the same manner as in the above steps [1] to [4], prepregs for forming the insulating layers 212, 213, 214, 215 and the conductor patterns 222, 223, 224 and laminates made of metal layers are respectively prepared. Then, conductor patterns 222, 223, and 224 and conductor posts 232, 233, and 234 are formed. Thereafter, the prepreg for the insulating layers 211, 212, 213, 214, and 215 is cured (completely cured) to obtain the wiring board 2C as shown in FIG.
　絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを積層する方法としては、例えば、真空プレス、ラミネート等が挙げられる。これらの中でも真空プレスによる接合方法が好ましい。これにより、絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグの密着強度を向上することができる。 Examples of the method for laminating the prepreg for the insulating layers 211, 212, 213, 214, and 215 include a vacuum press and a laminate. Among these, the joining method by a vacuum press is preferable. Thereby, the adhesion strength of the prepreg for the insulating layers 211, 212, 213, 214, and 215 can be improved.
　絶縁層２１１、２１２、２１３、２１４、２１５のためのプリプレグを硬化させる方法としては、特に限定されないが、例えば、熱処理が好適に用いられる。 The method for curing the prepreg for the insulating layers 211, 212, 213, 214, and 215 is not particularly limited, but for example, heat treatment is preferably used.
　［６］
　次に、配線基板２Ｃの下面に、絶縁材８１Ａを塗布した後、金属ボール（半田ボール）７１Ａを半田リフローにより半田接合する。これにより、金属バンプ７１および絶縁材８１が形成される。 [6]
Next, after applying an insulating material 81A to the lower surface of the wiring board 2C, a metal ball (solder ball) 71A is soldered by solder reflow. Thereby, the metal bump 71 and the insulating material 81 are formed.
　かかる半田接合は、特に限定されないが、配線基板２Ｃの下面に各金属バンプ７１が当接するように配置し、その状態で、例えば２００～２８０℃×１０～６０秒間加熱することにより行うことができる。 Such solder bonding is not particularly limited, but can be performed by placing each metal bump 71 in contact with the lower surface of the wiring board 2C and heating in that state, for example, 200 to 280 ° C. × 10 to 60 seconds. .
　また、絶縁材８１Ａは、前述した絶縁材８１を形成するためのものであり、例えば、加熱により硬化するものである。 Also, the insulating material 81A is for forming the above-described insulating material 81, and is cured by heating, for example.
　絶縁材８１を形成するに際しては、例えば、図１３（ｆ）に示すように、絶縁材８１Ａを配線基板２Ｃの下面に塗布し、前述したような半田接合の後、加熱により絶縁材８１Ａを硬化させることにより、絶縁材８１を得る。 When forming the insulating material 81, for example, as shown in FIG. 13F, the insulating material 81A is applied to the lower surface of the wiring board 2C, and after the solder bonding as described above, the insulating material 81A is cured by heating. By doing so, the insulating material 81 is obtained.
　このようにして得られた絶縁材８１は、前述したように金属バンプ７１の周囲を囲むように形成される。 The insulating material 81 thus obtained is formed so as to surround the periphery of the metal bump 71 as described above.
　このとき、絶縁材８１Ａは、半田接合時にフラックスとして機能し、且つ、金属ボール７１Ａとの界面張力により半田接合部周辺をリング状に補強する形状で硬化する。 At this time, the insulating material 81A functions as a flux at the time of solder joining, and is cured in a shape that reinforces the periphery of the solder joint portion in a ring shape by interfacial tension with the metal ball 71A.
　［７］
　次に、図１３（ｇ）に示すように、配線基板２Ｃの下面に、補強部材５Ｃを接合する。また、配線基板２Ｃの上面に、アンダーフィル材を塗布した後、半導体素子３を金属バンプ３１を介して半田リフローにより接合する。なお、この場合、アンダーフィル材として前述した絶縁材８１と同じようなフラックス活性のある樹脂を用いる。また、半導体素子３を搭載し、フラックスあるいは半田ペースト等を用いてリフローにより半導体素子３を配線基板２Ｃに接合させた後、通常のキャピラリーアンダーフィル材を配線基板２Ｃと半導体素子３との間に充填・硬化させることもできる。
　以上のようにして、半導体パッケージ１Ｃが得られる。 [7]
Next, as shown in FIG. 13G, the reinforcing member 5C is joined to the lower surface of the wiring board 2C. In addition, after applying an underfill material to the upper surface of the wiring board 2C, the semiconductor element 3 is joined by solder reflow through the metal bumps 31. In this case, a resin having flux activity similar to that of the insulating material 81 described above is used as the underfill material. Also, after mounting the semiconductor element 3 and bonding the semiconductor element 3 to the wiring board 2C by reflow using a flux or solder paste, a normal capillary underfill material is placed between the wiring board 2C and the semiconductor element 3. It can also be filled and cured.
The semiconductor package 1C is obtained as described above.
（半導体装置）
　図１４は、本発明の第５実施形態に係る半導体装置１００Ｃを模式的に示す断面図である。
　図１４に示すように、半導体装置１００Ｃは、マザーボード（基板）２００と、このマザーボード２００に搭載された半導体パッケージ１Ｃとを有している。 (Semiconductor device)
FIG. 14 is a cross-sectional view schematically showing a semiconductor device 100C according to the fifth embodiment of the present invention.
As illustrated in FIG. 14, the semiconductor device 100 </ b> C includes a mother board (substrate) 200 and a semiconductor package 1 </ b> C mounted on the mother board 200.
　このような半導体装置１００Ｃにおいては、半導体パッケージ１Ｃの金属バンプ７１がマザーボード２００の端子（図示せず）に接合されている。これにより、半導体パッケージ１Ｃとマザーボード２００とが電気的に接続され、これらの間で電気的信号の伝送が行われる。また、この接合部を介して、半導体パッケージ１Ｃの熱をマザーボード２００へ逃すことができる。 In such a semiconductor device 100C, the metal bumps 71 of the semiconductor package 1C are joined to terminals (not shown) of the mother board 200. Thereby, the semiconductor package 1C and the mother board 200 are electrically connected, and electrical signals are transmitted between them. Further, the heat of the semiconductor package 1 </ b> C can be released to the mother board 200 through this joint.
　以上説明したような半導体装置１００Ｃによれば、前述したような放熱性および信頼性に優れた半導体パッケージ１Ｃを備えるので、信頼性に優れる。 According to the semiconductor device 100C as described above, since the semiconductor package 1C having excellent heat dissipation and reliability as described above is provided, the reliability is excellent.
　以上、本発明の半導体パッケージおよび半導体装置を、図示の実施形態に基づいて説明したが、本発明はこれらに限定されるものでない。 As mentioned above, although the semiconductor package and semiconductor device of this invention were demonstrated based on embodiment of illustration, this invention is not limited to these.
　また、補強部材５Ｃに形成される開口部は、各金属バンプ７１と一対一で対応していなくてもよい。すなわち、補強部材５Ｃには、複数の金属バンプ７１に対して１つが対応するように、開口部が形成されていてもよい。 Further, the opening formed in the reinforcing member 5C may not correspond to each metal bump 71 on a one-to-one basis. That is, openings may be formed in the reinforcing member 5 </ b> C so that one corresponds to the plurality of metal bumps 71.
　また、前述した実施形態では平面視での補強部材５Ｃの外周縁５ｃの形状が四角状をなしていたが、これに限定されず、例えば、補強部材５Ｃよりも外側に位置する金属バンプ７１の形状や配置等に沿った形状をなしていてもよい。 In the above-described embodiment, the shape of the outer peripheral edge 5c of the reinforcing member 5C in a plan view is a square shape. However, the shape is not limited to this. For example, the metal bump 71 positioned outside the reinforcing member 5C A shape along the shape or arrangement may be formed.
　本発明の半導体パッケージによれば、補強部材を配線基板の半導体素子と反対側の面に接合することにより、配線基板は半導体素子と補強部材とに挟持された状態となるため、配線基板の両面の熱膨張差を防止または抑制することができる。特に、補強部材は、金属バンプ間にも及ぶように設けられているので、配線基板を強固に補強することができる。 According to the semiconductor package of the present invention, the wiring board is sandwiched between the semiconductor element and the reinforcing member by bonding the reinforcing member to the surface of the wiring board opposite to the semiconductor element. The difference in thermal expansion can be prevented or suppressed. In particular, since the reinforcing member is provided so as to extend between the metal bumps, the wiring board can be strongly reinforced.
　このようなことから、配線基板と半導体素子との熱膨張係数差に起因する配線基板の反りを抑制または防止することができる。 For this reason, it is possible to suppress or prevent the warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element.
　また、配線基板自体の剛性を高める必要がなく、配線基板の厚さを薄くすることができるので、配線基板の厚さ方向での熱伝導性を高めることができる。そのため、本発明の半導体パッケージは、半導体素子からの熱を配線基板を介して逃すことができ、放熱性に優れる。これにより、半導体素子および配線基板の昇温を抑えることができるので、この点でも、配線基板と半導体素子との熱膨張係数差に起因する配線基板の反りを抑制または防止することができる。 In addition, since it is not necessary to increase the rigidity of the wiring board itself and the thickness of the wiring board can be reduced, the thermal conductivity in the thickness direction of the wiring board can be increased. Therefore, the semiconductor package of the present invention can release heat from the semiconductor element through the wiring board, and is excellent in heat dissipation. Thereby, since the temperature rise of the semiconductor element and the wiring board can be suppressed, the warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the semiconductor element can also be suppressed or prevented.
　また、本発明の半導体装置によれば、前述したような半導体パッケージを備えるので、信頼性に優れる。 Moreover, according to the semiconductor device of the present invention, since the semiconductor package as described above is provided, the reliability is excellent.
１　　　　半導体パッケージ
１Ａ　　　半導体パッケージ
１Ｂ　　　半導体パッケージ
１Ｃ　　　半導体パッケージ
２　　　　配線基板
２Ａ　　　配線基板
２Ｃ　　　配線基板
３　　　　半導体素子
３Ａ　　　半導体素子
３ｃ　　　半導体素子の外周縁
４　　　　第１補強部材
５　　　　第２補強部材
５Ａ　　　補強部材
５Ｃ　　　補強部材
５ｃ　　　補強部材の外周縁
６　　　　熱伝導性材料
２１　　　　基板
２１Ａ　　　基板
２１Ｃ　　　基板
２４　　　　伝熱ポスト
３１　　　　金属バンプ
３２　　　　接着層
３３　　　　外周面
４１　　　　内周面
５１　　　　開口部
５１Ｃ　　　開口部
５２　　　　部分（枠部）
５２Ｃ　　　部分（枠部）
５３　　　　部分
５３Ｃ　　　部分
７１　　　　金属バンプ
７１Ａ　　　　金属ボール
８１　　　　絶縁材
８１Ａ　　　　絶縁材
９１　　　　伝熱バンプ
９１Ａ　　　金属ボール
１００　　　　半導体装置
１００Ｃ　　　半導体装置
２００　　　　マザーボード
２１１　　　　絶縁層
２１１Ａ　　　　プリプレグ
２１２　　　　絶縁層
２１３　　　　絶縁層
２１４　　　　絶縁層
２１５　　　　絶縁層
２２１　　　　導体パターン
２２１Ａ　　　　金属層
２２２　　　　導体パターン
２２３　　　　導体パターン
２２４　　　　導体パターン
２３１　　　　導体ポスト
２３２　　　　導体ポスト
２３３　　　　導体ポスト
２３４　　　　導体ポスト
２１１１　　　　貫通孔
Ｐ１、Ｐ２　　　最下点
Ｓ１　　　　　　半導体素子の平面視での面積
Ｓ２　　　　　　補強部材の平面視での外周縁で囲まれた領域内の面積 DESCRIPTION OF SYMBOLS 1 Semiconductor package 1A Semiconductor package 1B Semiconductor package 1C Semiconductor package 2 Wiring board 2A Wiring board 2C Wiring board 3 Semiconductor element 3A Semiconductor element 3c The outer periphery 4 of a semiconductor element 1st reinforcement member 5 2nd reinforcement member 5A Reinforcement member 5c Outer peripheral edge 6 of reinforcing member Thermally conductive material 21 Substrate 21A Substrate 21C Substrate 24 Heat transfer post 31 Metal bump 32 Adhesive layer 33 Outer peripheral surface 41 Inner peripheral surface 51 Opening 51C Opening 52 Part (frame)
52C part (frame part)
53 part 53C part 71 metal bump 71A metal ball 81 insulation material 81A insulation material 91 heat transfer bump 91A metal ball 100 semiconductor device 100C semiconductor device 200 motherboard 211 insulation layer 211A prepreg 212 insulation layer 213 insulation layer 214 insulation layer 215 insulation layer 221 conductor Pattern 221A Metal layer 222 Conductor pattern 223 Conductor pattern 224 Conductor pattern 231 Conductor post 232 Conductor post 233 Conductor post 234 Conductor post 2111 Through hole P1, P2 Bottom point S1 Area S2 of semiconductor element in plan view S2 In plan view of reinforcing member Area within the area surrounded by the outer periphery of

Claims (26)

  1. 　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
    　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
    　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい補強部材とを有し、
    　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、
    　前記補強部材は、前記各金属バンプに非接触で前記金属バンプ同士の間に位置する部分を有することを特徴とする半導体パッケージ。     A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
    A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
    A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
    A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate,
    The said reinforcement member has a part located between the said metal bumps in non-contact with each said metal bump, The semiconductor package characterized by the above-mentioned.
  2. 　前記補強部材は、複数の開口部を有し、
    　前記補強部材の前記開口部同士の間の部分が前記各金属バンプに非接触で前記金属バンプ同士の間に位置する請求項１に記載の半導体パッケージ。     The reinforcing member has a plurality of openings,
    2. The semiconductor package according to claim 1, wherein a portion between the openings of the reinforcing member is located between the metal bumps without contacting the metal bumps.
  3. 　前記補強部材は、前記半導体素子との熱膨張係数差が７ｐｐｍ／℃以下である請求項１または２に記載の半導体パッケージ。 The semiconductor package according to claim 1 or 2, wherein the reinforcing member has a difference in coefficient of thermal expansion from the semiconductor element of 7 ppm / ° C or less.
  4. 　前記補強部材は、金属材料で構成されている請求項１ないし３のいずれかに記載の半導体パッケージ。 4. The semiconductor package according to claim 1, wherein the reinforcing member is made of a metal material.
  5. 　前記金属材料は、Ｆｅ－Ｎｉ系合金である請求項４に記載の半導体パッケージ。 The semiconductor package according to claim 4, wherein the metal material is an Fe-Ni alloy.
  6. 　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
    　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
    　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい第２補強部材と、
    　前記第２補強部材の前記基板と反対側の面に設けられ、前記基板よりも高い熱伝導性を有する伝熱バンプとを有することを特徴とする半導体パッケージ。     A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
    A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
    A second reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
    A semiconductor package comprising heat transfer bumps provided on a surface of the second reinforcing member opposite to the substrate and having higher thermal conductivity than the substrate.
  7. 　前記伝熱バンプは、金属材料で構成されている請求項６に記載の半導体パッケージ。 The semiconductor package according to claim 6, wherein the heat transfer bump is made of a metal material.
  8. 　前記伝熱バンプは、その表面にメッキ処理が施されている請求項６または７に記載の半導体パッケージ。 The semiconductor package according to claim 6 or 7, wherein a surface of the heat transfer bump is plated.
  9. 　前記伝熱バンプは、複数設けられている請求項６ないし８のいずれかに記載の半導体パッケージ。 9. The semiconductor package according to claim 6, wherein a plurality of the heat transfer bumps are provided.
  10. 　前記複数の伝熱バンプは、前記第２補強部材の縁部に沿って互いに離間して設けられている請求項９に記載の半導体パッケージ。 10. The semiconductor package according to claim 9, wherein the plurality of heat transfer bumps are provided apart from each other along an edge of the second reinforcing member.
  11. 　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、
    　前記第２補強部材は、前記各金属バンプに非接触で前記各金属バンプを囲むように形成された複数の開口部を有する請求項６ないし１０のいずれかに記載の半導体パッケージ。     A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate,
    The semiconductor package according to claim 6, wherein the second reinforcing member has a plurality of openings formed so as to surround the metal bumps without contacting the metal bumps.
  12. 　前記基板の前記一方の面の、前記半導体素子が接合されていない部分に接合され、前記基板よりも熱膨張係数の小さい第１補強部材を更に有している請求項６ないし１１のいずれかに記載の半導体パッケージ。 12. The device according to claim 6, further comprising a first reinforcing member bonded to a portion of the one surface of the substrate where the semiconductor element is not bonded, and having a smaller coefficient of thermal expansion than the substrate. The semiconductor package described.
  13. 　前記第１補強部材と前記第２補強部材とを接続し、前記基板よりも熱伝導性の高い熱伝導部を更に有する請求項１２に記載の半導体パッケージ。 13. The semiconductor package according to claim 12, further comprising a heat conducting portion that connects the first reinforcing member and the second reinforcing member and has higher thermal conductivity than the substrate.
  14. 　前記熱伝導部は、前記基板をその厚さ方向に貫通するものである請求項１３に記載の半導体パッケージ。 14. The semiconductor package according to claim 13, wherein the heat conducting portion penetrates the substrate in the thickness direction.
  15. 　前記第１補強部材および前記第２補強部材は、それぞれ、板状をなしている請求項１３または１４に記載の半導体パッケージ。 The semiconductor package according to claim 13 or 14, wherein each of the first reinforcing member and the second reinforcing member has a plate shape.
  16. 　前記第１補強部材および前記第２補強部材は、それぞれ、前記半導体素子との熱膨張係数差が７ｐｐｍ／℃以下である請求項１２ないし１５のいずれかに記載の半導体パッケージ。 16. The semiconductor package according to claim 12, wherein each of the first reinforcing member and the second reinforcing member has a difference in thermal expansion coefficient from the semiconductor element of 7 ppm / ° C. or less.
  17. 　前記第１補強部材および前記第２補強部材は、それぞれ、金属材料で構成されている請求項１２ないし１６のいずれかに記載の半導体パッケージ。 The semiconductor package according to any one of claims 12 to 16, wherein each of the first reinforcing member and the second reinforcing member is made of a metal material.
  18. 　基板と、前記基板の一方の面側に設けられた第１導体パターンと、前記基板の他方の面側に設けられ、前記第１導体パターンと電気的に接続された第２導体パターンとを備える配線基板と、
    　前記基板の前記一方の面に接合され、前記第１導体パターンに電気的に接続される半導体素子と、
    　前記基板の前記他方の面に接合され、前記基板よりも熱膨張係数の小さい補強部材とを有し、
    　前記半導体素子の平面視での面積をＳ１とし、前記補強部材の平面視での外周縁で囲まれた領域内の面積をＳ２としたときに、
    　Ｓ２／Ｓ１が０．６４以上２．２５以下であることを特徴とする半導体パッケージ。     A substrate, a first conductor pattern provided on one surface side of the substrate, and a second conductor pattern provided on the other surface side of the substrate and electrically connected to the first conductor pattern. A wiring board;
    A semiconductor element bonded to the one surface of the substrate and electrically connected to the first conductor pattern;
    A reinforcing member bonded to the other surface of the substrate and having a smaller coefficient of thermal expansion than the substrate;
    When the area of the semiconductor element in plan view is S1, and the area in the region surrounded by the outer periphery of the reinforcing member in plan view is S2,
    S2 / S1 is 0.64 or more and 2.25 or less, The semiconductor package characterized by the above-mentioned.
  19. 　平面視にて、前記補強部材の外周縁は、前記半導体素子の外周縁と一致またはそれよりも外側に位置している請求項１８に記載の半導体パッケージ。 The semiconductor package according to claim 18, wherein the outer peripheral edge of the reinforcing member coincides with or is located outside the outer peripheral edge of the semiconductor element in a plan view.
  20. 　前記第２導体パターンの前記基板と反対側の面には、複数の金属バンプが接合され、
    　前記補強部材は、前記各金属バンプに非接触で前記金属バンプ同士の間に位置する部分を有する請求項１８または１９に記載の半導体パッケージ。     A plurality of metal bumps are bonded to the surface of the second conductor pattern opposite to the substrate,
    20. The semiconductor package according to claim 18, wherein the reinforcing member has a portion located between the metal bumps without contacting the metal bumps.
  21. 　前記補強部材は、複数の開口部を有し、
    　前記補強部材の前記開口部同士の間の部分が前記金属バンプ同士の間に位置する請求項２０に記載の半導体パッケージ。     The reinforcing member has a plurality of openings,
    21. The semiconductor package according to claim 20, wherein a portion between the openings of the reinforcing member is located between the metal bumps.
  22. 　前記補強部材は、前記基板よりも熱膨張係数が小さい請求項１８ないし２１のいずれかに記載の半導体パッケージ。 The semiconductor package according to any one of claims 18 to 21, wherein the reinforcing member has a smaller coefficient of thermal expansion than the substrate.
  23. 　前記補強部材の熱膨張係数は、３ｐｐｍ／℃以上１０ｐｐｍ／℃以下である請求項２２に記載の半導体パッケージ。 The semiconductor package according to claim 22, wherein the thermal expansion coefficient of the reinforcing member is 3 ppm / ° C or more and 10 ppm / ° C or less.
  24. 　前記補強部材は、前記半導体素子との熱膨張係数差が７ｐｐｍ／℃以下である請求項１８ないし２３のいずれかに記載の半導体パッケージ。 24. The semiconductor package according to claim 18, wherein the reinforcing member has a difference in thermal expansion coefficient with the semiconductor element of 7 ppm / ° C. or less.
  25. 　前記補強部材は、板状をなしている請求項１８ないし２４のいずれかに記載の半導体パッケージ。 25. The semiconductor package according to claim 18, wherein the reinforcing member has a plate shape.
  26. 　請求項１ないし２５のいずれかに記載の半導体パッケージを備えることを特徴とする半導体装置。 A semiconductor device comprising the semiconductor package according to any one of claims 1 to 25.
PCT/JP2011/068881 2010-08-30 2011-08-22 Semiconductor package and semiconductor device WO2012029579A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012531805A JPWO2012029579A1 (en) 2010-08-30 2011-08-22 Semiconductor package and semiconductor device

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2010-192905 2010-08-30
JP2010192904 2010-08-30
JP2010-192904 2010-08-30
JP2010192905 2010-08-30
JP2010-210158 2010-09-17
JP2010210158 2010-09-17

Publications (1)

Publication Number Publication Date
WO2012029579A1 true WO2012029579A1 (en) 2012-03-08

Family

ID=45772677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/068881 WO2012029579A1 (en) 2010-08-30 2011-08-22 Semiconductor package and semiconductor device

Country Status (3)

Country Link
JP (1) JPWO2012029579A1 (en)
TW (1) TW201216434A (en)
WO (1) WO2012029579A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023148840A1 (en) * 2022-02-02 2023-08-10 キオクシア株式会社 Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117703A (en) * 2007-11-08 2009-05-28 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
JP2009252859A (en) * 2008-04-03 2009-10-29 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP2009260335A (en) * 2008-03-28 2009-11-05 Ngk Spark Plug Co Ltd Multi-layer wiring board and manufacturing method thereof
JP2010103516A (en) * 2008-09-29 2010-05-06 Ngk Spark Plug Co Ltd Wiring board with reinforcement
JP2010129810A (en) * 2008-11-28 2010-06-10 Fujitsu Ltd Semiconductor device mounting board and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117703A (en) * 2007-11-08 2009-05-28 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same
JP2009260335A (en) * 2008-03-28 2009-11-05 Ngk Spark Plug Co Ltd Multi-layer wiring board and manufacturing method thereof
JP2009252859A (en) * 2008-04-03 2009-10-29 Shinko Electric Ind Co Ltd Semiconductor device and method of manufacturing the same
JP2010103516A (en) * 2008-09-29 2010-05-06 Ngk Spark Plug Co Ltd Wiring board with reinforcement
JP2010129810A (en) * 2008-11-28 2010-06-10 Fujitsu Ltd Semiconductor device mounting board and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023148840A1 (en) * 2022-02-02 2023-08-10 キオクシア株式会社 Semiconductor device

Also Published As

Publication number Publication date
TW201216434A (en) 2012-04-16
JPWO2012029579A1 (en) 2013-10-28

Similar Documents

Publication Publication Date Title
JP6048050B2 (en) Semiconductor package and semiconductor device
US8035035B2 (en) Multi-layer wiring board and method of manufacturing the same
JP5994776B2 (en) Semiconductor package, semiconductor device, and manufacturing method of semiconductor package
US9456492B2 (en) Printed circuit board with warpage prevention layer
US8110754B2 (en) Multi-layer wiring board and method of manufacturing the same
US8390106B2 (en) Circuit board with built-in semiconductor chip and method of manufacturing the same
WO2012029549A1 (en) Semiconductor package, and semiconductor device
EP2866257B1 (en) Printed circuit board and manufacturing method thereof and semiconductor pacakge using the same
JP5304940B2 (en) Manufacturing method of semiconductor package
JP2017108019A (en) Wiring board, semiconductor package, semiconductor device, method for manufacturing wiring board and method for manufacturing semiconductor package
JPWO2007135768A1 (en) Semiconductor device
US20140284820A1 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
WO2012035972A1 (en) Semiconductor package and semiconductor device
JP2004311598A (en) Substrate with reinforcement, wiring board consisting of semiconductor element, reinforcement and substrate
JP2009267149A (en) Part built-in wiring board, and method for manufacturing part built-in wiring board
JP2013084861A (en) Semiconductor package and semiconductor device
WO2012029579A1 (en) Semiconductor package and semiconductor device
WO2012029526A1 (en) Semiconductor package and semiconductor device
JP3554249B2 (en) Adhesive and electronic component using the same
JP2013080806A (en) Manufacturing method of reinforcing member
EP3512315B1 (en) Printed wiring board and printed circuit board
JP2013080804A (en) Manufacturing method of reinforcing member
JP2013080805A (en) Manufacturing method of reinforcing member
JP2013080802A (en) Manufacturing method of reinforcing member
JP2013055290A (en) Semiconductor package and semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11821596

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2012531805

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11821596

Country of ref document: EP

Kind code of ref document: A1