WO2012035730A1 - 画像復号装置、画像符号化装置、それらの方法、プログラム、集積回路およびトランスコード装置 - Google Patents
画像復号装置、画像符号化装置、それらの方法、プログラム、集積回路およびトランスコード装置 Download PDFInfo
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- WO2012035730A1 WO2012035730A1 PCT/JP2011/005074 JP2011005074W WO2012035730A1 WO 2012035730 A1 WO2012035730 A1 WO 2012035730A1 JP 2011005074 W JP2011005074 W JP 2011005074W WO 2012035730 A1 WO2012035730 A1 WO 2012035730A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
- H04N19/16—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter for a given display mode, e.g. for interlaced or progressive display mode
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/40—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/593—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/80—Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
- H04N19/82—Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
Definitions
- the present invention relates to an image decoding apparatus for decoding a coded image, an image coding apparatus for coding an image, and the like, and in particular, an image decoding apparatus for executing decoding in parallel and an image for executing coding in parallel.
- the present invention relates to an encoding apparatus and the like.
- An image coding apparatus for coding a moving picture divides each picture constituting the moving picture into macroblocks of 16 ⁇ 16 pixels, and codes the moving picture for each macroblock. Then, the image coding apparatus generates a coded stream indicating a coded moving image. The image decoding apparatus decodes this encoded stream in units of macroblocks, and reproduces each picture of the original moving image.
- ITU-T International Telecommunication Union Telecommunication Standardization Sector
- H.1 as one of the conventional coding schemes.
- H.264 standards see, for example, Non-Patent Document 1.
- H. In the H.264 standard variable-length codes are adopted, and in variable-length codes, each macroblock is encoded to a variable length.
- H. According to the H.264 standard in each process such as in-plane prediction, motion vector calculation, and deblock filter processing, data is encoded between a macroblock to be encoded or to be decoded and another macroblock adjacent to the macroblock. There is a dependency.
- FIG. 47 is a diagram showing the dependency of data.
- the pixels of the macroblocks MBa to MBd adjacent to the decoding target macroblock MBx are used.
- motion vectors of macroblocks MBa to MBc adjacent to the macroblock MBx to be decoded are used for calculating a motion vector of the macroblock MBx to be decoded.
- the pixels of the macroblocks MBa and MBb adjacent to the current block MBx to be decoded are used.
- FIG. 48A is a configuration diagram showing a configuration of the image decoding device in Patent Document 1 above.
- the stream analysis unit 1100 supplies the encoded stream to the two decoding units 1300a and 1300b
- the macroblock pipeline control unit 1200 controls the pipeline operation of the two decoding units 1300a and 1300b.
- the decoding units 1300a and 1300b respectively include a VCL 1301 that performs variable-length decoding, a TRF 1302 that performs inverse quantization and inverse frequency conversion, and an MC 1303 that performs motion compensation. That is, the decoding units 1300 a and 1300 b respectively perform variable length decoding, inverse quantization and inverse frequency conversion, and motion compensation to decode a macroblock to be decoded (inter prediction prediction).
- FIG. 48B is an explanatory diagram for describing an operation of the image decoding device 1000 in Patent Document 1 above.
- the macroblock pipeline control unit 1200 divides the position of the macroblocks decoded by the decoding units 1300a and 1300b into two macroblocks in the horizontal direction (one macroblock in the vertical direction). Shift. Furthermore, the macroblock pipeline control unit 1200 performs partial decoding processing on each of two decoding target macroblocks (processing of any one of variable length decoding, inverse quantization and inverse frequency conversion, and motion compensation) Are made to be executed by the decoding units 1300a and 1300b within each TS (time slot) time.
- the macroblock pipeline control unit 1200 operates so that the decoding units 1300a and 1300b decode one macroblock within a predetermined period, in other words, operates synchronously for each macroblock. , And control the decoding units 1300a and 1300b. As a result, decoding by parallel processing is performed while maintaining the data dependency.
- the image decoding apparatus 1000 of Patent Document 1 has a problem that the improvement of the decoding efficiency is hindered.
- the processes performed in parallel by the two decoding units 1300a and 1300b are variable-length decoding, inverse quantization, and inverse frequency conversion among the processes required for decoding. And motion compensation.
- the deblocking filter process is a process of changing not only the pixel value of the macro block to be processed processed by one decoding unit but also the pixel value of the macro block processed by the other decoding unit.
- processing such as the above-mentioned variable length decoding is performed on the macroblock to be decoded and the macroblocks around it, and the reconstructed image of those macroblocks is a frame. After being stored in memory, it is sequentially performed on individual macroblocks. As a result, it takes time for the deblocking filter processing, and other processing can not be performed during that time, so the overall decoding speed can not be sufficiently improved. As a result, the improvement of the decoding efficiency is hindered.
- the macroblocks processed by the two decoding units 1300a and 1300b are stored in the frame memory, and the macroblocks stored in the frame memory are read out and the deblock filter process is performed. Therefore, the frequency of access to the frame memory also increases.
- An object of the present invention is to solve the above-mentioned problems, and to provide an image decoding apparatus and an image encoding apparatus which improve the decoding efficiency or the coding efficiency and reduce the frequency of memory access. .
- an image decoding apparatus for decoding encoded image data, wherein the encoded image data includes an encoded picture, and the picture Is composed of a plurality of macroblock lines, and the macroblock lines are composed of a plurality of macroblocks arranged in a line, and the image decoding apparatus is configured to process at least one macroblock line that composes the picture.
- a division unit which divides the picture into first and second coded image data by assigning the at least one macroblock line to a part of the first or second coded image data; Macroblock lines adjacent to each other in the picture, included in each of the second encoded image data
- a first decoding unit for decoding data in a row and storing the decoded data in the frame storage unit, the first decoding unit using the second decoding result information stored in the information storage unit; 1 encoded image data is decoded, and a part of the information generated by the decoding is stored in the information storage unit as first decoding result information, and the decoding target included in the first encoded image data
- decoding a macroblock at least a portion of another macroblock decoded by the second decoding unit belonging to another macroblock line adjacent to the macroblock line to which the macroblock to be decoded belongs
- the image processing is performed on the second decoding result information and the macroblock to be decoded, and the image processing-processed macroblock to be decoded and the second decoding result information
- the first decoding result is at least a part of another macroblock decoded by the first decoding unit belonging to another macroblock line adjacent to the macroblock line to which the macroblock to be decoded belongs.
- Image processing is performed on the information and the macroblock to be decoded, and the macroblock to be decoded and the first decoded result information subjected to image processing At least a part of each is stored in the frame storage unit.
- the first decoding unit changes, by performing the image processing, pixel values of at least a part of the decoded other macroblocks indicated by the second decoding result information;
- the second decoding unit changes the pixel value of at least a part of the decoded other macroblock indicated by the first decoding result information by performing the image processing.
- the first decoding unit performs deblocking filter processing as the image processing on the second decoding result information and the macro block to be decoded, and the second decoding unit A deblocking filter process is performed as the image process on the first decoding result information and the macro block to be decoded.
- image processing such as deblock filter processing performed across macroblock lines is also performed on the first and second encoded image data (division stream) in parallel, so that overall decoding can be performed. Speeding up can be sufficiently achieved, and as a result, decoding performance or decoding efficiency can be improved.
- the macroblock is decoded by the first or second decoding unit and stored in the frame storage unit (frame memory)
- deblocking filter processing is already performed on the macroblock. Therefore, after the macro block is stored in the frame storage unit, it is not necessary to read the macro block from the frame storage unit in order to perform the deblocking filter process. As a result, the frequency of access to the frame storage unit can be reduced.
- the coded image data (coded stream) is divided into first and second coded image data (divided streams), and the first and second codes are divided. Since the decoded image data is decoded in parallel by the first and second decoding units, the macro block pipeline control unit as described in Patent Document 1 for centrally controlling the decoding timing of each decoding unit is omitted. Can. Furthermore, even when the image decoding apparatus divides encoded image data into three or more pieces of data, and includes many decoding units for decoding those pieces of data in parallel, the macro as described in Patent Document 1 described above There is no need to lay a signal line between the block line control unit and each decoding unit, and the image decoding apparatus can be realized easily.
- the H the first and second decoding result information (peripheral information) required by the data dependency in the H.264 standard is transmitted and received between the first and second decoding units via the information storage unit (peripheral information memory). Be done. Therefore, if the first and second decoding units respectively store the first and second decoding result information required for decoding in the information storage unit, the first and second decoding units do not wait for the decoding by the other decoding unit. Decoding of the first or second encoded image data can be continuously performed using the stored first or second decoding result information. As a result, it is possible to suppress the occurrence of a time loss due to the interruption of decoding as in the image decoding device of Patent Document 1 above, and improve the decoding efficiency.
- the image decoding apparatus further includes the information storage unit having first and second information storage units, and the first decoding unit is configured to obtain the second decoding result from the first information storage unit.
- the information is read and used to decode the first encoded image data, and the first decoding result information is stored in the second information storage unit, and the second decoding unit is configured to store the second information storage.
- the second decoding result information is stored in the first information storage unit.
- the second decoding result information is read out from the storage unit and used for decoding the second encoded image data.
- the first and second information storage units are provided, the second decoding result information is stored in the first information storage unit, and the first decoding result information is stored in the second information storage unit. Therefore, access to each information storage unit from the first and second decoding units can be distributed. As a result, the access performance required for each of the first and second information storage units can be suppressed, and the image decoding apparatus can be easily realized.
- the division unit assigns the macroblock line to a part of the first or second encoded image data for each macroblock line to make the picture into the first and second encoded image data. It may be divided.
- the division unit performs, for each of two mutually adjacent macro block lines constituting the picture, the two macro blocks.
- the picture is divided by assigning a line to a portion of the first or second encoded image data.
- a picture is assigned to the first or second encoded image data for every two adjacent macroblock lines.
- the encoded image data of the MBAFF structure according to the H.264 standard can be properly decoded.
- the first and second decoding units perform decoding in synchronization with each other via the first and second information storage units.
- the first decoding unit stores the second decoding result information necessary for decoding a macroblock to be decoded in the first encoded image data. If not, the decoding of the macroblock to be decoded is awaited until the second decoding result information is stored, and if the second decoding result information is stored, the decoding of the macroblock to be decoded is performed.
- the first decoding result information necessary for decoding a macroblock to be decoded in the second encoded image data is stored in the second information storage unit. If not stored, the decoding target macroblock is waited for decoding until the first decoding result information is stored, and when the first decoding result information is stored, the decoding target macroblock is stored. Against to start decoding.
- each of the first and second decoding units decoding of the macroblock to be decoded is performed synchronously, and the decoding result information necessary for decoding the macroblock to be decoded is stored in the information storage unit Since the decoding of the macroblock to be decoded is started, it is possible to eliminate the idle time and efficiently decode the coded image data. Also, the operating frequency of each decoding unit can be suppressed.
- the image decoding apparatus further stores a first switch that switches information stored in the first information storage unit between first information and second information, and the second information storage unit. And a second switch for switching the information to the third information and the fourth information, and the information stored in the first information storage unit is switched to the first information by the first switch
- the first decoding unit When the information stored in the second information storage unit is switched to the third information by the second switch, the first decoding unit generates the first decoding result information.
- the second information storage unit stores the third information as the third information
- the second decoding unit stores the second decoding result information as the first information in the first information storage unit.
- the information stored in the first information storage unit is the first switch Therefore, when the information is switched to the second information and the information stored in the second information storage unit is switched to the fourth information by the second switch, the first decoding unit is: Furthermore, the second information is read from the first information storage unit and used for decoding of other encoded image data, and a part of the information generated by the decoding is used as the new second information. The second decoding unit further reads the fourth information from the second information storage unit and uses the fourth information for decoding the encoded image data, and is generated by the decoding. A part of the information is stored as new fourth information in the second information storage unit.
- the first and second encodings are performed.
- the image data is decoded in parallel and the information stored in the first and second information storage units is switched to the second and fourth information by the first and second switches, respectively.
- Data and other encoded image data are decoded simultaneously. Therefore, it is possible to switch between the process of dividing one encoded image data and decoding in parallel and the process of simultaneously decoding two independent encoded image data by the first and second switches. The convenience of the device can be improved.
- the image decoding apparatus further includes a switch configured to switch data to be divided by the dividing unit between the encoded image data and another encoded image data, and the dividing unit is configured to use the switch to When the data to be divided is switched to the coded image data, the picture of the coded image data is divided, and the data to be divided by the switch is the other coded image When switched to data, the picture of the other encoded image data is divided.
- the image decoding apparatus further reads a moving image which is the decoded first and second encoded image data from the frame storage unit, and the moving image is read at a frame rate set by a display device.
- the display unit further includes an output unit that thins out a picture included in the moving image and outputs the moving image from which the picture is thinned to the display device so as to be displayed.
- the encoded image data is decoded at high speed, the pictures included in the moving image generated by the decoding are thinned, and the moving image from which the pictures are thinned is output to the display device, thereby achieving fast forward reproduction. It is possible to smoothly display the moving image on the display device.
- the encoded image data is decoded by the two decoding units, so that a picture is decoded at, for example, a double frame rate.
- display device display of a picture at a normal frame rate is set.
- the picture of the moving image stored in the frame storage unit is 2 so that the moving image is displayed at the frame rate set in the display device. Since the image is thinned out and output at a rate of one, the moving image fast-forwarded as described above is displayed on the display device.
- the frame storage unit includes a first frame storage unit and a second frame storage unit
- the first decoding unit is a reference image to be referred to for decoding of the first encoded image data.
- the first decoding unit is a reference image to be referred to for decoding of the first encoded image data.
- the second decoding unit is configured to execute the second encoding.
- the reference image to be referred to for decoding the image data is read from the second frame storage unit, and the decoded second encoded image data is written to the first and second frame storage units.
- the first and second frame storage units are provided, the read destination of the reference image by the first decoding unit becomes the first frame storage unit, and the read destination of the reference image by the second decoding unit is the second Since the first and second decoding units distribute access to each frame storage unit, the transfer amount of reference image per frame storage unit can be reduced. As a result, the access performance required for each of the first and second frame storage units can be suppressed, the first and second frame storage units can be easily realized, and the image decoding apparatus can be realized at low cost. It will be possible to
- an image coding apparatus for coding image data, wherein the image data includes a picture, and the picture includes a plurality of pictures.
- the macroblock line is composed of a plurality of macroblocks arranged in a line, and the image coding apparatus is configured to frame the first and second image data included in the image data.
- First and second encoding units that generate first and second encoded image data by reading out from the storage unit and encoding in parallel, and the first and second encoding units generated by the first and second encoding units The first and second symbols such that macroblock lines included in each of the first and second encoded image data are adjacent to each other in the picture.
- the first encoding unit encodes the first image data using the second encoding result information stored in the information storage unit;
- the second encoding result information which is at least a part of another macroblock belonging to another macroblock line adjacent to the macroblock line to which the macroblock to be encoded belongs, and the macroblock to be encoded Image processing, and at least a part of each of the macroblock to be encoded subjected to the image processing and the second decoding result information is stored in the frame storage unit.
- the second encoding unit encodes the second image data using the first encoding result information stored in the information storage unit, and a part of information generated by the encoding Is stored in the information storage unit as the second encoding result information, and when the macro block to be encoded included in the second image data is encoded, the macro block to be encoded belongs.
- Image processing is performed on the first encoding result information, which is at least a part of another macroblock belonging to another macroblock line adjacent to a macroblock line, and the macroblock to be encoded; At least a part of each of the macroblock to be encoded subjected to image processing and the first decoding result information is stored in the frame storage unit.
- the macroblock is stored in the frame storage unit (frame memory) by the first or second encoding unit
- image processing such as deblock filter processing is already performed on the macroblock. . Therefore, after the macro block is stored in the frame storage unit, it is not necessary to read the macro block from the frame storage unit in order to perform image processing. As a result, the frequency of access to the frame storage unit can be reduced.
- the image decoding apparatus since the first and second image data included in the image data (image) are encoded and combined in parallel, the encoding by each encoding unit can be performed.
- the control unit that centrally controls the timing can be omitted.
- the image coding apparatus includes many coding units for coding a part of image data, it is necessary to lay out signal lines between the control unit and the coding units as described above. Instead, the image coding apparatus can be easily realized.
- the H the image coding apparatus according to an aspect of the present invention.
- the first and second encoding result information (peripheral information) required by the data dependency in the H.264 standard is transmitted between the first and second encoding units via the information storage unit (peripheral information memory). Sent and received. Therefore, if the first and second encoding units respectively store the first and second encoding result information required for encoding in the information storage unit, the encoding by the other encoding unit is performed.
- the encoding of the first or second image data can be continuously performed using the stored first or second encoding result information without waiting for. As a result, it is possible to suppress the occurrence of a time loss due to the interruption of the encoding, and to improve the encoding efficiency. Further, by operating a plurality of encoding units in parallel, encoding can be performed at high speed, and processing performance can be improved.
- the present invention can not only be realized as such an image decoding apparatus and image encoding apparatus, but also a method of processing operations thereof, a program for causing a computer to perform processing operations thereof, and a recording for storing the program
- the present invention can also be realized as a transcoding device including one or both of a medium, an integrated circuit having some or all of the functions of those devices, and either of the devices.
- the image decoding apparatus and the image coding apparatus according to the present invention can improve the decoding efficiency or the coding efficiency and can reduce the frequency of memory access.
- FIG. 1 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a configuration diagram showing a configuration of a decoding unit according to Embodiment 1 of the present invention.
- FIG. 3A is an explanatory drawing showing the structure of a stream (picture) to be decoded by the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 3B is an explanatory drawing showing the structure of a stream decoded by the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 4A is an explanatory view showing processing sharing of decoding units operating in parallel according to Embodiment 1 of the present invention.
- FIG. 4B is an explanatory view showing processing sharing (split streams) of the decoding units operating in parallel according to Embodiment 1 of the present invention.
- FIG. 4C is an explanatory drawing showing processing sharing (split streams) of the decoding units operating in parallel according to Embodiment 1 of the present invention.
- FIG. 5A is an explanatory diagram showing the positions of two decoding target macroblocks decoded in parallel by the decoding unit according to the first embodiment of the present invention.
- FIG. 5B is an explanatory view showing the positions of two decoding target macroblocks decoded in parallel by the decoding unit according to the first embodiment of the present invention.
- FIG. 5A is an explanatory diagram showing the positions of two decoding target macroblocks decoded in parallel by the decoding unit according to the first embodiment of the present invention.
- FIG. 5B is an explanatory view showing the positions of two decoding target macroblocks decoded in parallel by the decoding unit according to the first embodiment of the present invention.
- FIG. 6 is a flowchart showing decoding of a slice by the decoding unit of the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 7 is a flowchart showing decoding processing of a macro block by the decoding unit of the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 8 is a flowchart showing decoding processing of a macroblock by the decoding unit of the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 9 is an explanatory view showing a method of calculating a motion vector according to Embodiment 1 of the present invention.
- FIG. 10 is an explanatory view showing in-plane prediction according to Embodiment 1 of the present invention.
- FIG. 11 is an explanatory view showing writing of a reconstructed image according to the first embodiment of the present invention.
- FIG. 12A is an explanatory view showing a deblocking filter process according to the first embodiment of the present invention.
- FIG. 12B is an explanatory view showing a deblocking filter process according to the first embodiment of the present invention.
- FIG. 12C is an explanatory drawing showing the deblocking filter processing according to Embodiment 1 of the present invention.
- FIG. 13 is an explanatory view showing writing of a deblock filter image according to Embodiment 1 of the present invention.
- FIG. 14 is a flowchart showing a process of reading out peripheral information from the peripheral information memory of the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 14 is a flowchart showing a process of reading out peripheral information from the peripheral information memory of the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 15 is a flowchart showing a process of writing peripheral information to the peripheral information memory of the image decoding apparatus according to Embodiment 1 of the present invention.
- FIG. 16 is an explanatory view showing a range of a decoded image written to the frame memory by the decoding unit according to Embodiment 1 of the present invention.
- FIG. 17 is an explanatory diagram showing a macroblock line to be decoded by the decoding unit according to Embodiment 1 of the present invention when the coded stream has an MBAFF structure.
- FIG. 18 is an explanatory diagram showing a range of a decoded image in the case where the coded stream has an MBAFF structure, which is written to the frame memory by the decoding unit according to the first embodiment of the present invention.
- FIG. 16 is an explanatory view showing a range of a decoded image written to the frame memory by the decoding unit according to Embodiment 1 of the present invention.
- FIG. 17 is an explanatory diagram showing a macroblock line to be
- FIG. 19A is an explanatory diagram showing, in the image decoding apparatus according to Embodiment 1 of the present invention, timings at which macroblocks are processed when the coded stream has a non-MBAFF structure.
- FIG. 19B is an explanatory diagram showing the timing at which a macroblock is processed when the encoded stream has a non-MBAFF structure in the conventional image decoding apparatus.
- FIG. 20 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 2 of the present invention.
- FIG. 21 is an explanatory drawing showing the division of the coded stream according to Embodiment 2 of the present invention.
- FIG. 22 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 3 of the present invention.
- FIG. 23 is a configuration diagram showing a configuration of an image decoding apparatus according to Embodiment 4 of the present invention.
- FIG. 24 is an explanatory drawing showing time division parallel decoding processing by the image decoding apparatus according to Embodiment 4 of the present invention.
- FIG. 25 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 5 of the present invention.
- FIG. 26 is an explanatory diagram showing an operation of the image output unit of the image decoding apparatus according to Embodiment 5 of the present invention.
- FIG. 27 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 6 of the present invention.
- FIG. 28 is a block diagram showing the configuration of an image coding apparatus according to Embodiment 7 of the present invention.
- FIG. 29 is a block diagram showing the configuration of a transcoder according to an eighth embodiment of the present invention.
- FIG. 30 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 9 of the present invention.
- FIG. 31 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 10 of the present invention.
- FIG. 32 is a block diagram showing a configuration of an image decoding apparatus according to Embodiment 11 of the present invention.
- FIG. 33 is an overall configuration diagram of a content supply system for realizing the content distribution service according to the twelfth embodiment of the present invention.
- FIG. 34 is an overall configuration diagram of a digital broadcasting system according to Embodiment 12 of the present invention.
- FIG. 35 is a block diagram showing an exemplary configuration of a television according to Embodiment 12 of the present invention.
- FIG. 36 is a block diagram showing an example of configuration of an information reproducing / recording unit according to Embodiment 12 of the present invention.
- FIG. 37 is a view showing an example of the structure of a recording medium which is an optical disc according to Embodiment 12 of the present invention.
- FIG. 38 is a block diagram showing an example of configuration of an integrated circuit for realizing the image decoding device according to Embodiment 13 of the present invention.
- FIG. 39 is a block diagram of an image decoding apparatus according to an aspect of the present invention.
- FIG. 40 is a flowchart showing an operation of the image decoding apparatus according to an aspect of the present invention.
- FIG. 40 is a flowchart showing an operation of the image decoding apparatus according to an aspect of the present invention.
- FIG. 41 is a block diagram of an integrated circuit according to another aspect of the present invention.
- FIG. 42 is a block diagram of an image decoding apparatus according to another aspect of the present invention.
- FIG. 43 is a block diagram of an image decoding apparatus according to still another aspect of the present invention.
- FIG. 44 is a block diagram of an image coding apparatus according to an aspect of the present invention.
- FIG. 45 is a flowchart showing an operation of the image coding apparatus according to an aspect of the present invention.
- FIG. 46 is a block diagram of a transcoder according to an aspect of the present invention.
- FIG. 8 is a diagram showing data dependency in the H.264 standard.
- FIG. 48A is a block diagram showing a configuration of a conventional image decoding apparatus.
- FIG. 48B is an explanatory drawing showing the operation of the conventional image decoding device.
- Embodiment 1 (1-1. Overview) First, an outline of the image decoding apparatus according to the first embodiment of the present invention will be described.
- the image decoding apparatus reads a coded stream generated by coding an image in a stream division unit, divides the read stream so that two decoding units can decode in parallel, and 2 generated by the division Store one split stream in two buffers respectively.
- Each of the two decoders reads out and decodes the divided stream stored in the buffer.
- each of the two decoding units decodes the divided stream while synchronizing with the other decoding unit by referring to a part of the decoding result of the other decoding unit via the peripheral information memory.
- FIG. 1 is a block diagram of an image decoding apparatus according to the present embodiment.
- the image decoding apparatus 100 stores a Coded Picture Buffer (CPB) 1 that buffers a coded stream, a stream division unit 2 that divides the coded stream, and a divided stream generated by division.
- CPB Coded Picture Buffer
- Buffers 3 and 4 decoders 5 and 6 for performing decoding by variable length decoding, inverse frequency conversion, motion compensation, etc., and a part of the decoding results of neighboring macroblocks, for decoding the decoding target macroblock
- Peripheral information memories 7, 8 for storing peripheral information to be used; transfer units 9, 10 for transferring data between the decoding units 5, 6 and the peripheral information memories 7, 8; And a frame memory 11 for storing the decoded image.
- the decoding unit 5, the decoding unit 6, the peripheral information memory 7, the peripheral information memory 8, the transfer unit 9 and the transfer unit 10 are collectively referred to as a parallel decoding unit 60.
- the peripheral macroblocks are macroblocks adjacent to the upper left, upper, upper right, and left of the decoding target macroblock. Among the peripheral macroblocks, part of the decoding results of the three macroblocks except for the macroblock adjacent to the left is transferred by the transfer units 9 and 10 as the above-mentioned peripheral information.
- FIG. 2 is a block diagram of the decoding unit 5 of the present embodiment.
- the description of the same components as in FIG. 1 will be omitted.
- the transfer part 9 is divided and shown to two for convenience of description.
- the decoding unit 5 includes a variable-length decoding unit 12 that performs variable-length decoding, an inverse quantization unit 13 that performs inverse quantization processing, an inverse frequency conversion unit 14 that performs inverse frequency conversion processing, and data that has been subjected to inverse frequency conversion processing.
- a reconstruction unit 15 that reconstructs an image (reconstructed image) from (difference image) and a predicted image generated by motion compensation or in-plane prediction, and an in-plane that generates a predicted image from four neighboring macroblocks in a picture
- a prediction unit 16 a motion vector calculation unit 17 for calculating a motion vector, a motion compensation unit 18 for obtaining a reference image at a position pointed by the motion vector from the frame memory 11 and generating a prediction image by filtering,
- a deblocking filter unit 19 that performs deblocking filter processing to reduce block noise in the configuration image.
- the configuration of the decoding unit 6 is the same as that of the decoding unit 5.
- FIG. 3A and FIG. 3B are diagrams showing the configuration of a coded stream.
- one picture included in the encoded stream includes a plurality of macroblocks each configured by 16 pixels ⁇ 16 pixels.
- a picture may have a slice consisting of one or more macroblocks. Since the H.264 standard does not necessarily have a slice, the slice is not described in FIG. 3A.
- This macroblock is a processing unit for decoding.
- the numbers in the macroblock of FIG. 3A are a macroblock number (macroblock address) indicating a general coding order of the macroblock.
- the picture header is H.1. 8 shows various types of header information added in units of pictures, such as PPS (Picture Parameter Set) and SPS (Sequence Parameter Set) in the H.264 standard.
- the start code is also referred to as a synchronization word, and is composed of a specific pattern that does not appear in data of a coded image such as slice data.
- the first processing operation is an operation in which the stream division unit 2 reads the encoded stream from the CPB 1 and divides it into two, and stores the two divided streams generated by the division in buffers 3 and 4, respectively.
- the second processing operation is an operation of reading the divided stream from each of the buffers 3 and 4 and decoding them in synchronization with the decoding units 5 and 6. The two processing operations can be performed asynchronously.
- the stream division unit 2 decodes the coded stream until at least a macroblock boundary is known, and stores each of a plurality of macroblock lines included in the picture in the buffer 3 or 4 for each picture constituting the coded stream. .
- the first macroblock line is stored in buffer 3
- the second macroblock line is stored in buffer 4
- the third macroblock line is stored in buffer 3. This splits the coded stream into two, resulting in two split streams.
- the macroblock line is composed of a plurality of macroblocks arranged in a line in the horizontal direction in the picture.
- FIG. 4A, FIG. 4B and FIG. 4C are diagrams showing macroblock lines to be decoded by the decoding unit 5 and the decoding unit 6, respectively.
- the stream division unit 2 reads the coded stream from the CPB 1 and, among the coded streams, the macroblock lines from macroblock addresses 0 to 9 and the macroblocks from macroblock addresses 20 to 29.
- the macroblock lines are stored in the buffer 3 so that the lines are decoded by the decoding unit 5.
- the stream division unit 2 is configured such that the macroblock lines from macroblock addresses 10 to 19 and the macroblock lines from macroblock addresses 30 to 39 in the encoded stream are decoded by the decoding unit 6.
- the macro block line of is stored in the buffer 4.
- FIGS. 4B and 4C the picture header and the slice header are duplicated and stored in both buffers 3 and 4.
- FIG. 4B and 4C the picture header and the slice header are duplicated and stored in both buffers 3 and 4.
- a macroblock line consisting of macroblocks from macroblock addresses 0 to 9 and a macroblock line consisting of macroblocks from macroblock addresses 10 to 19 are in the same slice.
- the slice header of the slice is before the macroblock at macroblock address 0 and not before the macroblock at macroblock address 10.
- the stream division unit 2 duplicates the slice header immediately before the macroblock at macroblock address 0, and inserts the slice header immediately before the macroblock at macroblock address 10.
- the stream division unit 2 decodes syntaxes (mb_qp_delta and mb_skip_run) that are dependent on the order of macroblocks and can not be divided for each macroblock line, and convert them so that they can be decoded in parallel for each macroblock line.
- mb_qp_delta is obtained by encoding the difference in qp value (quantization parameter) between macroblocks.
- the stream division unit 2 converts mb_qp_delta for the first macroblock of the macroblock line into the qp value itself rather than the difference, and stores the qp value in buffer 3 and buffer 4.
- the stream division unit 2 uses H.323 for mb_qp_delta for macroblocks other than the top. As specified in H.264, the difference is stored in buffer 3 and buffer 4 as mb_qp_delta.
- mb_skip_run is a syntax indicating how many skip macroblocks follow. The stream division unit 2 converts this mb_skip_run into a value indicating how many skip macroblocks will continue in units of macroblock lines.
- the coded stream is divided into macro block line units as shown in FIG. 4A, data dependence of the decoding target macro block and such peripheral macro blocks, particularly the upper peripheral macro block, is obtained.
- the two split streams can not be decoded in parallel without solving. Therefore, image decoding apparatus 100 according to the present embodiment decodes two divided streams in parallel while maintaining the above-described data dependency by shifting the horizontal position of two decoding target macroblocks decoded in parallel.
- the upper peripheral macroblock is at least one of the neighboring macroblocks adjacent to the upper left, upper and upper right with respect to the current macroblock.
- FIG. 5A and FIG. 5B are diagrams showing the positions of two decoding target macroblocks decoded in parallel.
- the decoding target macroblock decoded by the decoding unit 5 may be at least two macroblocks ahead in the horizontal direction compared with the decoding target macroblock decoded by the decoding unit 6.
- the data dependency between the block to be decoded and the neighboring macroblocks shown in FIG. 47 in particular, the data dependency between the macroblock to be decoded and the upper neighboring macroblock, is resolved.
- the decoding unit 5 and the decoding unit 6 can simultaneously perform parallel decoding. That is, when each of the decoding units 5 and 6 decodes two vertically adjacent macroblock lines, the decoding unit 6 calculates at least two macroblocks in the horizontal direction from the decoding target macroblocks decoded by the decoding unit 5.
- the macroblock on the left is decoded as a decoding target macroblock.
- the positions of the decoding target macroblocks decoded by the decoding unit 5 and the decoding unit 6 only need to be shifted by at least 2 macroblocks in the horizontal direction, and as shown in FIG. 5B, they are shifted more than 2 macroblocks. It does not matter.
- FIG. 6 is a flowchart showing decoding of a slice by the decoding unit 5 of the image decoding device 100.
- the decoding unit 5 decodes the macroblock lines of macroblock addresses 0 to 9, the macroblock lines of macroblock addresses 20 to 29, and the macroblock lines of macroblock addresses 40 to 49.
- the decoding unit 6 decodes the macroblock lines of the macroblock addresses 10 to 19, the macroblock lines of the macroblock addresses 30 to 39, and the macroblock lines of the macroblock addresses 50 to 59.
- the variable-length decoding unit 12 of the decoding unit 5 reads partial data of the divided stream from the buffer 3 (S100).
- the variable length decoding unit 12 searches the start code for the read data (S101). That is, the variable-length decoding unit 12 determines whether the read data has a start code. If the start code is not found (No in S101), the variable length decoding unit 12 further reads the next data from the buffer 3 until the start code is found (S100). If the start code is found (Yes in S101), the variable length decoding unit 12 decodes the header (S102). The variable length decoding unit 12 determines whether the data following the header is slice data based on the result of decoding the header (S103).
- variable length decoding unit 12 rereads the next data from the buffer 3 (S101).
- the decoding unit 5 decodes the macro block included in the slice data (slice) (S104). Details of the macroblock decoding process will be described later.
- the variable-length decoding unit 12 determines whether the decoding of all the macroblocks in the slice is completed (S105).
- the decoding unit 5 performs the decoding process of the macro block again (S104).
- the decoding unit 5 ends the decoding for the slice.
- FIG. 7 and 8 are flowcharts showing the process of decoding a macroblock.
- the variable-length decoding unit 12 performs variable-length decoding of the data of the macroblock read from the buffer 3 (S110).
- the inverse quantization unit 13 inversely quantizes the coefficient data obtained as a result of the variable length decoding (S111).
- the inverse frequency transform unit 14 performs inverse frequency transform on the inversely quantized coefficient data (S112).
- the motion vector calculation unit 17 uses the transfer unit 9 from the peripheral information memory 7 to set the motion vector of the upper peripheral macroblock as the peripheral information. Read out (S113). The details of the motion vector reading process (S113) will be described later.
- the in-plane prediction unit 16 uses the transfer unit 9 from the peripheral information memory 7 as peripheral information for a part of the reconstructed image of the upper neighboring macroblock. Read out (S114). Details of the read processing (S114) of the reconstructed image will be described later.
- the decoding unit 5 determines whether the decoding target macroblock is an inter MB (macro block decoded by inter-frame prediction) (S115). If it is determined to be the inter MB (Yes in S115), the motion vector calculation unit 17 uses the motion vector of the upper neighboring macroblock read out in step S113 to calculate the motion vector of the decoding target macroblock. Calculate (S116).
- the motion compensation unit 18 reads a reference image from the frame memory 11 using the motion vector calculated in step S116, and performs motion compensation based on the reference image to generate a predicted image (S117).
- step S115 when it is determined in step S115 that the decoding target macroblock is not an inter MB (No in S115), that is, the decoding target macroblock is an intra MB (macro block decoded by intra prediction).
- the in-plane prediction unit 16 performs in-plane prediction on the decoding target macroblock using the reconstructed image of the upper neighboring macroblock read out in step S114 (S118).
- the motion vector calculation unit 17 writes the motion vector of the decoding target macroblock calculated in step S116 in the peripheral information memory 8 via the transfer unit 9 as peripheral information (S120).
- the motion vectors written as peripheral information may be all calculated motion vectors, but may be only motion vectors used to calculate motion vectors of the lower macroblock. That is, in step S120, the motion vector calculation unit 17 does not necessarily write the motion vector calculated in step S116 into the peripheral information memory 8, and the motion vector is used to calculate the motion vector of the lower macroblock. Only in the case where the motion vector calculated in step S116 may be written in the peripheral information memory 8. The process of writing the motion vector to the peripheral information memory (S120) will be described later.
- the reconstruction unit 15 performs the reconstruction by adding the predicted image generated by the motion compensation (S117) or the in-plane prediction (S118) and the difference image generated by the inverse frequency transformation of step S112.
- An image is generated (S121).
- the process of generating a reconstructed image in this manner is hereinafter referred to as a reconstruction process.
- the reconstructing unit 15 writes a part of the reconstructed image generated in step S121 as peripheral information in the peripheral information memory 8 via the transfer unit 9 (S122).
- the reconstruction image to be written may be all of the reconstruction image, or only a portion used for in-plane prediction of the lower macroblock.
- the process of writing a reconstructed image (S122) will be described later.
- the deblocking filter unit 19 performs deblocking filter processing on the partial image (deblock filter image) of the peripheral macroblocks on which the deblocking filter processing has been performed using the peripheral information memory 7 to the transfer unit 9. It reads as (S123). The readout process of the deblock filter image will be described later.
- the deblocking filter unit 19 performs deblocking filter processing on the current block to be decoded using the deblocking filter image, and writes the processing result (decoded image) in the frame memory 11 (S 124).
- the deblock filter unit 19 uses the image to be used in the deblock filter processing of the lower macroblock among the decoding target macroblock subjected to the deblock filter processing and the neighboring macroblocks to the left thereof (described later,
- the write target deblock filter image) is written as peripheral information into the peripheral information memory 8 via the transfer unit 9 (S125).
- FIG. 9 is an explanatory diagram for explaining a method of calculating a motion vector in step S116 of FIG.
- the motion vector calculation unit 17 calculates the motion vector mv of the current block MBx to be decoded as shown in FIG. 9, the motion vector mvB of the neighboring macroblocks MBb and MBc above and to the upper right of the current block MBx to be decoded Use mvC and the motion vector mvA of the neighboring macroblock MBa to the left of the macroblock MBx to be decoded.
- the motion vector calculation unit 17 reads the motion vectors mvB and mvC of the upper peripheral macroblocks MBb and MBc in advance from the peripheral information memory 7 via the transfer unit 9 (in step S113 in FIG. 7). Can use those motion vectors mvB and mvC.
- the motion vector calculation unit 17 calculates a predicted motion vector mvp of the motion vector mv of the current block MBx to be decoded by obtaining a median of the motion vectors mvA, mvB, and mvC. Then, the motion vector calculation unit 17 calculates the motion vector mv of the current block MBx to be decoded by adding the difference motion vector mvd to the predicted motion vector mvp.
- the differential motion vector mvd is included in the divided stream (coded stream) in a state of being subjected to variable length coding. Therefore, the motion vector calculation unit 17 obtains the differential motion vector mvd subjected to the variable length decoding from the variable length decoding unit 12, and calculates the above-described motion vector mv using the differential motion vector mvd.
- FIG. 10 is an explanatory diagram for explaining the in-plane prediction in step S118 of FIG.
- the in-plane prediction unit 16 decodes the reconstructed image of the neighboring macroblocks MBa to MBd at the upper left, upper, upper right and left of the macroblock MBx to be decoded In-plane prediction is performed on the target macroblock MBx. Specifically, the intra prediction unit 16 determines the right lower part of the reconstructed image of the peripheral macroblock MBa, and the lower right of the reconstructed images of the peripheral macroblock MBd.
- the in-plane prediction unit 16 reads out the reconstructed partial images of the upper peripheral macroblocks MBc to MBd from the peripheral information memory 7 via the transfer unit 9 in advance (at step S114 in FIG. 7). , These reconstructed partial images can be used.
- the in-plane prediction mode is included in a divided stream (coded stream) in a state of being subjected to variable-length coding. Therefore, the in-plane prediction unit 16 acquires the variable length decoded in-plane prediction mode from the variable length decoding unit 12 and performs the above-described in-plane prediction according to the in-plane prediction mode.
- FIG. 11 is an explanatory diagram for describing writing of a reconstructed image in step S122 of FIG.
- step S122 of FIG. 8 the reconstruction unit 15 sets an image consisting of lower 16 ⁇ 1 pixels in the reconstruction image of the decoding target macroblock MBx as the writing target reconstruction partial image as shown in FIG. 11.
- the peripheral information memory 8 is written via the transfer unit 9. That is, the write target reconstructed partial image composed of the 16 ⁇ 1 pixels is used as a reconstructed partial image, for example, for in-plane prediction by the decoding unit 6 of another macroblock below the macroblock MBx to be decoded.
- 12A to 12C are explanatory diagrams for describing the deblocking filter process in step S124 of FIG.
- the deblocking filter process is performed using three pixels on each side of the boundary of the subblock consisting of 4 ⁇ 4 pixels, for a total of six pixels. Therefore, as shown in FIG. 12A, in the deblocking filter process of the decoding target macroblock MBx, the deblocking filter image of the peripheral macroblock MBb above the decoding target macroblock MBx and the left of the decoding target macroblock MBx A deblock filter image of a certain peripheral macroblock MBa is required.
- the deblock filter image of the peripheral macroblock MBb consists of the lower 16 ⁇ 3 pixels of the deblock-filtered peripheral macroblock MBb, and the deblock filter image of the peripheral macroblock MBa is deblock-filtered And 3 ⁇ 16 pixels on the right side of the neighboring macroblocks MBa.
- the deblocking filter unit 19 performs the deblocking filter process on the decoding target macroblock MBx, the neighboring macroblocks MBb from the peripheral information memory 7 via the transfer unit 9 in advance (step S123 in FIG. 8). Read out the deblock filter image of. Then, the deblocking filter unit 19 performs deblocking filter processing on the current block MBx to be decoded using the read deblocking filter image. Since the deblock filter unit 19 itself performs the deblock filter process on the peripheral macroblock MBa, the deblock filter unit 19 performs the deblock filter process on the macroblock MBx to be decoded. It already holds the deblock filter image.
- an image composed of 13 ⁇ 13 pixels on the upper left side of the macroblock MBx to be decoded an image composed of 16 ⁇ 3 pixels on the lower side of the neighboring macroblock MBb, and a periphery
- An image composed of 3 ⁇ 13 pixels on the upper right side of the macro block MBa is determined as a decoded image.
- an image composed of pixels on the right and below the decoding target macroblock MBx is subjected to deblocking filter processing on the macroblocks on the right and below the decoding target macroblock MBx, and thus is used as a decoded image. It is decided.
- the deblocking filter unit 19 when writing the decoded image shown in FIG. 12B to the frame memory 11, the deblocking filter unit 19 is shifted three pixels to the upper left from the decoding target macroblock MBx as shown in FIG. 12C to avoid a decrease in transfer efficiency.
- FIG. 13 is an explanatory diagram for describing writing of the writing target deblocking filter image in step S125 of FIG.
- step S125 of FIG. 8 the deblocking filter unit 19 transfers the writing target deblocking filter image including a part of the deblocking filtered image of the decoding target macroblock MBx, as shown in FIG.
- the information is written in the peripheral information memory 8 through the unit 9.
- This write target deblock filter image is an image consisting of 13 ⁇ 3 pixels at the lower left of the decoding target macroblock MBx subjected to the deblock filter processing, and the deblock filter processing of the macroblock MBa on the left of the decoding target macroblock MBx. And an image consisting of 3 ⁇ 3 pixels in the lower right of the selected images.
- the decoding unit 5 decodes the divided stream of the buffer 3 using the peripheral information stored in the peripheral information memory 7, and part of the information generated by the decoding is converted to the peripheral information. And stored in the peripheral information memory 8.
- the decoding unit 5 when decoding the macro block to be decoded included in the divided stream of the buffer 3, the decoding unit 5 performs image processing on the peripheral information of the peripheral information memory 7 and the macro block to be decoded. And store at least a part of each of the image processing target macroblock to be decoded and the peripheral information in the frame memory 11.
- the peripheral information of the peripheral information memory 7 described above is at least a part of another macroblock decoded by the decoding unit 6 belonging to another macroblock line adjacent to the macroblock line to which the macroblock to be decoded belongs. is there.
- the decoding unit 6 decodes the divided stream of the buffer 4 using the peripheral information stored in the peripheral information memory 8, and stores part of the information generated by the decoding in the peripheral information memory 7 as peripheral information. Do.
- the decoding unit 6 performs image processing on the peripheral information of the peripheral information memory 8 and the macro block to be decoded. And store at least a part of each of the image processing target macroblock to be decoded and the peripheral information in the frame memory 11.
- the peripheral information of the above-mentioned peripheral information memory 8 is at least a part of another macroblock decoded by the decoding unit 5 belonging to another macroblock line adjacent to the macroblock line to which the macroblock to be decoded belongs. is there.
- FIG. 14 is a flowchart showing a process of reading out peripheral information from the peripheral information memory 7 by the decoding unit 5 and the transfer unit 9.
- the peripheral information is a motion vector, a reconstructed partial image or a deblocked filter image.
- the decoding unit 6 writes peripheral information used for decoding of the macro block by the decoding unit 5 in the peripheral information memory 7 via the transfer unit 10.
- the transfer unit 9 acquires from the transfer unit 10 the value of the write pointer of the peripheral information memory 7 when the writing is performed.
- the value of the write pointer indicates the address in the peripheral information memory 7 to be written next.
- the transfer unit 9 compares the value of the write pointer with the value of the read pointer for reading the peripheral information from the peripheral information memory 7 (S130).
- the value of the read pointer indicates the address in the peripheral information memory 7 to be read next.
- the transfer unit 9 waits (Yes in S130).
- transfer unit 9 increments the value of the read pointer to perform transfer when the above two values are not equal, and if equal, it is assumed that the peripheral information to be read is not yet written in peripheral information memory 7 Judge and wait until the peripheral information is written.
- peripheral information memory in each of the motion vector writing process (S120), the writing process for the reconstruction target partial image (S122), and the writing process for the writing target deblocking filter image (S125) described later.
- a method of writing peripheral information to 8 will be described. In each of the processes described above, the operation is the same except that the type of the peripheral information to be written is different, so the above-described process will be collectively described using the flowchart shown in FIG.
- FIG. 15 is a flowchart showing a process of writing peripheral information to the peripheral information memory 8 by the decoding unit 5 and the transfer unit 9.
- the peripheral information is a motion vector, a write target reconstructed partial image, or a write target deblock filter image.
- the decoding unit 6 reads the peripheral information for decoding the decoding target macroblock from the peripheral information memory 8 through the transfer unit 10.
- the transfer unit 9 acquires from the transfer unit 10 the value of the read pointer of the peripheral information memory 8 when this read is performed.
- the value of the read pointer indicates the address in the peripheral information memory 8 to be read next.
- the transfer unit 9 compares the value of the read pointer with the value of the write pointer for writing the peripheral information used for decoding the macro block by the decoding unit 6 in the peripheral information memory 8 (S140).
- the value of this write pointer indicates the address in the peripheral information memory 8 to be written next.
- the transfer unit 9 waits.
- the transfer unit 9 determines that the value obtained by incrementing the value of the write pointer is not equal to the read pointer (No at S140)
- the transfer unit 9 increments the write pointer (S141).
- the peripheral information generated by the unit 5 is acquired and written in the peripheral information memory 8 (S142).
- the write pointer catches or overtakes the read pointer.
- the value obtained by incrementing the value of the write pointer is different from the value of the read pointer, the write pointer catches up with the read pointer even if the peripheral information is written to the peripheral information memory 8 next, or There is no possibility of overtaking.
- transfer unit 9 increments the value of the write pointer and writes the peripheral information when the above two values are not equal, and when the two values are equal, the process of decryption unit 6, that is, the peripheral information by transfer unit 10. It is determined that the reading of the peripheral information from the memory 8 is delayed, and the reading is performed to wait until the value of the reading pointer increases.
- FIGS. 14 and 15 do not describe the case where the value of the pointer exceeds the maximum value of the peripheral information memory 7 and the peripheral information memory 8, if it exceeds the maximum value, it will return to 0, so-called Those memories may be used as ring buffers.
- the above is the description of the decoding process by the decoding unit 5.
- the decryption process by the decryption unit 6 is the same as the decryption process by the decryption unit 5 except that the transfer unit 10 is used and the peripheral information is written in the peripheral information memory 7 and read out from the peripheral information memory 8. Therefore, the description of the decoding process by the decoding unit 6 is omitted.
- FIG. 16 is a diagram showing the range of the decoded image written to the frame memory 11 by the decoding unit 5 and the decoding unit 6.
- an image to be decoded included in a picture is assigned in units of macroblock lines.
- the decoded image (image subjected to the deblock filter processing) written to the frame memory 11 by each of the decoding unit 5 and the decoding unit 6 deviates from the assigned macroblock line as shown in FIG. 12C. Therefore, as shown in FIG. 16, the decoded image of the area (the area surrounded by the solid line in the horizontal direction in FIG. 16) shifted from the macroblock line (the area surrounded by the dotted line in the horizontal direction in FIG.
- Each of the decoding unit 5 and the decoding unit 6 writes the frame memory 11.
- H.264 operation in the case of the frame structure or the field structure in the H.264 standard.
- H.264 standard there is a coded stream called a Macro Block Adaptive Frame Field (MBAFF) structure.
- MWAFF Macro Block Adaptive Frame Field
- the frame structure or field structure is referred to as a non-MBAFF structure.
- the coding order is different between the MBAFF structure and the non-MBAFF structure.
- FIG. 17 is a diagram showing macroblock lines to be decoded by the decoding unit 5 and the decoding unit 6 when the encoded stream has the MBAFF structure.
- the encoded stream has this MBAFF structure, stream division unit 2 sets the macroblock pair line in buffer 3 or buffer 4 for every two adjacent macroblock lines (macro block pair line) that make up a picture. By allocating, the picture (coded stream) is divided. Then, as shown in FIG. 17, the image decoding apparatus 100 decodes the code of the MBAFF structure as in the case where the coded stream has the non-MBAFF structure as the decoding unit 5 and the decoding unit 6 respectively decode the macroblock pair line. Can be decoded.
- FIG. 18 is a diagram showing the range of the decoded image to be written to the frame memory 11 when the coded stream has the MBAFF structure.
- each of the decoding unit 5 and the decoding unit 6 is a region (horizontal direction in FIG. 18) shifted from a macroblock pair line (two regions surrounded by dotted lines in the horizontal direction in FIG. 18).
- the decoded image of the area enclosed by the solid line of (1) is written to the frame memory 11.
- the stream division unit 2 divides the encoded stream, and the decoding unit 5 and the decoding unit 6 operate in parallel and in parallel using the peripheral information memory 7 and the peripheral information memory 8.
- the original coded stream is not necessarily divided in units such as slices.
- the H.264 standard encoded stream can be decoded in parallel.
- the processing performance can be doubled as compared to the case where a coded stream is decoded by only one decoding unit.
- the operating frequency of each decoding unit can be halved, and power consumption can be reduced.
- FIGS. 19A and 19B are diagrams showing the timing when macroblocks are processed when the coded stream has a non-MBAFF structure.
- the decoding unit 5 and the decoding unit 6 operate in parallel and in parallel using the peripheral information memory 7 and the peripheral information memory 8 as a buffer, as shown in FIG. 19A, the decoding unit 5. And the decoding unit 6 can start processing at the same time. Furthermore, control of the start of decoding is facilitated. Further, in the decoding unit 6, if peripheral information necessary for processing is written to the peripheral information memory 8 by the decoding unit 5, processing of the decoding target macroblock becomes possible. On the other hand, as shown in FIG. 19B, in the image decoding apparatus according to Patent Document 1, two decoding units 1300a and 1300b each decode one macroblock within a predetermined period.
- the decoding units 1300a and 1300b operate in synchronization with a macroblock unit. In such a case, one of the two decoding units 1300a and 1300b, which completes decoding of the macroblock earlier, waits for the start of decoding of the next macroblock.
- the waiting time for processing start can be reduced compared to the image decoding device of Patent Document 1, and efficient operation can be performed.
- the encoded stream is divided into two divided streams, and the two divided streams are decoded in parallel by the decoding units 5 and 6, respectively.
- the macro block pipeline control unit as described in the above-mentioned patent document 1 which centrally controls the timing of can be omitted. Furthermore, even when the image decoding apparatus 100 divides a coded stream into three or more divided streams and includes many decoding units for decoding the divided streams in parallel, as described in Patent Document 1 above. It is not necessary to lay a signal line between the macro block line control unit and the decoding unit, and the image decoding apparatus 100 can be realized easily. Furthermore, in the image decoding apparatus 100 according to the present embodiment, the H.264 algorithm is used.
- peripheral information required by the data dependency in the H.264 standard is transmitted and received between the decoding units 5 and 6 via the peripheral information memories 7 and 8. Therefore, if peripheral information required for decoding is stored in the peripheral information memory, decoding units 5 and 6 use the stored peripheral information without waiting for the decoding by the other decoding unit. Decoding of the split stream can be continued. As a result, it is possible to suppress the occurrence of a time loss due to the interruption of decoding as in the image decoding device of Patent Document 1 above, and improve the decoding efficiency.
- the image decoding apparatus 100 is not limited to H.264. Although the decoding is performed according to the H.264 standard, the decoding may be performed according to another image coding standard such as VC-1, for example.
- the present embodiment may be realized as a hardware circuit or as software executed on a processor, or a part may be realized as a hardware circuit and a part may be executed on a processor. It may be realized as software.
- the image decoding apparatus 100 includes two decoding units, the present invention is not limited to two, and three, four, or a larger number of decoding units may be provided.
- the stream division unit 2 divides the coded stream to generate divided streams of the same number as the number of decoding units provided.
- the image decoding apparatus 100 is not limited to H.
- the four neighboring macroblocks on the left, top, upper right, and upper left are referred to according to the H.264 standard, only the neighboring macroblocks on the left or only the neighboring macroblocks on the left and on top may be referred to.
- the peripheral macroblocks to be referred to may be changed depending on the process.
- the component storing the peripheral information is the peripheral information memory, but the component may be any recording medium such as a flip flop or another storage element. .
- peripheral information used for motion vector calculation, in-plane prediction, and deblocking filter processing is stored in one peripheral information memory. It may be stored in an information memory (memory, memory element such as flip flop, etc.).
- deblock filter processing is performed using three pixels on each side of the boundary, and the decoded image of the write target area at a position shifted by the number of pixels is written in the frame memory 11
- the number of pixels may be larger than three.
- the motion vector, the reconstructed partial image, and the deblock filter image are stored in the peripheral information memory as peripheral information, but the present invention is not limited to these. Any kind of information may be stored as long as For example, the in-plane prediction mode, the total number of non-zero coefficients among the frequency coefficients of the macroblock (TotalCoeff), or a reference picture number (ref_idx) indicating a reference picture may be used as the peripheral information.
- the in-plane prediction mode the total number of non-zero coefficients among the frequency coefficients of the macroblock
- ref_idx reference picture number indicating a reference picture
- the image decoding apparatus 100 includes one transfer unit and one peripheral information memory for each of the decoding units, it does not have to be necessarily provided for each of the decoding units. For example, as long as the transfer performance is satisfied, one transfer unit and peripheral information memory shared by a plurality of decoding units may be provided.
- the stream division unit 2 of the present embodiment merely divides the coded stream, it does not merely divide the coded stream, but also decodes all or part of the divided stream, and another division stream encoding scheme. It is also possible to change to the coding scheme and store the divided stream converted from the coding scheme in the buffer.
- the decoding unit stores only the decoded image in the frame memory 11, the control data accompanying the decoded image, for example, H.264, may be stored. It may also store information necessary for the direct mode decoding of the H.264 standard.
- the image decoding apparatus divides the coded stream into four, and decodes four divided streams generated by the division in parallel by four decoding units.
- Each of the four decoders reads out and decodes the divided stream stored in the buffer.
- each of the four decoding units decodes the divided stream while synchronizing with the other decoding units by referring to a part of the decoding results of the other decoding units via the peripheral information memory.
- FIG. 20 is a block diagram of an image decoding apparatus according to this embodiment.
- the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- the image decoding apparatus 200 stores the CPB 1, the frame memory 11, the stream division unit 20 that divides the encoded stream into four, and the four divided streams generated by the division. Buffers 21, 22, 23, and 24, decoders 25, 26, 27, and 28 for decoding by variable-length decoding, inverse frequency conversion, motion compensation, etc., and peripheral information used for decoding a macroblock to be decoded Information for storing data, transfer units 33, 34 for transferring data between the decoding units 25, 26, 27, 28 and the peripheral information memories 29, 30, 31, 32; 35 and 36 are provided.
- the encoded stream stored in the CPB 1 is read by the stream division unit 20 and divided into four as shown in FIG. 21, and the four divided streams generated by the division are respectively buffer 21, buffer 22, buffer 23, stored in the buffer 24.
- FIG. 21 is an explanatory diagram for explaining division of a coded stream.
- the stream division unit 20 divides the encoded stream so that the macroblock line is assigned to any of the four decoding units 25, 26, 27, 28 for each macroblock line. For example, macroblock lines from macroblock addresses 0 to 9 and macroblock lines from macroblock addresses 40 to 49 are assigned to the decoding unit 25. Similarly, macroblock lines from macroblock addresses 10 to 19 and macroblock lines from macroblock addresses 50 to 59 are allocated to the decoding unit 26. Similarly, macroblock lines from macroblock addresses 20 to 29 and macroblock lines from macroblock addresses 60 to 69 are allocated to the decoding unit 27.
- the stream division unit 20 generates the first to fourth divided streams by dividing the encoded stream.
- the first divided stream includes macroblock lines of macroblock addresses 0 to 9 and macroblock lines of macroblock addresses 40 to 49.
- the second divided stream includes macroblock lines of macroblock addresses 10 to 19 and macroblock lines of macroblock addresses 50 to 59.
- the third divided stream includes macroblock lines of macroblock addresses 20 to 29 and macroblock lines of macroblock addresses 60 to 69.
- the fourth divided stream includes macroblock lines of macroblock addresses 30 to 39 and macroblock lines of macroblock addresses 70 to 79.
- the stream division unit 20 stores the first divided stream in the buffer 21, stores the second divided stream in the buffer 22, stores the third divided stream in the buffer 23, and stores the fourth divided stream in the buffer 24. Store in
- the decoding unit 25 reads the first divided stream from the buffer 21 and decodes it.
- the operation of the decoding unit 25 is the same as the operation of the decoding unit 5 shown in the first embodiment, but the peripheral information which is the decoding result of the decoding unit 28 is read from the peripheral information memory 29 using the transfer unit 33 The difference is that peripheral information, which is the decoding result, is written to the peripheral information memory 30.
- the decoding unit 25 writes the decoded image into the frame memory 11.
- the decoding unit 26 reads the second divided stream from the buffer 22 and decodes it.
- the operation of the decoding unit 26 is the same as the operation of the decoding unit 5 described in the first embodiment, but the peripheral information which is the decoding result of the decoding unit 25 is read from the peripheral information memory 30 using the transfer unit 34 The difference is that peripheral information, which is the decoding result, is written to the peripheral information memory 31.
- the decoding unit 26 writes the decoded image in the frame memory 11.
- the decoding unit 27 reads the third divided stream from the buffer 23 and decodes it.
- the operation of the decoding unit 27 is the same as the operation of the decoding unit 5 shown in the first embodiment, but the peripheral information which is the decoding result of the decoding unit 26 is read from the peripheral information memory 31 using the transfer unit 35 The difference is that peripheral information, which is the decoding result, is written to the peripheral information memory 32.
- the decoding unit 27 writes the decoded image into the frame memory 11.
- the decoding unit 28 reads the fourth divided stream from the buffer 24 and decodes it.
- the operation of the decoding unit 28 is the same as the operation of the decoding unit 5 shown in the first embodiment, but using the transfer unit 36, peripheral information which is the decoding result of the decoding unit 27 is read from the peripheral information memory 32 and The difference is that peripheral information, which is the decoding result, is written to the peripheral information memory 29.
- the decoding unit 28 writes the decoded image in the frame memory 11.
- the image decoding apparatus 200 in the present embodiment divides the coded stream into four by the stream dividing unit 20, but the operation of each decoding unit operates in the same manner as in the first embodiment.
- the stream division unit 20 divides the encoded stream into four, and the four decoding units decode four divided streams in parallel. Therefore, in the image decoding apparatus 200 according to the present embodiment, the processing performance is improved twice when operating at the same operating frequency as the image decoding apparatus 100 as compared with the image decoding apparatus 100 according to the first embodiment. be able to. Also, in the case of realizing the same performance, the operating frequency of each decoding unit can be halved, and power consumption can be reduced.
- each of the decoding units 25 26 27 does not need to be synchronized with the other three decoding units, and may be synchronized with one adjacent decoding unit. It becomes easy to draw the wiring between each component, and it becomes easy to realize an image decoding device that improves the decoding efficiency.
- image decoding apparatus 200 of the present embodiment includes four decoding units, the present invention is not limited to four, and may include eight, sixteen, or a larger number of decoding units.
- the image decoding apparatus includes a switch that switches data input to each of the decoding unit and the peripheral information memory. By switching by these switches, the image decoding apparatus according to the present embodiment synchronizes two decoding units and decodes one encoded stream, and operates two decoding units independently to perform two codes. Switching between the process of decoding the
- FIG. 22 is a block diagram of an image decoding apparatus according to this embodiment.
- the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- An image decoding apparatus 300 includes each component of the image decoding apparatus 100 according to the first embodiment, a CPB 37 storing an encoded stream, and a switch 38 for switching data input to the decoding unit 5.
- the switch 38, the switch 39, the switch 40 and the switch 41 all select the input of "0" or "1" simultaneously.
- the switch 38 selects the input of “0”, it switches the data input to the decoding unit 5 to the divided stream stored in the buffer 3, and when the input of “1” is selected, the input to the decoding unit 5 is Data to the encoded stream stored in the CPB 37.
- the switch 39 selects the input of “0”, it switches the data input to the decoding unit 6 to the divided stream stored in the buffer 4, and when the input of “1” is selected, the switch 39 is input to the decoding unit 6 Data to the encoded stream stored in CPB1.
- the switch 40 When the switch 40 selects the input of "0", the switch 40 switches the data input (stored) in the peripheral information memory 7 to the peripheral information transferred from the decoding unit 6 through the transfer unit 10, and inputs "1". Is selected, the data input to the peripheral information memory 7 is switched to the peripheral information transferred from the decoding unit 5 through the transfer unit 9.
- the switch 41 selects the input of “0”, it switches the data input (stored) in the peripheral information memory 8 to the peripheral information transferred from the decoding unit 5 through the transfer unit 9, and inputs “1”. Is selected, the data input to the peripheral information memory 8 is switched to the peripheral information transferred from the decoding unit 6 through the transfer unit 10.
- the image decoding apparatus 300 decodes the encoded stream stored in CPB 1 as in the first embodiment. Do. That is, the stream division unit 2 of the image decoding apparatus 300 reads the encoded stream from the CPB 1 and divides it, and writes the two divided streams generated by the division into the buffer 3 and the buffer 4 respectively, and the decoding unit 5 and the decoding unit 6 Decodes those split streams in parallel.
- the operation of the image decoding apparatus 300 in this case is exactly the same as that of the first embodiment, so the description will be omitted.
- the image decoding apparatus 300 performs an operation different from that of the first embodiment. That is, the decoding unit 5 and the decoding unit 6 of the image decoding apparatus 300 respectively read out different encoded streams stored in different CPBs 37 and 1 and decode the streams independently. The decoding unit 5 reads out and decodes the coded stream of the CPB 37. The operation of the decoding unit 5 at this time is except that the peripheral information is written to the peripheral information memory 7 through the transfer unit 9 and that the transfer unit 9 and the transfer unit 10 do not perform the decoding synchronized with the decoding unit 6. Is the same as in the first embodiment.
- the decryption unit 5 writes peripheral information, which is the result of decoding by itself, into the peripheral information memory 7 using the transfer unit 9, and reads out, using the transfer unit 9, peripheral information, the result of writing by itself.
- the decoding target macroblock is decoded using the peripheral information.
- the operation of the decoding unit 6 is the same as that of the decoding unit 5 and thus the description thereof is omitted.
- the two decoding units cooperate to realize high performance, and two different encoded streams simultaneously. It is possible to switch between the operation to be decoded.
- the image decoding apparatus 300 includes two decoding units in the present embodiment, the image decoding apparatus 300 may include four or more decoding units.
- switches 38 to 41 in the present embodiment do not necessarily have to be physical or circuit switches, and may be switches for switching data, for example, by switching memory addresses.
- Embodiment 4 (4-1. Overview) First, an outline of the image decoding apparatus according to the fourth embodiment of the present invention will be described.
- the image decoding apparatus includes a switch that switches the coded stream input to the stream division unit.
- the image decoding apparatus divides one encoded stream by switching by this switch, and parallel decoding processing in which two divided streams are synchronously decoded by two decoding units, and two encoded streams Switching between time division parallel decoding processing performed by dividing the parallel decoding processing for each of the time division in time.
- FIG. 23 is a block diagram of an image decoding apparatus according to this embodiment.
- the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- the image decoding apparatus 400 includes each component of the image decoding apparatus 100 according to the first embodiment, and switches the CPB 37 storing the encoded stream and the encoded stream input to the stream division unit 2 And a switch 42.
- the switch 42 selects the input of “0”, it switches the encoded stream input to the stream division unit 2 to the encoded stream stored in the CPB 1 and selects the input of “1”, the stream division unit
- the encoded stream input to 2 is switched to the encoded stream stored in the CPB 37.
- the image decoding apparatus 400 performs the above-described parallel decoding process, and the switch 42 repeatedly selects the input of “0” and the input of “1” alternately. In this case, the above-described time division parallel decoding process is performed.
- the image decoding apparatus 400 decodes the coded stream stored in the CPB 1 as in the first embodiment. That is, the stream division unit 2 of the image decoding apparatus 400 reads the encoded stream from the CPB 1 and divides it, writes the two divided streams generated by the division into the buffer 3 and the buffer 4 respectively, and the decoding unit 5 and the decoding unit 6 Decodes those split streams in parallel.
- the operation of the image decoding apparatus 400 in this case is exactly the same as that of the first embodiment, so the description will be omitted.
- the stream division unit 2 of the image decoding device 400 When the switch 42 selects the input of “0” and the input of “1” alternately alternately in time, the stream division unit 2 of the image decoding device 400 generates two different sets stored in different CPBs. The division process on the encoded stream is performed by switching over time. That is, when the switch 42 selects the input of “0”, the stream division unit 2 reads and divides the encoded stream stored in the CPB 1, and 2 generated by the division of the encoded stream The decoding unit 5 and the decoding unit 6 synchronously decode one divided stream. The operation of the image decoding apparatus 400 at this time is the same as that of the first embodiment, so the description will be omitted.
- the stream division unit 2 reads and divides the coded stream stored in the CPB 37, and 2 generated by the division of the coded stream
- the decoding unit 5 and the decoding unit 6 synchronously decode one divided stream.
- the operation of the image decoding apparatus 400 at this time is the same as that of the first embodiment except that the coded stream is read from the CPB 37, so the description will be omitted.
- FIG. 24 is an explanatory diagram for explaining time division parallel decoding processing.
- the switch 42 selects an input of "0".
- the image decoding apparatus 400 performs parallel decoding processing on picture 0 of the coded stream stored in CPB 1.
- the switch 42 selects the input of “1”.
- the image decoding apparatus 400 performs parallel decoding processing on picture 0 of the coded stream stored in the CPB 37.
- the switch 42 selects the “0” input again.
- the image decoding apparatus 400 performs parallel decoding processing on picture 1 of the coded stream stored in CPB 1.
- time division parallel decoding processing is performed on two coded streams using two CPBs, but the number of CPBs and coded streams is not limited to two, and three or three CPBs are used. It may be four or more.
- coding streams to be subjected to parallel decoding processing are alternately switched in units of one picture, but it is not necessary to switch in units of one picture.
- the switching may be performed in units of one slice, in a plurality of slices, or in units of GOP (Group Of Pictures).
- the switch 42 in the present embodiment does not necessarily have to be a physical or circuit switch, and may be, for example, a switch that switches data by switching the address of a memory.
- the image decoding apparatus includes an image output unit that thins out the decoded picture and outputs the thinned image to the display device.
- This image output unit enables the image decoding apparatus according to the present embodiment to display a smooth fast-forwarding image on the display device.
- FIG. 25 is a block diagram of an image decoding apparatus according to this embodiment.
- the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- An image decoding apparatus 500 includes each component of the image decoding apparatus 100 according to the first embodiment, and an image output unit that outputs an image to a display device from the decoded picture stored in the frame memory 11. 43 is provided.
- FIG. 26 is an explanatory diagram for explaining the operation of the image output unit 43.
- the picture output unit 43 does not output each picture at times 0, 2, and 4 out of a series of pictures decoded and written in the frame memory 11 to the display device, and does not , 5 are output to the display device. That is, the image output unit 43 thins out the picture from the moving image which is the two divided divided streams, and outputs the moving image from which the picture is thinned to the display device.
- the decoding unit 5 and the decoding unit 6 perform parallel decoding to achieve twice the performance of the case where the decoding unit 5 or the decoding unit 6 is operated alone. Can be realized. That is, the image decoding apparatus 500 according to the present embodiment can decode a picture at a frame rate twice that of a normal frame rate. On the other hand, in a general display device, the speed at which pictures are displayed is fixed or set to a normal frame rate, and display can not be performed at a double frame rate. Therefore, in the image decoding apparatus 500 according to the present embodiment, a double-speed smooth fast-forwarding image can be displayed on the display device by thinning out the decoded pictures by the image output unit 43.
- image decoding apparatus 500 of the present embodiment displays a double-speed fast-forwarding image on a display device, it may display a triple-speed or quadruple-speed fast-forwarding image.
- the image output unit 43 thins out the pictures at a ratio according to n-times speed (n is an integer of 2 or more). Note that n is not limited to an integer. If n is not an integer, the image output unit 43 may thin out pictures unevenly.
- the image decoding apparatus in the present embodiment is provided with two frame memories.
- Each of the decoding unit 5 and the decoding unit 6 simultaneously writes the decoded image into two frame memories, and reads a decoded image (reference image) from mutually different frame memories which are associated in advance.
- This can reduce the access to one frame memory, and can reduce the access performance required by the frame memory. That is, a frame memory with low access performance can be used. As a result, the configuration of the frame memory can be simplified.
- FIG. 27 is a block diagram of an image decoding apparatus according to this embodiment.
- the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- An image decoding apparatus 600 includes each component of the image decoding apparatus 100 according to the first embodiment, and a frame memory 44 for storing the image (decoded image) decoded by the decoding unit 5 and the decoding unit 6. Equipped with
- the operation of the decoding unit 5 of the image decoding apparatus 600 according to the present embodiment shown in FIG. 27 is the motion compensation (S117) and the deblocking filter by the motion compensation unit 18 shown in the flowcharts of FIG. 7 and FIG.
- the operation is the same as that of the decoding unit 5 of the first embodiment except for the deblocking filter process (S124) by the unit 19.
- the motion compensating unit 18 reads from the frame memory 44 a reference image (decoded image) necessary for the motion compensation.
- the deblocking filter unit 19 performs the deblocking filter processing and the decoded image (decoded image) is used as the frame memory 11 At the same time, the frame memory 44 is written.
- the motion compensation unit 18 of the decoding unit 6 in the present embodiment reads from the frame memory 11 a reference image (decoded image) required for motion compensation. Further, the deblock filter unit 19 of the decoding unit 6 in the present embodiment performs the same operation as the deblock filter unit 19 of the decoding unit 5 in the present embodiment. That is, the operation of the decoding unit 6 in the present embodiment is the same as the operation of the decoding unit 5 in the present embodiment except for reading out the reference image from the frame memory 11.
- the transfer amount when writing a decoded image may be 256 bytes per macro block.
- the transfer amount at the time of reading by motion compensation is 1352 bytes in the case of bi-directional reference of 8 ⁇ 8 pixels, which is about five times the transfer amount at the time of writing the decoded image.
- the decoded image is written to two frame memories, and the frame memory to be read by motion compensation is made different frame memories by two decoding units, thereby halving the access performance necessary for reading from the frame memory. This makes it possible to simplify the configuration of the frame memory.
- the image decoding apparatus 600 includes two frame memories in the present embodiment, the number of the frame memories is not limited to two, and may be three, four, or a larger number of frame memories.
- the decoding unit 5 and the decoding unit 6 store only the decoded image in the frame memories 11 and 14, control data associated with the decoded image, for example, H.264, etc. is stored. It may store information required for the direct mode decoding of the H.264 standard.
- the decoding unit 5 and the decoding unit 6 simultaneously write the decoded image in the frame memories 11 and 44, but it does not have to be simultaneous at the same time, and data of all decoded images can be written. It may be shifted in writing.
- the image coding apparatus codes two parts constituting an input image in parallel by two coding sections, and divides two divided streams generated by the coding into two buffers. Store. Then, the image coding apparatus reads the divided streams stored in each of the two buffers by the stream combination unit and combines them into one coded stream. Thereby, the input image is encoded into the encoding stream.
- each of the two encoding units refers to a part of the data used for encoding (peripheral information) through the peripheral information memory to synchronize the image with the other encoding unit. Encoding.
- FIG. 28 is a block diagram of an image coding apparatus according to this embodiment.
- the same components as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
- the image coding apparatus 700 includes the transfer unit 9 and the transfer unit 10, the peripheral information memory 7 and the peripheral information memory 8, and the frame memory 11, as in the first embodiment. Furthermore, the image coding apparatus 700 further includes an encoding unit 51 and an encoding unit 52 that encode an image input to the frame memory 11 from a camera, a decoder or the like, and a division generated by the encoding by the encoding unit 51.
- a buffer 53 for storing a stream, a buffer 54 for storing a divided stream generated by encoding by the encoding unit 52, and a divided stream written to each of the buffer 53 and the buffer 54 are combined, 1 It includes a stream combining unit 55 for converting into one encoded stream, and a CPB 56 for storing the encoded stream.
- the coding unit 51, the coding unit 52, the peripheral information memory 7, the peripheral information memory 8, the transfer unit 9, and the transfer unit 10 are collectively referred to as a parallel coding unit 62.
- the coding unit 51 and the coding unit 52 write in the frame memory 11 in the same manner as the operation described using FIG. 4A to FIG. 4C of the first embodiment.
- the resulting image is shared in units of macroblocks and read out and encoded.
- the encoding unit 51 includes macroblock lines from macroblock addresses 0 to 9 and macroblock lines from macroblock addresses 20 to 29 included in a picture that is an image. And sequentially encode the macroblocks included in each macroblock line.
- the encoding unit 52 reads the macroblock lines from macroblock addresses 10 to 19 and the macroblock lines from macroblock addresses 30 to 39, etc. included in the picture which is an image. , And sequentially encode macroblocks included in each macroblock line.
- the encoding unit 51 uses the transfer unit 9 to read the reconstructed partial image from the peripheral information memory 7 as peripheral information prior to in-plane prediction, and Prior to encoding, the motion vector is read out from the peripheral information memory 7 as peripheral information, and the deblock filter image is read out from the peripheral information memory 7 as peripheral information prior to the deblock filter processing.
- the encoding unit 51 writes the motion vector as peripheral information in the peripheral information memory 8 using the transfer unit 9 when the coding of the motion vector is finished, and uses the transfer unit 9 when the reconstruction processing is finished,
- the write target reconstructed partial image is written to the peripheral information memory 8 as peripheral information
- the deblock filter processing is completed, the write target deblock filter image is written to the peripheral information memory 8 using the transfer unit 9.
- the encoding unit 51 writes the divided stream generated by the encoding to the buffer 53.
- the operation of the other encoding unit 51 is generally H.264.
- the coding unit is the same as the coding unit corresponding to the H.264 standard, so the description will be omitted.
- the above is the description of the encoding process by the encoding unit 51.
- the encoding unit 52 is other than using the transfer unit 10, writing peripheral information to the peripheral information memory 7, reading peripheral information from the peripheral information memory 8, and writing the generated divided stream to the buffer 54. Performs the same operation as the encoding unit 51. Therefore, the detailed description of the encoding unit 52 is omitted.
- Such encoding by the parallel encoding unit 62 is a processing operation corresponding to the decoding by the parallel decoding unit 60 of the first embodiment.
- the stream combining unit 55 combines the split stream of the buffer 53 with the split stream of the buffer 54 to generate one coded stream, and writes the coded stream to the CPB 56.
- the encoding unit 51 and the encoding unit 52 operate in parallel in parallel using the peripheral information memory 7 and the peripheral information memory 8, and the stream combining unit 55 operates on two divided streams.
- the processing performance can be doubled as compared to the case where an image is encoded by only one encoding unit.
- the operating frequency of each encoding unit can be halved, and power consumption can be reduced.
- the peripheral information memory 7 and the peripheral information memory 8 are used as a buffer, and the encoding unit 51 and the encoding unit 52 operate in parallel and operate in parallel, as illustrated in the first embodiment. Similar to the process shown in 19A, the encoding unit 51 and the encoding unit 52 can simultaneously start the process. Furthermore, control of the coding start is facilitated. In addition, in the encoding unit 52, if peripheral information necessary for processing is written to the peripheral information memory 8 by the encoding unit 51, processing of the encoding target macroblock becomes possible. On the other hand, as in the process shown in FIG.
- the image coding apparatus 700 of this embodiment is not limited to H.1. Although coding is performed according to the H.264 standard, coding may be performed according to another image coding standard such as VC-1, for example.
- the present embodiment may be realized as a hardware circuit or as software executed on a processor, or a part may be realized as a hardware circuit and a part may be executed on a processor. It may be realized as software.
- the image coding apparatus 700 includes two coding units, the present invention is not limited to two, and three, four, or a larger number of coding units may be provided.
- the stream combining unit 55 combines the same number of divided streams as the number of encoding units provided.
- the image coding apparatus 700 is based on H.264.
- the four neighboring macroblocks on the left, top, upper right, and upper left are referred to according to the H.264 standard, only the neighboring macroblocks on the left or only the neighboring macroblocks on the left and on top may be referred to.
- the peripheral macroblocks to be referred to may be changed depending on the process.
- the component storing the peripheral information is the peripheral information memory, but the component may be any recording medium such as a flip flop or another storage element. Absent.
- peripheral information memory memory, memory element such as flip flop, etc.
- deblock filter processing is performed using three pixels on each side of the boundary, as in the image decoding apparatus 100 according to the first embodiment, and although the decoded image of the write target area is written to the frame memory 11, the number of pixels may be larger than three.
- the motion vector, the reconstructed partial image, and the deblock filter image are stored in the peripheral information memory as peripheral information.
- the present invention is not limited to these. Any kind of information may be stored as long as For example, the in-plane prediction mode, the total number of non-zero coefficients among the frequency coefficients of the macroblock (TotalCoeff), or a reference picture number (ref_idx) indicating a reference picture may be used as the peripheral information.
- the image coding apparatus 700 of the present embodiment includes one transfer unit and one peripheral information memory for each of the coding units, it is necessary to necessarily include each of the coding units. There is no. For example, as long as transfer performance is satisfied, one transfer unit and peripheral information memory shared by a plurality of encoding units may be provided.
- the stream combining unit 55 of the present embodiment combines two divided streams into one encoded stream, but not only combining them, decoding all or part of the encoded stream, and Alternatively, the coding scheme of the coded stream may be changed to another coding scheme, and the coded stream with the changed coding scheme may be stored in the CPB.
- the encoding unit of the present embodiment stores only the decoded image (local decoded image) in frame memory 11, control data generated at the time of encoding and accompanying the local decoded image, for example, H.264. It may also store information necessary for the direct mode decoding of the H.264 standard.
- the image coding apparatus 700 of the present embodiment has a configuration corresponding to the image decoding apparatus 100 shown in the first embodiment, a configuration corresponding to the image decoding apparatus of any of the second to sixth embodiments. May be included.
- the transcoding device in the present embodiment first decodes the input coded stream by the parallel decoding unit 60 shown in the first embodiment, and writes the decoded image which is the decoding result in the frame memory. Furthermore, the transcoder reads out and enlarges or reduces the decoded image from the frame memory, and writes the enlarged or reduced decoded image as a resized image in the frame memory again. Next, the transcoder re-encodes the resized image by the parallel encoding unit 62 shown in the seventh embodiment using an encoding method, an image size, or a bit rate different from that of the original encoded stream. In this way, high speed decoding and high speed encoding enable high speed transcoding.
- FIG. 29 is a block diagram of the transcoder of this embodiment.
- the same components as those in Embodiment 1 and Embodiment 7 are assigned the same reference numerals and descriptions thereof will be omitted.
- the transcoder 800 includes CPBs 1, 56, buffers 3, 4, 53, 54, frame memory 11, stream division unit 2, stream combination unit 55, and a plurality of decoding units in parallel.
- a parallel decoding unit 60 that performs decoding, a scaling unit 61 that enlarges or reduces the decoded image of the frame memory 11, and a parallel encoding unit 62 that performs encoding in parallel by a plurality of encoding units are provided.
- the image decoding apparatus 100 according to the first embodiment includes the CPB 1, the stream dividing unit 2, the buffer 3, the buffer 4, the frame memory 11, and the parallel decoding unit 60.
- An image coding apparatus 700 according to the seventh embodiment is composed of the frame memory 11, the buffer 53, the buffer 54, the stream combining unit 55, the CPB 56, and the parallel coding unit 62.
- the stream division unit 2 divides the coded stream stored in the CPB 1 into two, and writes the two divided streams into the buffer 3 and the buffer 4 respectively.
- parallel decoding unit 60 reads divided streams from buffer 3 and buffer 4 in parallel by two internal decoding units and decodes them, and decodes the decoded image that is the decoding result.
- the scaling unit 61 reads the decoded image generated by the parallel decoding unit 60 from the frame memory 11, enlarges or reduces the decoded image, and uses the enlarged or reduced decoded image as a resized image. Write to 11.
- the parallel encoding unit 62 encodes the resized image stored in the frame memory 11 in parallel by the two internal encoding units, and encodes the resized image.
- the two split streams generated by are written to buffer 53 and buffer 54 respectively.
- the parallel encoding unit 62 re-encodes the resized image with an encoding method, an image size, or a bit rate different from that of the original encoded stream.
- the stream combining unit 55 combines the divided streams written to each of the buffer 53 and the buffer 54 into one coded stream, and writes the coded stream to the CPB 56.
- the parallel encoding unit 62 performs encoding using a coding standard or a coding bit rate different from that of the CPB 1 coded stream, and thus the coded stream is coded differently. It can be converted to a coding standard or bit rate coded stream.
- the parallel encoding unit 62 performs encoding using a coding standard or a coding bit rate different from that of the CPB 1 coded stream, and thus the coded stream is coded differently. It can be converted to a coding standard or bit rate coded stream.
- the enlargement / reduction unit 61 it becomes possible to convert it into an encoded stream of an image size different from the image size of the CPB 1 encoded stream.
- transcoding can be performed at a higher speed than processing by a single decoding unit or a coding unit.
- transcoding can be performed at a lower operating frequency than processing by a single decoding unit or encoding unit.
- the scaling unit 61 of the transcoder 800 performs enlargement or reduction, high image quality processing may be performed, and enlargement or reduction may be performed together with high image quality processing. . Furthermore, the transcoding device 800 may encode the decoded image as it is without performing either enlargement or reduction.
- transcoder 800 of the present embodiment includes parallel decoding unit 60 and parallel encoding unit 62, instead of parallel decoding unit 60, it includes one decoding unit that does not perform parallel decoding. It is also good.
- transcoding apparatus 800 may include one decoding unit that does not perform parallel encoding instead of parallel encoding unit 62. That is, although the transcode device 800 of the present embodiment includes the decoding unit and the encoding unit, only one of them may be configured as the parallel decoding unit 60 or the parallel encoding unit 62.
- the parallel decoding unit 60 and the parallel encoding unit 62 of the transcoder 800 each include two decoding units and two encoding units, the number of them is necessarily limited to two. It is not a thing. Also, the number of decoding units included in the parallel decoding unit 60 may be different from the number of encoding units included in the parallel encoding unit 62.
- the transcoding device 800 of the present embodiment utilizes the image decoding device 100 of the first embodiment and the image coding device 700 of the seventh embodiment
- the transcoding device 800 of the first embodiment can Instead, the image decoding apparatus according to any one of the second to sixth embodiments may be used.
- the image coding apparatus 700 of the seventh embodiment an image coding apparatus corresponding to the image decoding apparatus of any of the second to sixth embodiments may be used.
- the image decoding apparatus includes LSI (Large Scale Integration) and DRAM (Dynamic Random Access Memory).
- FIG. 30 is a block diagram of an image decoding apparatus according to this embodiment.
- the image decoding apparatus 100a includes an LSI 71 which is a part of the image decoding apparatus 100 described in the first embodiment, and a DRAM 72 which is a remaining part of the image decoding apparatus 100.
- the LSI 71 is a semiconductor integrated circuit. Specifically, the LSI 71 includes the stream division unit 2 in the first embodiment, the decoding units 5 and 6, the peripheral information memories 7 and 8, and the transfer units 9 and 10.
- the DRAM 72 includes the CPB 1, the buffer 3, the buffer 4, and the frame memory 11 in the first embodiment.
- each component described above may be individually made into one chip, or may be made into one chip so as to include part or all.
- an LSI is used here, it may be called an IC (Integrated Circuit), a system LSI, a super LSI, or an ultra LSI depending on the degree of integration.
- the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible.
- a field programmable gate array FPGA
- a reconfigurable processor that can reconfigure connection and setting of circuit cells in the LSI may be used.
- the image decoding apparatus 100a of the present embodiment can be used as a decoding unit in a drawing device such as a mobile phone, a television, a digital video recorder, a digital video camera, and a car navigation.
- the display is, for example, a cathode ray tube (CRT), a liquid crystal display, a PDP (plasma display panel), a flat display such as an organic EL, or a projection type display represented by a projector.
- the image decoding apparatus 100a of the present embodiment is configured of an LSI and a DRAM
- another storage such as an eDRAM (embeded DRAM), an SRAM (Static Random Access Memory), or a hard disk.
- the device may be configured.
- the image decoding apparatus includes two LSIs and two DRAMs.
- FIG. 31 is a block diagram of an image decoding apparatus according to this embodiment.
- the image decoding apparatus 600a of the present embodiment includes LSIs 71a and 71b which are a part of the image decoding apparatus 600 shown in the sixth embodiment, and DRAMs 72a and 72b which are the remaining parts of the image decoding apparatus 600.
- the LSIs 71a and 71b are respectively semiconductor integrated circuits.
- the LSI 71a includes the stream division unit 2, the decoding unit 6, the transfer unit 10, and the peripheral information memory 8 in the sixth embodiment.
- the LSI 71 b includes the decoding unit 5 according to the sixth embodiment, the transfer unit 9, and the peripheral information memory 7.
- the DRAM 72a includes the CPB 1 according to the sixth embodiment, the buffer 4 and the frame memory 11.
- the DRAM 72 b includes the buffer 3 and the frame memory 44 in the sixth embodiment.
- this embodiment is realized using two LSIs, these may be integrated into a single chip, or may be integrated into a single chip so as to include part or all.
- an LSI is used here, it may be called an IC, a system LSI, a super LSI, or an ultra LSI depending on the degree of integration.
- the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible.
- a field programmable gate array FPGA
- a reconfigurable processor that can reconfigure connection and setting of circuit cells in the LSI may be used.
- the image decoding apparatus 600a of the present embodiment can be used as a decoding unit in a drawing device such as a mobile phone, a television, a digital video recorder, a digital video camera, a car navigation, and the like.
- the display is, for example, a cathode ray tube (CRT), a liquid crystal display, a PDP (plasma display panel), a flat display such as an organic EL, or a projection type display represented by a projector.
- the image decoding apparatus 600a of the present embodiment is configured of an LSI and a DRAM, it may be configured of another storage device such as eDRAM, SRAM, or a hard disk instead of the DRAM.
- the image decoding apparatus includes two LSIs and two DRAMs, but is characterized in that each of the two LSIs includes the stream division unit 2.
- FIG. 32 is a block diagram of an image decoding apparatus according to this embodiment.
- An image decoding apparatus 600b includes an LSI 71a and DRAMs 72a and 72b, as with the image decoding apparatus 600 according to the tenth embodiment. Further, the image decoding device 600 b includes an LSI 71 c instead of the LSI 71 b of the image decoding device 600.
- the LSI 71 c includes a stream division unit 2, a decoding unit 5, a transfer unit 9, and a peripheral information memory 7.
- the stream division unit 2 of the LSI 71a reads the encoded stream from the CPB 1 and divides it into two, and stores the divided stream generated by the division in the buffer 4 to be processed by the LSI 71a.
- the stream division unit 2 of the LSI 71c reads out the encoded stream from the CPB 1 and divides it into two, and stores the divided stream generated by the division in the buffer 3 to be processed by the LSI 71c.
- the LSIs 71a and 71c respectively decode the divided streams in parallel.
- the two stream division units 2 may store the two divided streams generated by the division in the buffer 3 or the buffer 4 respectively.
- the decoding unit 5 and the decoding unit 6 respectively select and read a divided stream to be processed from the buffer 3 or the buffer 4 and decode the divided streams in parallel.
- the storage medium may be any one capable of recording a program, such as a magnetic disk, an optical disk, a magneto-optical disk, an IC card, or a semiconductor memory.
- FIG. 33 is a diagram showing an overall configuration of a content supply system ex100 for realizing content distribution service.
- the area for providing communication service is divided into desired sizes, and base stations ex107 to ex110, which are fixed wireless stations, are installed in each cell.
- This content supply system ex100 includes the Internet ex101, the Internet service provider ex102 and the telephone network ex104, and the base stations ex107 to ex110, such as a computer ex111, a personal digital assistant (PDA) ex112, a camera ex113, and a mobile phone ex114.
- the device is connected.
- each device may be directly connected to the telephone network ex104 without going through the base stations ex107 to ex110 which are fixed wireless stations.
- the devices may be directly connected to each other via near field communication or the like.
- the camera ex113 is a device capable of shooting moving images such as a digital video camera
- the camera ex116 is a device capable of shooting still images and moving images such as a digital camera.
- the cellular phone ex114 is a GSM (Global System for Mobile Communications) system, a CDMA (Code Division Multiple Access) system, a W-CDMA (Wideband-Code Division Multiple Access) system, or an LTE (Long Term Evolution) system, HSPA ( It may be a High Speed Packet Access mobile phone, a PHS (Personal Handyphone System), or the like.
- live distribution and the like become possible by connecting the camera ex113 and the like to the streaming server ex103 through the base station ex109 and the telephone network ex104.
- live distribution encoding processing is performed on content (for example, video of music live, etc.) captured by the user using the camera ex113 as described in the above embodiments, and the encoded content is transmitted to the streaming server ex103.
- the streaming server ex 103 streams the content data transmitted to the requested client.
- the client is, for example, the computer ex 111, the PDA ex 112, the camera ex 113, or the mobile phone ex 114 capable of decoding the above-mentioned encoded data.
- Each device that has received the distributed data decrypts and reproduces the received data.
- encoding processing of captured data may be performed by the camera ex 113, may be performed by the streaming server ex 103 that performs data transmission processing, or may be performed sharing each other.
- the decryption processing of similarly distributed data may be performed by the client, may be performed by the streaming server ex 103, or may be performed sharing each other.
- not only the camera ex113 but also still images and / or moving image data captured by the camera ex116 may be transmitted to the streaming server ex103 via the computer ex111.
- the encoding process in this case may be performed by any of the camera ex 116, the computer ex 111, and the streaming server ex 103, or may be performed sharing each other.
- these encoding / decoding processes are generally performed in the LSI ex 500 that the computer ex 111 or each device has.
- the LSI ex 500 may be a single chip or a plurality of chips. Even if software for moving image encoding / decoding is incorporated in any recording medium (CD-ROM, flexible disk, hard disk, etc.) readable by computer ex111 etc., the encoding / decoding processing is performed using that software. Good.
- moving image data acquired by the camera may be transmitted. The moving image data at this time is data encoded by the LSI ex 500 included in the mobile phone ex 114.
- the streaming server ex103 may be a plurality of servers or a plurality of computers, and may process, record, or distribute data in a distributed manner.
- the client can receive and reproduce the encoded data.
- the client can receive, decode, and reproduce the information transmitted by the user in real time, and even a user who does not have special rights or facilities can realize personal broadcasting.
- the digital broadcasting system ex200 can incorporate at least one of the image encoding device and the image decoding device of each of the above embodiments. .
- a bit stream of video information is communicated via radio waves and transmitted to the satellite ex202.
- This bit stream is a coded bit stream coded by the image coding apparatus described in each of the above embodiments.
- the satellite ex202 receiving this transmits a radio wave for broadcasting, and this radio wave is received by a home antenna ex204 capable of receiving satellite broadcasting.
- a device such as a television (receiver) ex300 or a set top box (STB) ex217 decodes and reproduces the received bit stream.
- STB set top box
- the image decoding apparatus shown in the above embodiment is also mounted on a reproducing apparatus ex 212 that reads and decodes a bit stream recorded on a storage medium ex 214 such as a CD (Compact Disc) or a DVD (Digital Versatile Disc) as a recording medium. It is possible. In this case, the reproduced video signal is displayed on the monitor ex 213.
- a reproducing apparatus ex 212 that reads and decodes a bit stream recorded on a storage medium ex 214 such as a CD (Compact Disc) or a DVD (Digital Versatile Disc) as a recording medium. It is possible.
- the reproduced video signal is displayed on the monitor ex 213.
- the reader / recorder ex 218 which reads and decodes a coded bit stream recorded on a recording medium ex 215 such as DVD, BD (Blu-ray Disc) or the like, or codes and writes a video signal on the recording medium ex 215
- a recording medium ex 215 such as DVD, BD (Blu-ray Disc) or the like
- codes and writes a video signal on the recording medium ex 215 It is possible to implement the image decoding apparatus or the image coding apparatus shown in FIG. In this case, the reproduced video signal is displayed on the monitor ex 219, and the video signal can be reproduced in another apparatus or system by the recording medium ex 215 on which the encoded bit stream is recorded.
- the image decoding apparatus may be mounted in the set top box ex217 connected to the cable ex203 for cable television or the antenna ex204 for satellite / terrestrial broadcast, and this may be displayed on the monitor ex219 of the television. At this time, the image decoding apparatus may be incorporated in the television instead of the set top box.
- FIG. 35 is a diagram showing a television (receiver) ex300 that uses the image decoding method described in each of the above embodiments.
- the television ex300 acquires tuners ex301 for acquiring or outputting a bit stream of video information via the antenna ex204 for receiving the broadcast, the cable ex203 or the like, and encoded data for demodulating received encoded data or for transmitting it to the outside And a multiplexer / demultiplexer ex303 for multiplexing the demodulated video data and audio data, or for multiplexing the encoded video data and audio data.
- the television ex300 decodes the audio data and the video data, or the audio signal processing unit ex304 that encodes each information, a signal processing unit ex306 having the video signal processing unit ex305, and outputs the decoded audio signal.
- the television ex300 includes an interface unit ex317 including an operation input unit ex312 and the like that receive an input of a user operation.
- the television ex300 includes a control unit ex310 that centrally controls each unit, and a power supply circuit unit ex311 that supplies power to each unit.
- the interface unit ex317 is, besides the operation input unit ex312, a bridge ex313 connected to an external device such as a reader / recorder ex218, a slot unit ex314 for enabling attachment of a recording medium ex216 such as an SD card, external recording such as a hard disk It may have a driver ex 315 for connecting to a medium, a modem ex 316 connected to a telephone network, and the like. Note that the recording medium ex216 can electrically record information by a nonvolatile / volatile semiconductor memory element to be stored.
- the components of the television ex300 are connected to one another via a synchronization bus.
- the television ex300 decodes data acquired from the outside with the antenna ex204 and the like and reproduces the data.
- the television ex300 receives the user operation from the remote controller ex220 and the like, and demultiplexes the video data and audio data demodulated by the modulation / demodulation unit ex302 by the multiplexing / demultiplexing unit ex303 based on the control of the control unit ex310 having a CPU etc. .
- the television ex300 decodes the separated audio data by the audio signal processing unit ex304, and decodes the separated video data by the video signal processing unit ex305 using the image decoding method described in each of the above embodiments.
- the decoded audio signal and video signal are output from the output unit ex309 to the outside.
- these signals may be temporarily stored in the buffers ex318, ex319, etc. so that the audio signal and the video signal are reproduced synchronously.
- the television ex300 may read the encoded bit stream not from the broadcast or the like, but from the recording media ex215 and ex216 such as a magnetic / optical disc and an SD card.
- the television ex300 encodes an audio signal or a video signal and externally transmits the signal or writes the signal to a recording medium or the like.
- the television ex300 receives the user operation from the remote controller ex220 and the like, and based on the control of the control unit ex310, encodes the audio signal by the audio signal processing unit ex304, and the video signal processing unit ex305 according to the seventh embodiment.
- Coding is performed using the image coding method described above.
- the encoded audio signal and video signal are multiplexed by multiplexer / demultiplexer ex303 and output to the outside.
- these signals may be temporarily stored in the buffers ex320, ex321, etc. so that the audio signal and the video signal are synchronized.
- a plurality of buffers ex318 to ex321 may be provided as illustrated, or one or more buffers may be shared.
- data may be stored in a buffer as a buffer material to avoid system overflow and underflow, for example, between the modulation / demodulation unit ex302 and the multiplexing / demultiplexing unit ex303.
- television ex300 In addition to acquiring audio data and video data from broadcasts and recording media, etc., television ex300 is also configured to receive AV input from a microphone or a camera, and performs encoding processing on data acquired from them. It is also good. Although television ex300 is described here as a configuration capable of the above encoding processing, multiplexing, and external output, such processing can not be performed, and a configuration capable of only the above reception, decoding processing, and external output It may be
- the decoding process or the encoding process may be performed by either the television ex300 or the reader / recorder ex218, and the television ex300 and The reader / recorder ex 218 may share each other.
- FIG. 36 shows a configuration of an information reproducing / recording unit ex400 in the case of reading or writing data from an optical disc.
- the information reproducing / recording unit ex400 includes elements ex401 to ex407 described below.
- the optical head ex401 irradiates a laser spot on the recording surface of the recording medium ex215 which is an optical disk to write information, detects reflected light from the recording surface of the recording medium ex215, and reads the information.
- the modulation recording unit ex402 electrically drives the semiconductor laser incorporated in the optical head ex401 and modulates the laser light according to the recording data.
- the reproduction / demodulation unit ex403 amplifies the reproduction signal obtained by electrically detecting the reflected light from the recording surface by the photodetector incorporated in the optical head ex401, separates and demodulates the signal component recorded in the recording medium ex215, and Play back information.
- the buffer ex 404 temporarily holds information to be recorded on the recording medium ex 215 and information reproduced from the recording medium ex 215.
- the disk motor ex405 rotates the recording medium ex215.
- the servo control unit ex406 moves the optical head ex401 to a predetermined information track while controlling the rotational drive of the disk motor ex405, and performs the laser spot tracking process.
- the system control unit ex407 controls the entire information reproducing / recording unit ex400.
- the system control unit ex407 uses various information held in the buffer ex404, and generates / adds new information as necessary.
- the modulation recording unit ex402 and the reproduction / demodulation unit This is realized by performing recording and reproduction of information through the optical head ex401 while cooperatively operating the servo control unit ex406.
- the system control unit ex 407 is configured by, for example, a microprocessor, and executes the processing of reading and writing by executing the program.
- the optical head ex401 may be configured to perform higher-density recording using near-field light.
- FIG. 37 shows a schematic view of the recording medium ex 215 which is an optical disc.
- a guide groove (groove) is formed in a spiral shape on the recording surface of the recording medium ex215, and in the information track ex230, address information indicating the absolute position on the disc is recorded in advance by the change of the groove shape.
- the address information includes information for specifying the position of the recording block ex231, which is a unit for recording data, and the apparatus for recording and reproduction reproduces the information track ex230 and reads the address information to specify the recording block.
- the recording medium ex215 includes a data recording area ex233, an inner circumference area ex232, and an outer circumference area ex234.
- An area used to record user data is data recording area ex233, and inner circumference area ex232 and outer circumference area ex234 arranged on the inner circumference or the outer circumference of data recording area ex233 are used for specific applications other than user data recording. Used.
- the information reproducing / recording unit ex400 reads / writes encoded audio data, video data, or encoded data obtained by multiplexing those data from / to the data recording area ex233 of such a recording medium ex215.
- an optical disc such as a single layer DVD or BD has been described as an example, but the optical disc is not limited to these, and may be an optical disc having a multilayer structure and capable of recording other than the surface.
- an optical disc with multi-dimensional recording / reproduction such as recording information in the same place of the disc using light of colors of different wavelengths, recording layers of different information from various angles, etc. It may be
- the digital broadcasting system ex200 it is possible to receive data from the satellite ex202 and the like by the car ex210 having the antenna ex205 and reproduce a moving image on a display device such as a car navigation system ex211 which the car ex210 has.
- the configuration of the car navigation system ex211 may be, for example, the configuration shown in FIG.
- terminals such as the above-mentioned mobile phone ex114 etc. are three types, that is, a transmitting terminal with only an encoder, and a receiving terminal with only a decoder, in addition to a transmitting / receiving terminal having both an encoder
- the implementation style of can be considered.
- FIG. 38 shows a configuration of LSI ex 500 formed into one chip.
- the LSI ex 500 includes elements ex 502 to ex 509 described below, and the elements are connected via the bus ex 510.
- the power supply circuit unit ex505 starts up to an operable state by supplying power to each unit when the power is on.
- the LSI ex 500 is based on control of the microcomputer ex 502, encoded data obtained from the base station ex 107 by the stream I / O ex 504, or encoded data obtained by reading from the recording medium ex 215 Is temporarily stored in the memory ex511 or the like.
- the accumulated data is divided into a plurality of times as appropriate according to the processing amount and processing speed and sent to the signal processing unit ex507, and the signal processing unit ex507 decodes audio data and / or video data Decoding is performed.
- the video signal decoding process is the decoding process described in each of the above embodiments.
- the decoded output signal is output from the AVI / O ex 509 to the monitor ex 219 or the like via the memory ex 511 or the like as appropriate.
- the memory controller ex503 is used.
- the memory ex 511 has been described as an external configuration of the LSI ex 500, but may be included in the LSI ex 500.
- the LSI ex 500 may be integrated into one chip or a plurality of chips.
- LSI LSI
- IC system LSI
- super LSI ultra LSI
- the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible.
- a programmable field programmable gate array FPGA
- a reconfigurable processor that can reconfigure connection and setting of circuit cells in the LSI may be used.
- the image decoding apparatus 100 includes the peripheral information memories 7 and 8, the two memories may not be provided.
- FIG. 39 is a block diagram of an image decoding apparatus according to an aspect of the present invention.
- An image decoding device C100 is an image decoding device that decodes encoded image data.
- the encoded image data includes an encoded picture
- the picture is configured of a plurality of macroblock lines
- the macroblock line is configured of a plurality of macroblocks arranged in one column.
- Such an image decoding device C100 assigns a picture to at least one macroblock line forming a picture by allocating the at least one macroblock line to a part of the first or second coded image data.
- the first and second decoding units C103 and C104 stored in the storage unit C102 are provided.
- the first decoding unit C103 decodes the first coded image data using the second decoding result information stored in the information storage unit C105, and part of the information generated by the decoding It is stored in the information storage unit C105 as first decoding result information.
- the first decoding unit C 103 decodes a macroblock to be decoded included in the first encoded image data, another macro adjacent to the macroblock line to which the macroblock to be decoded belongs.
- Image processing is performed on the second decoding result information, which is at least a part of another macroblock decoded by the second decoding unit C104 belonging to the block line, and the macroblock to be decoded, and the image processing is performed.
- At least a part of each of the macroblock to be decoded and the second decoding result information is stored in the frame storage unit C102.
- the second decoding unit C104 decodes the second encoded image data using the first decoding result information stored in the information storage unit C105, and part of the information generated by the decoding It is stored in the information storage unit C105 as second decoding result information.
- the second decoding unit C104 decodes the macroblock to be decoded included in the second encoded image data, another macroblock adjacent to the macroblock line to which the macroblock to be decoded belongs
- the image processing is performed on the first decoding result information that is at least a part of another macro block decoded by the first decoding unit C103 belonging to the line and the macro block to be decoded
- At least a part of each of the macroblock to be decoded and the first decoding result information is stored in the frame storage unit C102.
- the image decoding device C100 including the division unit C101 and the first and second decoding units C103 and C104 may be configured as an integrated circuit.
- the division unit C101 corresponds to the stream division unit 2 in the first to sixth embodiments
- the frame storage unit C102 corresponds to the frame memory 11 in the first to sixth embodiments.
- the first decoding unit C103 corresponds to the decoding unit 5 and the transfer unit 9 in the first to sixth embodiments.
- the second decoding unit C104 corresponds to the decoding unit 6 and the transfer unit 10 of the first to sixth embodiments.
- the information storage unit C105 corresponds to a recording medium including the peripheral information memories 7 and 8 of the first to sixth embodiments.
- the encoded image data corresponds to the encoded stream of the first to sixth embodiments
- the first and second encoded image data correspond to the divided streams of the first to sixth embodiments, respectively.
- Decoding result information 2 corresponds to peripheral information in the first to sixth embodiments, respectively.
- FIG. 40 is a flowchart showing an operation of the image decoding device C100.
- the image decoding device C100 first assigns the at least one macroblock line to a part of the first or second encoded image data for each of at least one macroblock line constituting the picture. It is divided into 1 and 2nd encoded image data (S1501). Furthermore, the image decoding device C100 decodes, in parallel, macroblock lines adjacent to each other in the picture, which are included in each of the first and second encoded image data (S1502), and stores them in the frame storage unit C102. (S1503).
- the first decoding unit C103 of the image decoding device C100 uses the second decoding result information stored in the information storage unit C105 to execute the first decoding.
- the encoded image data is decoded (S1504), and a part of the information generated by the decoding is stored in the information storage unit C105 as first decoding result information (S1505).
- the first decoding unit C103 is configured to select another macro adjacent to the macro block line to which the macro block to be decoded belongs.
- Image processing is performed on the second decoding result information that is at least a part of another decoded macroblock belonging to the block line and the macroblock to be decoded, and the image block is subjected to image processing to be decoded; At least a part of each of the second decoding result information is stored in the frame storage unit C102.
- the second decoding unit C104 of the image decoding device C100 uses the first decoding result information stored in the information storage unit C105.
- the second encoded image data is decoded (S1506), and part of the information generated by the decoding is stored in the information storage unit C105 as second decoding result information (S1507).
- the second decoding unit C104 is configured to select another macro adjacent to the macroblock line to which the macroblock to be decoded belongs.
- the image processing is performed on the first decoding result information that is at least a part of another decoded macroblock belonging to the block line and the macroblock to be decoded, and the image block is subjected to image processing to be decoded; At least a part of each of the first decoding result information is stored in the frame storage unit C102.
- image processing such as deblock filter processing performed across macroblock lines is also performed on the first and second encoded image data (division stream) in parallel, so that overall decoding can be performed.
- Speeding up can be sufficiently achieved, and as a result, decoding performance or decoding efficiency can be improved.
- deblocking filter processing is already performed on the macroblock. There is. Therefore, after the macro block is stored in the frame storage unit C102, there is no need to read the macro block from the frame storage unit C102 in order to perform the deblock filter process. As a result, the frequency of access to the frame storage unit C 102 can be reduced.
- the encoded image data is divided into first and second encoded image data, and the first and second encoded image data are respectively divided into first and second decoding units C103, C103, Since the decoding of the first and second encoded image data is synchronized by the dependence of the data via the information storage unit C105 by the C104 in parallel, the timing of the decoding by each of the decoding units is intensively controlled.
- a macroblock pipeline control unit as described in reference 1 can be omitted.
- the image decoding device C100 divides encoded image data into three or more pieces of data and includes many decoding units for decoding those pieces of data in parallel, such as in Patent Document 1 described above There is no need to lay a signal line between the macroblock line control unit and each decoding unit, and the image decoding apparatus can be realized easily. Furthermore, in the image decoding device C100, the H.264 algorithm is used. The first and second decoding result information required by the data dependency in the H.264 standard is transmitted and received between the first and second decoding units C103 and C104 via the information storage unit C105.
- the first and second decoding units C103 and C104 perform decoding by the other decoding unit. Decoding of the first or second encoded image data can be continuously performed using the stored first or second decoding result information without waiting. As a result, it is possible to suppress the occurrence of a time loss due to the interruption of decoding as in the image decoding device of Patent Document 1 above, and improve the decoding efficiency.
- the image decoding apparatus can achieve the above-described effects even if it does not include the two memories (peripheral information memories 7 and 8) for storing a part of the decoding result. Furthermore, the image decoding apparatus of the present invention can achieve the above-described effects even if it does not include the frame storage unit C102 (frame memory 11) and the CPB 1 and the buffers 3 and 4 shown in FIG.
- the integrated circuit includes a dividing unit C101 and first and second decoding units C103 and C104. Only one of the decoding units C103 and C104 may be included.
- FIG. 41 is a block diagram of an integrated circuit according to another aspect of the present invention.
- An integrated circuit C2001 is an integrated circuit that decodes a part of encoded image data.
- the encoded image data includes an encoded picture, the picture is configured of a plurality of macroblock lines, and the macroblock line is configured of a plurality of macroblocks arranged in one column.
- Such an integrated circuit C2001 includes a division unit C101 and a decoding unit C2002.
- the division unit C101 assigns the first and the second pictures by assigning the at least one macroblock line to a part of the first or second encoded image data for each of at least one macroblock line constituting the picture. It is divided into 2 encoded image data.
- the second decoding unit C2002 is adjacent to the macroblock line in the picture in parallel with the decoding of the macroblock line included in the first encoded image data by the processing device C2004 connected to the integrated circuit C2001.
- the macroblock line included in the encoded image data is decoded and stored in the frame storage unit C102.
- the decoding unit C2002 decodes the second encoded image data using the first decoding result information stored in the information storage unit C2003, and uses the second part of the information generated by the decoding.
- the decryption result information is stored in the information storage unit C2003.
- the decoding unit C2002 belongs to another macroblock line adjacent to the macroblock line to which the macroblock to be decoded belongs.
- Image processing is performed on the first decoding result information which is at least a part of another macroblock decoded by the processing device C 2004, and the macroblock to be decoded, and the macroblock to be decoded subjected to image processing, and At least a part of each of the first decoding result information is stored in the frame storage unit C102.
- the processing device C 2004 decodes the first encoded image data using the second decoding result information stored in the processing device C 2004, and partially decodes the information generated by the decoding.
- the decryption result information is stored in the information storage unit C2003.
- the processing device C 2004 when the processing device C 2004 decodes the macroblock to be decoded included in the first encoded image data, the processing device C 2004 selects another macroblock line adjacent to the macroblock line to which the macroblock to be decoded belongs. Image processing is performed on the second decoding result information, which is at least a part of another macroblock decoded by the decoding unit C2002, and the macroblock to be decoded, and the image block is subjected to image processing to be decoded And at least a part of each of the second decoding result information is stored in the frame storage unit C102.
- the integrated circuit C2001 corresponds to the LSI 71a shown in FIG. 31 or 32.
- the decoding unit C2002 corresponds to the decoding unit 6 and the transfer unit 10 of the LSI 71a
- the information storage unit C2003 corresponds to the peripheral information memory 8 of the LSI 71a.
- Such an integrated circuit C2001 performs the operation in cooperation with the LSI 71b (processing device C2004) shown in FIG. 31 or the LSI 71c (processing device C2004) shown in FIG. 32 to exhibit the same function / effect as the image decoding device C100. .
- FIG. 42 is a block diagram of an image decoding apparatus according to another aspect of the present invention.
- An image decoding apparatus C 800 further includes an information storage unit having first and second information storage units C 105 a and C 105 b.
- the first decoding unit C103 reads the second decoding result information from the first information storage unit C105a and uses it for decoding the first encoded image data, and the first decoding result information is used as a second information storage unit.
- the second decoding unit C104 reads the first decoding result information from the second information storage unit C105b and uses it for decoding the second encoded image data, and the second decoding result information is used as a first information storage unit.
- the image decoding apparatus C 800 further includes a first switch C 803 that switches the information stored in the first information storage unit C 105 a between the first information and the second information, and a second information storage unit C 105 b. And a second switch C 804 for switching the information stored in the third information to the fourth information.
- the information stored in the first information storage unit C 105 a is switched to the first information by the first switch C 803, and the information stored in the second information storage unit C 105 b is the third information by the second switch C 804.
- the first decoding unit C103 stores the first decoding result information as the third information in the second information storage unit C105b.
- the second decoding unit C104 stores the second decoding result information as first information in the first information storage unit C105a.
- the information stored in the first information storage unit C 105 a is switched to the second information by the first switch C 803, and the information stored in the second information storage unit C 105 b is processed by the second switch C 804.
- the first and second decoding units C103 and C104 perform operations different from those described above. That is, the first decoding unit C103 further reads out the second information from the first information storage unit C105a and uses it for decoding of other encoded image data, and a part of the information generated by the decoding is newly added. Is stored in the first information storage unit C 105 a as the second information.
- the second decoding unit C104 further reads out fourth information from the second information storage unit C105b and uses it for decoding of the encoded image data, and part of the information generated by the decoding is newly added. 4 information is stored in the second information storage unit C 105 b.
- the information stored in the first and second information storage units C105a and C105b is switched to the first and third information by the first and second switches C803 and C804, respectively.
- the first and second encoded image data are decoded in parallel, and the information stored in the first and second information storage units C105a and C105b is subjected to the first and second switches C803 and C804.
- the first and second switches C 803 and C 804 can switch between processing for dividing one encoded image data and decoding in parallel and processing for simultaneously decoding two independent encoded image data. The convenience of the image decoding apparatus can be improved.
- the first decoding unit C103 switches the data to be decoded to the first coded image data and the other coded image data
- the second decoding unit C104 decodes The target data is switched to the second encoded image data and the encoded image data. Therefore, even if the image decoding apparatus of the present invention does not have the switch 38 and the switch 39 in the image decoding apparatus 300 of the third embodiment, the above-described effects can be achieved.
- FIG. 43 is a block diagram of an image decoding apparatus according to still another aspect of the present invention.
- An image decoding apparatus C 900 includes components of the image decoding apparatus C 100, and further, data to be divided by the dividing unit C 101 includes coded image data and other coded images.
- a switch C 901 for switching to data is provided.
- the division unit C101 divides the picture of the coded image data when the data to be divided is switched to the coded image data by the switch C901.
- the division unit C101 divides the picture of the other encoded image data.
- the image decoding device C 900 it is possible to temporally switch and decode two pieces of encoded image data. For example, when a picture included in encoded image data is decoded, data to be divided is switched to other encoded image data. As a result, pictures included in other encoded image data are divided and decoded. Thereafter, the data to be divided is switched to the encoded image data again. As described above, it is possible to switch on a picture basis and simultaneously decode two pieces of encoded image data.
- FIG. 44 is a block diagram of an image coding apparatus according to an aspect of the present invention.
- An image coding device C 1200 is an image coding device that codes image data.
- the image data includes a picture, the picture is configured of a plurality of macroblock lines, and the macroblock line is configured of a plurality of macroblocks arranged in a line.
- Such an image coding device C1200 reads out the first and second image data contained in the image data from the frame storage unit C1201 and codes them in parallel to generate the first and second coded image data.
- the first encoding unit C1202 encodes the first image data using the second encoding result information stored in the information storage unit C1204, and a part of the information generated by the encoding. Are stored in the information storage unit C 1204 as first encoding result information.
- the first encoding unit C1202 is adjacent to the macroblock line to which the macroblock to be encoded belongs. Image processing is performed on the second encoding result information which is at least a part of another macroblock belonging to the macroblock line of At least a part of each of the block and the second decoding result information is stored in the frame storage unit C1201.
- the second encoding unit C1203 encodes the second image data using the first encoding result information stored in the information storage unit C1204, and a part of the information generated by the encoding. Are stored in the information storage unit C 1204 as second encoding result information.
- the second encoding unit C 1203 codes the macroblock to be encoded included in the second image data
- the second encoding unit C 1203 is another one adjacent to the macroblock line to which the macroblock to be encoded belongs.
- Image processing is performed on the first encoding result information that is at least a part of another macroblock belonging to the macroblock line and the macroblock to be encoded, and the image processing is performed on the macroblock to be encoded And at least a part of each of the first decoding result information is stored in the frame storage unit C1201.
- the combining unit C 1205 corresponds to the stream combining unit 55 of the seventh embodiment, and the frame storage unit C 1201 corresponds to the frame memory 11 of the seventh embodiment.
- the first coding unit C1202 corresponds to the coding unit 51 and the transfer unit 9 of the seventh embodiment.
- the second encoding unit C1203 corresponds to the encoding unit 52 and the transfer unit 10 of the seventh embodiment.
- An information storage unit C 1204 corresponds to a recording medium including the peripheral information memories 7 and 8 of the seventh embodiment.
- the first and second encoded image data correspond to the divided stream of the seventh embodiment
- the data generated by the combination by the combining unit C 1205 corresponds to the encoded stream of the seventh embodiment
- the second encoding result information corresponds to the peripheral information of the seventh embodiment.
- FIG. 45 is a flowchart showing an operation of the image coding device C1200.
- the image coding device C1200 first reads out the first and second image data included in the image data from the frame storage unit C1201 (S1601), and codes them in parallel to generate the first and second coded image data. Are generated (S1602). Next, the image coding device C 1200 performs the first and second coding so that the macroblock lines included in each of the generated first and second coded image data are adjacent to each other in the picture. The image data are combined (S1603).
- the first encoding unit C1202 of the image encoding device C1200 uses the second encoding result information stored in the information storage unit C1204.
- the first image data is encoded (S1604), and part of the information generated by the encoding is stored in the information storage unit C1204 as first encoding result information (S1605).
- the first encoding unit C1202 is adjacent to the macroblock line to which the macroblock to be encoded belongs.
- Image processing is performed on the second encoding result information which is at least a part of another macroblock belonging to the macroblock line of At least a part of each of the block and the second decoding result information is stored in the frame storage unit C1201.
- the second encoding unit C1203 of the image encoding device C1200 uses the first encoding result information stored in the information storage unit C1204.
- the second image data is encoded using (S1606), and part of the information generated by the encoding is stored in the information storage unit C1204 as second encoding result information (S1607).
- the second coding unit C 1203 codes the macroblock to be encoded included in the second image data
- the second encoding unit C 1203 is another one adjacent to the macroblock line to which the macroblock to be encoded belongs.
- Image processing is performed on the first encoding result information that is at least a part of another macroblock belonging to the macroblock line and the macroblock to be encoded, and the image processing is performed on the macroblock to be encoded And at least a part of each of the first decoding result information is stored in the frame storage unit C1201.
- the image coding device C1200 since the first and second image data included in the image data are coded in parallel and combined, control to centrally control the coding timing by each coding unit is performed. The department can be omitted. Furthermore, even in the case where the image coding device C1200 includes many coding units for coding a part of image data, the signal lines between the control unit and the coding units as described above are laid. There is no need for this, and the image coding device can be realized easily. Furthermore, in the image coding device C1200, the H. The first and second coding result information required by the data dependency in the H.264 standard is transmitted and received between the first and second coding units C1202 and C1203 via the information storage unit C1204.
- the first and second coding units C 1202 and C 1203 perform the other coding
- the encoding of the first or second image data can be continuously performed using the stored first or second encoding result information without waiting for encoding by the unit. As a result, it is possible to suppress the occurrence of a time loss due to the interruption of the encoding, and to improve the encoding efficiency.
- the image coding apparatus can achieve the above-described effects even if it does not have two memories (peripheral information memories 7 and 8) for storing a part of the coding result. Furthermore, the image coding apparatus of the present invention can achieve the above-described effects even if it does not include the frame storage unit C 1201 (frame memory 11) and the CPB 56 and the buffers 53 and 54 shown in FIG.
- FIG. 46 is a block diagram of a transcoder according to an aspect of the present invention.
- a transcoding device C1300 includes an image decoding device C1301 and an image coding device C1302.
- the image coding device C1302 may be any image coding device.
- the image coding device C1302 is an image coding device corresponding to the image coding device 700 of the seventh embodiment or the image decoding device of any of the first to sixth embodiments
- the image decoding device C1301 may be any image decoding device.
- the image decoding device C1301 is any of the image decoding devices according to the first to sixth embodiments
- the image coding device C1302 is the image coding device 700 according to the seventh embodiment, or the first embodiment. It may be an image coding device corresponding to any of the image decoding devices of.
- the same operation and effect as at least one of the image decoding device and the image coding device of the present invention described above can be achieved.
- the image decoding device, the image encoding device, and the transcoding device according to the present invention can be used for various applications, with the effect of improving the decoding efficiency or the encoding efficiency and being easily realizable.
- it can be used for information display devices and imaging devices such as televisions, digital video recorders, car navigation systems, mobile phones, digital cameras, digital video cameras, etc., and has high utility value.
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Abstract
Description
(1-1.概要)
まず、本発明の実施の形態1における画像復号装置の概要について説明する。
次に、本実施の形態の画像復号装置の構成について説明する。
次に、図1および図2で示した画像復号装置100の動作について説明する。
このように、本実施の形態では、ストリーム分割部2が符号化ストリームを分割し、復号部5と復号部6が周辺情報メモリ7と周辺情報メモリ8を用いて同期して並列に動作することにより、元の符号化ストリームが必ずしもスライスなどの単位で分割されていないH.264規格の符号化ストリームを並列に復号することが可能となる。さらに、本実施の形態では、1つの復号部だけで符号化ストリームを復号する場合に比べて、処理性能を2倍にすることができる。また、同一性能を実現する場合には、各復号部の動作周波数を半分にすることができ、消費電力の低減が可能である。
なお、本実施の形態の画像復号装置100は、H.264規格にしたがって復号を行ったが、例えばVC-1など、他の画像符号化規格にしたがって復号を行ってもよい。
(2-1.概要)
まず、本発明の実施の形態2における画像復号装置の概要について説明する。
次に、本実施の形態の画像復号装置の構成について説明する。
次に、図20で示した画像復号装置200の動作について説明する。
このように、本実施の形態では、ストリーム分割部20によって符号化ストリームを4つに分割することにより、4つの復号部で4つの分割ストリームを並列に復号する。したがって、本実施の形態の画像復号装置200では、実施の形態1の画像復号装置100に比べて、画像復号装置100と同一の動作周波数で動作する場合には、処理性能を2倍に向上させることができる。また、同一性能を実現する場合には、各復号部の動作周波数を半分にすることができ、消費電力の低減が可能である。
なお、本実施の形態の画像復号装置200は、復号部を4個備えたが、4個に限るものではなく、8個や16個あるいはさらに大きな個数の復号部を備えてもよい。
(3-1.概要)
まず、本発明の実施の形態3における画像復号装置の概要について説明する。
次に、本実施の形態の画像復号装置の構成について説明する。
次に、図22に示す画像復号装置300の動作について説明する。
このように、本実施の形態では、スイッチ38、スイッチ39、スイッチ40およびスイッチ41を設けることにより、2つの復号部を連携させて高性能を実現する動作と、異なる2つの符号化ストリームを同時に復号する動作とを切り替えることが可能になる。
なお、本実施の形態では、画像復号装置300は復号部を2個備えたが、4個やさらに大きな個数の復号部を備えてもよい。
(4-1.概要)
まず、本発明の実施の形態4における画像復号装置の概要について説明する。
次に、本実施の形態の画像復号装置の構成について説明する。
次に、図23に示す画像復号装置400の動作について説明する。
このように、本実施の形態では、スイッチ42によって入力を切り替えることにより、2つの復号部を連携させて高性能を実現する動作と、異なる2つの符号化ストリームを同時に復号する動作を切り替えて動作させることが可能になる。
なお、本実施の形態では、2つのCPBを用いて、2つの符号化ストリームに対する時分割並列復号処理を行ったが、CPBおよび符号化ストリームの数は、2つに限るものではなく、3つや4つあるいはさらに大きな数であってもよい。
(5-1.概要)
まず、本発明の実施の形態5における画像復号装置の概要について説明する。
次に、本実施の形態の画像復号装置の構成について説明する。
次に、本実施の形態の画像復号装置500の動作について説明する。
本実施の形態では、実施の形態1と同様、復号部5と復号部6を用いて並列に復号することにより、復号部5あるいは復号部6を単独で動作させる場合に比べて2倍の性能を実現することができる。つまり、本実施の形態における画像復号装置500は、通常のフレームレートの2倍のフレームレートでピクチャを復号することができる。一方、一般的な表示装置では、ピクチャを表示する速度が通常のフレームレートに固定または設定され、2倍のフレームレートで表示することができない。そこで、本実施の形態における画像復号装置500では、出画部43によって、復号されたピクチャを間引くことにより、2倍速の滑らかな早送り画像を表示装置に表示させることができる。
なお、本実施の形態の画像復号装置500は、2倍速の早送り画像を表示装置に表示させたが、3倍速や4倍速の早送り画像を表示させてもよい。この場合、出画部43は、n倍速(nは2以上の整数)に応じた比率でピクチャを間引く。なお、nは整数に限らない。nが整数でない場合は、出画部43は不均一にピクチャを間引いてもよい。
(6-1.概要)
まず、本発明の実施の形態6における画像復号装置の概要について説明する。
次に、本実施の形態の画像復号装置の構成について説明する。
次に、本実施の形態の画像復号装置600の動作について説明する。
H.264規格では、復号画像を書き込む際の転送量は、1つのマクロブロックあたり256バイトでよい。これに対して、動き補償で読み出す際の転送量は、8×8画素の双方向参照の場合では1352バイトであり、復号画像を書き込む際の転送量の約5倍である。本実施の形態では、復号画像を2つのフレームメモリに書き込み、動き補償で読み出すフレームメモリを2つの復号部で異なるフレームメモリとすることにより、フレームメモリから読み出すのに必要なアクセス性能を半分にすることが可能になり、フレームメモリの構成が容易になる。
なお、本実施の形態では、画像復号装置600はフレームメモリを2個備えたが、2個に限るものではなく、3個や4個あるいはさらに大きな個数のフレームメモリを備えてもよい。
(7-1.概要)
まず、本発明の実施の形態7における画像符号化装置の概要について説明する。
次に、本実施の形態の画像符号化装置の構成について説明する。
次に、本実施の形態の画像符号化装置の動作について説明する。
このように、本実施の形態では、符号化部51と符号化部52が周辺情報メモリ7と周辺情報メモリ8を用いて同期して並列に動作し、ストリーム結合部55が2つの分割ストリームを結合することにより、つまり、符号化対象の画像を構成する2つの部分を並列に符号化して結合することにより、例えばスライスなどの単位で構成されていないH.264規格の符号化ストリームを生成することが可能となる。さらに、本実施の形態では、1つの符号化部だけで画像を符号化する場合に比べて、処理性能を2倍にすることができる。また、同一性能を実現する場合には、各符号化部の動作周波数を半分にすることができ、消費電力の低減が可能である。
なお、本実施の形態の画像符号化装置700は、H.264規格にしたがって符号化を行ったが、例えばVC-1など、他の画像符号化規格にしたがって符号化を行ってもよい。
(8-1.概要)
まず、本発明の実施の形態8におけるトランスコード装置の概要について説明する。
次に、本実施の形態のトランスコード装置の構成について説明する。
次に、本実施の形態のトランスコード装置800の動作について説明する。
このように、本実施の形態では、CPB1の符号化ストリームの規格とは異なる符号化規格あるいは符号化ビットレートで、並列符号化部62が符号化を行うことにより、その符号化ストリームを異なる符号化規格又はビットレートの符号化ストリームに変換することができる。また、拡大縮小部61で画像の拡大または縮小を行うことによって、CPB1の符号化ストリームの画像サイズと異なる画像サイズの符号化ストリームに変換することが可能になる。
なお、本実施の形態におけるトランスコード装置800の拡大縮小部61は、拡大または縮小を行ったが、高画質処理を行ってもよく、拡大または縮小と高画質処理とを合わせて行ってもよい。さらに、トランスコード装置800は、拡大および縮小の何れも行わず、復号画像をそのまま符号化しても構わない。
本実施の形態の画像復号装置は、LSI(Large Scale Integration)とDRAM(Dynamic Random Access Memory)とを備える。
本実施の形態の画像復号装置は、2つのLSIと2つのDRAMとを備える。
本実施の形態の画像復号装置は、実施の形態10と同様、2つのLSIと2つのDRAMとを備えるが、2つのLSIのそれぞれにストリーム分割部2が備えられている点に特徴がある。
上記各実施の形態で示した画像復号装置、画像符号化装置またはトランスコード装置を実現するためのプログラムを記憶メディアに記録することにより、上記各実施の形態で示した処理を独立したコンピュータシステムにおいて簡単に実施することが可能となる。記憶メディアは、磁気ディスク、光ディスク、光磁気ディスク、ICカード、または半導体メモリ等、プログラムを記録できるものであればよい。
上記各実施の形態で示した画像復号装置および方法は、典型的には集積回路であるLSIで実現される。一例として、図38に1チップ化されたLSIex500の構成を示す。LSIex500は、以下に説明する要素ex502~ex509を備え、各要素はバスex510を介して接続している。電源回路部ex505は電源がオン状態の場合に各部に対して電力を供給することで動作可能な状態に起動する。
2,20 ストリーム分割部
3,4,21~24,53,54 バッファ
5,6,25~28,C2002 復号部
7,8,29~32 周辺情報メモリ
9,10,33~36 転送部
11,44 フレームメモリ
12 可変長復号部
13 逆量子化部
14 逆周波数変換部
15 再構成部
16 面内予測部
17 動きベクトル計算部
18 動き補償部
19 デブロックフィルタ部
38~42,C901 スイッチ
43 出画部
51,52 符号化部
55 ストリーム結合部
60 並列復号部
61 拡大縮小部
62 並列符号化部
100,100a,200,300,400,500,600,600a,600b,C100,C800,C900,C1301 画像復号装置
700,C1200,C1302 画像符号化装置
800,C1300 トランスコード装置
C101 分割部
C102,C1201 フレーム記憶部
C103 第1の復号部
C104 第2の復号部
C105,C1204,C2003 情報記憶部
C105a 第1の情報記憶部
C105b 第2の情報記憶部
C803 第1のスイッチ
C804 第2のスイッチ
C1202 第1の符号化部
C1203 第2の符号化部
C1205 結合部
C2001 集積回路
ex100 コンテンツ供給システム
ex101 インターネット
ex102 インターネットサービスプロバイダ
ex103 ストリーミングサーバ
ex104 電話網
ex107~ex110 基地局
ex111 コンピュータ
ex112 PDA(Personal Digital Assistant)
ex113 カメラ
ex114 携帯電話
ex116 カメラ
ex200 デジタル放送用システム
ex201 放送局
ex202 衛星
ex203 ケーブル
ex204,ex205 アンテナ
ex210 車
ex211 カーナビゲーション
ex212 再生装置
ex213,ex219 モニタ
ex215,ex216 記録メディア
ex217 セットトップボックス(STB)
ex218 リーダ/レコーダ
ex220 リモートコントローラ
ex230 情報トラック
ex231 記録ブロック
ex232 内周領域
ex233 データ記録領域
ex234 外周領域
ex300 テレビ(受信機)
ex301 チューナ
ex302 変調/復調部
ex303 多重/分離部
ex304 音声信号処理部
ex305 映像信号処理部
ex306 信号処理部
ex307 スピーカ
ex308 表示部
ex309 出力部
ex310 制御部
ex311 電源回路部
ex312 操作入力部
ex313 ブリッジ
ex314 スロット部
ex315 ドライバ
ex316 モデム
ex317 インタフェース部
ex318,ex319,ex404 バッファ
ex400 情報再生/記録部
ex401 光ヘッド
ex402 変調記録部
ex403 再生復調部
ex405 ディスクモータ
ex406 サーボ制御部
ex407 システム制御部
ex500 LSI
ex502 マイコン
ex503 メモリコントローラ
ex504 ストリームI/O
ex505 電源回路部
ex507 信号処理部
ex509 AVI/O
ex510 バス
ex511 メモリ
Claims (20)
- 符号化画像データを復号する画像復号装置であって、
前記符号化画像データは符号化されたピクチャを含み、前記ピクチャは複数のマクロブロックラインから構成され、前記マクロブロックラインは一列に配列された複数のマクロブロックから構成されており、
前記画像復号装置は、
前記ピクチャを構成する少なくとも1つのマクロブロックラインごとに、当該少なくとも1つのマクロブロックラインを第1または第2の符号化画像データの一部に割り当てることによって、前記ピクチャを第1および第2の符号化画像データに分割する分割部と、
前記第1および第2の符号化画像データのそれぞれに含まれる、前記ピクチャ内で互いに隣接するマクロブロックラインを並列に復号してフレーム記憶部に格納する第1および第2の復号部とを備え、
前記第1の復号部は、
情報記憶部に格納されている第2の復号結果情報を用いて前記第1の符号化画像データを復号し、当該復号によって生成される情報の一部を第1の復号結果情報として前記情報記憶部に格納し、
前記第1の符号化画像データに含まれる復号対象のマクロブロックを復号する際には、
当該復号対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する前記第2の復号部によって復号された他のマクロブロックの少なくとも一部である前記第2の復号結果情報と、前記復号対象のマクロブロックとに対して、画像処理を行い、画像処理された前記復号対象のマクロブロックおよび前記第2の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納し、
前記第2の復号部は、
前記情報記憶部に格納されている前記第1の復号結果情報を用いて前記第2の符号化画像データを復号し、当該復号によって生成される情報の一部を前記第2の復号結果情報として前記情報記憶部に格納し、
前記第2の符号化画像データに含まれる復号対象のマクロブロックを復号する際には、
当該復号対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する前記第1の復号部によって復号された他のマクロブロックの少なくとも一部である前記第1の復号結果情報と、前記復号対象のマクロブロックとに対して、画像処理を行い、画像処理された前記復号対象のマクロブロックおよび前記第1の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納する、
画像復号装置。 - 前記第1の復号部は、
前記第2の復号結果情報によって示される、復号された前記他のマクロブロックの少なくとも一部の画素値を、前記画像処理を行うことによって変化させ、
前記第2の復号部は、
前記第1の復号結果情報によって示される、復号された前記他のマクロブロックの少なくとも一部の画素値を、前記画像処理を行うことによって変化させる、
請求項1記載の画像復号装置。 - 前記第1の復号部は、
前記第2の復号結果情報と前記復号対象のマクロブロックとに対して、デブロックフィルタ処理を前記画像処理として行い、
前記第2の復号部は、
前記第1の復号結果情報と前記復号対象のマクロブロックとに対して、デブロックフィルタ処理を前記画像処理として行う、
請求項2記載の画像復号装置。 - 前記画像復号装置は、さらに、第1および第2の情報記憶部を有する前記情報記憶部を備え、
前記第1の復号部は、前記第1の情報記憶部から前記第2の復号結果情報を読み出して前記第1の符号化画像データの復号に用い、前記第1の復号結果情報を前記第2の情報記憶部に格納し、
前記第2の復号部は、前記第2の情報記憶部から前記第1の復号結果情報を読み出して前記第2の符号化画像データの復号に用い、前記第2の復号結果情報を前記第1の情報記憶部に格納する、
請求項1~3の何れか1項に記載の画像復号装置。 - 前記分割部は、前記ピクチャがMBAFF(Macro Block Adaptive Frame Field)構造によって符号化されている場合には、前記ピクチャを構成する互いに隣接する2つのマクロブロックラインごとに、当該2つのマクロブロックラインを第1または第2の符号化画像データの一部に割り当てることによって、前記ピクチャを分割する、
請求項1~4の何れか1項に記載の画像復号装置。 - 前記第1および第2の復号部は、前記第1および第2の情報記憶部を介して互いに同期した復号を行う、
請求項4に記載の画像復号装置。 - 前記第1の復号部は、前記第1の符号化画像データのうちの復号対象のマクロブロックの復号に必要な前記第2の復号結果情報が、前記第1の情報記憶部に格納されていない場合は、前記第2の復号結果情報が格納されるまで、前記復号対象のマクロブロックに対する復号を待ち、前記第2の復号結果情報が格納されると、前記復号対象のマクロブロックに対する復号を開始し、
前記第2の復号部は、前記第2の符号化画像データのうちの復号対象のマクロブロックの復号に必要な前記第1の復号結果情報が、前記第2の情報記憶部に格納されていない場合は、前記第1の復号結果情報が格納されるまで、前記復号対象のマクロブロックに対する復号を待ち、前記第1の復号結果情報が格納されると、前記復号対象のマクロブロックに対する復号を開始する、
請求項6に記載の画像復号装置。 - 前記画像復号装置は、さらに、
前記第1の情報記憶部に格納される情報を第1の情報と第2の情報とに切り替える第1のスイッチと、
前記第2の情報記憶部に格納される情報を第3の情報と第4の情報とに切り替える第2のスイッチとを備え、
前記第1の情報記憶部に格納される情報が前記第1のスイッチによって前記第1の情報に切り替えられ、前記第2の情報記憶部に格納される情報が前記第2のスイッチによって前記第3の情報に切り替えられた際には、
前記第1の復号部は、前記第1の復号結果情報を前記第3の情報として前記第2の情報記憶部に格納し、
前記第2の復号部は、前記第2の復号結果情報を前記第1の情報として前記第1の情報記憶部に格納し、
前記第1の情報記憶部に格納される情報が前記第1のスイッチによって前記第2の情報に切り替えられ、前記第2の情報記憶部に格納される情報が前記第2のスイッチによって前記第4の情報に切り替えられた際には、
前記第1の復号部は、さらに、前記第1の情報記憶部から前記第2の情報を読み出して他の符号化画像データの復号に用い、当該復号によって生成される情報の一部を新たな第2の情報として前記第1の情報記憶部に格納し、
前記第2の復号部は、さらに、前記第2の情報記憶部から前記第4の情報を読み出して前記符号化画像データの復号に用い、当該復号によって生成される情報の一部を新たな第4の情報として前記第2の情報記憶部に格納する、
請求項4に記載の画像復号装置。 - 前記画像復号装置は、さらに、
前記分割部による分割の対象とされるデータを前記符号化画像データと他の符号化画像データとに切り替えるスイッチを備え、
前記分割部は、
前記スイッチによって、分割の対象とされるデータが前記符号化画像データに切り替えられた際には、前記符号化画像データのピクチャを分割し、
前記スイッチによって、分割の対象とされるデータが前記他の符号化画像データに切り替えられた際には、前記他の符号化画像データのピクチャを分割する、
請求項1~8の何れか1項に記載の画像復号装置。 - 前記画像復号装置は、さらに、
復号された前記第1および第2の符号化画像データである動画像を前記フレーム記憶部から読み出し、表示装置によって設定されているフレームレートで前記動画像が表示されるように、前記動画像に含まれるピクチャを間引き、ピクチャが間引きされた前記動画像を前記表示装置に出力する出画部を備える、
請求項1~9の何れか1項に記載の画像復号装置。 - 前記フレーム記憶部は、第1のフレーム記憶部と、第2のフレーム記憶部とを備え、
前記第1の復号部は、前記第1の符号化画像データの復号に参照される参照画像を前記第1のフレーム記憶部から読み出し、復号された前記第1の符号化画像データを前記第1および第2のフレーム記憶部に書き込み、
前記第2の復号部は、前記第2の符号化画像データの復号に参照される参照画像を前記第2のフレーム記憶部から読み出し、復号された前記第2の符号化画像データを前記第1および第2のフレーム記憶部に書き込む、
請求項1~10の何れか1項に記載の画像復号装置。 - 画像データを符号化する画像符号化装置であって、
前記画像データはピクチャを含み、前記ピクチャは複数のマクロブロックラインから構成され、前記マクロブロックラインは一列に配列された複数のマクロブロックから構成されており、
前記画像符号化装置は、
前記画像データに含まれる第1および第2の画像データをフレーム記憶部から読み出して並列に符号化することによって第1および第2の符号化画像データを生成する第1および第2の符号化部と、
前記第1および第2の符号化部によって生成された第1および第2の符号化画像データのそれぞれに含まれるマクロブロックラインが前記ピクチャ内で互いに隣接するように、前記第1および第2の符号化画像データを結合する結合部とを備え、
前記第1の符号化部は、
情報記憶部に格納されている第2の符号化結果情報を用いて前記第1の画像データを符号化し、当該符号化によって生成される情報の一部を第1の符号化結果情報として前記情報記憶部に格納し、
前記第1の画像データに含まれる符号化対象のマクロブロックを符号化する際には、
当該符号化対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する他のマクロブロックの少なくとも一部である前記第2の符号化結果情報と、前記符号化対象のマクロブロックとに対して、画像処理を行い、画像処理された前記符号化対象のマクロブロックおよび前記第2の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納し、
前記第2の符号化部は、
前記情報記憶部に格納されている前記第1の符号化結果情報を用いて前記第2の画像データを符号化し、当該符号化によって生成される情報の一部を前記第2の符号化結果情報として前記情報記憶部に格納し、
前記第2の画像データに含まれる符号化対象のマクロブロックを符号化する際には、
当該符号化対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する他のマクロブロックの少なくとも一部である前記第1の符号化結果情報と、前記符号化対象のマクロブロックとに対して、画像処理を行い、画像処理された前記符号化対象のマクロブロックおよび前記第1の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納する、
画像符号化装置。 - 符号化画像データを復号してさらに符号化するトランスコード装置であって、
請求項1~11の何れか1項に記載の画像復号装置と、
前記画像復号装置によって復号された前記第1および第2の符号化画像データであって前記フレーム記憶部に格納されている画像データを符号化する画像符号化装置とを備える
トランスコード装置。 - 符号化画像データを復号してさらに符号化するトランスコード装置であって、
前記符号化画像データを復号する画像復号装置と、
前記画像復号装置によって復号された符号化画像データである画像データを符号化する請求項12に記載の画像符号化装置とを備える
トランスコード装置。 - 符号化画像データを復号する画像復号方法であって、
前記符号化画像データは符号化されたピクチャを含み、前記ピクチャは複数のマクロブロックラインから構成され、前記マクロブロックラインは一列に配列された複数のマクロブロックから構成されており、
前記画像復号方法は、
前記ピクチャを構成する少なくとも1つのマクロブロックラインごとに、当該少なくとも1つのマクロブロックラインを第1または第2の符号化画像データの一部に割り当てることによって、前記ピクチャを第1および第2の符号化画像データに分割し、
前記第1および第2の符号化画像データのそれぞれに含まれる、前記ピクチャ内で互いに隣接するマクロブロックラインを並列に復号してフレーム記憶部に格納し、
前記第1の符号化画像データを復号する際には、
情報記憶部に格納されている第2の復号結果情報を用いて前記第1の符号化画像データを復号し、当該復号によって生成される情報の一部を第1の復号結果情報として前記情報記憶部に格納し、
前記第1の符号化画像データに含まれる復号対象のマクロブロックを復号する際には、
当該復号対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する復号された他のマクロブロックの少なくとも一部である前記第2の復号結果情報と、前記復号対象のマクロブロックとに対して、画像処理を行い、画像処理された前記復号対象のマクロブロックおよび前記第2の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納し、
前記第2の符号化画像データを復号する際には、
前記情報記憶部に格納されている前記第1の復号結果情報を用いて前記第2の符号化画像データを復号し、当該復号によって生成される情報の一部を前記第2の復号結果情報として前記情報記憶部に格納し、
前記第2の符号化画像データに含まれる復号対象のマクロブロックを復号する際には、
当該復号対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する復号された他のマクロブロックの少なくとも一部である前記第1の復号結果情報と、前記復号対象のマクロブロックとに対して、画像処理を行い、画像処理された前記復号対象のマクロブロックおよび前記第1の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納する、
画像復号方法。 - 画像データを符号化する画像符号化方法であって、
前記画像データはピクチャを含み、前記ピクチャは複数のマクロブロックラインから構成され、前記マクロブロックラインは一列に配列された複数のマクロブロックから構成されており、
前記画像符号化方法は、
前記画像データに含まれる第1および第2の画像データをフレーム記憶部から読み出して並列に符号化することによって第1および第2の符号化画像データを生成し、
生成された前記第1および第2の符号化画像データのそれぞれに含まれるマクロブロックラインが前記ピクチャ内で互いに隣接するように、前記第1および第2の符号化画像データを結合し、
前記第1の画像データを符号化する際には、
情報記憶部に格納されている第2の符号化結果情報を用いて前記第1の画像データを符号化し、当該符号化によって生成される情報の一部を第1の符号化結果情報として前記情報記憶部に格納し、
前記第1の画像データに含まれる符号化対象のマクロブロックを符号化する際には、
当該符号化対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する他のマクロブロックの少なくとも一部である前記第2の符号化結果情報と、前記符号化対象のマクロブロックとに対して、画像処理を行い、画像処理された前記符号化対象のマクロブロックおよび前記第2の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納し、
前記第2の画像データを符号化する際には、
前記情報記憶部に格納されている前記第1の符号化結果情報を用いて前記第2の画像データを符号化し、当該符号化によって生成される情報の一部を前記第2の符号化結果情報として前記情報記憶部に格納し、
前記第2の画像データに含まれる符号化対象のマクロブロックを符号化する際には、
当該符号化対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する他のマクロブロックの少なくとも一部である前記第1の符号化結果情報と、前記符号化対象のマクロブロックとに対して、画像処理を行い、画像処理された前記符号化対象のマクロブロックおよび前記第1の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納する
画像符号化方法。 - コンピュータを、請求項1~11の何れか1項に記載の画像復号装置として機能させるためのプログラム。
- コンピュータを、請求項12に記載の画像符号化装置として機能させるためのプログラム。
- 符号化画像データを復号する集積回路であって、
前記符号化画像データは符号化されたピクチャを含み、前記ピクチャは複数のマクロブロックラインから構成され、前記マクロブロックラインは一列に配列された複数のマクロブロックから構成されており、
前記集積回路は、
前記ピクチャを構成する少なくとも1つのマクロブロックラインごとに、当該少なくとも1つのマクロブロックラインを第1または第2の符号化画像データの一部に割り当てることによって、前記ピクチャを第1および第2の符号化画像データに分割する分割部と、
前記第1および第2の符号化画像データのそれぞれに含まれる、前記ピクチャ内で互いに隣接するマクロブロックラインを並列に復号してフレーム記憶部に格納する第1および第2の復号部とを備え、
前記第1の復号部は、
情報記憶部に格納されている第2の復号結果情報を用いて前記第1の符号化画像データを復号し、当該復号によって生成される情報の一部を第1の復号結果情報として前記情報記憶部に格納し、
前記第1の符号化画像データに含まれる復号対象のマクロブロックを復号する際には、
当該復号対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する前記第2の復号部によって復号された他のマクロブロックの少なくとも一部である前記第2の復号結果情報と、前記復号対象のマクロブロックとに対して、画像処理を行い、画像処理された前記復号対象のマクロブロックおよび前記第2の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納し、
前記第2の復号部は、
前記情報記憶部に格納されている前記第1の復号結果情報を用いて前記第2の符号化画像データを復号し、当該復号によって生成される情報の一部を前記第2の復号結果情報として前記情報記憶部に格納し、
前記第2の符号化画像データに含まれる復号対象のマクロブロックを復号する際には、
当該復号対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する前記第1の復号部によって復号された他のマクロブロックの少なくとも一部である前記第1の復号結果情報と、前記復号対象のマクロブロックとに対して、画像処理を行い、画像処理された前記復号対象のマクロブロックおよび前記第1の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納する
集積回路。 - 画像データを符号化する集積回路であって、
前記画像データはピクチャを含み、前記ピクチャは複数のマクロブロックラインから構成され、前記マクロブロックラインは一列に配列された複数のマクロブロックから構成されており、
前記集積回路は、
前記画像データに含まれる第1および第2の画像データをフレーム記憶部から読み出して並列に符号化することによって第1および第2の符号化画像データを生成する第1および第2の符号化部と、
前記第1および第2の符号化部によって生成された第1および第2の符号化画像データのそれぞれに含まれるマクロブロックラインが前記ピクチャ内で互いに隣接するように、前記第1および第2の符号化画像データを結合する結合部とを備え、
前記第1の符号化部は、
情報記憶部に格納されている第2の符号化結果情報を用いて前記第1の画像データを符号化し、当該符号化によって生成される情報の一部を第1の符号化結果情報として前記情報記憶部に格納し、
前記第1の画像データに含まれる符号化対象のマクロブロックを符号化する際には、
当該符号化対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する他のマクロブロックの少なくとも一部である前記第2の符号化結果情報と、前記符号化対象のマクロブロックとに対して、画像処理を行い、画像処理された前記符号化対象のマクロブロックおよび前記第2の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納し、
前記第2の符号化部は、
前記情報記憶部に格納されている前記第1の符号化結果情報を用いて前記第2の画像データを符号化し、当該符号化によって生成される情報の一部を前記第2の符号化結果情報として前記情報記憶部に格納し、
前記第2の画像データに含まれる符号化対象のマクロブロックを符号化する際には、
当該符号化対象のマクロブロックが属するマクロブロックラインに隣接する他のマクロブロックラインに属する他のマクロブロックの少なくとも一部である前記第1の符号化結果情報と、前記符号化対象のマクロブロックとに対して、画像処理を行い、画像処理された前記符号化対象のマクロブロックおよび前記第1の復号結果情報のそれぞれの少なくとも一部を前記フレーム記憶部に格納する、
集積回路。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014087861A1 (ja) * | 2012-12-06 | 2014-06-12 | ソニー株式会社 | 画像処理装置、画像処理方法、およびプログラム |
CN111103829A (zh) * | 2019-12-11 | 2020-05-05 | 旋智电子科技(上海)有限公司 | 一种电机控制装置和方法 |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8311111B2 (en) | 2008-09-11 | 2012-11-13 | Google Inc. | System and method for decoding using parallel processing |
FR2982983A1 (fr) * | 2011-11-22 | 2013-05-24 | Thomson Licensing | Procede de codage et de reconstruction d'un bloc de pixels et dispositifs correspondants |
US9100657B1 (en) | 2011-12-07 | 2015-08-04 | Google Inc. | Encoding time management in parallel real-time video encoding |
US20130259137A1 (en) * | 2012-03-30 | 2013-10-03 | Google Inc. | System and Method for Multi-Core Hardware Video Encoding And Decoding |
US8928804B2 (en) * | 2012-11-19 | 2015-01-06 | Broadcom Corporation | Managing encoder parameters for parallel transcoding |
US9357213B2 (en) * | 2012-12-12 | 2016-05-31 | Imagine Communications Corp. | High-density quality-adaptive multi-rate transcoder systems and methods |
JP6129574B2 (ja) * | 2013-02-13 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | 画像処理装置 |
US9210424B1 (en) | 2013-02-28 | 2015-12-08 | Google Inc. | Adaptive prediction block size in video coding |
CN103414902A (zh) * | 2013-08-26 | 2013-11-27 | 上海富瀚微电子有限公司 | 用于低功耗应用的avc并行编码方法 |
CN103458245B (zh) * | 2013-08-30 | 2016-12-28 | 上海高清数字科技产业有限公司 | 解码器运动补偿模块的流水设计方法及*** |
JP6234770B2 (ja) * | 2013-10-24 | 2017-11-22 | ルネサスエレクトロニクス株式会社 | 動画像復号処理装置、動画像符号化処理装置およびその動作方法 |
JP6490896B2 (ja) * | 2013-12-17 | 2019-03-27 | 株式会社メガチップス | 画像処理装置 |
WO2015118841A1 (ja) | 2014-02-10 | 2015-08-13 | 日本電気株式会社 | 映像符号化装置、映像符号化方法およびプログラム |
JP6390627B2 (ja) * | 2014-02-10 | 2018-09-19 | 日本電気株式会社 | 映像符号化装置、映像符号化方法およびプログラム |
US9154156B2 (en) * | 2014-02-25 | 2015-10-06 | Qualcomm Incorporated | Ternary line code design for controlled decision feedback equalizer error propagation |
US9787986B2 (en) * | 2014-06-30 | 2017-10-10 | Intel Corporation | Techniques for parallel video transcoding |
US9854261B2 (en) * | 2015-01-06 | 2017-12-26 | Microsoft Technology Licensing, Llc. | Detecting markers in an encoded video signal |
JP6540132B2 (ja) * | 2015-03-20 | 2019-07-10 | カシオ計算機株式会社 | 復号装置、復号方法、及び、プログラム |
US10027989B2 (en) * | 2015-05-06 | 2018-07-17 | Integrated Device Technology, Inc. | Method and apparatus for parallel decoding |
US9883194B2 (en) * | 2015-06-15 | 2018-01-30 | Microsoft Technology Licensing, Llc | Multiple bit rate video decoding |
US9832476B2 (en) | 2015-06-15 | 2017-11-28 | Microsoft Technology Licensing, Llc | Multiple bit rate video decoding |
US9807416B2 (en) | 2015-09-21 | 2017-10-31 | Google Inc. | Low-latency two-pass video coding |
CN105898380A (zh) * | 2015-12-14 | 2016-08-24 | 乐视云计算有限公司 | 快速启播网络视频的方法和装置 |
US9794574B2 (en) | 2016-01-11 | 2017-10-17 | Google Inc. | Adaptive tile data size coding for video and image compression |
US10542258B2 (en) | 2016-01-25 | 2020-01-21 | Google Llc | Tile copying for video compression |
CN107517399B (zh) * | 2016-06-16 | 2021-04-13 | 腾讯科技(深圳)有限公司 | 一种媒体信息同步的方法以及服务器 |
CN108833932B (zh) * | 2018-07-19 | 2021-01-05 | 湖南君瀚信息技术有限公司 | 一种实现高清视频超低延迟编解码及传输的方法及*** |
US10972744B2 (en) * | 2018-11-12 | 2021-04-06 | Analog Devices International Unlimited Company | Image scaling |
CN109660810B (zh) * | 2018-12-29 | 2021-07-27 | 湖南国科微电子股份有限公司 | 一种数据编码方法 |
US11019359B2 (en) * | 2019-01-15 | 2021-05-25 | Tencent America LLC | Chroma deblock filters for intra picture block compensation |
CN115203383A (zh) * | 2021-04-13 | 2022-10-18 | 澜起科技股份有限公司 | 用于在候选向量集中查询相似向量的方法和装置 |
US20230237730A1 (en) * | 2022-01-21 | 2023-07-27 | Meta Platforms Technologies, Llc | Memory structures to support changing view direction |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007060487A (ja) * | 2005-08-26 | 2007-03-08 | Sony Corp | 画像処理装置および画像処理方法、記録媒体、並びに、プログラム |
JP2008042571A (ja) | 2006-08-07 | 2008-02-21 | Renesas Technology Corp | 動画符号化と動画復号とのいずれかを実行する機能モジュールおよびそれを含む半導体集積回路 |
JP2008066973A (ja) * | 2006-09-06 | 2008-03-21 | Oki Electric Ind Co Ltd | 画像符号化装置及び画像符号化方法並びに画像復号化装置及び画像復号化方法 |
WO2009142021A1 (ja) * | 2008-05-23 | 2009-11-26 | パナソニック株式会社 | 画像復号化装置、画像復号化方法、画像符号化装置、及び画像符号化方法 |
JP2010035146A (ja) * | 2008-07-02 | 2010-02-12 | Canon Inc | 符号化装置および符号化方法 |
WO2010041472A1 (ja) | 2008-10-10 | 2010-04-15 | パナソニック株式会社 | 画像復号化装置および画像復号化方法 |
WO2010067505A1 (ja) | 2008-12-08 | 2010-06-17 | パナソニック株式会社 | 画像復号化装置および画像復号化方法 |
JP2010166533A (ja) * | 2009-01-19 | 2010-07-29 | Canon Inc | 符号化装置及びその制御方法、コンピュータプログラム |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06351000A (ja) * | 1993-06-07 | 1994-12-22 | Matsushita Electric Ind Co Ltd | 画像信号符号化装置と画像信号復号装置 |
JPH10178644A (ja) * | 1996-12-18 | 1998-06-30 | Sharp Corp | 動画像復号装置 |
JP4427827B2 (ja) * | 1998-07-15 | 2010-03-10 | ソニー株式会社 | データ処理方法、データ処理装置及び記録媒体 |
JP2004512784A (ja) | 2000-10-24 | 2004-04-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | エンベッドフィルタによるトランスコーディング方法及びトランスコーディング装置 |
FR2823943A1 (fr) * | 2001-04-24 | 2002-10-25 | Koninkl Philips Electronics Nv | Procede de detection de bruit dans un flux de donnees video codees |
US7305036B2 (en) | 2002-05-14 | 2007-12-04 | Broadcom Corporation | System and method for entropy code preprocessing |
US7660352B2 (en) * | 2003-04-04 | 2010-02-09 | Sony Corporation | Apparatus and method of parallel processing an MPEG-4 data stream |
JP4517592B2 (ja) * | 2003-06-16 | 2010-08-04 | ソニー株式会社 | 画像処理装置、画像処理方法、画像処理プログラムおよび記録媒体 |
DE10343220B3 (de) | 2003-09-18 | 2005-05-25 | Siemens Ag | Verfahren und Vorrichtung zur Transcodierung eines Datenstroms, der ein oder mehrere codierte digitalisierte Bilder umfasst |
JP4658563B2 (ja) | 2004-10-13 | 2011-03-23 | パナソニック株式会社 | 画像データ処理装置及び画像データ処理方法 |
DE102004056446A1 (de) * | 2004-11-23 | 2006-06-29 | Siemens Ag | Verfahren zur Transcodierung sowie Transcodiervorrichtung |
JP2007060488A (ja) * | 2005-08-26 | 2007-03-08 | Sony Corp | 画像処理素子および画像処理方法、記録媒体、並びに、プログラム |
JP5042568B2 (ja) * | 2006-09-07 | 2012-10-03 | 富士通株式会社 | Mpegデコーダ及びmpegエンコーダ |
JP2008072647A (ja) * | 2006-09-15 | 2008-03-27 | Toshiba Corp | 情報処理装置、デコーダおよび再生装置の動作制御方法 |
JP4875008B2 (ja) | 2007-03-07 | 2012-02-15 | パナソニック株式会社 | 動画像符号化方法、動画像復号化方法、動画像符号化装置及び動画像復号化装置 |
WO2008139708A1 (ja) * | 2007-04-27 | 2008-11-20 | Panasonic Corporation | 画像復号装置、画像復号システム、画像復号方法、及び集積回路 |
JP5294688B2 (ja) * | 2007-06-18 | 2013-09-18 | キヤノン株式会社 | 動画像圧縮符号化装置 |
US8649615B2 (en) | 2007-06-18 | 2014-02-11 | Canon Kabushiki Kaisha | Moving picture compression coding apparatus |
US20100020883A1 (en) | 2007-07-11 | 2010-01-28 | Panasonic Corporation | Transcoder, transcoding method, decoder, and decoding method |
JP4907487B2 (ja) * | 2007-10-24 | 2012-03-28 | 株式会社リコー | 画像処理装置、画像処理方法及び該方法を実行させるためのプログラムを格納したコンピュータ読み取り可能な記録媒体 |
KR100973657B1 (ko) * | 2007-11-01 | 2010-08-02 | 경희대학교 산학협력단 | 디블록킹 필터링을 포함하는 코덱 사이의 트랜스코딩 방법 및 장치 |
JP5309700B2 (ja) * | 2008-06-03 | 2013-10-09 | 富士通株式会社 | 動画像復号装置および符号化装置 |
EP2290985B1 (en) | 2008-06-10 | 2017-05-03 | Panasonic Intellectual Property Management Co., Ltd. | Image decoding apparatus and image coding apparatus |
JP2010136245A (ja) * | 2008-12-08 | 2010-06-17 | Toshiba Corp | 動画像処理装置及び方法 |
JP2010141513A (ja) * | 2008-12-10 | 2010-06-24 | Toshiba Corp | 演算装置及び動画像符号化装置 |
-
2011
- 2011-09-09 CN CN201180003835.7A patent/CN102550030B/zh not_active Expired - Fee Related
- 2011-09-09 EP EP11824746.9A patent/EP2618580B1/en not_active Not-in-force
- 2011-09-09 US US13/575,033 patent/US8982964B2/en not_active Expired - Fee Related
- 2011-09-09 US US13/496,341 patent/US9185406B2/en not_active Expired - Fee Related
- 2011-09-09 JP JP2012507539A patent/JPWO2012035730A1/ja active Pending
- 2011-09-09 EP EP11822877.4A patent/EP2618579B1/en not_active Not-in-force
- 2011-09-09 WO PCT/JP2011/005074 patent/WO2012035730A1/ja active Application Filing
- 2011-09-09 CN CN201180007180.0A patent/CN103098474B/zh not_active Expired - Fee Related
- 2011-09-09 WO PCT/JP2011/005063 patent/WO2012035728A1/ja active Application Filing
- 2011-09-09 JP JP2012533853A patent/JPWO2012035728A1/ja active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007060487A (ja) * | 2005-08-26 | 2007-03-08 | Sony Corp | 画像処理装置および画像処理方法、記録媒体、並びに、プログラム |
JP2008042571A (ja) | 2006-08-07 | 2008-02-21 | Renesas Technology Corp | 動画符号化と動画復号とのいずれかを実行する機能モジュールおよびそれを含む半導体集積回路 |
JP2008066973A (ja) * | 2006-09-06 | 2008-03-21 | Oki Electric Ind Co Ltd | 画像符号化装置及び画像符号化方法並びに画像復号化装置及び画像復号化方法 |
WO2009142021A1 (ja) * | 2008-05-23 | 2009-11-26 | パナソニック株式会社 | 画像復号化装置、画像復号化方法、画像符号化装置、及び画像符号化方法 |
JP2010035146A (ja) * | 2008-07-02 | 2010-02-12 | Canon Inc | 符号化装置および符号化方法 |
WO2010041472A1 (ja) | 2008-10-10 | 2010-04-15 | パナソニック株式会社 | 画像復号化装置および画像復号化方法 |
WO2010067505A1 (ja) | 2008-12-08 | 2010-06-17 | パナソニック株式会社 | 画像復号化装置および画像復号化方法 |
JP2010166533A (ja) * | 2009-01-19 | 2010-07-29 | Canon Inc | 符号化装置及びその制御方法、コンピュータプログラム |
Non-Patent Citations (2)
Title |
---|
See also references of EP2618579A4 * |
THOMAS WIEGAND ET AL.: "Overview of the H.264/AVC Video Coding Standard", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, July 2003 (2003-07-01), pages 1 - 19 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014087861A1 (ja) * | 2012-12-06 | 2014-06-12 | ソニー株式会社 | 画像処理装置、画像処理方法、およびプログラム |
JPWO2014087861A1 (ja) * | 2012-12-06 | 2017-01-05 | ソニー株式会社 | 画像処理装置、画像処理方法、およびプログラム |
CN111103829A (zh) * | 2019-12-11 | 2020-05-05 | 旋智电子科技(上海)有限公司 | 一种电机控制装置和方法 |
CN111103829B (zh) * | 2019-12-11 | 2024-05-17 | 旋智电子科技(上海)有限公司 | 一种电机控制装置和方法 |
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