WO2012018119A1 - Solar cell and method for manufacturing solar cell - Google Patents
Solar cell and method for manufacturing solar cell Download PDFInfo
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- WO2012018119A1 WO2012018119A1 PCT/JP2011/067961 JP2011067961W WO2012018119A1 WO 2012018119 A1 WO2012018119 A1 WO 2012018119A1 JP 2011067961 W JP2011067961 W JP 2011067961W WO 2012018119 A1 WO2012018119 A1 WO 2012018119A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
Definitions
- the present invention relates to a solar cell and a method for manufacturing a solar cell.
- Patent Document 1 a so-called back junction type solar cell in which a plurality of types of semiconductor junctions are formed on the back side of the solar cell is known (for example, Patent Document 1 below).
- this back junction solar cell it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher photoelectric conversion efficiency can be realized.
- the present invention has been made in view of such a point, and an object thereof is to provide a solar cell having high photoelectric conversion efficiency.
- the solar cell according to the present invention includes a crystalline semiconductor substrate, a first semiconductor layer, a first electrode, a second semiconductor layer, and a second electrode.
- the crystalline semiconductor substrate has first and second main surfaces.
- the crystalline semiconductor substrate has one of the first conductivity type of n-type and p-type.
- the first semiconductor layer is formed on the first main surface.
- the first semiconductor layer has the first conductivity type.
- the first electrode is formed on the first semiconductor layer.
- the second semiconductor layer is formed on the first main surface.
- the second semiconductor layer has the other second conductivity type of n-type and p-type.
- the second electrode is formed on the second semiconductor layer.
- the first and second electrodes are formed in a region excluding the edge portion of the first main surface.
- the solar cell according to the present invention further includes a third semiconductor layer.
- the amorphous semiconductor layer is formed on at least a part of the edge portion of the first main surface where the first and second electrodes are not formed.
- a method for manufacturing a solar cell according to the present invention includes a crystalline semiconductor substrate having first and second main surfaces and having one of n-type and p-type first conductivity types, and a first main surface.
- a first semiconductor layer formed on the surface and having a first conductivity type; a first electrode formed on the first semiconductor layer; and formed on the first main surface.
- a solar cell comprising: a second semiconductor layer having the second conductivity type of the other of n-type and p-type; and a second electrode formed on the second semiconductor layer It relates to a method for manufacturing.
- the first and second electrodes are formed in a region excluding an edge portion of the first major surface. A first on at least a portion of the end edge of the main surface where the first and second electrode is not formed to form the third semiconductor layer.
- a solar cell with high photoelectric conversion efficiency can be provided.
- FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
- FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 1.
- It is a flowchart showing the manufacturing process of the solar cell in 1st Embodiment.
- It is schematic sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.
- It is schematic sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.
- It is schematic sectional drawing for demonstrating the manufacturing process of the solar cell in 1st Embodiment.
- FIG. 1 is a plan view of the solar cell 1.
- the IN stacked body 12 and the IP stacked body 13 are drawn.
- the IN stacked body 12 and the IP stacked body 13 Since it is located under the electrode 15, it cannot be visually recognized.
- the solar cell 1 is a back junction solar cell.
- the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
- the solar cell 1 includes a semiconductor substrate 10.
- the semiconductor substrate 10 has a light receiving surface 10a as a second main surface and a back surface 10b as a first main surface.
- the semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a.
- the carriers are holes and electrons generated when light is absorbed by the semiconductor substrate 10.
- the semiconductor substrate 10 is composed of a crystalline semiconductor substrate having n-type or p-type conductivity.
- “Crystalline semiconductor substrate” means a single crystal semiconductor substrate or a polycrystalline semiconductor substrate. That is, the crystalline semiconductor substrate is not limited to a single crystal semiconductor substrate. Specific examples of the crystalline semiconductor substrate include a crystalline silicon substrate such as a single crystal silicon substrate and a polycrystalline silicon substrate.
- the semiconductor substrate 10 is formed of an n-type crystalline silicon substrate will be described.
- An i-type amorphous semiconductor layer 17 i is formed on the light receiving surface 10 a of the semiconductor substrate 10.
- the i-type amorphous semiconductor layer 17i is made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”).
- “Amorphous semiconductor” includes a microcrystalline semiconductor.
- a microcrystalline semiconductor refers to a semiconductor in which the average particle diameter of semiconductor crystals precipitated in an amorphous semiconductor is in the range of 1 nm to 50 nm.
- the semiconductor layer 17i is specifically formed of i-type amorphous silicon.
- the thickness of the semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation.
- the thickness of the semiconductor layer 17i can be, for example, about several to 250 inches.
- the n-type amorphous semiconductor layer 17n is formed on the semiconductor layer 17i.
- the n-type amorphous semiconductor layer 17 n has the same conductivity type as that of the semiconductor substrate 10. That is, the semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type. Specifically, in the present embodiment, the semiconductor layer 17n is made of n-type amorphous silicon.
- the thickness of the semiconductor layer 17n is not particularly limited. The thickness of the semiconductor layer 17n can be, for example, about 20 to 500 mm.
- an insulating layer 16 having a function as an antireflection film and a function as a protective film is formed on the semiconductor layer 17n.
- the insulating layer 16 can be formed of, for example, silicon oxide such as SiO2, silicon nitride such as SiN, or silicon oxynitride such as SiON.
- the thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied.
- the thickness of the insulating layer 16 can be set to, for example, about 80 nm to 1 ⁇ m.
- an IN stacked body 12 and an IP stacked body 13 are formed on the back surface 10b of the semiconductor substrate 10.
- each of the IN laminated body 12 and the IP laminated body 13 is formed in a comb-tooth shape.
- the IN stacked body 12 and the IP stacked body 13 are formed so as to be inserted into each other. For this reason, the IN stacked bodies 12 and the IP stacked bodies 13 are alternately arranged along the direction x perpendicular to the intersecting width direction y on the back surface 10b.
- the adjacent IN stacked body 12 and the IP stacked body 13 are in contact with each other in the direction x.
- the entire back surface 10 b is covered with the IN stacked body 12 and the IP stacked body 13.
- Each of the width W1 (see FIG. 2) of the IN stacked body 12 and the interval W2 between the IN stacked bodies 12 in the direction x can be set to about 100 ⁇ m to 1.5 mm, for example.
- the width W1 and the interval W2 may be equal to each other or may be different.
- the IN stacked body 12 includes an i-type amorphous semiconductor layer 12i formed on the back surface 10b and an n-type amorphous semiconductor layer 12n formed on the i-type amorphous semiconductor layer 12i. It is constituted by the laminate.
- the semiconductor layer 12i is made of an i-type semiconductor, like the semiconductor layer 17i.
- the thickness of the semiconductor layer 12i is not particularly limited as long as the thickness does not substantially contribute to power generation.
- the thickness of the semiconductor layer 12i can be, for example, about several to 250 inches.
- the semiconductor layer 12n is doped with an n-type dopant similarly to the semiconductor layer 17n, and has an n-type conductivity type like the semiconductor substrate 10.
- the semiconductor layer 12n is made of n-type amorphous silicon.
- the thickness of the semiconductor layer 12n is not particularly limited. The thickness of the semiconductor layer 12n can be, for example, about 20 to 500 mm.
- the insulating layer 18 is formed on both ends excluding the central portion in the direction x of the IN laminate 12.
- the central portion in the direction x of the IN stacked body 12 is exposed from the insulating layer 18.
- the width W3 in the direction x of the insulating layer 18 is not particularly limited, and can be, for example, about 1/3 of the width W1.
- the interval W4 in the direction x between the insulating layers 18 is not particularly limited, and can be, for example, about 3 of the width W1.
- the material of the insulating layer 18 is not particularly limited.
- the insulating layer 18 can be formed of, for example, silicon oxide such as SiO 2, silicon nitride such as SiN, or silicon oxynitride such as SiON.
- the insulating layer 18 can also be formed of a metal oxide such as titanium oxide or tantalum oxide.
- the insulating layer 18 is formed of silicon nitride.
- the insulating layer 18 improves the passivation of each of the semiconductor layers 12i, 12n, 13i, and 13p so that carriers generated in the semiconductor substrate 10 do not recombine in each of the semiconductor layers 12i, 12n, 13i, and 13p. Therefore, it is preferable that hydrogen is contained.
- IP stack 13 has a portion exposed from the IN laminate 12 of the back surface 10b, it is formed on the end portion of the insulating layer 18. For this reason, both end portions of the IP stacked body 13 overlap with the IN stacked body 12 in the height direction z.
- the IP stacked body 13 includes an i-type amorphous semiconductor layer 13i formed on the back surface 10b and a p-type amorphous semiconductor layer 13p formed on the i-type amorphous semiconductor layer 13i. It is constituted by the laminate.
- the semiconductor layer 13i is made of an i-type semiconductor.
- the thickness of the semiconductor layer 13i is not particularly limited as long as the thickness does not substantially contribute to power generation.
- the thickness of the semiconductor layer 13i can be, for example, about several to 250 inches.
- the semiconductor layer 13p is added p-type dopant, an amorphous semiconductor layer having p-type conductivity. Specifically, in the present embodiment, the semiconductor layer 13p is made of p-type amorphous silicon.
- the thickness of the semiconductor layer 13p is not particularly limited. The thickness of the semiconductor layer 13p can be, for example, about 20 to 500 mm.
- the semiconductor layer 13i having a thickness that does not substantially contribute to power generation is provided between the crystalline semiconductor substrate 10 and the semiconductor layer 13p.
- each of the semiconductor layers 17n, 12n, 13p, 17i, 12i, and 13i contains hydrogen in order to improve the passivation property of each junction interface.
- An electrode 14 for collecting holes is formed on the semiconductor layer 12n.
- an electrode 15 for collecting electrons is formed on the semiconductor layer 13p.
- the distance W5 between the electrodes 14 and 15 in the top of the insulating layer 18, for example, may be about 1/3 of the width W3.
- each of the IN laminate 12 and the IP laminate 13 is formed in a comb shape.
- the electrodes 14 and 15 are formed in a comb-tooth shape including a bus bar and a plurality of fingers.
- the electrodes 14 and 15 may be so-called bus bar-less electrodes that are configured by only a plurality of fingers and do not have a bus bar.
- the electrodes 14 and 15 are not particularly limited as long as they can collect carriers.
- the electrodes 14 and 15 can be made of, for example, a metal such as Cu or Ag, or an alloy containing one or more of these metals.
- the electrodes 14 and 15 can also be formed by, for example, TCO (Transparent Conductive Oxide) such as ITO (Indium Tin Oxide).
- TCO Transparent Conductive Oxide
- ITO Indium Tin Oxide
- the electrodes 14 and 15 may be composed of a laminate of a plurality of conductive layers made of the above metal, alloy or TCO.
- the electrodes 14 and 15 are formed in the central portion excluding the edge portion of the back surface 10b.
- the central portion of the back surface 10b where the electrodes 14 and 15 are formed is defined as a region 10b1.
- the edge part in which the electrodes 14 and 15 are not formed among the back surfaces 10b is set as the area
- the amorphous semiconductor layer 32 is formed on at least a part of the region 10b2 where the back surface 10b is exposed. Specifically, in the present embodiment, substantially the entire region 10 b 2 is covered with the amorphous semiconductor layer 32.
- the amorphous semiconductor layer 32 contains hydrogen in order to improve the passivation property of the amorphous semiconductor layer 32 so that carriers generated in the semiconductor substrate 10 do not recombine in the amorphous semiconductor layer 32. preferable.
- the amorphous semiconductor layer 32 includes an i-type amorphous semiconductor layer 32i and an n-type amorphous semiconductor layer 32n.
- the semiconductor layer 32i is formed on the region 10b2.
- the semiconductor layer 32i is made of an intrinsic amorphous semiconductor.
- the semiconductor layer 32i can be formed of, for example, i-type amorphous silicon.
- the semiconductor layer 32i is preferably made of the same material as the semiconductor layer 12i.
- the thickness of the semiconductor layer 32i is not particularly limited. The thickness of the semiconductor layer 32i can be, for example, about several to 250 inches.
- the amorphous semiconductor layer 32n is formed on the semiconductor layer 32i.
- the semiconductor layer 32 n has the same n-type conductivity as that of the semiconductor substrate 10.
- the semiconductor layer 32n can be formed of, for example, n-type amorphous silicon.
- the semiconductor layer 32n is preferably made of the same material as the semiconductor layer 12n.
- the thickness of the semiconductor layer 32n is not particularly limited. The thickness of the semiconductor layer 32n can be, for example, about 20 to 500 mm.
- An insulating layer 33 is formed on the amorphous semiconductor layer 32.
- the insulating layer 33 covers substantially the entire amorphous semiconductor layer 32.
- Insulating layer 33 is, for example, may be formed of a silicon oxide, silicon nitride, silicon oxynitride, a metal oxide such as titanium oxide or tantalum oxide.
- the insulating layer 33 is preferably formed of silicon oxide, silicon nitride, or silicon oxynitride.
- the insulating layer 33 is preferably made of the same material as the insulating layer 18.
- the insulating layer 33 improves the passivation of each of the semiconductor layers 12i, 12n, 13i, and 13p so that carriers generated in the semiconductor substrate 10 do not recombine in each of the semiconductor layers 12i, 12n, 13i, and 13p. Therefore, it is preferable that hydrogen is contained.
- the thickness of the insulating layer 33 is not particularly limited. The thickness of the insulating layer 33 can be, for example, about 10 nm to 1 ⁇ m.
- An amorphous semiconductor layer 34 is formed on the insulating layer 33.
- the amorphous semiconductor layer 34 substantially covers the entire insulating layer 33.
- the amorphous semiconductor layer 34 includes an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p.
- the semiconductor layer 34 i is formed on the insulating layer 33.
- the semiconductor layer 34i is made of an intrinsic amorphous semiconductor.
- the semiconductor layer 34i can be formed of, for example, i-type amorphous silicon. In the present embodiment, the semiconductor layer 34i is formed integrally with the semiconductor layer 13i located closest to the region 10b2.
- the semiconductor layer 34p is formed on the semiconductor layer 34i.
- the semiconductor layer 34p is made of a p-type amorphous semiconductor.
- the semiconductor layer 34p can be formed of, for example, p-type amorphous silicon.
- the semiconductor layer 34p is formed integrally with the semiconductor layer 13p.
- the amorphous semiconductor layer 32 is formed on the region 10b2.
- substantially the entire region 10 b 2 is covered with the amorphous semiconductor layer 32. Accordingly, recombination of minority carriers in the region 10b2 can be effectively suppressed. As a result, high photoelectric conversion efficiency can be realized.
- the amorphous semiconductor layer 32 contains hydrogen, recombination of minority carriers in the region 10b2 can be more effectively suppressed. As a result, higher photoelectric conversion efficiency can be realized.
- the semiconductor layer 32i in contact with the semiconductor substrate 10 is made of an intrinsic semiconductor. For this reason, the semiconductor layer 32i has few defects. Accordingly, recombination of minority carriers in the region 10b2 can be more effectively suppressed. As a result, higher photoelectric conversion efficiency can be realized.
- the semiconductor layer 32n is formed having the same conductivity type as the semiconductor substrate 10. For this reason, a BSF (Back Surface Field) effect is produced by the stacked body of the semiconductor layers 32i and 32n. As a result, higher photoelectric conversion efficiency can be realized.
- BSF Back Surface Field
- the electrodes 14 and 15 are formed up to the edge of the back surface 10b and the region 10b2 is not provided. However, for example, when forming the electrodes 14 and 15 made of a plating film, a region for preventing the electrodes 14 and 15 from being formed beyond the edge is required on the back surface 10b. it is preferable to provide a.
- the insulating layer 33 is formed on the amorphous semiconductor layer 32. For this reason, for example, it is possible to effectively suppress the occurrence of defects in the amorphous semiconductor layer 32 due to intrusion of heavy metal ions, alkali metal ions, transition metal ions, and the like into the amorphous semiconductor layer 32. As a result, high photoelectric conversion efficiency can be maintained over a long period of time. Insulating layer 33, silicon oxide, preferably formed of silicon nitride, the silicon oxynitride, and more preferably formed of silicon nitride. This is because the weather resistance and gas barrier properties of the insulating layer 33 can be improved, and the penetration of various ions into the amorphous semiconductor layer 32 can be more effectively suppressed.
- the semiconductor substrate 10 is covered with the semiconductor layer 12i in a region where the electrodes 14 and 15 between the electrodes 14 and 15 in the region 10b1 are not formed. Therefore, recombination of minority carriers in a region where the electrode 14 and 15 between the electrodes 14 and 15 in the region 10b1 are not formed can be effectively suppressed. Therefore, higher photoelectric conversion efficiency can be realized.
- FIGS. 7 to 13 are cross-sectional views of the portion including the edge portion, as in FIG.
- a semiconductor substrate 10 (see FIG. 5) is prepared.
- step S1 the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned.
- the semiconductor substrate 10 can be cleaned using, for example, an HF aqueous solution.
- step S2 a semiconductor layer 17i and a semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and an i-type amorphous material is formed on the back surface 10b.
- each of the semiconductor layers 17i, 17n, 21, 22 is not particularly limited.
- the semiconductor layers 17i, 17n, 21, and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a thin film forming method such as a sputtering method.
- CVD Chemical Vapor Deposition
- the insulating layer 16 is formed on the semiconductor layer 17n, and the insulating layer 23 is formed on the semiconductor layer 22.
- the formation method of the insulating layers 16 and 23 is not specifically limited.
- the insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
- step S4 the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, of the insulating layer 23, the portion located over the area which process bonding the p-type semiconductor layer on the semiconductor substrate 10 in a later removed. Thereby, the insulating layer 23a and the insulating layer 33 shown in FIG. 3 are formed.
- the insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.
- step S5 the semiconductor layers 21 and 22 are etched using an alkaline etchant using the insulating layers 23a and 33 as a mask. By this etching, portions other than the portions covered by the insulating layers 23a and 33 of the semiconductor layer 21 and the semiconductor layer 22 are removed. This exposes a portion of the back surface 10b where the insulating layer 23 is not located above, and forms the semiconductor layers 12i, 12n, 32i, and 32n from the semiconductor layers 21 and 22.
- the insulating layers 23a and 33 are made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layers 23a and 33 by the acidic etching solution is high, the etching rate of the insulating layers 23a and 33 by the alkaline etching solution is low.
- the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution.
- the insulating layers 23a and 33 are etched by the acidic etching solution used in step S4, the semiconductor layers 21 and 22 are not substantially etched.
- the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in step S5, but the insulating layers 23a and 33 are not substantially etched. Therefore, in steps S4 and S5, the insulating layers 23a and 33 or the semiconductor layers 21 and 22 can be selectively etched.
- step S6 the i-type amorphous semiconductor layer 24 and the p-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b.
- a method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited.
- the semiconductor layers 24 and 25 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
- step S7 a part of the portion of the semiconductor layers 24 and 25 (see FIG. 9) located on the insulating layer 23a is etched. Thereby, the semiconductor layers 13i, 13p, 34i, and 34p are formed from the amorphous semiconductor layers 24 and 25.
- step S7 a first etching agent having an etching rate for the amorphous semiconductor layers 24 and 25 (see FIG. 9) larger than that for the insulating layers 23a and 33 is used. Therefore, in the insulating layer 23a, 33 and the amorphous semiconductor layer 24, the amorphous semiconductor layers 24 and 25 are selectively etched.
- a specific example of the first etching agent is an aqueous NaOH solution containing NaOH.
- the insulating layer 23a is etched in step S8. Specifically, the exposed portion of the insulating layer 23 is removed from above the semiconductor layers 13i, 13p, 34i, and 34p by etching using a second etching agent. Thus, the semiconductor layer 12n is exposed and the insulating layer 18 is formed from the insulating layer 23a.
- a second etching agent having an etching rate for the insulating layer 23a larger than that for the semiconductor layers 13i, 13p, 34i, and 34p is used. For this reason, the insulating layer 23a is selectively etched among the insulating layer 23a and the semiconductor layers 13i, 13p, 34i, and 34p.
- a specific example of the second etching agent is an HF aqueous solution containing HF.
- the solar cell 1 can be completed by performing the electrode formation process which forms the electrodes 14 and 15 on each of the semiconductor layer 12n and the semiconductor layer 13p in step S9. .
- the formation method of the electrodes 14 and 15 can be suitably selected according to the material of the electrode. Specifically, in this embodiment, the electrodes 14 and 15 are formed as follows.
- a conductive layer 26 made of TCO and a conductive layer 27 made of a metal or alloy such as Cu are formed into a thin film such as a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a sputtering method. by law they are formed in this order.
- CVD Chemical Vapor Deposition
- the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided by, for example, photolithography. At the same time, the portions of the conductive layers 26 and 27 located on the insulating layer 33 are also etched. Then, the semiconductor layers 13i, 13p, 34i, and 34p located on the insulating layer 18 are also divided at the same time. Next, the electrodes 14 and 15 can be completed by forming a plating film on the conductive layer 27.
- the manufacturing method of the solar cell 1 is formed by an amorphous semiconductor layer 32 and the IN laminate 12 common process.
- the insulating layer 33 is formed by a process common to the insulating layer 18. Therefore, the solar cell 1 can be easily manufactured with a small number of processes without complicating the manufacturing process.
- the insulating layer 33 is damaged or removed, for example, in the step of forming the insulating layer 18 by etching the insulating layer 23a or the step of dividing the conductive layers 26 and 27. It may be done.
- the insulating layer 33 is covered with the amorphous semiconductor layer 34. For this reason, it can suppress effectively that the insulating layer 33 is damaged or removed in the etching process of the insulating layer 23a, the dividing process of the conductive layers 26 and 27, and the like.
- the amorphous semiconductor layer 34 is formed integrally with the IP stacked body 13 adjacent to the region 10b2. Therefore, the manufacturing process of the solar cell 1 can be simplified.
- FIG. 14 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (first modification) of the first embodiment.
- the i-type amorphous semiconductor layer 32i is formed on the back surface 10b of the semiconductor substrate 10, and the n-type amorphous semiconductor layer 32i has n.
- the example in which the type amorphous semiconductor layer 32n is formed has been described.
- an n-type amorphous semiconductor layer may be formed immediately above the back surface 10b of the semiconductor substrate 10 without interposing an i-type amorphous semiconductor layer.
- an amorphous semiconductor layer 34 formed of a stacked body of an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p may be provided on the back surface 10b.
- a p-type amorphous semiconductor layer may be formed immediately above the back surface 10b.
- the insulating layer is not formed.
- the amorphous semiconductor layer 34 is not electrically connected to any of the electrodes 14 and 15.
- FIGS. 29 to 30 may be used. Specifically, this will be described with reference to FIGS.
- FIG. 29 is a schematic cross-sectional view of a second modification corresponding to the schematic cross-sectional view (FIG. 3) of the first embodiment.
- the second modification is different from the first embodiment in that the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are formed on the back surface region 10b2 of the semiconductor substrate 10. It is a point provided with the IP laminated body 34 laminated
- the stack position of the IP stacked body 34 in the region 10b1 of the first embodiment is the region.
- the configuration is opposite to that formed on the semiconductor substrate 10 side of the stacking position of the 10b2 IP stack 34. That is, in the second modification, the stack position of the IP stacked body 34 in the region 10b2 is formed closer to the semiconductor substrate 10 than the stack position of the IP stacked body 34 in the region 10b1.
- the conductive layers 26 and 27 on the region 10b2 are removed. Then, electrodes 14 and 15 made of a plating film are formed on the remaining conductive layers 26 and 27. Then, the solar cell 1 of FIG. 29 provided with the IP stacked body 34 in which the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order is obtained in the region 10b1.
- the IN stacked body 32 in which the i-type amorphous semiconductor layer 32i and the n-type amorphous semiconductor layer 32n are stacked in this order is etched, then the insulating layers 18 and 33 are etched, and then the i-type amorphous semiconductor layer 32n is etched.
- the stacked structure of the solar cell 1 of FIG. 29 is obtained by etching the IP stacked body 34 in which the amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order.
- Figure 30 a schematic cross-sectional view of a third modified example corresponding to the schematic cross-sectional view of the first embodiment (FIG. 3).
- the third modification is different from the first embodiment in that an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p are formed on a region 10b2 on the back surface side of the semiconductor substrate 10. It is a point provided with the IP laminated body 34 and the insulating layer 33 laminated
- the region 10b2 When manufacturing the third modification, after forming the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p on the entire surface of the n-type semiconductor substrate 10, the region 10b2 The upper i-type amorphous semiconductor layer 34i and p-type amorphous semiconductor layer 34p are removed. Then, conductive layers 26 and 27 are formed only on the remaining i-type amorphous semiconductor layer 34 i and p-type amorphous semiconductor layer 34 p, and an electrode 14 made of a plating film is formed on the conductive layers 26 and 27. , to form a 15. As a result, the solar cell 1 of FIG. 30 including the IP stacked body 34 and the insulating layer 33 in which the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order is obtained in the region 10b2. .
- FIG. 15 is a schematic plan view of a solar cell in the second embodiment.
- FIG. 16 is a schematic cross-sectional view of the central portion of the solar cell in the second embodiment.
- FIG. 17 is a schematic cross-sectional view of an edge portion of the solar cell in the second embodiment.
- the insulating layer 18 is formed on both ends in the x direction of the n-type amorphous semiconductor layer 12n, and the p-type amorphous is formed on the insulating layer 18.
- An example in which a part of the semiconductor layer 13p is located has been described.
- the insulating layer 18 is formed on the p-type amorphous semiconductor layer 13p, and a part of the n-type amorphous semiconductor layer 12n is formed on the insulating layer 18. positioned.
- the solar cell 2 has substantially the same configuration as the solar cell 1 according to the first embodiment.
- the minority carriers are holes. Accordingly, to suppress loss due to recombination of holes which are minority carriers is important from the viewpoint of enhancing the photoelectric conversion efficiency of the solar cell 1.
- minority carriers (holes) generated below the p-type amorphous semiconductor layer 13p have a short moving distance until they are collected by the electrode 15. For this reason, minority carriers generated below the p-type amorphous semiconductor layer 13p are unlikely to disappear due to recombination before being collected by the electrode 15.
- the minority carriers generated below the n-type amorphous semiconductor layer 12n have a long distance that must be moved before being collected by the electrode 15. For this reason, minority carriers generated below the n-type amorphous semiconductor layer 12 n are likely to disappear due to recombination before being collected by the electrode 15.
- the widths of the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p are reduced and the width of the n-type amorphous semiconductor layer 12n is set to p. It is preferable to make it relatively small with respect to the type amorphous semiconductor layer 13p. By doing so, the distance that minority carriers must travel before being collected by the electrode 15 can be reduced.
- the width of the semiconductor layer located under the insulating layer cannot be reduced so much. Therefore, when the n-type amorphous semiconductor layer 12n is located under the insulating layer 18 as in the solar cell 1 according to the first embodiment, the width of the n-type amorphous semiconductor layer 12n is sufficiently large. can not be reduced to.
- the p-type amorphous semiconductor layer 13p is located under the insulating layer 18, and the insulating layer is formed on the n-type amorphous semiconductor layer 12n. It has not been. For this reason, it becomes easy to make the width of the n-type amorphous semiconductor layer 12n relatively smaller than the p-type amorphous semiconductor layer 13p. Accordingly, it is possible to reduce the distance that must be traveled before the holes generated below the n-type amorphous semiconductor layer 12n are collected by the electrode 15. As a result, recombination of minority carriers can be suppressed. Therefore, the photoelectric conversion efficiency of the solar cell 2 can be improved.
- the width of the p-type amorphous semiconductor layer 13p along the x direction is 1.1 times or more than the width of the n-type amorphous semiconductor layer 12n along the x direction. Preferably, it is 1.5 times or more.
- the semiconductor substrate 10 is n-type, it is preferable to make the semiconductor layer located under the insulating layer 18 p-type.
- the insulating layer is preferably n-type. That is, it is preferable that the semiconductor layer located under the semiconductor layer has a conductivity type different from that of the semiconductor substrate so as to improve passivation properties so that carriers generated in the semiconductor substrate 10 do not recombine.
- FIG. 18 is a flowchart showing the manufacturing process of the solar cell in the second embodiment.
- 19 to 27 are schematic cross-sectional views for explaining a manufacturing process of the solar cell in the second embodiment. Next, an example of a method for manufacturing the solar cell 2 will be described with reference to FIGS. 19 to 27 are cross-sectional views of the portion including the edge portion, similarly to FIG.
- step S11 the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned in the same manner as in step S1 of the first embodiment.
- step S12 the semiconductor layer 17i and the semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and the i-type amorphous semiconductor layer 21 is formed on the back surface 10b.
- a p-type amorphous semiconductor layer 40 is formed.
- step S13 the insulating layer 16 is formed on the semiconductor layer 17n, and the insulating layer 23 is formed on the semiconductor layer 40.
- step S14 the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, of the insulating layer 23, the portion located over the area which process bonding the n-type semiconductor layer on the semiconductor substrate 10 in a later removed. Thereby, the insulating layer 23a and the insulating layer 33 are formed.
- step S15 using the insulating layers 23a and 33 as a mask, the semiconductor layer 21 (see FIG. 21) and the semiconductor layer 40 (see FIG. 21) are mixed with an alkaline etching solution. Etching is used to remove portions of the semiconductor layer 21 and the semiconductor layer 40 other than the portions covered with the insulating layers 23a and 33. As a result, the portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the semiconductor layers 13i, 13p, 34i, and 34p are formed from the semiconductor layers 21 and 40.
- step S16 the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 41 are sequentially formed in this order so as to cover the exposed portion of the back surface 10b.
- step S17 etching the portion of the portion located on the insulating layer 23a of the semiconductor layer 24, 41.
- the semiconductor layers 12i, 12n, 32i, and 32n are formed from the amorphous semiconductor layers 24 and 41.
- step S18 the insulating layer 23a is etched. Specifically, the exposed portion of the insulating layer 23 is removed by etching from above the semiconductor layers 12i, 12n, 32i, and 32n using a second etching agent. Thereby, the semiconductor layer 13p is exposed and the insulating layer 18 is formed from the insulating layer 23a.
- step S19 the solar cell 2 can be completed by performing an electrode formation process for forming the electrodes 14 and 15 on the semiconductor layer 12n and the semiconductor layer 13p, respectively. it can.
- a conductive layer 26 made of TCO and a conductive layer 27 made of a metal or alloy such as Cu first, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method, a sputtering method, or the like. These are formed in this order by the thin film forming method.
- CVD Chemical Vapor Deposition
- the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided by, for example, photolithography. At the same time, the portions of the conductive layers 26 and 27 located on the insulating layer 33 are also etched. Then, the semiconductor layers 12i, 12n, 32i, and 32n located on the insulating layer 18 are also divided at the same time. Next, the electrodes 14 and 15 can be completed by forming a plating film on the conductive layer 27.
- the solar cell 2 can be easily manufactured by a small number of processes without complicating the manufacturing process. Moreover, since the insulating layer 33 is covered with the amorphous semiconductor layer 32, it is possible to effectively suppress the insulating layer 33 from being damaged or removed in the manufacturing process of the solar cell 2.
- the amorphous semiconductor layer 32 is formed integrally with the IN stacked body 12 adjacent to the region 10b2. Therefore, the manufacturing process of the solar cell 2 can be simplified.
- the p-type amorphous semiconductor layer 13p is formed before the n-type amorphous semiconductor layer 12n.
- the semiconductor layers 13i and 13p are formed on the back surface 10b immediately after the substrate 10 is cleaned in step S1. For this reason, the cleanliness of the back surface 10b immediately before forming the semiconductor layers 13i and 13p can be further increased. Therefore, a higher quality pn junction can be formed. Therefore, higher photoelectric conversion efficiency can be obtained.
- FIG. 28 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (second modification) of the second embodiment.
- the i-type amorphous semiconductor layer 34i is formed on the back surface 10b of the semiconductor substrate 10, and the p-type amorphous semiconductor layer 34i has a p
- the example in which the type amorphous semiconductor layer 34p is formed has been described.
- a p-type amorphous semiconductor layer may be formed immediately above the back surface 10b of the semiconductor substrate 10 without using an i-type amorphous semiconductor layer.
- an amorphous semiconductor layer 32 made of a stacked body of an i-type amorphous semiconductor layer 32i and an n-type amorphous semiconductor layer 32n may be provided on the back surface 10b.
- an n-type amorphous semiconductor layer may be formed directly on the back surface 10b.
- the amorphous semiconductor layer 32 is not electrically connected to any of the electrodes 14 and 15.
- the present invention is not limited to this configuration.
- a p-type amorphous semiconductor layer may be provided immediately above the back surface 10b without providing an i-type amorphous semiconductor layer.
- n-type amorphous semiconductor layer 24 ... i-type amorphous semiconductor layer 25 ... p-type amorphous semiconductor layers 26, 27 ... conductive layer 32 ... amorphous Semiconductor layer 32i ... i-type amorphous semiconductor layer 32n ... n-type amorphous semiconductor layer 34 ... amorphous semiconductor layer 34i ... i-type amorphous semiconductor layer 34p ... p-type amorphous semiconductor layer
Abstract
[Problem] To provide a solar cell which has high photoelectric conversion efficiency. [Solution] A solar cell (1) comprises: a crystalline semiconductor substrate (10) that has a first conductivity type; a first semiconductor layer (12n) that has the first conductivity type; a first electrode (14) that is formed on the first semiconductor layer (12n); a second semiconductor layer (13p) that has a second conductivity type; and a second electrode (15) that is formed on the second semiconductor layer (13p). The first and second semiconductor layers (12n, 13p) are formed on a first main surface (10a). The first and second electrodes (14, 15) are formed in a region (10b1) of the first main surface (10a) excluding an end edge portion (10b2). The solar cell (1) additionally comprises a third semiconductor layer (32). The amorphous semiconductor layer (32) is formed on at least a part of the end edge portion (10b2).
Description
本発明は、太陽電池及び太陽電池の製造方法に関する。
The present invention relates to a solar cell and a method for manufacturing a solar cell.
従来、太陽電池の裏面側に複数種類の半導体接合が形成されている所謂裏面接合型の太陽電池が知られている（例えば、下記の特許文献１）。この裏面接合型の太陽電池では、受光面側に電極を設ける必要がない。このため、裏面接合型の太陽電池では、光の受光効率を高めることができる。従って、より高い光電変換効率を実現し得る。
Conventionally, a so-called back junction type solar cell in which a plurality of types of semiconductor junctions are formed on the back side of the solar cell is known (for example, Patent Document 1 below). In this back junction solar cell, it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher photoelectric conversion efficiency can be realized.
裏面接合型の太陽電池の光電変換効率をさらに高めたいという要望がある。
There is a desire to further increase the photoelectric conversion efficiency of back junction solar cells.
本発明は、斯かる点に鑑みてなされたものであり、その目的は、光電変換効率の高い太陽電池を提供することにある。
The present invention has been made in view of such a point, and an object thereof is to provide a solar cell having high photoelectric conversion efficiency.
本発明に係る太陽電池は、結晶性半導体基板と、第１の半導体層と、第１の電極と、第２の半導体層と、第２の電極とを備えている。結晶性半導体基板は、第１及び第２の主面を有する。結晶性半導体基板は、ｎ型及びｐ型のうちの一方の第１の導電型を有する。第１の半導体層は、第１の主面の上に形成されている。第１の半導体層は、第１の導電型を有する。第１の電極は、第１の半導体層の上に形成されている。第２の半導体層は、第１の主面の上に形成されている。第２の半導体層は、ｎ型及びｐ型のうちの他方の第２の導電型を有する。第２の電極は、第２の半導体層の上に形成されている。第１及び第２の電極は、第１の主面の端縁部を除く領域に形成されている。本発明に係る太陽電池は、第３の半導体層をさらに備えている。非晶質半導体層は、第１及び第２の電極が形成されていない第１の主面の端縁部の少なくとも一部の上に形成されている。
The solar cell according to the present invention includes a crystalline semiconductor substrate, a first semiconductor layer, a first electrode, a second semiconductor layer, and a second electrode. The crystalline semiconductor substrate has first and second main surfaces. The crystalline semiconductor substrate has one of the first conductivity type of n-type and p-type. The first semiconductor layer is formed on the first main surface. The first semiconductor layer has the first conductivity type. The first electrode is formed on the first semiconductor layer. The second semiconductor layer is formed on the first main surface. The second semiconductor layer has the other second conductivity type of n-type and p-type. The second electrode is formed on the second semiconductor layer. The first and second electrodes are formed in a region excluding the edge portion of the first main surface. The solar cell according to the present invention further includes a third semiconductor layer. The amorphous semiconductor layer is formed on at least a part of the edge portion of the first main surface where the first and second electrodes are not formed.
本発明に係る太陽電池の製造方法は、第１及び第２の主面を有し、ｎ型及びｐ型のうちの一方の第１の導電型を有する結晶性半導体基板と、第１の主面の上に形成されており、第１の導電型を有する第１の半導体層と、第１の半導体層の上に形成されている第１の電極と、第１の主面の上に形成されており、ｎ型及びｐ型のうちの他方の第２の導電型を有する第２の半導体層と、第２の半導体層の上に形成されている第２の電極とを備える太陽電池の製造方法に関する。本発明に係る太陽電池の製造方法では、第１及び第２の電極を、第１の主面の端縁部を除く領域に形成する。第１及び第２の電極が形成されていない第１の主面の端縁部の少なくとも一部の上に第３の半導体層を形成する。
A method for manufacturing a solar cell according to the present invention includes a crystalline semiconductor substrate having first and second main surfaces and having one of n-type and p-type first conductivity types, and a first main surface. A first semiconductor layer formed on the surface and having a first conductivity type; a first electrode formed on the first semiconductor layer; and formed on the first main surface. A solar cell comprising: a second semiconductor layer having the second conductivity type of the other of n-type and p-type; and a second electrode formed on the second semiconductor layer It relates to a method for manufacturing. The method for manufacturing a solar cell according to the present invention, the first and second electrodes are formed in a region excluding an edge portion of the first major surface. A first on at least a portion of the end edge of the main surface where the first and second electrode is not formed to form the third semiconductor layer.
本発明によれば、光電変換効率の高い太陽電池を提供することができる。
According to the present invention, a solar cell with high photoelectric conversion efficiency can be provided.
以下、本発明の好ましい実施形態の一例について説明する。但し、下記の実施形態は、単なる一例である。本発明は、下記の実施形態に何ら限定されない。
Hereinafter, an example of a preferred embodiment of the present invention will be described. However, the following embodiment is merely an example. The present invention is not limited to the following embodiments.
また、実施形態等において参照する各図面において、実質的に同一の機能を有する部材は同一の符号で参照することとする。また、実施形態等において参照する図面は、模式的に記載されたものである。図面に描画された物体の寸法の比率などは、現実の物体の寸法の比率などとは異なる場合がある。図面相互間においても、物体の寸法比率等が異なる場合がある。具体的な物体の寸法比率等は、以下の説明を参酌して判断されるべきである。
In each drawing referred to in the embodiment and the like, members having substantially the same function are referred to by the same reference numerals. The drawings referred to in the embodiments and the like are schematically described. A ratio of dimensions of an object drawn in a drawing may be different from a ratio of dimensions of an actual object. The dimensional ratio of the object may be different between the drawings. The specific dimensional ratio of the object should be determined in consideration of the following description.
《第１の実施形態》
（太陽電池１の構成）
本実施形態に係る太陽電池１の構成について、図１～図３を参照しながら詳細に説明する。なお、図１は、太陽電池１の平面図である。図１においては、説明の便宜上、ＩＮ積層体１２及びＩＰ積層体１３を描画しているが、太陽電池１を平面視した際には、ＩＮ積層体１２及びＩＰ積層体１３は、電極１４または電極１５の下に位置しているため、視認することはできない。 << First Embodiment >>
(Configuration of solar cell 1)
The configuration of the solar cell 1 according to this embodiment will be described in detail with reference to FIGS. FIG. 1 is a plan view of the solar cell 1. In FIG. 1, for convenience of explanation, the INstacked body 12 and the IP stacked body 13 are drawn. However, when the solar cell 1 is viewed in plan, the IN stacked body 12 and the IP stacked body 13 Since it is located under the electrode 15, it cannot be visually recognized.
（太陽電池１の構成）
本実施形態に係る太陽電池１の構成について、図１～図３を参照しながら詳細に説明する。なお、図１は、太陽電池１の平面図である。図１においては、説明の便宜上、ＩＮ積層体１２及びＩＰ積層体１３を描画しているが、太陽電池１を平面視した際には、ＩＮ積層体１２及びＩＰ積層体１３は、電極１４または電極１５の下に位置しているため、視認することはできない。 << First Embodiment >>
(Configuration of solar cell 1)
The configuration of the solar cell 1 according to this embodiment will be described in detail with reference to FIGS. FIG. 1 is a plan view of the solar cell 1. In FIG. 1, for convenience of explanation, the IN
太陽電池１は、裏面接合型の太陽電池である。なお、本実施形態の太陽電池１単体では、十分に大きな出力が得られない場合は、太陽電池１は、複数の太陽電池１が配線材により接続された太陽電池モジュールとして利用されることもある。
The solar cell 1 is a back junction solar cell. In addition, when the solar cell 1 of this embodiment alone cannot obtain a sufficiently large output, the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
図２及び図３に示すように、太陽電池１は、半導体基板１０を備えている。半導体基板１０は、第２の主面としての受光面１０ａと、第１の主面としての裏面１０ｂとを有する。半導体基板１０は、受光面１０ａにおいて、光１１を受光することによってキャリアを生成する。ここで、キャリアとは、光が半導体基板１０に吸収されることにより生成する正孔及び電子のことである。
As shown in FIGS. 2 and 3, the solar cell 1 includes a semiconductor substrate 10. The semiconductor substrate 10 has a light receiving surface 10a as a second main surface and a back surface 10b as a first main surface. The semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a. Here, the carriers are holes and electrons generated when light is absorbed by the semiconductor substrate 10.
半導体基板１０は、ｎ型またはｐ型の導電型を有する結晶性半導体基板により構成されている。「結晶性半導体基板」とは、単結晶半導体基板または多結晶半導体基板を意味するものとする。すなわち、結晶性半導体基板は、単結晶半導体基板に限定されない。結晶性半導体基板の具体例としては、例えば、単結晶シリコン基板、多結晶シリコン基板などの結晶シリコン基板が挙げられる。以下、本実施形態では、半導体基板１０がｎ型の結晶性シリコン基板により構成されている例について説明する。
The semiconductor substrate 10 is composed of a crystalline semiconductor substrate having n-type or p-type conductivity. “Crystalline semiconductor substrate” means a single crystal semiconductor substrate or a polycrystalline semiconductor substrate. That is, the crystalline semiconductor substrate is not limited to a single crystal semiconductor substrate. Specific examples of the crystalline semiconductor substrate include a crystalline silicon substrate such as a single crystal silicon substrate and a polycrystalline silicon substrate. Hereinafter, in the present embodiment, an example in which the semiconductor substrate 10 is formed of an n-type crystalline silicon substrate will be described.
半導体基板１０の受光面１０ａの上には、ｉ型非晶質半導体層１７ｉが形成されている。ｉ型非晶質半導体層１７ｉは、真性な非晶質半導体（以下、真性な半導体を「ｉ型半導体」とする。）からなる。「非晶質半導体」には、微結晶半導体を含むものとする。微結晶半導体とは、非晶質半導体中に析出している半導体結晶の平均粒子径が１ｎｍ～５０ｎｍの範囲内にある半導体をいう。本実施形態においては、半導体層１７ｉは、具体的には、ｉ型のアモルファスシリコンにより形成されている。半導体層１７ｉの厚みは、発電に実質的に寄与しない程度の厚みである限りにおいて特に限定されない。半導体層１７ｉの厚みは、例えば、数Å～２５０Å程度とすることができる。
An i-type amorphous semiconductor layer 17 i is formed on the light receiving surface 10 a of the semiconductor substrate 10. The i-type amorphous semiconductor layer 17i is made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”). “Amorphous semiconductor” includes a microcrystalline semiconductor. A microcrystalline semiconductor refers to a semiconductor in which the average particle diameter of semiconductor crystals precipitated in an amorphous semiconductor is in the range of 1 nm to 50 nm. In the present embodiment, the semiconductor layer 17i is specifically formed of i-type amorphous silicon. The thickness of the semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the semiconductor layer 17i can be, for example, about several to 250 inches.
半導体層１７ｉの上には、ｎ型非晶質半導体層１７ｎが形成されている。ｎ型非晶質半導体層１７ｎは、半導体基板１０と同じ導電型を有する。すなわち、半導体層１７ｎは、ｎ型のドーパントが添加されており、ｎ型の導電型を有する非晶質半導体層である。具体的には、本実施形態では、半導体層１７ｎは、ｎ型アモルファスシリコンからなる。半導体層１７ｎの厚みは、特に限定されない。半導体層１７ｎの厚みは、例えば、２０Å～５００Å程度とすることができる。
An n-type amorphous semiconductor layer 17n is formed on the semiconductor layer 17i. The n-type amorphous semiconductor layer 17 n has the same conductivity type as that of the semiconductor substrate 10. That is, the semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type. Specifically, in the present embodiment, the semiconductor layer 17n is made of n-type amorphous silicon. The thickness of the semiconductor layer 17n is not particularly limited. The thickness of the semiconductor layer 17n can be, for example, about 20 to 500 mm.
半導体層１７ｎの上には、反射防止膜としての機能と保護膜としての機能とを兼ね備えた絶縁層１６が形成されている。絶縁層１６は、例えば、ＳｉＯ２などの酸化ケイ素、ＳｉＮなどの窒化ケイ素、ＳｉＯＮなどの酸窒化ケイ素により形成することができる。絶縁層１６の厚みは、付与しようとする反射防止膜の反射防止特性などに応じて適宜設定することができる。絶縁層１６の厚みは、例えば８０ｎｍ～１μｍ程度とすることができる。
On the semiconductor layer 17n, an insulating layer 16 having a function as an antireflection film and a function as a protective film is formed. The insulating layer 16 can be formed of, for example, silicon oxide such as SiO2, silicon nitride such as SiN, or silicon oxynitride such as SiON. The thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied. The thickness of the insulating layer 16 can be set to, for example, about 80 nm to 1 μm.
半導体基板１０の裏面１０ｂの上には、ＩＮ積層体１２とＩＰ積層体１３とが形成されている。図１に示すように、ＩＮ積層体１２とＩＰ積層体１３とのそれぞれは、くし歯状に形成されている。ＩＮ積層体１２とＩＰ積層体１３とは互いに間挿し合うように形成されている。このため、裏面１０ｂ上において、ＩＮ積層体１２とＩＰ積層体１３とは、交差幅方向ｙに垂直な方向ｘに沿って交互に配列されている。図２に示すように、方向ｘにおいて隣り合うＩＮ積層体１２とＩＰ積層体１３とは接触している。すなわち、本実施形態では、ＩＮ積層体１２とＩＰ積層体１３とによって、裏面１０ｂの実質的に全体が被覆されている。なお、ＩＮ積層体１２の幅Ｗ１（図２を参照）と、方向ｘにおけるＩＮ積層体１２の間隔Ｗ２とのそれぞれは、例えば、１００μｍ～１．５ｍｍ程度とすることができる。幅Ｗ１と間隔Ｗ２とは、互いに等しくてもよいし、異なっていてもよい。
On the back surface 10b of the semiconductor substrate 10, an IN stacked body 12 and an IP stacked body 13 are formed. As shown in FIG. 1, each of the IN laminated body 12 and the IP laminated body 13 is formed in a comb-tooth shape. The IN stacked body 12 and the IP stacked body 13 are formed so as to be inserted into each other. For this reason, the IN stacked bodies 12 and the IP stacked bodies 13 are alternately arranged along the direction x perpendicular to the intersecting width direction y on the back surface 10b. As shown in FIG. 2, the adjacent IN stacked body 12 and the IP stacked body 13 are in contact with each other in the direction x. In other words, in the present embodiment, the entire back surface 10 b is covered with the IN stacked body 12 and the IP stacked body 13. Each of the width W1 (see FIG. 2) of the IN stacked body 12 and the interval W2 between the IN stacked bodies 12 in the direction x can be set to about 100 μm to 1.5 mm, for example. The width W1 and the interval W2 may be equal to each other or may be different.
ＩＮ積層体１２は、裏面１０ｂの上に形成されているｉ型非晶質半導体層１２ｉと、ｉ型非晶質半導体層１２ｉの上に形成されているｎ型非晶質半導体層１２ｎとの積層体により構成されている。
The IN stacked body 12 includes an i-type amorphous semiconductor layer 12i formed on the back surface 10b and an n-type amorphous semiconductor layer 12n formed on the i-type amorphous semiconductor layer 12i. It is constituted by the laminate.
半導体層１２ｉは、上記半導体層１７ｉと同様に、ｉ型半導体からなる。半導体層１２ｉの厚みは、発電に実質的に寄与しない程度の厚みである限りにおいて特に限定されない。半導体層１２ｉの厚みは、例えば、数Å～２５０Å程度とすることができる。
The semiconductor layer 12i is made of an i-type semiconductor, like the semiconductor layer 17i. The thickness of the semiconductor layer 12i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the semiconductor layer 12i can be, for example, about several to 250 inches.
半導体層１２ｎは、上記半導体層１７ｎと同様に、ｎ型のドーパントが添加されており、半導体基板１０と同様に、ｎ型の導電型を有する。具体的には、本実施形態では、半導体層１２ｎは、ｎ型アモルファスシリコンからなる。半導体層１２ｎの厚みは、特に限定されない。半導体層１２ｎの厚みは、例えば、２０Å～５００Å程度とすることができる。
The semiconductor layer 12n is doped with an n-type dopant similarly to the semiconductor layer 17n, and has an n-type conductivity type like the semiconductor substrate 10. Specifically, in the present embodiment, the semiconductor layer 12n is made of n-type amorphous silicon. The thickness of the semiconductor layer 12n is not particularly limited. The thickness of the semiconductor layer 12n can be, for example, about 20 to 500 mm.
ＩＮ積層体１２の方向ｘにおける中央部を除く両端部の上には、絶縁層１８が形成されている。ＩＮ積層体１２の方向ｘにおける中央部は、絶縁層１８から露出している。絶縁層１８の方向ｘにおける幅Ｗ３は特に限定されず、例えば、幅Ｗ１の約１／３程度とすることができる。また、絶縁層１８間の方向ｘにおける間隔Ｗ４も特に限定されず、例えば、幅Ｗ１の約１／３程度とすることができる。
The insulating layer 18 is formed on both ends excluding the central portion in the direction x of the IN laminate 12. The central portion in the direction x of the IN stacked body 12 is exposed from the insulating layer 18. The width W3 in the direction x of the insulating layer 18 is not particularly limited, and can be, for example, about 1/3 of the width W1. Further, the interval W4 in the direction x between the insulating layers 18 is not particularly limited, and can be, for example, about ３ of the width W1.
絶縁層１８の材質は、特に限定されない。絶縁層１８は、例えば、ＳｉＯ２などの酸化ケイ素、ＳｉＮなどの窒化ケイ素、ＳｉＯＮなどの酸窒化ケイ素により形成することができる。また、絶縁層１８は、酸化チタンや酸化タンタルなどの金属酸化物により形成することもできる。なかでも、絶縁層１８は、窒化ケイ素により形成されていることが好ましい。また、絶縁層１８は、半導体基板１０で発生したキャリアが半導体層１２ｉ，１２ｎ，１３ｉ，１３ｐの各々で再結合しないように、半導体層１２ｉ，１２ｎ，１３ｉ，１３ｐの各々のパッシベーション性を向上させるために水素を含んでいることが好ましい。
The material of the insulating layer 18 is not particularly limited. The insulating layer 18 can be formed of, for example, silicon oxide such as SiO 2, silicon nitride such as SiN, or silicon oxynitride such as SiON. The insulating layer 18 can also be formed of a metal oxide such as titanium oxide or tantalum oxide. Especially, it is preferable that the insulating layer 18 is formed of silicon nitride. In addition, the insulating layer 18 improves the passivation of each of the semiconductor layers 12i, 12n, 13i, and 13p so that carriers generated in the semiconductor substrate 10 do not recombine in each of the semiconductor layers 12i, 12n, 13i, and 13p. Therefore, it is preferable that hydrogen is contained.
ＩＰ積層体１３は、裏面１０ｂのＩＮ積層体１２から露出した部分と、絶縁層１８の端部との上に形成されている。このため、ＩＰ積層体１３の両端部は、ＩＮ積層体１２と高さ方向ｚにおいて重なっている。
IP stack 13 has a portion exposed from the IN laminate 12 of the back surface 10b, it is formed on the end portion of the insulating layer 18. For this reason, both end portions of the IP stacked body 13 overlap with the IN stacked body 12 in the height direction z.
ＩＰ積層体１３は、裏面１０ｂの上に形成されているｉ型非晶質半導体層１３ｉと、ｉ型非晶質半導体層１３ｉの上に形成されているｐ型非晶質半導体層１３ｐとの積層体により構成されている。
The IP stacked body 13 includes an i-type amorphous semiconductor layer 13i formed on the back surface 10b and a p-type amorphous semiconductor layer 13p formed on the i-type amorphous semiconductor layer 13i. It is constituted by the laminate.
半導体層１３ｉは、ｉ型半導体からなる。半導体層１３ｉの厚みは、発電に実質的に寄与しない程度の厚みである限りにおいて特に限定されない。半導体層１３ｉの厚みは、例えば、数Å～２５０Å程度とすることができる。
The semiconductor layer 13i is made of an i-type semiconductor. The thickness of the semiconductor layer 13i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the semiconductor layer 13i can be, for example, about several to 250 inches.
半導体層１３ｐは、ｐ型のドーパントが添加されており、ｐ型の導電型を有する非晶質半導体層である。具体的には、本実施形態では、半導体層１３ｐは、ｐ型のアモルファスシリコンからなる。半導体層１３ｐの厚みは、特に限定されない。半導体層１３ｐの厚みは、例えば、２０Å～５００Å程度とすることができる。
The semiconductor layer 13p is added p-type dopant, an amorphous semiconductor layer having p-type conductivity. Specifically, in the present embodiment, the semiconductor layer 13p is made of p-type amorphous silicon. The thickness of the semiconductor layer 13p is not particularly limited. The thickness of the semiconductor layer 13p can be, for example, about 20 to 500 mm.
このように、本実施形態では、結晶性の半導体基板１０と半導体層１３ｐとの間に、実質的に発電に寄与しない程度の厚みの半導体層１３ｉが設けられている。これにより、半導体基板１０とＩＰ積層体１３との接合界面における少数キャリアの再結合を抑制することができる。その結果、光電変換効率の向上を図ることができる。
Thus, in this embodiment, the semiconductor layer 13i having a thickness that does not substantially contribute to power generation is provided between the crystalline semiconductor substrate 10 and the semiconductor layer 13p. Thereby, recombination of minority carriers at the bonding interface between the semiconductor substrate 10 and the IP stacked body 13 can be suppressed. As a result, the photoelectric conversion efficiency can be improved.
なお、半導体層１７ｎ、１２ｎ、１３ｐ、１７ｉ、１２ｉ、１３ｉのそれぞれは、それぞれの接合界面のパッシベーション性を向上させるために水素を含むものであることが好ましい。
In addition, it is preferable that each of the semiconductor layers 17n, 12n, 13p, 17i, 12i, and 13i contains hydrogen in order to improve the passivation property of each junction interface.
半導体層１２ｎの上には、正孔を収集する電極１４が形成されている。一方、半導体層１３ｐの上には、電子を収集する電極１５が形成されている。なお、絶縁層１８の上における電極１４と電極１５との間の間隔Ｗ５は、例えば、幅Ｗ３の１／３程度とすることができる。
An electrode 14 for collecting holes is formed on the semiconductor layer 12n. On the other hand, an electrode 15 for collecting electrons is formed on the semiconductor layer 13p. The distance W5 between the electrodes 14 and 15 in the top of the insulating layer 18, for example, may be about 1/3 of the width W3.
上述の通り、本実施形態では、ＩＮ積層体１２とＩＰ積層体１３とのそれぞれはくし歯状に形成されている。このため、電極１４，１５は、バスバー及び複数のフィンガーを含むくし歯状に形成されている。もっとも、電極１４，１５は、複数のフィンガーのみにより構成されており、バスバーを有さない所謂バスバーレス型の電極であってもよい。
As described above, in the present embodiment, each of the IN laminate 12 and the IP laminate 13 is formed in a comb shape. For this reason, the electrodes 14 and 15 are formed in a comb-tooth shape including a bus bar and a plurality of fingers. However, the electrodes 14 and 15 may be so-called bus bar-less electrodes that are configured by only a plurality of fingers and do not have a bus bar.
なお、電極１４，１５は、キャリアを収集できるものである限りにおいて特に限定されない。電極１４，１５は、例えば、Ｃｕ，Ａｇなどの金属や、それらの金属のうちの一種以上を含む合金により形成することができる。また、電極１４，１５は、例えば、ＩＴＯ（インジウム錫酸化物）などのＴＣＯ（Ｔｒａｎｓｐａｒｅｎｔ Ｃｏｎｄｕｃｔｉｖｅ Ｏｘｉｄｅ）等により形成することもできる。電極１４，１５は、上記金属、合金またはＴＣＯからなる複数の導電層の積層体により構成されていてもよい。
The electrodes 14 and 15 are not particularly limited as long as they can collect carriers. The electrodes 14 and 15 can be made of, for example, a metal such as Cu or Ag, or an alloy containing one or more of these metals. The electrodes 14 and 15 can also be formed by, for example, TCO (Transparent Conductive Oxide) such as ITO (Indium Tin Oxide). The electrodes 14 and 15 may be composed of a laminate of a plurality of conductive layers made of the above metal, alloy or TCO.
図１に示すように、電極１４，１５は、裏面１０ｂの端縁部を除く中央部に形成されている。本実施形態においては、裏面１０ｂのうち、電極１４，１５が形成されている中央部を、領域１０ｂ１とする。裏面１０ｂのうち、電極１４，１５が形成されていない端縁部を、領域１０ｂ２とする。
As shown in FIG. 1, the electrodes 14 and 15 are formed in the central portion excluding the edge portion of the back surface 10b. In the present embodiment, the central portion of the back surface 10b where the electrodes 14 and 15 are formed is defined as a region 10b1. The edge part in which the electrodes 14 and 15 are not formed among the back surfaces 10b is set as the area | region 10b2.
図３に示すように、本実施形態では、裏面１０ｂが露出している領域１０ｂ２の少なくとも一部の上には、非晶質半導体層３２が形成されている。具体的には、本実施形態では、実質的に領域１０ｂ２の全体が非晶質半導体層３２により覆われている。非晶質半導体層３２は、半導体基板１０で発生したキャリアが非晶質半導体層３２で再結合しないように、非晶質半導体層３２のパッシベーション性を向上させるために水素を含んでいることが好ましい。
As shown in FIG. 3, in this embodiment, the amorphous semiconductor layer 32 is formed on at least a part of the region 10b2 where the back surface 10b is exposed. Specifically, in the present embodiment, substantially the entire region 10 b 2 is covered with the amorphous semiconductor layer 32. The amorphous semiconductor layer 32 contains hydrogen in order to improve the passivation property of the amorphous semiconductor layer 32 so that carriers generated in the semiconductor substrate 10 do not recombine in the amorphous semiconductor layer 32. preferable.
非晶質半導体層３２は、ｉ型非晶質半導体層３２ｉと、ｎ型非晶質半導体層３２ｎとを有する。半導体層３２ｉは、領域１０ｂ２の上に形成されている。半導体層３２ｉは、真性な非晶質半導体からなる。半導体層３２ｉは、例えば、ｉ型のアモルファスシリコンにより形成することができる。半導体層３２ｉは、半導体層１２ｉと同一の材料からなることが好ましい。なお、半導体層３２ｉの厚みは、特に限定されない。半導体層３２ｉの厚みは、例えば、数Å～２５０Å程度とすることができる。
The amorphous semiconductor layer 32 includes an i-type amorphous semiconductor layer 32i and an n-type amorphous semiconductor layer 32n. The semiconductor layer 32i is formed on the region 10b2. The semiconductor layer 32i is made of an intrinsic amorphous semiconductor. The semiconductor layer 32i can be formed of, for example, i-type amorphous silicon. The semiconductor layer 32i is preferably made of the same material as the semiconductor layer 12i. The thickness of the semiconductor layer 32i is not particularly limited. The thickness of the semiconductor layer 32i can be, for example, about several to 250 inches.
非晶質半導体層３２ｎは、半導体層３２ｉの上に形成されている。半導体層３２ｎは、半導体基板１０と同じｎ型の導電型を有している。半導体層３２ｎは、例えば、ｎ型のアモルファスシリコンにより形成することができる。半導体層３２ｎは、半導体層１２ｎと同一の材料からなることが好ましい。なお、半導体層３２ｎの厚みは、特に限定されない。半導体層３２ｎの厚みは、例えば、２０Å～５００Å程度とすることができる。
The amorphous semiconductor layer 32n is formed on the semiconductor layer 32i. The semiconductor layer 32 n has the same n-type conductivity as that of the semiconductor substrate 10. The semiconductor layer 32n can be formed of, for example, n-type amorphous silicon. The semiconductor layer 32n is preferably made of the same material as the semiconductor layer 12n. The thickness of the semiconductor layer 32n is not particularly limited. The thickness of the semiconductor layer 32n can be, for example, about 20 to 500 mm.
非晶質半導体層３２の上には、絶縁層３３が形成されている。この絶縁層３３により非晶質半導体層３２の実質的に全体が覆われている。絶縁層３３は、例えば、酸化シリコン、窒化シリコン、酸窒化シリコン、酸化チタンや酸化タンタルなどの金属酸化物により形成することができる。なかでも、絶縁層３３は、酸化シリコン、窒化シリコンまたは酸窒化シリコンにより形成されていることが好ましい。絶縁層３３は、絶縁層１８と同一の材料からなることが好ましい。また、絶縁層３３は、半導体基板１０で発生したキャリアが半導体層１２ｉ，１２ｎ，１３ｉ，１３ｐの各々で再結合しないように、半導体層１２ｉ，１２ｎ，１３ｉ，１３ｐの各々のパッシベーション性を向上させるために水素を含んでいることが好ましい。なお、絶縁層３３の厚みは、特に限定されない。絶縁層３３の厚みは、例えば、１０ｎｍ～１μｍ程度とすることができる。
An insulating layer 33 is formed on the amorphous semiconductor layer 32. The insulating layer 33 covers substantially the entire amorphous semiconductor layer 32. Insulating layer 33 is, for example, may be formed of a silicon oxide, silicon nitride, silicon oxynitride, a metal oxide such as titanium oxide or tantalum oxide. In particular, the insulating layer 33 is preferably formed of silicon oxide, silicon nitride, or silicon oxynitride. The insulating layer 33 is preferably made of the same material as the insulating layer 18. The insulating layer 33 improves the passivation of each of the semiconductor layers 12i, 12n, 13i, and 13p so that carriers generated in the semiconductor substrate 10 do not recombine in each of the semiconductor layers 12i, 12n, 13i, and 13p. Therefore, it is preferable that hydrogen is contained. The thickness of the insulating layer 33 is not particularly limited. The thickness of the insulating layer 33 can be, for example, about 10 nm to 1 μm.
絶縁層３３の上には、非晶質半導体層３４が形成されている。この非晶質半導体層３４により絶縁層３３の実質的に全体が覆われている。非晶質半導体層３４は、ｉ型非晶質半導体層３４ｉと、ｐ型非晶質半導体層３４ｐとを有する。半導体層３４ｉは、絶縁層３３の上に形成されている。半導体層３４ｉは、真性な非晶質半導体からなる。半導体層３４ｉは、例えば、ｉ型のアモルファスシリコンにより形成することができる。本実施形態においては、半導体層３４ｉは、最も領域１０ｂ２側に位置している半導体層１３ｉと一体に形成されている。
An amorphous semiconductor layer 34 is formed on the insulating layer 33. The amorphous semiconductor layer 34 substantially covers the entire insulating layer 33. The amorphous semiconductor layer 34 includes an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p. The semiconductor layer 34 i is formed on the insulating layer 33. The semiconductor layer 34i is made of an intrinsic amorphous semiconductor. The semiconductor layer 34i can be formed of, for example, i-type amorphous silicon. In the present embodiment, the semiconductor layer 34i is formed integrally with the semiconductor layer 13i located closest to the region 10b2.
半導体層３４ｐは、半導体層３４ｉの上に形成されている。半導体層３４ｐは、ｐ型の非晶質半導体からなる。半導体層３４ｐは、例えば、ｐ型のアモルファスシリコンにより形成することができる。本実施形態では、半導体層３４ｐは、半導体層１３ｐと一体に形成されている。
The semiconductor layer 34p is formed on the semiconductor layer 34i. The semiconductor layer 34p is made of a p-type amorphous semiconductor. The semiconductor layer 34p can be formed of, for example, p-type amorphous silicon. In the present embodiment, the semiconductor layer 34p is formed integrally with the semiconductor layer 13p.
ところで、領域１０ｂ２において、結晶性半導体基板１０の表面が露出している場合、半導体基板１０の露出部において少数キャリアの再結合が生じやすい。従って、光電変換効率が低くなりやすい。それに対して本実施形態では、領域１０ｂ２の上に、非晶質半導体層３２が形成されている。特に、本実施形態では、領域１０ｂ２の実質的に全体が非晶質半導体層３２により覆われている。このため、半導体基板１０の裏面１０ｂの露出面積を小さくすることができる。従って、領域１０ｂ２における少数キャリアの再結合を効果的に抑制することができる。その結果、高い光電変換効率を実現することができる。
Incidentally, when the surface of the crystalline semiconductor substrate 10 is exposed in the region 10b2, minority carrier recombination tends to occur in the exposed portion of the semiconductor substrate 10. Therefore, the photoelectric conversion efficiency tends to be low. On the other hand, in this embodiment, the amorphous semiconductor layer 32 is formed on the region 10b2. In particular, in the present embodiment, substantially the entire region 10 b 2 is covered with the amorphous semiconductor layer 32. For this reason, the exposed area of the back surface 10b of the semiconductor substrate 10 can be reduced. Accordingly, recombination of minority carriers in the region 10b2 can be effectively suppressed. As a result, high photoelectric conversion efficiency can be realized.
また、本実施形態では、非晶質半導体層３２が水素を含んでいるため、領域１０ｂ２における少数キャリアの再結合をより効果的に抑制することができる。その結果、より高い光電変換効率を実現することができる。
In this embodiment, since the amorphous semiconductor layer 32 contains hydrogen, recombination of minority carriers in the region 10b2 can be more effectively suppressed. As a result, higher photoelectric conversion efficiency can be realized.
また、非晶質半導体層３２のうち、半導体基板１０に接触している半導体層３２ｉは、真性な半導体からなる。このため、半導体層３２ｉには、欠陥が少ない。従って、領域１０ｂ２における少数キャリアの再結合をより効果的に抑制することができる。その結果、より高い光電変換効率を実現することができる。
Of the amorphous semiconductor layer 32, the semiconductor layer 32i in contact with the semiconductor substrate 10 is made of an intrinsic semiconductor. For this reason, the semiconductor layer 32i has few defects. Accordingly, recombination of minority carriers in the region 10b2 can be more effectively suppressed. As a result, higher photoelectric conversion efficiency can be realized.
また、本実施形態では、半導体層３２ｉの上に、半導体基板１０と同じ導電型を有する半導体層３２ｎが形成されている。このため、半導体層３２ｉ、３２ｎの積層体により、ＢＳＦ（Ｂａｃｋ Ｓｕｒｆａｃｅ Ｆｉｅｌｄ）効果が奏される。その結果、さらに高い光電変換効率を実現することができる。
Further, in the present embodiment, on the semiconductor layer 32i, the semiconductor layer 32n is formed having the same conductivity type as the semiconductor substrate 10. For this reason, a BSF (Back Surface Field) effect is produced by the stacked body of the semiconductor layers 32i and 32n. As a result, higher photoelectric conversion efficiency can be realized.
なお、電極１４，１５を裏面１０ｂの端縁まで形成し、領域１０ｂ２を設けないことも考えられる。しかしながら、例えばめっき膜からなる電極１４，１５を形成する際に端縁を越えて電極１４，１５が形成されるのを防止するための領域が裏面１０ｂに必要になるなどの理由から、領域１０ｂ２を設けることが好ましい。
It is also conceivable that the electrodes 14 and 15 are formed up to the edge of the back surface 10b and the region 10b2 is not provided. However, for example, when forming the electrodes 14 and 15 made of a plating film, a region for preventing the electrodes 14 and 15 from being formed beyond the edge is required on the back surface 10b. it is preferable to provide a.
本実施形態では、非晶質半導体層３２の上に、絶縁層３３が形成されている。このため、例えば、重金属イオン、アルカリ金属イオン、遷移金属イオンなどが非晶質半導体層３２内に侵入し、非晶質半導体層３２に欠陥が生じることを効果的に抑制することができる。その結果、高い光電変換効率を長期間にわたって維持することができる。絶縁層３３は、酸化シリコン、窒化シリコン、酸窒化シリコンにより形成されていることが好ましく、窒化シリコンにより形成されていることがより好ましい。絶縁層３３の耐候性、ガスバリア性を向上でき、各種イオンの非晶質半導体層３２内への侵入をより効果的に抑制できるためである。
In this embodiment, the insulating layer 33 is formed on the amorphous semiconductor layer 32. For this reason, for example, it is possible to effectively suppress the occurrence of defects in the amorphous semiconductor layer 32 due to intrusion of heavy metal ions, alkali metal ions, transition metal ions, and the like into the amorphous semiconductor layer 32. As a result, high photoelectric conversion efficiency can be maintained over a long period of time. Insulating layer 33, silicon oxide, preferably formed of silicon nitride, the silicon oxynitride, and more preferably formed of silicon nitride. This is because the weather resistance and gas barrier properties of the insulating layer 33 can be improved, and the penetration of various ions into the amorphous semiconductor layer 32 can be more effectively suppressed.
本実施形態では、領域１０ｂ１の電極１４，１５相互間の電極が形成されていない領域において、半導体基板１０が半導体層１２ｉにより覆われている。従って、領域１０ｂ１の電極１４，１５相互間の電極が形成されていない領域における少数キャリアの再結合も効果的に抑制することができる。従って、より高い光電変換効率を実現することができる。
In the present embodiment, the semiconductor substrate 10 is covered with the semiconductor layer 12i in a region where the electrodes 14 and 15 between the electrodes 14 and 15 in the region 10b1 are not formed. Therefore, recombination of minority carriers in a region where the electrode 14 and 15 between the electrodes 14 and 15 in the region 10b1 are not formed can be effectively suppressed. Therefore, higher photoelectric conversion efficiency can be realized.
次に、図４～図１３を主として参照しながら、本実施形態の太陽電池１の製造方法について説明する。なお、図７～図１３は、図３と同様に、端縁部を含む部分の断面図である。
Next, a method for manufacturing the solar cell 1 of the present embodiment will be described with reference mainly to FIGS. 7 to 13 are cross-sectional views of the portion including the edge portion, as in FIG.
まず、半導体基板１０（図５を参照）を用意する。次に、図４に示すように、ステップＳ１において、半導体基板１０の受光面１０ａ及び裏面１０ｂの洗浄を行う。半導体基板１０の洗浄は、例えば、ＨＦ水溶液などを用いて行うことができる。
First, a semiconductor substrate 10 (see FIG. 5) is prepared. Next, as shown in FIG. 4, in step S1, the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned. The semiconductor substrate 10 can be cleaned using, for example, an HF aqueous solution.
次に、図４及び図５に示すように、ステップＳ２において、半導体基板１０の受光面１０ａの上に半導体層１７ｉと半導体層１７ｎとを形成すると共に、裏面１０ｂの上にｉ型非晶質半導体層２１とｎ型非晶質半導体層２２とを形成する。
Next, as shown in FIGS. 4 and 5, in step S2, a semiconductor layer 17i and a semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and an i-type amorphous material is formed on the back surface 10b. A semiconductor layer 21 and an n-type amorphous semiconductor layer 22 are formed.
半導体層１７ｉ，１７ｎ，２１，２２のそれぞれの形成方法は、特に限定されない。半導体層１７ｉ，１７ｎ，２１，２２は、例えば、プラズマＣＶＤ法等のＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法やスパッタリング法等の薄膜形成法により形成することができる。
The formation method of each of the semiconductor layers 17i, 17n, 21, 22 is not particularly limited. The semiconductor layers 17i, 17n, 21, and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a thin film forming method such as a sputtering method.
次に、図４及び図６に示すように、ステップＳ３において、半導体層１７ｎの上に絶縁層１６を形成すると共に、半導体層２２の上に絶縁層２３を形成する。なお、絶縁層１６，２３の形成方法は特に限定されない。絶縁層１６，２３は、例えば、スパッタリング法やＣＶＤ法等の薄膜形成法などにより形成することができる。
Next, as shown in FIGS. 4 and 6, in step S3, the insulating layer 16 is formed on the semiconductor layer 17n, and the insulating layer 23 is formed on the semiconductor layer 22. In addition, the formation method of the insulating layers 16 and 23 is not specifically limited. The insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
次に、図４及び図７に示すように、ステップＳ４において、絶縁層２３をエッチングすることにより、絶縁層２３の一部分を除去する。具体的には、絶縁層２３のうち、後の工程で半導体基板１０にｐ型半導体層を接合させる領域の上に位置する部分を除去する。これにより、絶縁層２３ａと、図３に示す絶縁層３３とを形成する。なお、絶縁層２３のエッチングは、絶縁層２３が酸化シリコン、窒化シリコンまたは酸窒化シリコンからなる場合は、例えば、ＨＦ水溶液等の酸性のエッチング液を用いて行うことができる。
Next, as shown in FIGS. 4 and 7, in step S4, the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, of the insulating layer 23, the portion located over the area which process bonding the p-type semiconductor layer on the semiconductor substrate 10 in a later removed. Thereby, the insulating layer 23a and the insulating layer 33 shown in FIG. 3 are formed. The insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.
次に、図４及び図８に示すように、ステップＳ５において、絶縁層２３ａ、３３をマスクとして用いて、半導体層２１と半導体層２２とを、アルカリ性のエッチング液を用いてエッチングする。このエッチングにより、半導体層２１及び半導体層２２の絶縁層２３ａ、３３により覆われている部分以外の部分を除去する。これにより、裏面１０ｂのうち、上方に絶縁層２３が位置していない部分を露出させると共に、半導体層２１，２２から、半導体層１２ｉ，１２ｎ，３２ｉ，３２ｎを形成する。
Next, as shown in FIGS. 4 and 8, in step S5, the semiconductor layers 21 and 22 are etched using an alkaline etchant using the insulating layers 23a and 33 as a mask. By this etching, portions other than the portions covered by the insulating layers 23a and 33 of the semiconductor layer 21 and the semiconductor layer 22 are removed. This exposes a portion of the back surface 10b where the insulating layer 23 is not located above, and forms the semiconductor layers 12i, 12n, 32i, and 32n from the semiconductor layers 21 and 22.
ここで、上述の通り、本実施形態では、絶縁層２３ａ、３３が酸化シリコン、窒化シリコンまたは酸窒化シリコンからなる。このため、酸性のエッチング液による絶縁層２３ａ、３３のエッチング速度は高いものの、アルカリ性のエッチング液による絶縁層２３ａ、３３のエッチング速度は低い。一方、半導体層２１，２２は非晶質シリコンからなる。このため、半導体層２１，２２に関しては、酸性のエッチング液によるエッチング速度が低く、アルカリ性のエッチング液によるエッチング速度が高い。このため、ステップＳ４において用いた酸性のエッチング液によって、絶縁層２３ａ、３３はエッチングされるものの、半導体層２１，２２は、実質的にエッチングされない。一方、ステップＳ５において用いたアルカリ性のエッチング液によって半導体層２１，２２はエッチングされるものの、絶縁層２３ａ、３３は実質的にエッチングされない。従って、ステップＳ４及びステップＳ５において、絶縁層２３ａ、３３または半導体層２１，２２を選択的にエッチングすることができる。
Here, as described above, in this embodiment, the insulating layers 23a and 33 are made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layers 23a and 33 by the acidic etching solution is high, the etching rate of the insulating layers 23a and 33 by the alkaline etching solution is low. On the other hand, the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution. For this reason, although the insulating layers 23a and 33 are etched by the acidic etching solution used in step S4, the semiconductor layers 21 and 22 are not substantially etched. On the other hand, the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in step S5, but the insulating layers 23a and 33 are not substantially etched. Therefore, in steps S4 and S5, the insulating layers 23a and 33 or the semiconductor layers 21 and 22 can be selectively etched.
次に、図４及び図９に示すように、ステップＳ６において、裏面１０ｂを覆うように、ｉ型非晶質半導体層２４とｐ型非晶質半導体層２５とをこの順番で順次形成する。非晶質半導体層２４，２５の形成方法は特に限定されない。半導体層２４，２５は、例えば、スパッタリング法やＣＶＤ法などの薄膜形成法により形成することができる。
Next, as shown in FIGS. 4 and 9, in step S6, the i-type amorphous semiconductor layer 24 and the p-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b. A method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited. The semiconductor layers 24 and 25 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
次に、図４及び図１０に示すように、ステップＳ７において、半導体層２４，２５（図９を参照）の絶縁層２３ａの上に位置している部分の一部分をエッチングする。これにより、非晶質半導体層２４，２５から半導体層１３ｉ，１３ｐ，３４ｉ，３４ｐを形成する。
Next, as shown in FIGS. 4 and 10, in step S7, a part of the portion of the semiconductor layers 24 and 25 (see FIG. 9) located on the insulating layer 23a is etched. Thereby, the semiconductor layers 13i, 13p, 34i, and 34p are formed from the amorphous semiconductor layers 24 and 25.
このステップＳ７においては、非晶質半導体層２４，２５（図９を参照）に対するエッチング速度が絶縁層２３ａ、３３に対するエッチング速度よりも大きな第１のエッチング剤を使用する。このため、絶縁層２３ａ、３３と非晶質半導体層２４，２５のうち、非晶質半導体層２４，２５が選択的にエッチングされる。なお、第１のエッチング剤の具体例としては、ＮａＯＨを含むＮａＯＨ水溶液などが挙げられる。
In step S7, a first etching agent having an etching rate for the amorphous semiconductor layers 24 and 25 (see FIG. 9) larger than that for the insulating layers 23a and 33 is used. Therefore, in the insulating layer 23a, 33 and the amorphous semiconductor layer 24, the amorphous semiconductor layers 24 and 25 are selectively etched. A specific example of the first etching agent is an aqueous NaOH solution containing NaOH.
次に、図４及び図１１に示すように、ステップＳ８において絶縁層２３ａのエッチングを行う。具体的には、半導体層１３ｉ，１３ｐ，３４ｉ，３４ｐの上から、第２のエッチング剤を用いて、絶縁層２３の露出部をエッチングにより除去する。これにより、半導体層１２ｎを露出させると共に、絶縁層２３ａから絶縁層１８を形成する。
Next, as shown in FIGS. 4 and 11, the insulating layer 23a is etched in step S8. Specifically, the exposed portion of the insulating layer 23 is removed from above the semiconductor layers 13i, 13p, 34i, and 34p by etching using a second etching agent. Thus, the semiconductor layer 12n is exposed and the insulating layer 18 is formed from the insulating layer 23a.
このステップＳ８においては、絶縁層２３ａに対するエッチング速度が半導体層１３ｉ，１３ｐ，３４ｉ，３４ｐに対するエッチング速度よりも大きな第２のエッチング剤を使用する。このため、絶縁層２３ａと半導体層１３ｉ，１３ｐ，３４ｉ，３４ｐのうち、絶縁層２３ａが選択的にエッチングされる。なお、第２のエッチング剤の具体例としては、ＨＦを含むＨＦ水溶液などが挙げられる。
In this step S8, a second etching agent having an etching rate for the insulating layer 23a larger than that for the semiconductor layers 13i, 13p, 34i, and 34p is used. For this reason, the insulating layer 23a is selectively etched among the insulating layer 23a and the semiconductor layers 13i, 13p, 34i, and 34p. A specific example of the second etching agent is an HF aqueous solution containing HF.
次に、図４に示すように、ステップＳ９において、半導体層１２ｎ及び半導体層１３ｐのそれぞれの上に電極１４，１５を形成する電極形成工程を行うことにより、太陽電池１を完成させることができる。
Next, as shown in FIG. 4, the solar cell 1 can be completed by performing the electrode formation process which forms the electrodes 14 and 15 on each of the semiconductor layer 12n and the semiconductor layer 13p in step S9. .
電極１４，１５の形成方法は、電極の材質に応じて適宜選択することができる。詳細には、本実施形態では、以下のようにして電極１４，１５が形成される。
The formation method of the electrodes 14 and 15 can be suitably selected according to the material of the electrode. Specifically, in this embodiment, the electrodes 14 and 15 are formed as follows.
まず、図１２に示すように、ＴＣＯからなる導電層２６と、Ｃｕなどの金属や合金からなる導電層２７とを、プラズマＣＶＤ法等のＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法やスパッタリング法等の薄膜形成法によりこの順番で形成する。
First, as shown in FIG. 12, a conductive layer 26 made of TCO and a conductive layer 27 made of a metal or alloy such as Cu are formed into a thin film such as a CVD (Chemical Vapor Deposition) method such as a plasma CVD method or a sputtering method. by law they are formed in this order.
次に、図１３に示すように、導電層２６，２７の絶縁層１８の上に位置している部分を、例えば、フォトリソグラフィー法などにより分断する。このとき同時に、導電層２６，２７の絶縁層３３の上に位置している部分もエッチングしておく。それから、絶縁層１８の上に位置している半導体層１３ｉ，１３ｐ，３４ｉ，３４ｐも同時に分断しておく。次に、導電層２７の上にめっき膜を形成することにより、電極１４，１５を完成させることができる。
Next, as shown in FIG. 13, the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided by, for example, photolithography. At the same time, the portions of the conductive layers 26 and 27 located on the insulating layer 33 are also etched. Then, the semiconductor layers 13i, 13p, 34i, and 34p located on the insulating layer 18 are also divided at the same time. Next, the electrodes 14 and 15 can be completed by forming a plating film on the conductive layer 27.
このように、本実施形態に係る太陽電池１の製造方法では、非晶質半導体層３２をＩＮ積層体１２と共通のプロセスにより形成する。絶縁層３３を絶縁層１８と共通のプロセスにより形成する。従って、製造工程を煩雑化させることなく、少ないプロセスで容易に太陽電池１を製造することができる。
Thus, in the manufacturing method of the solar cell 1 according to this embodiment is formed by an amorphous semiconductor layer 32 and the IN laminate 12 common process. The insulating layer 33 is formed by a process common to the insulating layer 18. Therefore, the solar cell 1 can be easily manufactured with a small number of processes without complicating the manufacturing process.
ところで、例えば、絶縁層３３の上に非晶質半導体層が形成されておらず、絶縁層３３が露出していても、非晶質半導体層３２への各種イオンの侵入を抑制することができる。しかしながら、絶縁層３３が露出していると、例えば、絶縁層２３ａをエッチングして絶縁層１８を形成する工程や、導電層２６，２７の分断工程などにおいて、絶縁層３３が損傷したり、除去されてしまったりする場合がある。
By the way, for example, even if the amorphous semiconductor layer is not formed on the insulating layer 33 and the insulating layer 33 is exposed, intrusion of various ions into the amorphous semiconductor layer 32 can be suppressed. . However, if the insulating layer 33 is exposed, the insulating layer 33 is damaged or removed, for example, in the step of forming the insulating layer 18 by etching the insulating layer 23a or the step of dividing the conductive layers 26 and 27. It may be done.
それに対して本実施形態では、絶縁層３３は、非晶質半導体層３４により覆われている。このため、絶縁層２３ａのエッチング工程や導電層２６，２７の分断工程などにおいて絶縁層３３が損傷したり除去されたりすることを効果的に抑制することができる。
In contrast, in this embodiment, the insulating layer 33 is covered with the amorphous semiconductor layer 34. For this reason, it can suppress effectively that the insulating layer 33 is damaged or removed in the etching process of the insulating layer 23a, the dividing process of the conductive layers 26 and 27, and the like.
また、本実施形態では、非晶質半導体層３４を、領域１０ｂ２に隣接するＩＰ積層体１３と一体に形成する。従って、太陽電池１の製造プロセスを簡略化することができる。
In this embodiment, the amorphous semiconductor layer 34 is formed integrally with the IP stacked body 13 adjacent to the region 10b2. Therefore, the manufacturing process of the solar cell 1 can be simplified.
（第１の実施形態の変形例（第１の変形例））
図１４は、第１の実施形態の変形例（第１の変形例）に係る太陽電池の端縁部の略図的断面図である。 (Modification of First Embodiment (First Modification))
FIG. 14 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (first modification) of the first embodiment.
図１４は、第１の実施形態の変形例（第１の変形例）に係る太陽電池の端縁部の略図的断面図である。 (Modification of First Embodiment (First Modification))
FIG. 14 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (first modification) of the first embodiment.
上記第１の実施形態では、領域１０ｂ２において、半導体基板１０の裏面１０ｂの上には、ｉ型非晶質半導体層３２ｉが形成されており、ｉ型非晶質半導体層３２ｉの上に、ｎ型非晶質半導体層３２ｎが形成されている例について説明した。
In the first embodiment, in the region 10b2, the i-type amorphous semiconductor layer 32i is formed on the back surface 10b of the semiconductor substrate 10, and the n-type amorphous semiconductor layer 32i has n. The example in which the type amorphous semiconductor layer 32n is formed has been described.
但し、本発明は、この構成に限定されない。例えば、領域１０ｂ２において、ｉ型非晶質半導体層を介在させずに、半導体基板１０の裏面１０ｂの直上にｎ型非晶質半導体層を形成してもよい。
However, the present invention is not limited to this configuration. For example, in the region 10b2, an n-type amorphous semiconductor layer may be formed immediately above the back surface 10b of the semiconductor substrate 10 without interposing an i-type amorphous semiconductor layer.
また、図１４に示すように、裏面１０ｂの上に、ｉ型非晶質半導体層３４ｉと、ｐ型非晶質半導体層３４ｐとの積層体からなる非晶質半導体層３４を設けてもよい。また、裏面１０ｂの直上にｐ型非晶質半導体層を形成してもよい。
Further, as shown in FIG. 14, an amorphous semiconductor layer 34 formed of a stacked body of an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p may be provided on the back surface 10b. . Further, a p-type amorphous semiconductor layer may be formed immediately above the back surface 10b.
これらの場合であっても、領域１０ｂ２の上に非晶質半導体層が形成されているため、上記第１の実施形態と同様に、高い光電変換効率を実現することができる。
Even in these cases, since the amorphous semiconductor layer is formed on the region 10b2, high photoelectric conversion efficiency can be realized as in the first embodiment.
なお、図１４に示す第１の変形例に係る太陽電池では、非晶質半導体層３４の上には、絶縁層は形成されていない。
In the solar cell according to a first modification shown in FIG. 14, on the amorphous semiconductor layer 34, the insulating layer is not formed.
非晶質半導体層３４は、電極１４，１５のいずれにも電気的に接続されていない。
The amorphous semiconductor layer 34 is not electrically connected to any of the electrodes 14 and 15.
また、図２９～３０に示すような第２の変形例および第３の変形例でも構わない。具体的には、図２９～３０を参照しながら説明する。
Also, a second modification and a third modification as shown in FIGS. 29 to 30 may be used. Specifically, this will be described with reference to FIGS.
図２９では、第１の実施形態の略図的断面図（図３）に対応する第２の変形例の略図的断面図である。
29 is a schematic cross-sectional view of a second modification corresponding to the schematic cross-sectional view (FIG. 3) of the first embodiment.
第２の変形例において、第１の実施形態との相違点は、半導体基板１０の裏面側の領域１０ｂ２の上にｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとをこの順で積層させたIP積層体３４を備えている点である。また、第２の変形例では、IP積層体３４が半導体基板１０の上に積層されているため、第１の実施形態（図３を参照）の領域１０ｂ１のIP積層体３４の積層位置が領域１０ｂ２のIP積層体３４の積層位置よりも半導体基板１０側に形成されているのとは逆の構成である。すなわち、第２の変形例では、領域１０ｂ２のIP積層体３４の積層位置が領域１０ｂ１のIP積層体３４の積層位置よりも半導体基板１０側に形成された構成である。
The second modification is different from the first embodiment in that the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are formed on the back surface region 10b2 of the semiconductor substrate 10. It is a point provided with the IP laminated body 34 laminated | stacked in order. In the second modification, since the IP stacked body 34 is stacked on the semiconductor substrate 10, the stack position of the IP stacked body 34 in the region 10b1 of the first embodiment (see FIG. 3) is the region. The configuration is opposite to that formed on the semiconductor substrate 10 side of the stacking position of the 10b2 IP stack 34. That is, in the second modification, the stack position of the IP stacked body 34 in the region 10b2 is formed closer to the semiconductor substrate 10 than the stack position of the IP stacked body 34 in the region 10b1.
なお、第２の変形例を製造する際は、ｎ型半導体基板１０の上の全面に導電層２６、２７を形成した後に、領域１０ｂ２の上の導電層２６、２７を除去する。そして、残った導電層２６、２７の上にめっき膜からなる電極１４，１５を形成する。そうすると、領域１０ｂ１にはｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとをこの順で積層させたIP積層体３４を備えた図２９の太陽電池１が得られる。なお、ｉ型非晶質半導体層３２ｉとｎ型非晶質半導体層３２ｎとをこの順で積層させたIＮ積層体３２をエッチングし、次に絶縁層１８，３３をエッチングし、その後にｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとをこの順で積層させたIP積層体３４をエッチングすることにより、図２９の太陽電池１の積層構造が得られる。
When manufacturing the second modification, after forming the conductive layers 26 and 27 on the entire surface of the n-type semiconductor substrate 10, the conductive layers 26 and 27 on the region 10b2 are removed. Then, electrodes 14 and 15 made of a plating film are formed on the remaining conductive layers 26 and 27. Then, the solar cell 1 of FIG. 29 provided with the IP stacked body 34 in which the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order is obtained in the region 10b1. Note that the IN stacked body 32 in which the i-type amorphous semiconductor layer 32i and the n-type amorphous semiconductor layer 32n are stacked in this order is etched, then the insulating layers 18 and 33 are etched, and then the i-type amorphous semiconductor layer 32n is etched. The stacked structure of the solar cell 1 of FIG. 29 is obtained by etching the IP stacked body 34 in which the amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order.
図３０では、第１の実施形態の略図的断面図（図３）に対応する第３の変形例の略図的断面図である。
In Figure 30 a schematic cross-sectional view of a third modified example corresponding to the schematic cross-sectional view of the first embodiment (FIG. 3).
第３の変形例において、第１の実施形態との相違点は、半導体基板１０の裏面側の領域１０ｂ２の上にｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとをこの順で積層させたIP積層体３４および絶縁層３３を備えている点である。
The third modification is different from the first embodiment in that an i-type amorphous semiconductor layer 34i and a p-type amorphous semiconductor layer 34p are formed on a region 10b2 on the back surface side of the semiconductor substrate 10. It is a point provided with the IP laminated body 34 and the insulating layer 33 laminated | stacked in order.
なお、第３の変形例を製造する際は、ｎ型半導体基板１０の上の全面に、ｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとを形成した後に、領域１０ｂ２の上のｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとを除去する。そして、残ったｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐの上にのみに導電層２６、２７を形成し、その導電層２６、２７の上にめっき膜からなる電極１４，１５を形成する。そうすると、領域１０ｂ２にはｉ型非晶質半導体層３４ｉとｐ型非晶質半導体層３４ｐとを順で積層させたIP積層体３４および絶縁層３３を備えた図３０の太陽電池１が得られる。
When manufacturing the third modification, after forming the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p on the entire surface of the n-type semiconductor substrate 10, the region 10b2 The upper i-type amorphous semiconductor layer 34i and p-type amorphous semiconductor layer 34p are removed. Then, conductive layers 26 and 27 are formed only on the remaining i-type amorphous semiconductor layer 34 i and p-type amorphous semiconductor layer 34 p, and an electrode 14 made of a plating film is formed on the conductive layers 26 and 27. , to form a 15. As a result, the solar cell 1 of FIG. 30 including the IP stacked body 34 and the insulating layer 33 in which the i-type amorphous semiconductor layer 34i and the p-type amorphous semiconductor layer 34p are stacked in this order is obtained in the region 10b2. .
以下、本発明の好ましい形態の他の例について説明する。なお、以下の説明において、上記第１の実施形態と実質的に共通の機能を有する部材を共通の符号で参照し、説明を省略する。
Hereinafter, other examples of preferred embodiments of the present invention will be described. In the following description, members having substantially the same functions as those of the first embodiment are referred to by the same reference numerals, and description thereof is omitted.
（第２の実施形態）
図１５は、第２の実施形態における太陽電池の略図的平面図である。図１６は、第２の実施形態における太陽電池の中央部の略図的断面図である。図１７は、第２の実施形態における太陽電池の端縁部の略図的断面図である。 (Second Embodiment)
FIG. 15 is a schematic plan view of a solar cell in the second embodiment. FIG. 16 is a schematic cross-sectional view of the central portion of the solar cell in the second embodiment. FIG. 17 is a schematic cross-sectional view of an edge portion of the solar cell in the second embodiment.
図１５は、第２の実施形態における太陽電池の略図的平面図である。図１６は、第２の実施形態における太陽電池の中央部の略図的断面図である。図１７は、第２の実施形態における太陽電池の端縁部の略図的断面図である。 (Second Embodiment)
FIG. 15 is a schematic plan view of a solar cell in the second embodiment. FIG. 16 is a schematic cross-sectional view of the central portion of the solar cell in the second embodiment. FIG. 17 is a schematic cross-sectional view of an edge portion of the solar cell in the second embodiment.
上記第１の実施形態に係る太陽電池１では、ｎ型非晶質半導体層１２ｎのｘ方向における両端部の上に絶縁層１８が形成されており、絶縁層１８の上にｐ型非晶質半導体層１３ｐの一部が位置している例について説明した。それに対して本実施形態の太陽電池２では、ｐ型非晶質半導体層１３ｐの上に絶縁層１８が形成されており、絶縁層１８の上にｎ型非晶質半導体層１２ｎの一部が位置している。すなわち、太陽電池２と太陽電池１とでは、ｐ型非晶質半導体層１３ｐを含む半導体層１３と、ｎ型非晶質半導体層１２ｎを含む半導体層１２との位置関係が逆になっている。それに伴い、電極１４と電極１５との位置関係も太陽電池２と太陽電池１とで逆となっている。それら以外の点については、太陽電池２は、第１の実施形態に係る太陽電池１と実質的に同様の構成を有する。
In the solar cell 1 according to the first embodiment, the insulating layer 18 is formed on both ends in the x direction of the n-type amorphous semiconductor layer 12n, and the p-type amorphous is formed on the insulating layer 18. An example in which a part of the semiconductor layer 13p is located has been described. On the other hand, in the solar cell 2 of the present embodiment, the insulating layer 18 is formed on the p-type amorphous semiconductor layer 13p, and a part of the n-type amorphous semiconductor layer 12n is formed on the insulating layer 18. positioned. That is, in the solar cell 2 and the solar cell 1, the positional relationship between the semiconductor layer 13 including the p-type amorphous semiconductor layer 13p and the semiconductor layer 12 including the n-type amorphous semiconductor layer 12n is reversed. . Accordingly, the positional relationship between the electrode 14 and the electrode 15 is reversed between the solar cell 2 and the solar cell 1. Regarding other points, the solar cell 2 has substantially the same configuration as the solar cell 1 according to the first embodiment.
ところで、本実施形態のように半導体基板１０がｎ型である場合は、少数キャリアは、ホールとなる。このため、太陽電池１の光電変換効率を高める観点からは少数キャリアであるホールの再結合による消失を抑制することが重要となる。
By the way, when the semiconductor substrate 10 is n-type as in this embodiment, the minority carriers are holes. Accordingly, to suppress loss due to recombination of holes which are minority carriers is important from the viewpoint of enhancing the photoelectric conversion efficiency of the solar cell 1.
ここで、ｐ型非晶質半導体層１３ｐの下方で生成した少数キャリア（ホール）は、電極１５により集電されるまでの移動距離が短い。このため、ｐ型非晶質半導体層１３ｐの下方で生成した少数キャリアは、電極１５に収集されるまでに再結合により消失し難い。一方、ｎ型非晶質半導体層１２ｎの下方で生成した少数キャリアは、電極１５により集電されるまでに移動しなければならない距離が長い。このため、ｎ型非晶質半導体層１２ｎの下方で生成した少数キャリアは、電極１５に収集されるまでに再結合により消失しやすい。従って、少数キャリアの再結合を抑制する観点からは、ｎ型非晶質半導体層１２ｎ及びｐ型非晶質半導体層１３ｐの幅を小さくすると共に、ｎ型非晶質半導体層１２ｎの幅をｐ型非晶質半導体層１３ｐに対して相対的に小さくすることが好ましい。そうすることにより、少数キャリアが電極１５により収集されるまでに移動しなければならない距離を短くすることができる。
Here, minority carriers (holes) generated below the p-type amorphous semiconductor layer 13p have a short moving distance until they are collected by the electrode 15. For this reason, minority carriers generated below the p-type amorphous semiconductor layer 13p are unlikely to disappear due to recombination before being collected by the electrode 15. On the other hand, the minority carriers generated below the n-type amorphous semiconductor layer 12n have a long distance that must be moved before being collected by the electrode 15. For this reason, minority carriers generated below the n-type amorphous semiconductor layer 12 n are likely to disappear due to recombination before being collected by the electrode 15. Therefore, from the viewpoint of suppressing recombination of minority carriers, the widths of the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p are reduced and the width of the n-type amorphous semiconductor layer 12n is set to p. It is preferable to make it relatively small with respect to the type amorphous semiconductor layer 13p. By doing so, the distance that minority carriers must travel before being collected by the electrode 15 can be reduced.
しかしながら、絶縁層の下に位置している半導体層には、絶縁層を設けるための領域と、電極と半導体層とを接触させるための領域との両方を設ける必要がある。このため、絶縁層の下に位置している半導体層は、それほど幅を小さくすることはできない。よって、第１の実施形態に係る太陽電池１のように、絶縁層１８の下にｎ型非晶質半導体層１２ｎが位置している場合は、ｎ型非晶質半導体層１２ｎの幅を十分に小さくすることができない。
However, it is necessary to provide both a region for providing the insulating layer and a region for contacting the electrode and the semiconductor layer in the semiconductor layer located under the insulating layer. For this reason, the width of the semiconductor layer located under the insulating layer cannot be reduced so much. Therefore, when the n-type amorphous semiconductor layer 12n is located under the insulating layer 18 as in the solar cell 1 according to the first embodiment, the width of the n-type amorphous semiconductor layer 12n is sufficiently large. can not be reduced to.
それに対して本実施形態に係る太陽電池２では、絶縁層１８の下にｐ型非晶質半導体層１３ｐが位置しており、ｎ型非晶質半導体層１２ｎの上には、絶縁層が形成されていない。このため、ｎ型非晶質半導体層１２ｎの幅を、ｐ型非晶質半導体層１３ｐに対して相対的に小さくすることが容易になる。従って、ｎ型非晶質半導体層１２ｎの下方で生成した正孔が電極１５により収集されるまでに移動しなければならない距離を短くすることができる。その結果、少数キャリアの再結合を抑制することができる。よって、太陽電池２の光電変換効率を改善することができる。
On the other hand, in the solar cell 2 according to this embodiment, the p-type amorphous semiconductor layer 13p is located under the insulating layer 18, and the insulating layer is formed on the n-type amorphous semiconductor layer 12n. It has not been. For this reason, it becomes easy to make the width of the n-type amorphous semiconductor layer 12n relatively smaller than the p-type amorphous semiconductor layer 13p. Accordingly, it is possible to reduce the distance that must be traveled before the holes generated below the n-type amorphous semiconductor layer 12n are collected by the electrode 15. As a result, recombination of minority carriers can be suppressed. Therefore, the photoelectric conversion efficiency of the solar cell 2 can be improved.
光電変換効率をさらに改善する観点からは、ｐ型非晶質半導体層１３ｐのｘ方向に沿った幅がｎ型非晶質半導体層１２ｎのｘ方向に沿った幅の１．１倍以上であることが好ましく、１．５倍以上であることがより好ましい。
From the viewpoint of further improving the photoelectric conversion efficiency, the width of the p-type amorphous semiconductor layer 13p along the x direction is 1.1 times or more than the width of the n-type amorphous semiconductor layer 12n along the x direction. Preferably, it is 1.5 times or more.
なお、本実施形態では、半導体基板１０がｎ型であるため、絶縁層１８の下に位置する半導体層をｐ型にすることが好ましいが、半導体基板がｐ型である場合は、絶縁層の下に位置する半導体層をｎ型にすることが好ましい。すなわち、半導体基板１０で発生したキャリアが再結合しないように、半導体層の下に位置する半導体層は、パッシベーション性を向上させるために半導体基板とは異なる導電型を有していることが好ましい。
In this embodiment, since the semiconductor substrate 10 is n-type, it is preferable to make the semiconductor layer located under the insulating layer 18 p-type. However, when the semiconductor substrate is p-type, the insulating layer The underlying semiconductor layer is preferably n-type. That is, it is preferable that the semiconductor layer located under the semiconductor layer has a conductivity type different from that of the semiconductor substrate so as to improve passivation properties so that carriers generated in the semiconductor substrate 10 do not recombine.
（太陽電池２の製造方法）
図１８は、第２の実施形態における太陽電池の製造工程を表すフローチャートである。図１９～図２７は、第２の実施形態における太陽電池の製造工程を説明するための略図的断面図である。次に、図１８～図２７を参照しながら太陽電池２の製造方法の一例について説明する。なお、図１９～図２７は、図１６と同様に、端縁部を含む部分の断面図である。 (Manufacturing method of solar cell 2)
FIG. 18 is a flowchart showing the manufacturing process of the solar cell in the second embodiment. 19 to 27 are schematic cross-sectional views for explaining a manufacturing process of the solar cell in the second embodiment. Next, an example of a method for manufacturing thesolar cell 2 will be described with reference to FIGS. 19 to 27 are cross-sectional views of the portion including the edge portion, similarly to FIG.
図１８は、第２の実施形態における太陽電池の製造工程を表すフローチャートである。図１９～図２７は、第２の実施形態における太陽電池の製造工程を説明するための略図的断面図である。次に、図１８～図２７を参照しながら太陽電池２の製造方法の一例について説明する。なお、図１９～図２７は、図１６と同様に、端縁部を含む部分の断面図である。 (Manufacturing method of solar cell 2)
FIG. 18 is a flowchart showing the manufacturing process of the solar cell in the second embodiment. 19 to 27 are schematic cross-sectional views for explaining a manufacturing process of the solar cell in the second embodiment. Next, an example of a method for manufacturing the
なお、以下の説明において、上記第１の実施形態と実質的に同様の工程は、第１の実施形態において例示した具体的方法により行うことができるため、第１の実施形態の記載を援用し、説明を省略する。
In the following description, since substantially the same steps as those in the first embodiment can be performed by the specific method exemplified in the first embodiment, the description of the first embodiment is incorporated. , the description thereof is omitted.
まず、半導体基板１０を用意する。次に、図１８に示すように、ステップＳ１１（図１９を参照）において、第１の実施形態のステップＳ１と同様に、半導体基板１０の受光面１０ａ及び裏面１０ｂの洗浄を行う。
First, a semiconductor substrate 10. Next, as shown in FIG. 18, in step S11 (see FIG. 19), the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned in the same manner as in step S1 of the first embodiment.
次に、ステップＳ１２（図１９を参照）において、半導体基板１０の受光面１０ａの上に半導体層１７ｉと半導体層１７ｎとを形成すると共に、裏面１０ｂの上にｉ型非晶質半導体層２１とｐ型非晶質半導体層４０とを形成する。
Next, in step S12 (see FIG. 19), the semiconductor layer 17i and the semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and the i-type amorphous semiconductor layer 21 is formed on the back surface 10b. A p-type amorphous semiconductor layer 40 is formed.
次に、ステップＳ１３（図２０を参照）において、半導体層１７ｎの上に絶縁層１６を形成すると共に、半導体層４０の上に絶縁層２３を形成する。
Next, in step S13 (see FIG. 20), the insulating layer 16 is formed on the semiconductor layer 17n, and the insulating layer 23 is formed on the semiconductor layer 40.
次に、ステップＳ１４（図２１を参照）において、絶縁層２３をエッチングすることにより、絶縁層２３の一部分を除去する。具体的には、絶縁層２３のうち、後の工程で半導体基板１０にｎ型半導体層を接合させる領域の上に位置する部分を除去する。これにより、絶縁層２３ａと、絶縁層３３とを形成する。
Next, in step S14 (see FIG. 21), the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, of the insulating layer 23, the portion located over the area which process bonding the n-type semiconductor layer on the semiconductor substrate 10 in a later removed. Thereby, the insulating layer 23a and the insulating layer 33 are formed.
次に、ステップＳ１５（図２２を参照）において、絶縁層２３ａ、３３をマスクとして用いて、半導体層２１（図２１を参照）と半導体層４０（図２１を参照）とを、アルカリ性のエッチング液を用いてエッチングすることにより、半導体層２１及び半導体層４０の絶縁層２３ａ、３３により覆われている部分以外の部分を除去する。これにより、裏面１０ｂのうち、上方に絶縁層２３が位置していない部分を露出させると共に、半導体層２１，４０から、半導体層１３ｉ，１３ｐ，３４ｉ，３４ｐを形成する。
Next, in step S15 (see FIG. 22), using the insulating layers 23a and 33 as a mask, the semiconductor layer 21 (see FIG. 21) and the semiconductor layer 40 (see FIG. 21) are mixed with an alkaline etching solution. Etching is used to remove portions of the semiconductor layer 21 and the semiconductor layer 40 other than the portions covered with the insulating layers 23a and 33. As a result, the portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the semiconductor layers 13i, 13p, 34i, and 34p are formed from the semiconductor layers 21 and 40.
次に、ステップＳ１６（図２３を参照）において、裏面１０ｂの露出部を覆うように、ｉ型非晶質半導体層２４とｎ型非晶質半導体層４１とをこの順番で順次形成する。
Next, in step S16 (see FIG. 23), the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 41 are sequentially formed in this order so as to cover the exposed portion of the back surface 10b.
次に、ステップＳ１７（図２４を参照）において、半導体層２４，４１の絶縁層２３ａの上に位置している部分の一部分をエッチングする。これにより、非晶質半導体層２４，４１から半導体層１２ｉ，１２ｎ，３２ｉ，３２ｎを形成する。
Next, in step S17 (see FIG. 24), etching the portion of the portion located on the insulating layer 23a of the semiconductor layer 24, 41. Thereby, the semiconductor layers 12i, 12n, 32i, and 32n are formed from the amorphous semiconductor layers 24 and 41.
次に、ステップＳ１８（図２５を参照）において絶縁層２３ａのエッチングを行う。具体的には、半導体層１２ｉ，１２ｎ，３２ｉ，３２ｎの上から、第２のエッチング剤を用いて、絶縁層２３の露出部をエッチングにより除去する。これにより、半導体層１３ｐを露出させると共に、絶縁層２３ａから絶縁層１８を形成する。
Next, in step S18 (see FIG. 25), the insulating layer 23a is etched. Specifically, the exposed portion of the insulating layer 23 is removed by etching from above the semiconductor layers 12i, 12n, 32i, and 32n using a second etching agent. Thereby, the semiconductor layer 13p is exposed and the insulating layer 18 is formed from the insulating layer 23a.
次に、ステップＳ１９（図２６～２７を参照）において、半導体層１２ｎ及び半導体層１３ｐのそれぞれの上に電極１４，１５を形成する電極形成工程を行うことにより、太陽電池２を完成させることができる。
Next, in step S19 (see FIGS. 26 to 27), the solar cell 2 can be completed by performing an electrode formation process for forming the electrodes 14 and 15 on the semiconductor layer 12n and the semiconductor layer 13p, respectively. it can.
具体的には、本実施形態では、まず、ＴＣＯからなる導電層２６と、Ｃｕなどの金属や合金からなる導電層２７とを、プラズマＣＶＤ法等のＣＶＤ（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法やスパッタリング法等の薄膜形成法によりこの順番で形成する。
Specifically, in the present embodiment, first, a conductive layer 26 made of TCO and a conductive layer 27 made of a metal or alloy such as Cu, a CVD (Chemical Vapor Deposition) method such as a plasma CVD method, a sputtering method, or the like. These are formed in this order by the thin film forming method.
次に、導電層２６，２７の絶縁層１８の上に位置している部分を、例えば、フォトリソグラフィー法などにより分断する。このとき同時に、導電層２６，２７の絶縁層３３の上に位置している部分もエッチングしておく。それから、絶縁層１８の上に位置している半導体層１２ｉ，１２ｎ，３２ｉ，３２ｎも同時に分断しておく。次に、導電層２７の上にめっき膜を形成することにより、電極１４，１５を完成させることができる。
Next, the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided by, for example, photolithography. At the same time, the portions of the conductive layers 26 and 27 located on the insulating layer 33 are also etched. Then, the semiconductor layers 12i, 12n, 32i, and 32n located on the insulating layer 18 are also divided at the same time. Next, the electrodes 14 and 15 can be completed by forming a plating film on the conductive layer 27.
本実施形態においても、第１の実施形態と同様に、製造工程を煩雑化させることなく、少ないプロセスで容易に太陽電池２を製造することができる。また、絶縁層３３が非晶質半導体層３２により覆われているため、太陽電池２の製造工程において絶縁層３３が損傷したり除去されたりすることを効果的に抑制することができる。
Also in the present embodiment, as in the first embodiment, the solar cell 2 can be easily manufactured by a small number of processes without complicating the manufacturing process. Moreover, since the insulating layer 33 is covered with the amorphous semiconductor layer 32, it is possible to effectively suppress the insulating layer 33 from being damaged or removed in the manufacturing process of the solar cell 2.
また、本実施形態では、非晶質半導体層３２を、領域１０ｂ２に隣接するＩＮ積層体１２と一体に形成する。従って、太陽電池２の製造プロセスを簡略化することができる。
In this embodiment, the amorphous semiconductor layer 32 is formed integrally with the IN stacked body 12 adjacent to the region 10b2. Therefore, the manufacturing process of the solar cell 2 can be simplified.
また、本実施形態では、ｐ型非晶質半導体層１３ｐをｎ型非晶質半導体層１２ｎよりも先に形成する。具体的には、ステップＳ１において基板１０の洗浄を行った直後に、半導体層１３ｉ、１３ｐを裏面１０ｂの上に形成する。このため、半導体層１３ｉ、１３ｐを形成する直前の裏面１０ｂの清浄度をより高めることができる。よって、より高品位なｐｎ接合を形成することができる。従って、より高い光電変換効率を得ることができる。
In this embodiment, the p-type amorphous semiconductor layer 13p is formed before the n-type amorphous semiconductor layer 12n. Specifically, the semiconductor layers 13i and 13p are formed on the back surface 10b immediately after the substrate 10 is cleaned in step S1. For this reason, the cleanliness of the back surface 10b immediately before forming the semiconductor layers 13i and 13p can be further increased. Therefore, a higher quality pn junction can be formed. Therefore, higher photoelectric conversion efficiency can be obtained.
（第２の実施形態の変形例（第２の変形例）
図２８は、第２の実施形態の変形例（第２の変形例）に係る太陽電池の端縁部の略図的断面図である。 (Modification of the second embodiment (second modification)
FIG. 28 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (second modification) of the second embodiment.
図２８は、第２の実施形態の変形例（第２の変形例）に係る太陽電池の端縁部の略図的断面図である。 (Modification of the second embodiment (second modification)
FIG. 28 is a schematic cross-sectional view of an edge portion of a solar cell according to a modification (second modification) of the second embodiment.
上記第２の実施形態では、領域１０ｂ２において、半導体基板１０の裏面１０ｂの上には、ｉ型非晶質半導体層３４ｉが形成されており、ｉ型非晶質半導体層３４ｉの上に、ｐ型非晶質半導体層３４ｐが形成されている例について説明した。
In the second embodiment, in the region 10b2, the i-type amorphous semiconductor layer 34i is formed on the back surface 10b of the semiconductor substrate 10, and the p-type amorphous semiconductor layer 34i has a p The example in which the type amorphous semiconductor layer 34p is formed has been described.
但し、本発明は、この構成に限定されない。例えば、領域１０ｂ２において、ｉ型非晶質半導体層を介さずに、半導体基板１０の裏面１０ｂの直上にｐ型非晶質半導体層を形成してもよい。
However, the present invention is not limited to this configuration. For example, in the region 10b2, a p-type amorphous semiconductor layer may be formed immediately above the back surface 10b of the semiconductor substrate 10 without using an i-type amorphous semiconductor layer.
また、図２８に示すように、裏面１０ｂの上に、ｉ型非晶質半導体層３２ｉと、ｎ型非晶質半導体層３２ｎとの積層体からなる非晶質半導体層３２を設けてもよい。また、裏面１０ｂの直上にｎ型非晶質半導体層を形成してもよい。
As shown in FIG. 28, an amorphous semiconductor layer 32 made of a stacked body of an i-type amorphous semiconductor layer 32i and an n-type amorphous semiconductor layer 32n may be provided on the back surface 10b. . Further, an n-type amorphous semiconductor layer may be formed directly on the back surface 10b.
これらの場合であっても、領域１０ｂ２の上に非晶質半導体層が形成されているため、上記第２の実施形態と同様に、高い光電変換効率を実現することができる。
Even in these cases, since the amorphous semiconductor layer is formed on the region 10b2, high photoelectric conversion efficiency can be realized as in the second embodiment.
なお、図２８に示す第１の変形例に係る太陽電池では、非晶質半導体層３２の上には、絶縁層は形成されていない。
In the solar cell according to the first modification shown in FIG. 28, no insulating layer is formed on the amorphous semiconductor layer 32.
非晶質半導体層３２は、電極１４，１５のいずれにも電気的に接続されていない。
The amorphous semiconductor layer 32 is not electrically connected to any of the electrodes 14 and 15.
（変形例）
第１及び第２の実施形態では、ｎ型非晶質半導体層１２ｎと裏面１０ｂとの間にｉ型非晶質半導体層１２ｉが設けられている例について説明した。但し、本発明は、この構成に限定されない。例えば、ｉ型非晶質半導体層を設けず、裏面１０ｂの直上にｎ型非晶質半導体層を設けてもよい。 (Modification)
In the first and second embodiments, the example in which the i-typeamorphous semiconductor layer 12i is provided between the n-type amorphous semiconductor layer 12n and the back surface 10b has been described. However, the present invention is not limited to this configuration. For example, an n-type amorphous semiconductor layer may be provided immediately above the back surface 10b without providing an i-type amorphous semiconductor layer.
第１及び第２の実施形態では、ｎ型非晶質半導体層１２ｎと裏面１０ｂとの間にｉ型非晶質半導体層１２ｉが設けられている例について説明した。但し、本発明は、この構成に限定されない。例えば、ｉ型非晶質半導体層を設けず、裏面１０ｂの直上にｎ型非晶質半導体層を設けてもよい。 (Modification)
In the first and second embodiments, the example in which the i-type
また、第１及び第２の実施形態では、ｐ型非晶質半導体層１３ｐと裏面１０ｂとの間にｉ型非晶質半導体層１３ｉが設けられている例について説明した。但し、本発明は、この構成に限定されない。例えば、ｉ型非晶質半導体層を設けず、裏面１０ｂの直上にｐ型非晶質半導体層を設けてもよい。
In the first and second embodiments, the example in which the i-type amorphous semiconductor layer 13i is provided between the p-type amorphous semiconductor layer 13p and the back surface 10b has been described. However, the present invention is not limited to this configuration. For example, a p-type amorphous semiconductor layer may be provided immediately above the back surface 10b without providing an i-type amorphous semiconductor layer.
１，２…太陽電池
１０…結晶性半導体基板
１０ａ…受光面
１０ｂ…裏面
１１…光
１２…ＩＮ積層体
１２ｉ…ｉ型非晶質半導体層
１２ｎ…ｎ型非晶質半導体層
１３…ＩＰ積層体
１３ｉ…ｉ型非晶質半導体層
１３ｐ…ｐ型非晶質半導体層
１４…電極
１５…電極
１６，１８，２３，２３ａ，３３…絶縁層
１７ｉ…ｉ型非晶質半導体層
１７ｎ…ｎ型非晶質半導体層
２１…ｉ型非晶質半導体層
２２…ｎ型非晶質半導体層
２４…ｉ型非晶質半導体層
２５…ｐ型非晶質半導体層
２６，２７…導電層
３２…非晶質半導体層
３２ｉ…ｉ型非晶質半導体層
３２ｎ…ｎ型非晶質半導体層
３４…非晶質半導体層
３４ｉ…ｉ型非晶質半導体層
３４ｐ…ｐ型非晶質半導体層 DESCRIPTION OFSYMBOLS 1, 2 ... Solar cell 10 ... Crystalline semiconductor substrate 10a ... Light-receiving surface 10b ... Back surface 11 ... Light 12 ... IN laminated body 12i ... i-type amorphous semiconductor layer 12n ... n-type amorphous semiconductor layer 13 ... IP laminated body 13i ... i-type amorphous semiconductor layer 13p ... p-type amorphous semiconductor layer 14 ... electrode 15 ... electrodes 16, 18, 23, 23a, 33 ... insulating layer 17i ... i-type amorphous semiconductor layer 17n ... n-type non- Crystalline semiconductor layer 21 ... i-type amorphous semiconductor layer 22 ... n-type amorphous semiconductor layer 24 ... i-type amorphous semiconductor layer 25 ... p-type amorphous semiconductor layers 26, 27 ... conductive layer 32 ... amorphous Semiconductor layer 32i ... i-type amorphous semiconductor layer 32n ... n-type amorphous semiconductor layer 34 ... amorphous semiconductor layer 34i ... i-type amorphous semiconductor layer 34p ... p-type amorphous semiconductor layer
１０…結晶性半導体基板
１０ａ…受光面
１０ｂ…裏面
１１…光
１２…ＩＮ積層体
１２ｉ…ｉ型非晶質半導体層
１２ｎ…ｎ型非晶質半導体層
１３…ＩＰ積層体
１３ｉ…ｉ型非晶質半導体層
１３ｐ…ｐ型非晶質半導体層
１４…電極
１５…電極
１６，１８，２３，２３ａ，３３…絶縁層
１７ｉ…ｉ型非晶質半導体層
１７ｎ…ｎ型非晶質半導体層
２１…ｉ型非晶質半導体層
２２…ｎ型非晶質半導体層
２４…ｉ型非晶質半導体層
２５…ｐ型非晶質半導体層
２６，２７…導電層
３２…非晶質半導体層
３２ｉ…ｉ型非晶質半導体層
３２ｎ…ｎ型非晶質半導体層
３４…非晶質半導体層
３４ｉ…ｉ型非晶質半導体層
３４ｐ…ｐ型非晶質半導体層 DESCRIPTION OF
Claims (18)
- 第１及び第２の主面を有し、第１の導電型を有する結晶性半導体基板と、
前記第１の主面の上に形成されており、前記第１の導電型を有する第１の半導体層と、
前記第１の半導体層の上に形成されている第１の電極と、
前記第１の主面の上に形成されており、前記第１の導電型と逆の第２の導電型を有する第２の半導体層と、
前記第２の半導体層の上に形成されている第２の電極と、
を備える太陽電池であって、
前記第１及び第２の電極は、前記第１の主面の端縁部を除く領域に形成されており、
前記第１及び第２の電極が形成されていない前記第１の主面の端縁部の少なくとも一部の上に形成されている第３の半導体層をさらに備える、太陽電池。 A crystalline semiconductor substrate having first and second main surfaces and having a first conductivity type;
A first semiconductor layer formed on the first main surface and having the first conductivity type;
A first electrode formed on the first semiconductor layer;
A second semiconductor layer formed on the first main surface and having a second conductivity type opposite to the first conductivity type;
A second electrode formed on the second semiconductor layer;
A solar cell comprising:
The first and second electrodes are formed in a region excluding an edge portion of the first main surface,
A solar cell further comprising a third semiconductor layer formed on at least a part of an edge portion of the first main surface on which the first and second electrodes are not formed. - 前記第３の半導体層は、水素を含む、請求項１に記載の太陽電池。 The solar cell according to claim 1, wherein the third semiconductor layer contains hydrogen.
- 前記第３の半導体層は、真性な非晶質半導体からなる第１の非晶質半導体層を含む、請求項１または２に記載の太陽電池。 The solar cell according to claim 1 or 2, wherein the third semiconductor layer includes a first amorphous semiconductor layer made of an intrinsic amorphous semiconductor.
- 前記第３の半導体層は、前記第１の非晶質半導体層の上に形成されており、前記第１の導電型を有する第２の非晶質半導体層を含む、請求項３に記載の太陽電池。 4. The third semiconductor layer according to claim 3, wherein the third semiconductor layer is formed on the first amorphous semiconductor layer and includes a second amorphous semiconductor layer having the first conductivity type. Solar cell.
- 前記第３の半導体層を覆うように形成されている第１の絶縁層をさらに備える、請求項１～４のいずれか一項に記載の太陽電池。 The solar cell according to any one of claims 1 to 4, further comprising a first insulating layer formed so as to cover the third semiconductor layer.
- 前記第１の絶縁層は、水素を含む、請求項５に記載の太陽電池。 The solar cell according to claim 5, wherein the first insulating layer contains hydrogen.
- 前記第１の絶縁層を覆うように形成されている第３の非晶質半導体層をさらに備える、請求項５または６に記載の太陽電池。 The solar cell according to claim 5 or 6, further comprising a third amorphous semiconductor layer formed so as to cover the first insulating layer.
- 前記第３の非晶質半導体層は、前記第１または第２の半導体層と一体に形成されている、請求項７に記載の太陽電池。 The solar cell according to claim 7, wherein the third amorphous semiconductor layer is formed integrally with the first or second semiconductor layer.
- 前記第１の主面の前記第１及び第２の電極が形成されている領域において、前記第１の電極と前記第２の電極との間の領域にも前記第２の非晶質半導体層が形成されている、請求項１～８のいずれか一項に記載の太陽電池。 In the region where the first and second electrodes are formed on the first main surface, the second amorphous semiconductor layer is also formed in a region between the first electrode and the second electrode. The solar cell according to any one of claims 1 to 8, wherein is formed.
- 前記第３の非晶質半導体層は、前記第１及び第２の電極が形成されていない前記第１の主面の端縁部の実質的に全体を覆うように形成されている、請求項１～９のいずれか一項に記載の太陽電池。 The third amorphous semiconductor layer is formed so as to cover substantially the entire edge portion of the first main surface where the first and second electrodes are not formed. The solar cell according to any one of 1 to 9.
- 前記第２の半導体層の中央部を除く両端部の上に設けられている第２の絶縁層をさらに備え、
前記第１の半導体層は、前記第１の主面の前記第２の半導体層に隣接した部分の上と、前記第２の絶縁層の少なくとも一部の上に跨がって設けられている、請求項１～１０のいずれか
一項に記載の太陽電池。 A second insulating layer provided on both ends excluding the central portion of the second semiconductor layer;
The first semiconductor layer is provided over a portion of the first main surface adjacent to the second semiconductor layer and over at least a part of the second insulating layer. The solar cell according to any one of claims 1 to 10. - 前記第１の非晶質半導体層は、前記第１及び第２の電極のいずれにも電気的に接続されていない、請求項１～１１のいずれか一項に記載の太陽電池。 The solar cell according to any one of claims 1 to 11, wherein the first amorphous semiconductor layer is not electrically connected to any of the first and second electrodes.
- 第１及び第２の主面を有し、ｎ型及びｐ型のうちの一方の第１の導電型を有する結晶性半導体基板と、
前記第１の主面の上に形成されており、前記第１の導電型を有する第１の半導体層と、
前記第１の半導体層の上に形成されている第１の電極と、
前記第１の主面の上に形成されており、前記第１の導電型と逆の第２の導電型を有する第２の半導体層と、
前記第２の半導体層の上に形成されている第２の電極と、
を備える太陽電池の製造方法であって、
前記第１及び第２の電極を、前記第１の主面の端縁部を除く領域に形成し、
前記第１及び第２の電極が形成されていない前記第１の主面の端縁部の少なくとも一部
の上に第３の半導体層を形成する、太陽電池の製造方法。 A crystalline semiconductor substrate having first and second main surfaces and having one of n-type and p-type first conductivity types;
A first semiconductor layer formed on the first main surface and having the first conductivity type;
A first electrode formed on the first semiconductor layer;
A second semiconductor layer formed on the first main surface and having a second conductivity type opposite to the first conductivity type;
A second electrode formed on the second semiconductor layer;
A method for producing a solar cell comprising:
Forming the first and second electrodes in a region excluding an edge of the first main surface;
A method for manufacturing a solar cell, comprising forming a third semiconductor layer on at least a part of an edge portion of the first main surface where the first and second electrodes are not formed. - 前記第１の主面の上に前記第１の導電型を有する半導体層を形成する工程と、
前記第１の導電型を有する半導体層をパターニングすることにより、前記第１の導電型を有する半導体層から、前記第１の半導体層と、前記第３の半導体層とを形成する工程と、を備える、請求項１３に記載の太陽電池の製造方法。 Forming a semiconductor layer having the first conductivity type on the first main surface;
Forming the first semiconductor layer and the third semiconductor layer from the semiconductor layer having the first conductivity type by patterning the semiconductor layer having the first conductivity type. The manufacturing method of the solar cell of Claim 13 provided. - 前記第１の導電型を有する半導体層の一部の上に絶縁層を形成する工程と、
前記絶縁層の上から、前記第１の導電型を有する半導体層の前記絶縁層から露出した部分をエッチングすることにより前記第１の主面の一部を露出させると共に、前記第１の半導体層と前記第３の半導体層とを形成する工程と、
前記絶縁層と前記第１の主面の露出部とを覆うように前記第２の導電型を有する半導体層を形成する工程と、
前記第２の導電型を有する半導体層のうち、前記第１の半導体層の上に位置する絶縁層を覆っている部分の少なくとも一部を除去することにより、前記第２の半導体層を形成すると共に、前記第１の半導体層の上に位置する絶縁層の少なくとも一部を露出させる工程と、
前記第２の導電型を有する半導体層の上から、前記絶縁層の露出部をエッチングにより除去し、前記第１の半導体層を露出させる工程と、
を備える、請求項１４に記載の太陽電池の製造方法。 Forming an insulating layer on a portion of the semiconductor layer having the first conductivity type;
A portion of the first main surface is exposed by etching a portion of the semiconductor layer having the first conductivity type exposed from the insulating layer on the insulating layer, and the first semiconductor layer is exposed. And forming the third semiconductor layer;
Forming a semiconductor layer having the second conductivity type so as to cover the insulating layer and the exposed portion of the first main surface;
The second semiconductor layer is formed by removing at least part of a portion of the semiconductor layer having the second conductivity type that covers the insulating layer located on the first semiconductor layer. And exposing at least a part of the insulating layer located on the first semiconductor layer;
Removing an exposed portion of the insulating layer from above the semiconductor layer having the second conductivity type by etching to expose the first semiconductor layer;
The manufacturing method of the solar cell of Claim 14 provided with these. - 前記第２の半導体層を前記第１の半導体層よりも先に形成する、請求項１３に記載の太
陽電池の製造方法。 The method for manufacturing a solar cell according to claim 13, wherein the second semiconductor layer is formed prior to the first semiconductor layer. - 前記第１の主面の上に前記第２の導電型を有する半導体層を形成する工程と、
前記第２の導電型を有する半導体層をパターニングすることにより、前記第２の導電型を有する半導体層から、前記第２の半導体層と、前記第３の半導体層とを形成する工程と、
前記第２の導電型を有する半導体層を形成した後に前記第１の半導体層を形成する工程と、
を備える、請求項１６に記載の太陽電池の製造方法。 Forming a semiconductor layer having the second conductivity type on the first main surface;
Forming the second semiconductor layer and the third semiconductor layer from the semiconductor layer having the second conductivity type by patterning the semiconductor layer having the second conductivity type;
Forming the first semiconductor layer after forming the semiconductor layer having the second conductivity type;
The manufacturing method of the solar cell of Claim 16 provided with these. - 前記第２の導電型を有する半導体層の一部の上に絶縁層を形成する工程と、
前記絶縁層の上から、前記第２の導電型を有する半導体層の前記絶縁層から露出した部分をエッチングすることにより前記第１の主面の一部を露出させると共に、前記第２の半導体層と前記第３の半導体層とを形成する工程と、
前記絶縁層と前記第１の主面の露出部とを覆うように前記第１の導電型を有する半導体層を形成する工程と、
前記第１の導電型を有する半導体層のうち、前記第２の半導体層の上に位置する絶縁層を覆っている部分の少なくとも一部を除去することにより、前記第１の半導体層を形成すると共に、前記第２の半導体層の上に位置する絶縁層の少なくとも一部を露出させる工程と、
前記第１の導電型を有する半導体層の上から、前記絶縁層の露出部をエッチングにより除去し、前記第２の半導体層を露出させる工程と、
を備える、請求項１７に記載の太陽電池の製造方法。 Forming an insulating layer on a part of the semiconductor layer having the second conductivity type;
A portion of the first main surface is exposed by etching a portion of the semiconductor layer having the second conductivity type exposed from the insulating layer from above the insulating layer, and the second semiconductor layer is exposed. And forming the third semiconductor layer;
Forming a semiconductor layer having the first conductivity type so as to cover the insulating layer and the exposed portion of the first main surface;
The first semiconductor layer is formed by removing at least part of a portion of the semiconductor layer having the first conductivity type that covers the insulating layer located on the second semiconductor layer. And exposing at least a portion of the insulating layer located on the second semiconductor layer;
Removing the exposed portion of the insulating layer by etching from above the semiconductor layer having the first conductivity type, and exposing the second semiconductor layer;
The manufacturing method of the solar cell of Claim 17 provided with these.
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