WO2011132302A1 - Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique - Google Patents

Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique Download PDF

Info

Publication number
WO2011132302A1
WO2011132302A1 PCT/JP2010/057211 JP2010057211W WO2011132302A1 WO 2011132302 A1 WO2011132302 A1 WO 2011132302A1 JP 2010057211 W JP2010057211 W JP 2010057211W WO 2011132302 A1 WO2011132302 A1 WO 2011132302A1
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
block
power storage
blocks
parallel
Prior art date
Application number
PCT/JP2010/057211
Other languages
English (en)
Japanese (ja)
Inventor
晴見 竹田
佳史 竹田
志朗 藤原
Original Assignee
株式会社ジェイピーパワーモジュール
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社ジェイピーパワーモジュール filed Critical 株式会社ジェイピーパワーモジュール
Priority to PCT/JP2010/057211 priority Critical patent/WO2011132302A1/fr
Publication of WO2011132302A1 publication Critical patent/WO2011132302A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0024—Parallel/serial switching of connection of batteries to charge or load circuit
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices

Definitions

  • the present invention relates to a charge control method and a discharge control method for a power storage device using an electric double layer capacitor as a power storage device.
  • Electric Double Layer Capacitors are attracting attention as new storage devices that replace secondary batteries due to their long cycle life and wide operating temperature range.
  • capacitor an electric double layer capacitor
  • the DC power supplied from the DC power source 1 such as a solar battery is temporarily stored in the power storage unit 21 of the power storage device 2.
  • the capacitor has a voltage between terminals that varies greatly in proportion to the amount of stored charge, and therefore cannot store the power stored in the power storage unit 21 directly to the load 3. For this reason, the power stored in the power storage unit 21 is supplied to the load 3 after the voltage is stabilized in the power converter 22 such as a DC-DC converter or a DC-AC inverter.
  • the control unit 23 controls charging / discharging in the power storage unit 21.
  • the power converter 22 has an allowable input voltage range. Therefore, in order to continuously supply stable power to the load 3, the output voltage (hereinafter referred to as “power storage unit voltage”) Vt of the power storage unit 21 must be maintained within the allowable input voltage range of the power converter 22. I must.
  • the power storage unit 21 is often used by connecting a plurality of capacitors in series. Further, in order to secure the necessary accumulated charge amount, a plurality of capacitors are often connected in parallel. Therefore, power storage unit 21 of a power storage device using a capacitor is generally configured by connecting a plurality of capacitors in series and in parallel.
  • Series-parallel switching is one of the methods used for improving the charge / discharge characteristics and the discharge depth in the power storage device 2 in which the power storage unit 21 is configured by connecting a plurality of capacitors in series or in parallel. It is.
  • the power storage unit 21 of the power storage device 2 using “series-parallel switching” described in Patent Document 1 is configured as shown in FIG. That is, one circuit block (hereinafter simply abbreviated as “block”) is constituted by a pair of capacitors C, C having the same capacitance and a plurality of switches S for switching the series connection and the parallel connection of the pair of capacitors C, C.
  • the blocks are connected in n stages (B1 to Bn) in series.
  • FIG. 19 is a simplified diagram showing the connection pattern of capacitor C of power storage unit 21 in FIG.
  • each capacitor C Charge is accumulated in each capacitor C as charging progresses, and the storage unit voltage Vt increases.
  • the switches (S11 to S33) in FIG. 18 are appropriately turned on or off.
  • the capacitors C of each block are arranged in a predetermined order such that the power storage unit voltage Vt falls within the allowable input voltage range of the power converter 22, for example, FIG. 19B ⁇ FIG. 19C ⁇ FIG.
  • switching from the serial connection to the parallel connection is performed in stages, and charging is performed so that the capacitors C of each block are finally connected in parallel.
  • the switches (S11 to S33) in FIG. By turning off, the capacitor of each block in a predetermined order opposite to that during charging, for example, in the order of FIG. 19 (d) ⁇ FIG. 19 (c) ⁇ FIG. 19 (b) ⁇ FIG. C is gradually switched from parallel connection to series connection, and discharging is performed.
  • the series-parallel switching is performed in order to improve the charge / discharge characteristics and the depth of discharge by maintaining the power storage unit voltage Vt within the allowable input voltage range of the power converter 22.
  • a circuit called “parallel monitor” configured by a resistor R and a switch S as shown in FIG.
  • this parallel monitor turns on the switch S as shown in FIG.
  • the capacitor C is prevented from being overcharged by forcibly bypassing Ic.
  • the charging control method of the power storage device developed by the inventors is not only for preventing overcharging of the parallel monitor, but also by controlling the parallel monitor at regular intervals so that the voltage between terminals of each capacitor is within a certain range. It is also used as a countermeasure for so-called “cross current” that occurs when the capacitors of each block are switched from serial connection to parallel connection, for correction so as to be within the range (called constant correction). With this and the serial / parallel switching control method described later, the operation time of the parallel monitor and the heat generated by the operation can be significantly reduced as compared with the method described in Patent Document 1, and the charging efficiency can be increased.
  • the power storage unit voltage Vt reaches the upper limit of the allowable input voltage range of the power converter 22 to appropriately control the switches (S01 to S33). Then, the capacitor C of any one block is switched to the parallel connection, and the power storage unit voltage Vt is lowered within the allowable input voltage range of the power converter 22.
  • block voltage blocks having the highest sum of voltages between terminals of the two capacitors C in the block. That is, the state shown in FIG. 22 (a) is switched to the state shown in FIG. 22 (b), FIG. 22 (c), or FIG. 22 (d).
  • the block is set so that the storage unit voltage Vt falls within the allowable input voltage range of the power converter 22 every time the storage unit voltage Vt reaches the upper limit value of the allowable input voltage range of the power converter 22.
  • the block with the highest voltage is selected, the capacitor C of that block is switched to parallel connection, and the power storage unit voltage Vt is lowered.
  • the block connected in parallel is switched to the serial connection, such as switching from the state of FIG. 22B to the state of FIG. 22D, and the other one block is switched from the serial connection to the parallel connection.
  • each capacitor C is charged while maintaining the power storage unit voltage Vt within the allowable input voltage range of the power converter 22 by increasing the number of blocks to be connected in parallel. That is, the state is switched from any of the states of FIG. 22 (b), FIG. 22 (c), or FIG. 22 (d) to any of the states of FIG. 22 (e), FIG. 22 (f), or FIG. It is done. Also in this case, two blocks are selected in descending order of the block voltage, and the capacitors C of these blocks are connected in parallel.
  • the capacitors C of all the blocks (B1 to B3) are connected in parallel, and the power storage unit voltage Vt when all the capacitors C are fully charged is It is set to be within the allowable input voltage range.
  • the block voltage is set so that the power storage unit voltage Vt falls within the allowable input voltage range of the power converter 22 every time the power storage unit voltage Vt decreases to the lower limit value of the allowable input voltage range of the power converter 22.
  • the highest block is preferentially connected in series to increase the power storage unit voltage Vt. At this time, for example, the block connected in series is returned to the parallel connection, such as switching from the state of FIG. 22E to the state of FIG. 22F, and the other one block is connected in series.
  • discharging is performed so that the storage unit voltage Vt maintains the allowable input voltage range of the power converter 22 by switching the series-parallel connection state of each block.
  • the feature of the serial-parallel switching method described in Patent Document 2 is that the order of blocks to be serial-parallel switched and the pattern of serial-parallel switching are not fixed as in the method described in Patent Document 1. It is in. By doing so, it is possible to finely control the voltage across the terminals of the capacitors C in each block, and furthermore, it is possible to suppress variations in the voltages across the terminals of all the capacitors C constituting the power storage unit 21.
  • the conventional charge control method and discharge control method for a power storage device achieve efficient charge and discharge by using series-parallel switching control and a parallel monitor together.
  • series-parallel switching is performed because the storage unit voltage Vt is the upper limit of the allowable input voltage range of the power converter 22.
  • the correction is always performed by parallel monitoring.
  • the number of series-parallel switching is small, and the terminal voltage of each capacitor still varies. It was.
  • the present invention has been made in view of the above-described conventional problems, and a power storage device charge control method capable of suppressing variations in voltage between terminals of a capacitor only by switching a series-parallel connection without using a parallel monitor. It is another object of the present invention to provide a discharge control method.
  • a method for controlling the charge of a power storage device includes, as power storage means, a block composed of two capacitors having the same capacitance and a plurality of switches in series (n Is a natural number of 2 or more), and each block is a power storage device capable of switching the connection of the two capacitors in series or in parallel by turning on / off the plurality of switches.
  • a charge control method comprising: When a predetermined interval time elapses, a block voltage that is a sum of voltages between terminals of two capacitors constituting the block is compared for each block, Connection of capacitors of each block so that k blocks (k is a natural number equal to or less than n) are connected in parallel and other (nk) blocks are connected in series in order from the block with the highest block voltage. Switch state, In addition, the comparison of the block voltages and the switching of the connection state of each block are repeated at each interval time until the output voltage of the power storage unit reaches a preset first voltage value.
  • the output voltage of the power storage unit reaches the first voltage value
  • the number of blocks connected in parallel among the n blocks is changed from k to (k + 1).
  • the two capacitors constituting the block may be formed by connecting a plurality of capacitors having the same capacitance in parallel.
  • n blocks (n is a natural number of 2 or more) connected in series with two capacitors having the same capacitance and a plurality of switches are connected.
  • the capacitor group is used, and each block is a discharge control method of a power storage device that can switch the connection of the two capacitors in series or in parallel by turning on / off the plurality of switches,
  • the block voltage that is the sum of the voltages across the terminals of each capacitor constituting the block is compared for each block, In order from the block with the highest block voltage, (nk) (k is a natural number less than n) blocks are connected in series, and the other k capacitors are connected in parallel so that the other blocks are connected in parallel.
  • Switch state In addition, the comparison of the block voltages and the switching of the connection state of each block are repeated at each interval time until the output voltage of the power storage means reaches a preset second voltage value.
  • the output voltage of the power storage means reaches the second voltage value
  • the number of blocks connected in series among the n blocks is changed from (nk) to (nk + 1).
  • the two capacitors constituting the block may be formed by connecting a plurality of capacitors having the same capacitance in parallel.
  • the discharge is stopped when the voltage between terminals of any one of the capacitors constituting the power storage unit falls below the lower limit voltage.
  • the charge control method for a power storage device since the series-parallel connection of each block is switched so that the block voltage does not vary every short interval time, the variation in the voltage between the terminals of the capacitor can be suppressed.
  • the discharge control method for a power storage device the series-parallel connection of each block is switched so as to eliminate the variation in the block voltage every short interval time, so that the variation in the voltage between the terminals of the capacitor can be suppressed.
  • the second voltage value for example, the lower limit value of the allowable input voltage range of the power converter
  • the discharging time of the power storage means that is, the operation of the power converter The time can be lengthened.
  • FIG. 1 is a block diagram illustrating a configuration of a power supply system including a power storage device.
  • FIG. 2 is a circuit diagram showing a specific example of the configuration of the power storage unit of FIG.
  • FIG. 3 is an explanatory diagram of “block voltage”.
  • FIG. 4 is a graph showing a temporal change in the power storage unit voltage Vt.
  • FIG. 5 is a graph showing temporal changes in the block voltage in the present invention and the conventional charge control method.
  • FIG. 6 is a diagram illustrating capacitor switching control in the charge control method of the present invention.
  • FIG. 7 shows a block configuration of the power storage unit.
  • FIG. 8 is a circuit diagram illustrating a configuration example of a block.
  • FIG. 9 is a flowchart for carrying out the charge control method of the present invention.
  • FIG. 1 is a block diagram illustrating a configuration of a power supply system including a power storage device.
  • FIG. 2 is a circuit diagram showing a specific example of the configuration of the power storage
  • FIG. 10 is a diagram illustrating capacitor switching control in the discharge control method of the present invention.
  • FIG. 11 is a flowchart for carrying out the discharge control method of the present invention.
  • FIG. 12 is a flowchart in a case where the discharge control method of the present invention is performed on a power storage device using a capacitor in which upper limit voltage and lower limit voltage are limited.
  • FIG. 13 is a flowchart when the charge control method and the discharge control method of the present invention are combined.
  • FIG. 14 is a flowchart in the case where the charge control method and the discharge control method of the present invention are performed on a power storage device using a capacitor in which the upper limit voltage and the lower limit voltage are limited.
  • FIG. 15 is a graph showing temporal changes in the power storage unit voltage Vt and the capacitor terminal voltage Vc when charge control and discharge control are performed according to the flow of FIG.
  • FIG. 16 is a block diagram illustrating a configuration of a power supply system using a plurality of capacitors as an electricity storage device.
  • FIG. 17 is a circuit diagram illustrating a configuration of the power storage unit.
  • FIG. 18 is a circuit diagram of a power storage unit configured by three blocks.
  • FIG. 19 is a diagram showing a simplified connection pattern of capacitor C in the power storage unit shown in FIG.
  • FIG. 20 is a circuit diagram illustrating the “parallel monitor”.
  • FIG. 21 is a circuit diagram illustrating a configuration of the power storage unit described in Patent Document 2.
  • FIG. 22 is a simplified view of the connection pattern of capacitor C in the power storage unit shown in FIG.
  • charge control method and a discharge control method (hereinafter simply referred to as “charge control method” and “discharge control method”) for a power storage device according to an embodiment of the present invention will be described with reference to the drawings.
  • FIG. 1 illustrates a configuration of a power supply system including a power storage device.
  • a charge control method performed by power storage device 2 in FIG. 1 will be described.
  • the power storage device 2 stores the DC power supplied from the DC power source 1 and supplies the DC power to the load 3 as it is or converted into AC power.
  • the DC power supply 1 is preferably a current source, but may be a voltage source.
  • the DC power source 1 for example, a solar cell, a wind power generator, an engine generator, or the like is used. However, other power supply sources can be used. To use.
  • the power storage device 2 includes a power storage unit 21, a power converter 22, and a control unit 23.
  • the power storage unit 21 stores DC power supplied from the DC power supply 1.
  • the power converter 22 is composed of a DC-AC inverter or the like, converts the DC power stored in the power storage unit 21 into AC power, and stabilizes the output voltage.
  • a DC-DC converter or the like is used as the power converter 22.
  • the power storage unit 21 that is a power storage unit of the power storage device 2 is a block in which n blocks (n is a natural number of 2 or more) connected in series are two blocks each having two capacitors (that is, electric double layer capacitors).
  • n blocks n is a natural number of 2 or more
  • capacitors that is, electric double layer capacitors
  • each block (B1 to B5) is composed of two capacitors C and three switches S having the same capacitance. By switching each switch S on and off, the two capacitors C are connected in series or Connected in parallel. The reason for configuring each block with two capacitors will be described in detail later.
  • the electric double layer capacitor in the narrow sense means a symmetric electric double layer capacitor using electric double layer capacitance for both the positive electrode and the negative electrode of the electrode, but the electric double layer capacitor in the broad sense includes a symmetric capacitor.
  • an asymmetric type electric double layer capacitor in which one pole is a redox pseudocapacitance (redox pseudocapacitance) generated with a redox reaction and the other pole is an electric double layer capacitance is also included.
  • the present invention can be applied to an electric double layer capacitor in a broad sense.
  • the switch S a semiconductor switch composed of an FET or the like is usually used. However, when the amount of current flowing through the switch S is large, a thyristor or IGBT may be used.
  • control unit 23 controls charging / discharging in the power storage unit 21.
  • the control unit 23 includes a series / parallel switching circuit 24, an inter-terminal voltage detection circuit 25, a power storage unit voltage detection circuit 26, and a control circuit 27.
  • the series-parallel switching circuit 24 switches between the state in which the two capacitors C are connected in series and the state in which the capacitors are connected in parallel by switching each of the three switches S in each block.
  • the inter-terminal voltage detection circuit 25 detects the inter-terminal voltage Vc of the capacitor C in each block.
  • the power storage unit voltage detection circuit 26 detects the output voltage of the power storage unit 21, that is, the power storage unit voltage Vt.
  • the inter-terminal voltage Vc detected by the inter-terminal voltage detection circuit 25 and the power storage unit voltage Vt detected by the power storage unit voltage detection circuit 26 are input to the control circuit 27.
  • the control circuit 27 includes a block voltage calculation circuit 28 and an oscillation circuit 29.
  • the block voltage calculation circuit 28 calculates the block voltage Vb of each block based on the terminal voltage Vc of each capacitor C detected by the terminal voltage detection circuit 25.
  • the oscillation circuit 29 generates a pulse for each interval period from the clock signal and outputs it as a timing signal for the series-parallel switching circuit 24 and the inter-terminal voltage detection circuit 25.
  • the control circuit 27 controls the series / parallel switching circuit 24 based on the block voltage Vb calculated by the block voltage calculation circuit 28 and the storage unit voltage Vt output from the storage unit voltage detection circuit 26.
  • control circuit 27 When the control circuit 27 is configured by a CPU (Central Processing Unit), the functions of the control circuit 27, the block voltage calculation circuit 28, and the oscillation circuit 29 are software (programs) stored in a ROM (Read Only Memory). This is realized by reading out to the CPU and executing it.
  • CPU Central Processing Unit
  • ROM Read Only Memory
  • the “block voltage” Vb defined in this specification is not a voltage across the block but a value obtained by adding a voltage between terminals of two capacitors constituting the block.
  • the block voltage Vb is the voltage Vc1 between the terminals of the capacitor C1 and the voltage between the terminals of the capacitor C2. A value obtained by adding Vc2.
  • the block voltage Vb is a value obtained by adding the inter-terminal voltage Vc3 of the capacitor C1 and the inter-terminal voltage Vc4 of the capacitor C2.
  • control circuit 27 needs to control the discharge so that the amount of power stored in the power storage unit 21 does not fall below the amount of power required by the control circuit 27.
  • the charge control method according to the present invention is the same as the control method described in Patent Document 2 described above, in which the block is switched in series and parallel when the storage unit voltage Vt reaches a preset first voltage value. .
  • the block voltage Vb is always detected at every predetermined interval time except when the capacitors of all the blocks are connected in series and when the capacitors of all the blocks are connected in parallel. The series-parallel connection is switched so that the variation in the voltage Vb is reduced.
  • the block voltage Vb of each capacitor constituting the block is compared for each block, and k blocks (in order from the block having the highest block voltage Vb) k is a natural number equal to or less than n), and the connection state of the capacitors in each block is switched so that the other (n ⁇ k) blocks are connected in series.
  • the comparison of the block voltage Vb and the switching of the connection state of each block are repeated for each interval time Ti until the power storage unit voltage Vt reaches a preset first voltage value.
  • the first voltage value is normally set to a value that provides the best efficiency, that is, the upper limit value of the allowable input voltage range of the power converter 22, but the efficiency is not limited even if it is set to a lower value. Although slightly reduced, the effect of the charge control method of the present invention is exhibited.
  • the first voltage value is set to the upper limit value of the allowable input voltage range of the power converter 22.
  • FIG. 4 is a graph showing temporal changes in the power storage unit voltage Vt
  • FIG. 5A is a graph showing temporal changes in the block voltage in the charge control method of the present invention
  • FIG. It is a graph which shows the time change of the block voltage in a charge control method.
  • the transition of the block voltage of each block is as shown in FIG. That is, the series-parallel connection is switched at point a (time Ta) when the storage unit voltage Vt reaches the upper limit of the allowable input voltage range of the power converter 22, and at this time, the block B1 having the highest block voltage Vb is switched. Two capacitors are connected in parallel. As a result, the charging speed of the two capacitors in the block B1 becomes slow, and the difference in the block voltage Vb from the other blocks (blocks B2 and B3) decreases.
  • the storage unit voltage Vt reaches the upper limit value of the allowable input voltage range of the power converter 22 again.
  • the switching of the series-parallel connection is not performed until (time Tb), and the two capacitors of the block B1 are continuously charged while being connected in parallel.
  • the block voltage Vb of the block B1 is much lower than the block voltages Vb of the other blocks (B2, B3), which causes the block voltage Vb to vary.
  • the block voltage Vb of the block B2 is When it becomes the highest at the point c (time Tc), the connection state of the two capacitors in the block B1 is returned in series at this point, and the connection state of the two capacitors in the block B2 is switched in parallel.
  • the block voltage Vb of each block is always detected at every predetermined interval time Ti, and the two capacitors of the block having the highest block voltage Vb are switched to the parallel connection. The two capacitors in the block that were were returned to the serial connection.
  • the switching of the block connection state is repeated every interval time Ti, thereby suppressing the variation in the block voltage Vb.
  • the switching control of the capacitor connection state will be described more specifically. 6, the case where the power storage unit 21 shown in FIG. 2, that is, the power storage unit 21 in which five blocks (B1 to B5) are connected in series, will be described.
  • the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B3, B5, B4, B1, Suppose B2.
  • the control circuit 27 switches the connection between the blocks B3 and B5 having a high voltage level in parallel, and instead switches the blocks B1 and B2 connected in parallel to series connection.
  • the connection state of each block when the time T2 has elapsed is shown in the upper part of FIG.
  • the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B4, B1, Assume that B2, B3, and B5 are obtained.
  • the control circuit 27 switches the blocks B4 and B1 having a high voltage level from series connection to parallel connection, and instead switches the blocks B3 and B5 having low voltage level connected in parallel to series connection. .
  • the connection state of each block when the time T3 has elapsed is shown in the upper part of FIG.
  • the interval time Ti By setting the interval time Ti to a short time (for example, within 10 seconds) and repeating the switching operation described above, the variation in the block voltage Vb of each block is suppressed as shown in the graph of FIG. Furthermore, variations in the terminal voltage Vc of the capacitors constituting the block are also suppressed. As a result, since the inter-terminal voltage Vc of each capacitor does not exceed the rated voltage until almost all capacitors are fully charged, it is not necessary to provide a parallel monitor.
  • each capacitor When charging is started from a completely discharged state, the capacitors C of all the blocks are connected in series, so that the block voltage of each block and the voltage between terminals of each capacitor are not changed until the series-parallel switching is started. It varies. However, each capacitor does not reach the rated voltage during this period, and the block voltage of each block and the voltage between terminals of each capacitor are equalized by subsequent series-parallel switching.
  • the capacitors C of all the blocks are connected in parallel, and when the power storage unit as shown in FIG. 2 is used, the block voltage of each block varies. However, until the capacitors C of all the blocks are connected in parallel, the block voltage of the block and the voltage between terminals of each capacitor are equalized by serial / parallel switching. Are very few.
  • each block of the power storage unit 21 is composed of two capacitors in the present invention.
  • Both the power storage unit 21A shown in FIG. 7A and the power storage unit 21B shown in FIG. 7B are each composed of a total of 12 capacitors C having the same nominal capacitance.
  • one block includes four capacitors C, and the two capacitors C are connected in series.
  • the power storage unit 21B of FIG. 7B one block is composed of two capacitors C, and each capacitor C is a single capacitor.
  • the configuration of the power storage unit 21B can reduce variations in the block voltage Vb of each block and the inter-terminal voltage Vc of each capacitor compared to the configuration of the power storage unit 21A. Furthermore, the fluctuation
  • each of the capacitors C in each block in FIG. 7B is configured by a plurality of capacitors (two in the figure) having the same capacitance connected in parallel as shown in FIG. These can be regarded as one capacitor in terms of characteristics. Therefore, a block having the configuration shown in FIG.
  • FIG. 9 shows a flow for carrying out the charge control method according to the present invention.
  • the flow of charge control will be described with reference to the block diagram of FIG. 1 and the flowchart of FIG. 9.
  • each capacitor C of the power storage unit 21 is in a completely discharged state, that is, all the capacitors C are in a state where no charge is accumulated.
  • step S13 the control circuit 27 waits for the interval time Ti to elapse, and after the interval time Ti elapses, proceeds to the processing in step S14.
  • step S14 the inter-terminal voltage detection circuit 25 measures the inter-terminal voltage Vc of each capacitor C of the power storage unit 21.
  • the power storage unit voltage detection circuit 26 measures a power storage unit voltage Vt that is an output voltage of the power storage unit 21.
  • step S15 the block voltage calculation circuit 28 of the control circuit 27 calculates the block voltage Vb of each block based on the terminal voltage Vc of each capacitor C detected by the terminal voltage detection circuit 25.
  • step S16 the control circuit 27 determines whether or not the terminal voltage Vc of each capacitor C is equal to or lower than the rated voltage VCU.
  • the process proceeds to step S21, and when the inter-terminal voltage Vc of any capacitor C does not exceed the rated voltage VCU (YES). Advances to step S17.
  • step S21 the control circuit 27 stops charging and ends the charging control.
  • the terminal voltage Vc of the capacitor C is rated as long as all the capacitors C are not fully charged. None exceed the voltage. Therefore, when the inter-terminal voltage Vc of any capacitor C exceeds the rated voltage, it is determined that all the capacitors C are almost fully charged, or the capacitance of any capacitor C is abnormal. To stop charging.
  • control circuit 27 determines whether or not power storage unit voltage Vt exceeds upper limit value VU of the allowable input voltage range of power converter 22 based on power storage unit voltage Vt detected by power storage unit voltage detection circuit 26. To do. When power storage unit voltage Vt exceeds upper limit value VU (NO), the process proceeds to step 18, and when power storage unit voltage Vt does not exceed upper limit value VU (YES), the process proceeds to step S20.
  • step S18 if the number k of parallel-connected blocks is n (YES), the process proceeds to step S21, and it is determined that all capacitors C are fully charged, and charging is stopped.
  • step S19 the block number k is set to “k + 1”, and then the process proceeds to step S20.
  • step S20 the control circuit 27 controls the series / parallel switching shown in FIG. That is, k blocks of capacitors C are connected in parallel from the block with the highest block voltage Vb, and the other (nk) blocks of capacitors C are connected in series.
  • step S20 After the process of step S20 is completed, the process returns to the process of step S13, and the processes of steps S14 to S20 are repeated every interval time Ti until the power storage unit voltage Vt exceeds the upper limit value VU of the allowable input voltage range.
  • the variation in the block voltage Vb is not limited to when the power storage unit voltage Vt reaches the upper limit value of the allowable input voltage range of the power converter 22 but also at every predetermined interval time.
  • the series-parallel switching control is performed so that the number is reduced. As a result, not only variations in the block voltage Vb but also variations in the voltage Vc between the terminals of each capacitor C can be suppressed.
  • the discharge control method according to the present invention is always the same as the charge control method described in the first embodiment, except when the capacitors of all the blocks are connected in series and when the capacitors of all the blocks are connected in parallel.
  • the block voltage Vb is detected at every predetermined interval time, and the series-parallel connection is switched so that the variation of the block voltage Vb between the blocks is reduced.
  • the block voltage Vb of each capacitor constituting the block is compared for each block, and (n ⁇ k)
  • the connection state of the capacitors of each block is switched so that the blocks (k is a natural number equal to or less than n) are connected in series and the other k blocks are connected in parallel.
  • the comparison of the block voltage Vb and the switching of the connection state of each block are repeated every interval time Ti until the output voltage Vt of the power storage unit 21 reaches a preset second voltage value.
  • the second voltage value is usually set to a value that provides the best efficiency, that is, the lower limit value of the allowable input voltage range of the power converter 22, but the efficiency slightly decreases even if it is set to a higher value.
  • the effect of the discharge control method of the present invention is exhibited.
  • the block voltage Vb of each block calculated by the block voltage calculation circuit 28 is B4, B5, B3, B2, Suppose B1.
  • the control circuit 27 switches the connection between the blocks B4 and B5 having a high voltage level from parallel to series, and switches the blocks B1 and B2 connected in series to parallel connection instead.
  • the upper part of FIG. 10 shows the connection state of each block when time T6 has elapsed.
  • the control circuit 27 switches the blocks B3 and B2 having a higher block voltage level among the blocks connected in parallel to serial connection, and instead connects the blocks B4 and B5 connected in series in parallel. Switch to connection.
  • the upper part of FIG. 10 shows the connection state of each block when time T6 has elapsed.
  • the interval time Ti is set to a short time (for example, within 10 seconds) and repeating the switching operation described above, the variation in the block voltage Vb of each block is suppressed, and furthermore, the capacitors constituting the block Variations in the inter-terminal voltage Vc are also suppressed, and as a result, the discharge time of the power storage unit 21 (operation time of the power converter 22) can be lengthened.
  • FIG. 11 shows a flow for carrying out the discharge control method of the present invention.
  • the flow of discharge control will be described with reference to the block diagram of FIG. 1 and the flowchart of FIG. 11 when discharging from a fully charged state.
  • each capacitor C of the power storage unit 21 is almost fully charged.
  • step S33 the control circuit 27 waits for the interval time Ti to elapse, and after the interval time Ti elapses, proceeds to the process of step S34.
  • step 34 the inter-terminal voltage detection circuit 25 measures the inter-terminal voltage Vc of each capacitor C of the power storage unit 21.
  • the storage unit voltage detection circuit 26 measures the storage unit voltage Vt.
  • step S35 the block voltage calculation circuit 28 of the control circuit 27 calculates the block voltage Vb of each block based on the terminal voltage Vc of the capacitor C detected by the terminal voltage detection circuit 25.
  • step S36 the control circuit 27 determines whether or not the power storage unit voltage Vt is equal to or higher than the lower limit value VL of the allowable input voltage range of the power converter 22.
  • the process proceeds to step 37.
  • the process proceeds to step S39.
  • step S37 when the number of blocks k connected in parallel is “0” (YES), the process proceeds to step S40, and the power storage unit 21 cannot supply a voltage equal to or higher than the lower limit value VL of the allowable input voltage range of the power converter 22. Judgment is made and discharge is stopped.
  • step S38 the number k of parallel blocks is set to (k ⁇ 1), and then the process proceeds to step S39.
  • step S39 the control circuit 27 controls the series / parallel switching shown in FIG. That is, (k) blocks of capacitors C are connected in series from the block with the highest block voltage Vb, and the other k blocks of capacitors C are connected in parallel.
  • step S39 After the process of step S39 is completed, the process returns to the process of step S33, and the processes of steps S34 to S39 are repeated every time the interval time Ti elapses until the power storage unit voltage Vt becomes less than the lower limit value VL of the allowable input voltage range.
  • FIG. 12 shows a flow in the case of using a capacitor in which the upper limit voltage and the lower limit voltage are limited.
  • step S41 is added between steps S35 and S36 of the flow of FIG. That is, in step S41, the control circuit 27 determines whether or not the terminal voltage Vc of each capacitor C is higher than the lower limit voltage VCL. When the inter-terminal voltage Vc of any one of the capacitors C becomes equal to or lower than the lower limit voltage VCL (NO), the process proceeds to step S40 and the discharge is stopped. On the other hand, if the inter-terminal voltage Vc of any capacitor C is higher than the rated lower limit voltage VCL (YES), the process proceeds to step S36.
  • the variation in the voltage Vc between the terminals of the capacitor is suppressed. Therefore, when the voltage Vc between the terminals of any one of the capacitors C becomes the lower limit voltage VCL, It is determined that the discharge of the capacitor C has been completed, or it is determined that there is an abnormality in the capacitance of any one of the capacitors C, and charging is stopped.
  • FIG. 13 shows a flow when the charge control method and the discharge control method of the present invention are implemented in combination.
  • the same steps as those in FIGS. 9 and 11 are denoted by the same reference numerals, and description thereof is omitted.
  • the allowable input voltage range of the power converter 22 is larger than the rated voltage (upper limit voltage) of each capacitor, that is, (VU ⁇ VL)> the rated voltage (upper limit voltage) of each capacitor. It is assumed that.
  • step S17 the power storage unit voltage Vt is compared with the upper limit value VU of the allowable input voltage range of the power converter, and when the power storage unit voltage Vt exceeds the upper limit value VU (NO), a discharge is possible. Discharging is started (step S32), and then the control circuit 27 instructs the series-parallel switching circuit 24 to set the number k of parallel connection blocks to “1” (step S51).
  • the control circuit 27 subsequently performs the process of step S20, that is, performs serial / parallel switching of the blocks, and subsequently executes the steps (steps S13 to S21) of the charging control described in FIG.
  • step S17 in the lower part of the flow of FIG. 13, when the power storage unit voltage Vt does not exceed the upper limit value VU of the allowable input voltage range of the power converter (YES), the process proceeds to step S36.
  • step S36 the control circuit 27 determines whether or not the power storage unit voltage Vt is lower than the lower limit value VL of the allowable input voltage range of the power converter 22 due to discharging, and if it is lower than the lower limit value VL (NO). The process proceeds to step S37, and if not lower (YES), the process proceeds to step S52.
  • step S52 the control circuit 27 determines whether or not the charging of the power storage unit 21 is stopped.
  • the control circuit 27 proceeds to the process of step S53 and restarts the charging, and then returns to the process of step S20.
  • the charging is not stopped (NO)
  • the process directly returns to step S20.
  • step S37 when the number of blocks k connected in parallel is “0” (YES), the process proceeds to step S40, and the power storage unit 21 cannot supply a voltage equal to or higher than the lower limit value VL of the allowable input voltage range of the power converter 22. Judgment is made and discharge is stopped.
  • step S38 the number k of parallel blocks is set to (k ⁇ 1), and then the process proceeds to step S39. The process returns to step S13 in the lower part of the flow.
  • FIG. 14 similarly to FIG. 12 described above, a capacitor having a limitation on the upper limit voltage (rated voltage) and the lower limit voltage is used as an electricity storage device, and the charge control method and the discharge control method of the present invention are combined. The flow in the case of implementation is shown.
  • step S41 is added between step S17 and step S36 shown in the lower part of the flow of FIG. That is, in step S41, the control circuit 27 determines whether or not the terminal voltage Vc of the capacitor C exceeds the lower limit voltage VCL. When the inter-terminal voltage Vc of any one of the capacitors C becomes equal to or lower than the lower limit voltage VCL (NO), the process proceeds to step S40 to stop discharging, and the inter-terminal voltage Vc of any capacitor C is higher than the lower limit voltage VCL. If yes (YES), the process proceeds to step S36.
  • 15 (a) and 15 (b) show the storage unit voltage when charge control and discharge control are performed according to the flow of FIG. 13 for the storage unit 21 in which the five blocks shown in FIG. 2 are connected in series.
  • 5 is a graph showing temporal changes in Vt and a voltage Vc between terminals of a capacitor C.
  • the graph of FIG. 15 shows a case where the discharge to the load is performed after all the capacitors C are fully charged.
  • an electric double layer capacitor having a rated voltage of 2.7 [V] and a nominal capacitance of 5000 [F] is used as the capacitor C.
  • the allowable input voltage range of the power converter 22 was set to 10.5 to 15 [V]
  • the interval time Ti was set to 5 seconds to perform charge control and discharge control.
  • the circuit having the configuration shown in FIG. 2 is used as the power storage unit 21 that implements the charge control method and the discharge control method of the present invention.
  • the present invention is not limited to this. .
  • the same effect can be obtained by using the circuit having the configuration shown in FIG.
  • the charge control method and the discharge control method according to the present invention can be applied to various power supply systems without being limited by the amount of power to be handled because the charge / discharge efficiency is high and the configuration of the power storage device can be simplified. Is.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

L'invention concerne un procédé de commande de charge et un procédé de commande de décharge pour un dispositif accumulateur électrique, permettant de supprimer les variations de tension aux bornes de condensateurs électriques double couche par seule commutation de liaisons en série/parallèle sans utiliser de dispositif de surveillance en parallèle. Le procédé de commande de charge comprend les étapes consistant à : comparer la tension de bloc (Vb), représentant la somme de la tension (Vc) aux bornes de deux condensateurs électriques double couche formant un bloc, pour chaque bloc au cours d'un intervalle de temps prescrit (Ti) ; relier, dans l'ordre, k blocs en parallèle en partant du bloc dont la tension de bloc (Vb) est la plus élevée ; et commuter les modes de liaison des condensateurs électriques à double couche des (n-k) autres blocs de manière à relier les blocs en série. Le procédé comprend en outre l'étape consistant à répéter, pour chaque intervalle de temps (Ti), les étapes consistant à comparer les tensions de bloc (Vb) et à commuter les modes de liaison des blocs jusqu'à ce que la tension de sortie (Vt) d'un module accumulateur électrique (21) atteigne une limite supérieure (VU) d'une plage de tensions d'entrée admissibles d'un convertisseur de courant (22).
PCT/JP2010/057211 2010-04-23 2010-04-23 Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique WO2011132302A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2010/057211 WO2011132302A1 (fr) 2010-04-23 2010-04-23 Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2010/057211 WO2011132302A1 (fr) 2010-04-23 2010-04-23 Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique

Publications (1)

Publication Number Publication Date
WO2011132302A1 true WO2011132302A1 (fr) 2011-10-27

Family

ID=44833854

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/057211 WO2011132302A1 (fr) 2010-04-23 2010-04-23 Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique

Country Status (1)

Country Link
WO (1) WO2011132302A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014057192A2 (fr) * 2012-10-11 2014-04-17 Renault S.A.S Structure pour la modulation de tension d'une batterie et son équilibrage actif
EP2736145A1 (fr) * 2012-11-26 2014-05-28 Nxp B.V. Dispositifs à alimentation sans fil
WO2015189907A1 (fr) * 2014-06-10 2015-12-17 株式会社Ｋａｇｒａ Procédé de charge d'élément de stockage d'électricité et dispositif de stockage d'électricité
JP2017169389A (ja) * 2016-03-17 2017-09-21 トヨタ自動車株式会社 電池制御システム
JP2019041534A (ja) * 2017-08-28 2019-03-14 トヨタ自動車東日本株式会社 Ｄｃ／ｄｃコンバータ及び電力供給方法
CN110521080A (zh) * 2017-04-24 2019-11-29 罗伯特·博世有限公司 用于电蓄能***的电路装置和充电方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007046138A1 (fr) * 2005-10-19 2007-04-26 Limited Company Tm Dispositif de stockage de charge utilisant un condensateur et son procede de commande

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007046138A1 (fr) * 2005-10-19 2007-04-26 Limited Company Tm Dispositif de stockage de charge utilisant un condensateur et son procede de commande

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10193192B2 (en) 2012-10-11 2019-01-29 Renault S.A.S. Structure for modulating the voltage of a battery and the active equilibration thereof
FR2996965A1 (fr) * 2012-10-11 2014-04-18 Renault Sas Structure pour la modulation de tension d'une batterie et son equilibrage actif
WO2014057192A3 (fr) * 2012-10-11 2014-07-03 Renault S.A.S Structure pour la modulation de tension d'une batterie et son équilibrage actif
KR20150070202A (ko) * 2012-10-11 2015-06-24 르노 에스.아.에스. 배터리의 전압을 조정하기 위한 구조 및 그것의 능동적 평형
CN104756353A (zh) * 2012-10-11 2015-07-01 雷诺两合公司 用于将电池电压模块化的结构及其主动均衡
JP2015531586A (ja) * 2012-10-11 2015-11-02 ルノー エス．ア．エス． 電池の電圧を変調させるための構造、及びその能動的平衡化
KR102206532B1 (ko) * 2012-10-11 2021-01-22 르노 에스.아.에스. 배터리의 전압을 조정하기 위한 구조 및 그것의 능동적 평형
WO2014057192A2 (fr) * 2012-10-11 2014-04-17 Renault S.A.S Structure pour la modulation de tension d'une batterie et son équilibrage actif
EP2736145A1 (fr) * 2012-11-26 2014-05-28 Nxp B.V. Dispositifs à alimentation sans fil
US9601268B2 (en) 2012-11-26 2017-03-21 Nxp B.V. Wirelessly powered devices
JP6032516B2 (ja) * 2014-06-10 2016-11-30 株式会社Ｋａｇｒａ 蓄電素子の充電方法および蓄電装置
US10833523B2 (en) 2014-06-10 2020-11-10 Kagra Inc. Electricity storage element charging method and electricity storage device
WO2015189907A1 (fr) * 2014-06-10 2015-12-17 株式会社Ｋａｇｒａ Procédé de charge d'élément de stockage d'électricité et dispositif de stockage d'électricité
JP2017169389A (ja) * 2016-03-17 2017-09-21 トヨタ自動車株式会社 電池制御システム
CN110521080A (zh) * 2017-04-24 2019-11-29 罗伯特·博世有限公司 用于电蓄能***的电路装置和充电方法
CN110521080B (zh) * 2017-04-24 2023-08-08 罗伯特·博世有限公司 用于电蓄能***的电路装置和充电方法
JP2019041534A (ja) * 2017-08-28 2019-03-14 トヨタ自動車東日本株式会社 Ｄｃ／ｄｃコンバータ及び電力供給方法

Similar Documents

Publication Publication Date Title
JP4368924B2 (ja) キャパシタを用いた蓄電装置とその制御方法
CN110281810B (zh) 智能电池的直流充电
JP4977804B2 (ja) 蓄電装置の充電制御方法および放電制御方法
US10141551B2 (en) Battery system
US9270127B2 (en) Method and system for balancing electrical cells
JP5502282B2 (ja) 組電池の充電方法
WO2011132302A1 (fr) Procédé de commande de charge et procédé de commande de décharge pour dispositif accumulateur électrique
JP2012019685A (ja) 複数のバッテリセルを有するバッテリシステムの動作方法及び回路
CN112655131B (zh) 蓄电装置和充电方法
JP2013078242A (ja) 電源装置
JP2005151683A (ja) 電池パックの充電装置
JP2009247145A (ja) 電源システム
Hou et al. A battery power bank of serial battery power modules with buck-boost converters
JP2012034446A (ja) 蓄電装置及びエネルギバランス調整方法
EP3649719A1 (fr) Gestion de batterie
JP6214131B2 (ja) 組電池充電システムおよび組電池充電方法
JP2002281686A (ja) 蓄電電源の充電装置及び充電方法
WO2016129227A1 (fr) Dispositif de commande d'accumulateur et système d'accumulateur
KR101500709B1 (ko) 배터리 수명 향상이 가능한 에너지 저장 장치
JP2000023381A (ja) 組電池の充電制御方法及びその制御装置
WO2017150141A1 (fr) Système de commande d'alimentation électrique, procédé de commande d'alimentation électrique, et programme de commande d'alimentation électrique
JPH10313534A (ja) 太陽電池用電源装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10850243

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10850243

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP