WO2011086797A1 - Method of manufacturing substrate with built-in capacitor - Google Patents

Method of manufacturing substrate with built-in capacitor Download PDF

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Publication number
WO2011086797A1
WO2011086797A1 PCT/JP2010/071976 JP2010071976W WO2011086797A1 WO 2011086797 A1 WO2011086797 A1 WO 2011086797A1 JP 2010071976 W JP2010071976 W JP 2010071976W WO 2011086797 A1 WO2011086797 A1 WO 2011086797A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
electrode layer
sheet
substrate
capacitor element
Prior art date
Application number
PCT/JP2010/071976
Other languages
French (fr)
Japanese (ja)
Inventor
田中　直樹
江崎　賢一
一也 二木
野口　仁志
真吾 前田
Original Assignee
三洋電機株式会社
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Publication of WO2011086797A1 publication Critical patent/WO2011086797A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • H01G13/003—Apparatus or processes for encapsulating capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances

Definitions

  • the present invention relates to a method for manufacturing a capacitor built-in substrate in which a capacitor element is built in an insulating substrate.
  • capacitors are provided at a plurality of locations in a surface region (305) (upper surface in FIG. 20; hereinafter referred to as “upper surface”) on which a semiconductor element such as a CPU is mounted.
  • a ground terminal (306) and a power supply terminal (307) to which both electrode layers (301) and (302) of the element (300) are to be electrically connected are formed.
  • the capacitor element (300) is embedded in the insulating substrate (304) so that both electrode layers (301) and (302) are substantially parallel to the upper surface (305) of the insulating substrate (304).
  • the first electrode layer (301) and each ground terminal (306) are electrically connected to each other through conductive vias (308) and (309) formed in the insulating substrate (304), while the capacitor element
  • the second electrode layer (302) of (300) and each power supply terminal (307) are electrically connected to each other through a conductive via (310) formed in the insulating substrate (304).
  • the capacitor element (300) is mounted on one of the two insulating substrates constituting the insulating substrate (304), and then the other insulating substrate. Is laminated on one insulating substrate.
  • the capacitor element (300) mounted on the insulating base material has a small thickness and is in the form of a sheet.
  • Such a capacitor element (300) requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements (300) to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements (300) on the insulating base material becomes complicated.
  • an object of the present invention is to simplify the process of mounting a capacitor element on an insulating base material in the method of manufacturing a capacitor built-in substrate.
  • a method for manufacturing a capacitor-embedded substrate according to the present invention includes one or a plurality of capacitor elements having a dielectric layer interposed between a first electrode layer and a second electrode layer, and an insulating substrate.
  • a method of manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in an insulating substrate by embedding the capacitor element includes a sticking step, a peeling step, and a stacking step.
  • the capacitor element is applied to one or a plurality of predetermined regions in the surface of the sheet by using a sheet capable of attaching and peeling the capacitor element by applying an external action.
  • An element attachment sheet is prepared by attaching and attaching.
  • the element attachment sheet is placed at a predetermined position on one of the two insulating bases constituting the insulating substrate, and the capacitor element attached to the element attaching sheet is placed on the one side.
  • the capacitor elements are peeled off from the sheet and mounted on the one insulating substrate by superimposing them in a posture toward the insulating substrate and applying the external action to the element attachment sheet in that state.
  • the insulating substrate is formed by laminating the other insulating base material on the one insulating base material.
  • the capacitor element mounted on the insulating substrate has a small thickness dimension and is in the form of a sheet.
  • Such a capacitor element requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements on the insulating base material becomes complicated.
  • the capacitor element is mounted at a predetermined position on the insulating substrate using the element attachment sheet to which the capacitor element is attached. For this reason, it is not necessary to handle the capacitor elements individually, and the process of mounting the capacitor elements on the insulating substrate is simplified.
  • the capacitor element has the first electrode layer formed of a metal foil while the second electrode layer is formed of a metal thin film or a metal foil.
  • the capacitor element is attached to the sheet in a state where the first electrode layer is in surface contact with a predetermined region on the surface of the sheet.
  • the first electrode layer made of metal foil is not easily damaged even if it is peeled off after being attached to a sheet. Therefore, even if the capacitor element is peeled off from the sheet in the peeling step after the first electrode layer is stuck on the sheet in the sticking step as in the above specific configuration, the first electrode layer is hardly damaged. .
  • the first electrode layer of the capacitor element has a part of the surface on the second electrode layer side covered with the second electrode layer.
  • the process of mounting the capacitor element on the insulating base material can be simplified.
  • FIG. 1 is a sectional view showing a capacitor built-in substrate according to an embodiment of the present invention.
  • FIG. 2 is a plan view of the capacitor element built in the capacitor built-in substrate as viewed from the second electrode layer side.
  • FIG. 3 is a diagram showing impedance characteristics of the capacitor built-in substrate.
  • FIG. 4 is a perspective view for explaining a dielectric layer forming step of the method of manufacturing the capacitor element.
  • FIG. 5 is a perspective view for explaining an annealing process of the manufacturing method.
  • FIG. 6 is a perspective view for explaining a resist forming step of the manufacturing method.
  • FIG. 7 is a perspective view for explaining a plating step of the manufacturing method.
  • FIG. 8 is a plan view for explaining the state of the second sheet for element formation after execution of the plating step.
  • FIG. 9 is a plan view for explaining a resist stripping step of the manufacturing method.
  • FIG. 10 is a plan view for explaining a cutting step of the manufacturing method.
  • FIG. 11 is a perspective view for explaining a sticking step among the capacitor element mounting methods executed in the element mounting step of the method for manufacturing a capacitor built-in substrate.
  • FIG. 12 is a perspective view for explaining the first stage of the peeling process of the mounting method.
  • FIG. 13 is a perspective view for explaining the middle stage of the peeling process of the mounting method.
  • FIG. 14 is a perspective view for explaining the latter stage of the peeling process of the mounting method.
  • FIG. 15 is a perspective view for explaining a lamination process of the method for manufacturing a capacitor built-in substrate.
  • FIG. 16 is a plan view of the capacitor-embedded substrate according to the first modification of the present invention when the capacitor element built in the capacitor-embedded substrate is viewed from the second electrode layer side.
  • FIG. 17: is the top view which looked at the capacitor
  • FIG. 18 is a cross-sectional view showing a capacitor built-in substrate according to a third modification of the present invention.
  • FIG. 19 is a cross-sectional view showing a capacitor built-in substrate according to a fourth modification of the present invention.
  • FIG. 20 is a cross-sectional view showing a conventional capacitor built-in substrate.
  • FIG. 21 is a cross-sectional view showing a conventional capacitor mounting board.
  • FIG. 1 is a cross-sectional view showing a capacitor built-in substrate according to an embodiment of the present invention.
  • the capacitor-embedded substrate of this embodiment includes a capacitor element (1) having a dielectric layer (13) interposed between a first electrode layer (11) and a second electrode layer (12).
  • the capacitor element (1) is built in the insulating substrate (2) by embedding the capacitor element (1) in the insulating substrate (2).
  • the capacitor element (1) is embedded in the insulating substrate (2) in such a posture that the surfaces of the electrode layers (11), (12) are substantially parallel to the surface of the insulating substrate (2).
  • the insulating substrate (2) is formed from a material having flame retardancy, for example, a material of FR-4 (Flame Retardant Type 4).
  • FR-4 Flame Retardant Type 4
  • the material of FR-4 is a flame retardant material made of, for example, a composite material of glass fiber and epoxy resin.
  • the first electrode layer (11) of the capacitor element (1) is formed of a metal foil.
  • the metal foil is formed of a metal material that can form a foil and can be an electrode layer, such as copper (Cu), nickel (Ni), aluminum (Al), platinum (Pt), or the like.
  • the metal foil can be handled by itself, for example, can hold itself.
  • the thickness dimension of the metal foil is preferably 1 ⁇ m or more.
  • copper (Cu) is used as the metal material of the metal foil forming the first electrode layer (11).
  • the second electrode layer (12) of the capacitor element (1) is formed of a metal thin film.
  • the metal thin film is a metal film formed thinly on the surface of the base material such as the dielectric layer (13), and a thin film such as copper (Cu) can be formed and can be an electrode layer. It is formed from a metal material. Therefore, the metal thin film is difficult to handle by itself, and is handled integrally with the base material.
  • the thickness dimension of the metal thin film is preferably 20 ⁇ m or less.
  • copper (Cu) is used as the metal material of the metal thin film that forms the second electrode layer (12).
  • FIG. 2 is a plan view of the capacitor element (1) as seen from the second electrode layer (12) side.
  • the first electrode layer (11) of the capacitor element (1) has a surface (111) on the second electrode layer (12) side (upper surface in FIG. 1; hereinafter referred to as “upper surface”). Is covered with the second electrode layer (12).
  • the first electrode layer (11) has a substantially square shape
  • the second electrode layer (12) has a substantially square shape having a smaller area than the first electrode layer (11).
  • the second electrode layer (12) covers the central region of the upper surface (111) of the first electrode layer (11).
  • the dielectric layer (13) is a region (112) covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). ) And is not formed on the region (113) not covered by the second electrode layer (12).
  • the insulating substrate (2) is electrically connected to a region (113) of the upper surface (111) of the first electrode layer (11) that is not covered by the second electrode layer (12).
  • the connected first conductive via (31) and the surface (121) of the second electrode layer (12) on the opposite side of the first electrode layer (11) (upper surface in FIG. 1; hereinafter referred to as “upper surface”) ) are electrically connected to the second conductive via (32).
  • the conductive vias 31 and 32 are formed on the surface region 21 on the second electrode layer 12 side of the capacitor element 1 on the surface of the insulating substrate 2 (the upper surface in FIG. 1).
  • both conductive vias (31) and (32) are exposed in the surface region (21).
  • a conductive material such as copper (Cu) is used to form both conductive vias (31) and (32).
  • the first electrode layer is formed at 12 locations on the upper surface (111) of the first electrode layer (11) on the region (113) not covered by the second electrode layer (12).
  • Conductive vias (31) are formed, and second conductive vias (32) are formed at four locations on the upper surface (121) of the second electrode layer (12).
  • These first conductive vias (31) (31) and second conductive vias (32) to (32) are arranged in a 4 ⁇ 4 matrix on the paper surface of FIG.
  • a ground terminal (41) and a power supply terminal (42) are formed on the upper surface (21) of the insulating substrate (2).
  • the tip of each first conductive via (31) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected to the ground terminal (41), and the power terminal (42)
  • the tip of each second conductive via (32) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected. Therefore, an electrical path is formed between the ground terminal (41) and the power supply terminal (42) via the capacitor element (1).
  • each second conductive via (32) may be connected to the ground terminal (41), and the tip of each first conductive via (31) may be connected to the power supply terminal (42).
  • each first conductive via (31) extends toward the upper surface (21) of the insulating substrate (2) without being in electrical contact with the second electrode layer (12), and is formed on the upper surface (21).
  • the front end portion of the first conductive via (31) can be exposed. Therefore, the conductive via to be electrically connected to the conventional capacitor-embedded substrate, specifically the first electrode layer (11), is the first electrode of the capacitor element (1) in the surface of the insulating substrate (2).
  • this embodiment Compared with the capacitor built-in substrate (see FIG. 20) routed to the surface region (22) on the layer (11) side (the lower surface in FIG. 1; hereinafter referred to as the “lower surface”), this embodiment has a built-in capacitor.
  • the substrate FIG. 1
  • the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced. This improves the impedance characteristics of the capacitor built-in substrate in the high frequency region.
  • FIG. 3 is a graph (91) showing the impedance characteristics of the substrate with a built-in capacitor of the present embodiment obtained by simulation.
  • the impedance characteristic of the conventional capacitor mounting board as shown in FIG. 21 is also shown by a graph (92).
  • a chip-like capacitor element (316) is mounted on the lower surface (311) of the insulating substrate (304).
  • an electrical path is formed between the power supply terminal (306) and the ground terminal (307) formed on the upper surface (305) of the insulating substrate (304) via the capacitor element (316). Yes.
  • FIG. 4 is a perspective view for explaining a dielectric layer forming step of the method of manufacturing the capacitor element (1).
  • a film forming apparatus (71) is used on the surface (501) of the metal foil (50) to be the first electrode layer (11) of the capacitor element (1).
  • the dielectric layer (13) of the capacitor element (1) is formed.
  • a dielectric layer (13) having a square shape is formed in a 4 ⁇ 4 matrix on the surface (501) of one metal foil (50) made of copper (Cu). .
  • the first sheet for element formation (61) in which a plurality of dielectric layers (13) are formed on the surface (501) of the metal foil (50) is formed.
  • FIG. 5 is a perspective view for explaining the annealing step of the method for manufacturing the capacitor element (1).
  • An annealing process is a process performed after execution of a dielectric material layer formation process. As shown in FIG. 5, in the annealing step, each dielectric layer (13) is irradiated with a laser to thereby anneal the dielectric layer (13). Thereby, the characteristics of the dielectric layer (13) can be further improved.
  • the annealing step is not an essential step for manufacturing the capacitor element (1) according to the present invention, and the annealing step may be performed only when the characteristics of the dielectric layer are further improved.
  • annealing may be performed by a method such as microwave heating, heating in the atmosphere or nitrogen atmosphere (using a furnace or the like), or the like.
  • FIG. 6 is a perspective view for explaining a resist forming step of the method of manufacturing the capacitor element (1).
  • the resist formation step is a step that is executed after the annealing step.
  • a masking process is performed on the first element forming sheet (61).
  • a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next.
  • the dielectric layer 13
  • the resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.
  • FIG. 7 is a perspective view for explaining a plating step of the method of manufacturing the capacitor element (1).
  • a plating process is a process performed after execution of a resist formation process.
  • the element forming second sheet (62) is subjected to electroless plating by immersing the element forming second sheet (62) in a plating solution (72).
  • a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) is formed on each dielectric layer (13).
  • copper (Cu) is used as the metal material for the electroless plating process.
  • a method such as sputtering, vapor deposition, screen printing, and ink jet can be used in addition to plating.
  • FIG. 9 is a plan view for explaining the resist stripping step of the method of manufacturing the capacitor element (1).
  • the resist stripping process is a process executed after the plating process.
  • the resist (52) (see FIG. 8) formed on the surface (501) of the metal foil (50) is stripped and the surface (501) of the metal foil (50) is removed. )
  • the third sheet for element formation (63) is formed.
  • a chemical method can be used for removing the resist (52).
  • FIG. 10 is a plan view for explaining a cutting step of the method of manufacturing the capacitor element (1).
  • a cutting process is a process performed after execution of a resist peeling process.
  • the third sheet for element formation (63) is cut.
  • the first electrode layer (11) is formed from the metal foil (50) by cutting the metal foil (50) along the broken line shown in FIG.
  • the metal foil (50) is cut so that a part of the surface of the formed first electrode layer (11) is covered with the second electrode layer (12). Specifically, in the metal foil (50), the central region of the surface of the first electrode layer (11) is covered with the second electrode layer (12), and the shape of the first electrode layer (11) is substantially square. It is cut like this.
  • the capacitor element (1) is completed by carrying out the manufacturing method described above, and the capacitor element (1) manufactured as described above has a small thickness and a sheet shape.
  • the capacitor element (1) is placed on one insulating base material (20) of the two insulating base materials (20) and (20) (see FIG. 15) constituting the insulating substrate (2).
  • the element mounting process to be mounted is executed.
  • FIG. 11 is a perspective view for explaining a sticking process of the mounting method of the capacitor element (1).
  • the carrier sheet (80) capable of adhering and peeling the capacitor element (1) by applying an external action such as heat and pressure is used.
  • the element attachment sheet (8) is produced by attaching and attaching the capacitor element (1) to one or a plurality of predetermined regions (81) of the surface of the sheet (80).
  • the capacitor element (1) is adhered to the carrier sheet (80) in a state where the first electrode layer (11) is in surface contact with a predetermined region (81) on the surface of the carrier sheet (80).
  • the predetermined area (81) is set corresponding to a predetermined position on the insulating base material (20) on which the capacitor element (1) is to be mounted.
  • FIGS. 12 to 14 are perspective views for explaining the peeling process of the mounting method of the capacitor element (1).
  • a peeling process is a process performed after execution of a sticking process.
  • the pair of prepregs (201) (201) and the core material (202) constituting the insulating base material (20) are combined with the pair of prepregs (201) ( 201) and sandwiching the core material (202).
  • the element attachment sheet (8) is superposed at a predetermined position on the prepreg (201) with the capacitor element (1) attached to the element attachment sheet (8) in a posture toward the prepreg (201). .
  • the laminated body (82) which consists of a pair of prepreg (201) (201), core material (202), and element attachment sheet (8) is formed.
  • the pair of prepregs (201) (201) and the core material (202) are thermocompression bonded.
  • the capacitor substrate (1) attached to the element attachment sheet (8) is thermocompression-bonded to the surface of the prepreg (201) on which the element attachment sheet (8) overlaps. To do. At this time, since heat is applied to the element attachment sheet (8), the capacitor element (1) is easily peeled off from the carrier sheet (80).
  • the capacitor element (1) is peeled from the carrier sheet (80) by peeling the carrier sheet (80) from the insulating base (20) in the latter stage of the peeling step. As a result, the capacitor element (1) is mounted at a predetermined position on the insulating substrate (20).
  • the carrier sheet (80) A non-peelable sheet such as a PET (polyethylene terephthalate) sheet having adhesiveness can be used.
  • FIG. 15 is a perspective view for explaining a stacking process of a method for producing a capacitor built-in substrate.
  • a lamination process is a process performed after execution of an element mounting process.
  • another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20).
  • the insulating substrate (2) is formed by the two insulating base materials (20) laminated.
  • a first conductive via (31) and a second conductive via (32) are formed on the insulating substrate (2), and a ground terminal is formed on the upper surface (21) of the insulating substrate (2). (41) and a power supply terminal (42) are formed. As a result, the capacitor built-in substrate is completed.
  • the capacitor element (1) mounted on the insulating base (20) has a small thickness and is in the form of a sheet.
  • Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the element mounting process for mounting the capacitor element (1) on the insulating base material (20) is complicated. Become.
  • the capacitor element (1) is mounted at a predetermined position on the insulating base (20) using the element attachment sheet (8) to which the capacitor element (1) is attached. For this reason, it is not necessary to handle the capacitor elements (1) individually, and the element mounting process for mounting the capacitor elements (1) on the insulating substrate (20) is simplified.
  • the first conductive layer (11) of the capacitor element (1) made of metal foil is hardly damaged even when it is peeled off after being stuck on the carrier sheet (80). Therefore, like the mounting method of the capacitor element (1), after the first electrode layer (11) is attached to the carrier sheet (80) in the attaching step, the capacitor element (1) is attached to the carrier sheet in the releasing step. Even when peeled from (80), the first electrode layer (11) is hardly damaged.
  • substrate with a built-in capacitor exists in the range of 5 micrometers or more and 100 micrometers or less. This is because when the thickness is smaller than 5 ⁇ m, it is difficult to handle the capacitor element (1), and problems such as an increase in resistance occur. Further, when the thickness dimension is larger than 100 ⁇ m, the thickness of the capacitor element (1) affects the surface of the insulating base material (20), so that irregularities are formed on the surface of the insulating base material (20). This is because it becomes difficult to laminate another insulating base material (20) thereon.
  • FIG. 16 is a plan view of the capacitor built-in substrate according to the first modified example of the present invention when the capacitor element (1) built in the capacitor built-in substrate is viewed from the second electrode layer (12) side.
  • the first conductive via (31) is located on the upper surface (111) of the first electrode layer (11) over the region (113) not covered by the second electrode layer (12).
  • the second conductive vias (32) are formed at 25 locations on the upper surface (121) of the second electrode layer (12), and the first conductive vias (31) to (31) are formed.
  • the second conductive vias (32) to (32) may be arranged in a 7 ⁇ 7 matrix on the paper surface of FIG.
  • FIG. 17 is a plan view of the capacitor-embedded substrate according to the second modification of the present invention when the capacitor element (1) built in the capacitor-embedded substrate is viewed from the second electrode layer (12) side.
  • An electrode layer (12) may be provided, and the second electrode layers (12) provided at the four locations may be arranged apart from each other.
  • the conductive vias arranged in the first row, the fourth row, and the seventh row, the first column A total of 33 conductive vias arranged in the row and the seventh row are first conductive vias (31), and the other 16 conductive vias are second conductive vias (32).
  • the 16 second conductive vias (32) are connected to the second electrode layers (12) provided at the four locations, four by four.
  • the number of the first conductive vias (31) can be increased.
  • the first conductive via (31) has a gap between the second conductive via (32). There are many things with the smallest distance. Therefore, the inductance generated in the capacitor built-in substrate can be further reduced.
  • FIG. 18 is a cross-sectional view showing a capacitor built-in substrate according to a third modification of the present invention.
  • the surface of the insulating substrate (2) opposite to the second electrode layer (12) of the first electrode layer (11) of the capacitor element (1) (114) A third conductive via (33) electrically connected to the lower surface (the lower surface in FIG. 1 and FIG. 18) is formed, and the third conductive via (33) is formed on the lower surface of the insulating substrate (2) ( 22) and the tip of the third conductive via (33) may be exposed on the lower surface (22).
  • FIG. 19 is a cross-sectional view showing a capacitor built-in substrate according to a fourth modification of the present invention.
  • the dielectric layer (13) is formed on the upper surface (111) of the first electrode layer (11) on the region (112) covered with the second electrode layer (12). In addition, it may be formed on a region (113) not covered with the second electrode layer (12).
  • the first conductive via (31) extends through the dielectric layer (13) toward the upper surface (21) of the insulating substrate (2).
  • the second electrode layer (12) of the capacitor element (1) may be formed of a metal foil.
  • the shape of the first electrode layer (11) and the second electrode layer (12) of the capacitor element (1) is not limited to a substantially square shape, but the first electrode layer (11) and the second electrode layer (12). ) Various shapes can be used.
  • the first electrode layer (11) of the capacitor element (1) may be formed integrally with a power supply pattern or a ground pattern formed in the insulating substrate (2).
  • the first conductive via (31) may be formed only at one location in the insulating substrate (2).
  • the second conductive via (32) may be formed only at one place in the insulating substrate (2).
  • Capacitor element (11) First electrode layer (12) Second electrode layer (13) Dielectric layer (2) Insulating substrate (20) Insulating substrate (31) First conductive via (32) Second conductive via (33) Third conductive via (41) Ground terminal (42) Power supply terminal (8) Element attachment sheet (80) Carrier sheet (81) Predetermined area

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Abstract

Disclosed is a method of manufacturing a substrate with a built-in capacitor, wherein a process for mounting capacitor elements upon an insulating base material is simplified. The method of manufacturing a substrate with a built-in capacitor is provided with a pasting process, a peeling-off process, and a laminating process. In the pasting process, an element attached sheet (8) is created, using a sheet (80) that can have capacitor elements (1) pasted on or peeled off by applying external action thereto, and by pasting on and attaching the capacitor element (1) onto one or a plurality of prescribed areas within the surface of the sheet (80). In the peeling-off process, the capacitor elements (1) are peeled off from the sheet (8) and mounted onto the insulating base material (20), by superimposing the element attached sheet (8) onto a prescribed position of the insulating base material (20), with the element attached sheet (8) taking a posture of having the capacitor elements (1) attached thereto facing the insulating base material (20), and applying an external action onto the element attached sheet (8) at that state to peel off the capacitor elements (1). In the laminating process, an insulating substrate is formed by laminating another insulating base material (20) upon the insulating base material (20).

Description

コンデンサ内蔵基板の製造方法Manufacturing method of substrate with built-in capacitor
　本発明は、コンデンサ素子が絶縁基板に内蔵されたコンデンサ内蔵基板の製造方法に関する。 The present invention relates to a method for manufacturing a capacitor built-in substrate in which a capacitor element is built in an insulating substrate.
　従来から、回路基板を小型化及び薄型化するべく、絶縁基板内に電子部品を埋設することにより絶縁基板に電子部品が内蔵された電子部品内蔵基板が提案されている。特に、本願に関連する技術として、図２０に示す様に、絶縁基板(304)に、第１電極層(301)と第２電極層(302)との間に誘電体層(303)が介在したコンデンサ素子(300)を埋設したコンデンサ内蔵基板が提案されている（例えば、特許文献１参照）。 2. Description of the Related Art Conventionally, in order to reduce the size and thickness of a circuit board, an electronic component built-in board in which an electronic component is embedded in an insulating substrate by embedding the electronic component in the insulating substrate has been proposed. In particular, as a technique related to the present application, as shown in FIG. 20, a dielectric layer (303) is interposed between a first electrode layer (301) and a second electrode layer (302) on an insulating substrate (304). A capacitor built-in substrate in which the capacitor element (300) is embedded has been proposed (see, for example, Patent Document 1).
　具体的には、絶縁基板(304)の表面の内、ＣＰＵ等の半導体素子が搭載される表面領域(305)（図２０の紙面において上面。以下、「上面」という）の複数箇所に、コンデンサ素子(300)の両電極層(301)(302)がそれぞれ電気的に接続されるべきグランド端子(306)及び電源端子(307)が形成されている。そして、コンデンサ素子(300)は、その両電極層(301)(302)が絶縁基板(304)の上面(305)に略平行となる姿勢で絶縁基板(304)内に埋設され、コンデンサ素子(300)の第１電極層(301)と各グランド端子(306)とが、絶縁基板(304)内に形成された導電ビア(308)(309)を通じて互いに電気的に接続される一方、コンデンサ素子(300)の第２電極層(302)と各電源端子(307)とが、絶縁基板(304)内に形成された導電ビア(310)を通じて互いに電気的に接続されている。 Specifically, among the surfaces of the insulating substrate (304), capacitors are provided at a plurality of locations in a surface region (305) (upper surface in FIG. 20; hereinafter referred to as “upper surface”) on which a semiconductor element such as a CPU is mounted. A ground terminal (306) and a power supply terminal (307) to which both electrode layers (301) and (302) of the element (300) are to be electrically connected are formed. The capacitor element (300) is embedded in the insulating substrate (304) so that both electrode layers (301) and (302) are substantially parallel to the upper surface (305) of the insulating substrate (304). 300) the first electrode layer (301) and each ground terminal (306) are electrically connected to each other through conductive vias (308) and (309) formed in the insulating substrate (304), while the capacitor element The second electrode layer (302) of (300) and each power supply terminal (307) are electrically connected to each other through a conductive via (310) formed in the insulating substrate (304).
　上記コンデンサ内蔵基板を作製する工程では、絶縁基板(304)を構成する２枚の絶縁基材の内、一方の絶縁基材上にコンデンサ素子(300)を搭載し、その後、他方の絶縁基材を一方の絶縁基材に積層する。 In the process of manufacturing the capacitor built-in substrate, the capacitor element (300) is mounted on one of the two insulating substrates constituting the insulating substrate (304), and then the other insulating substrate. Is laminated on one insulating substrate.
特開２００４－１０３９６７号公報JP 2004-103967 A
　しかしながら、絶縁基材上に搭載する上記コンデンサ素子(300)は、その厚さ寸法が小さくてシート状のものである。この様なコンデンサ素子(300)は、これを絶縁基材上に搭載するときに高いハンドリング性能を必要とする。このため、絶縁基材上に搭載せんとするコンデンサ素子(300)を個々にハンドリングしたのでは、絶縁基材上にコンデンサ素子(300)を搭載する工程が煩雑化することになる。 However, the capacitor element (300) mounted on the insulating base material has a small thickness and is in the form of a sheet. Such a capacitor element (300) requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements (300) to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements (300) on the insulating base material becomes complicated.
　そこで本発明の目的は、コンデンサ内蔵基板の製造方法において、絶縁基材上にコンデンサ素子を搭載する工程を簡略化することである。 Therefore, an object of the present invention is to simplify the process of mounting a capacitor element on an insulating base material in the method of manufacturing a capacitor built-in substrate.
　本発明に係るコンデンサ内蔵基板の製造方法は、第１電極層と第２電極層との間に誘電体層が介在した１又複数のコンデンサ素子と、絶縁基板とを具え、該絶縁基板内にコンデンサ素子を埋設することにより絶縁基板にコンデンサ素子が内蔵されたコンデンサ内蔵基板を製造する方法であって、貼着工程と、剥離工程と、積層工程とを有する。ここで、貼着工程では、外的な作用を与えることにより前記コンデンサ素子の貼着と剥離とが可能なシートを用いて、該シートの表面の内、１又は複数の所定領域に前記コンデンサ素子を貼着して添付することにより素子添付シートを作製する。剥離工程では、前記絶縁基板を構成する２つの絶縁基材の内、一方の絶縁基材上の所定位置に、前記素子添付シートを、該素子添付シートに添付されているコンデンサ素子を前記一方の絶縁基材に向けた姿勢で重ね合わせ、その状態で前記素子添付シートに前記外的な作用を与えることにより、前記コンデンサ素子をシートから剥離して前記一方の絶縁基材上に搭載する。積層工程では、前記一方の絶縁基材上に他方の絶縁基材を積層することにより前記絶縁基板を形成する。 A method for manufacturing a capacitor-embedded substrate according to the present invention includes one or a plurality of capacitor elements having a dielectric layer interposed between a first electrode layer and a second electrode layer, and an insulating substrate. A method of manufacturing a capacitor-embedded substrate in which a capacitor element is embedded in an insulating substrate by embedding the capacitor element, and includes a sticking step, a peeling step, and a stacking step. Here, in the attaching step, the capacitor element is applied to one or a plurality of predetermined regions in the surface of the sheet by using a sheet capable of attaching and peeling the capacitor element by applying an external action. An element attachment sheet is prepared by attaching and attaching. In the peeling step, the element attachment sheet is placed at a predetermined position on one of the two insulating bases constituting the insulating substrate, and the capacitor element attached to the element attaching sheet is placed on the one side. The capacitor elements are peeled off from the sheet and mounted on the one insulating substrate by superimposing them in a posture toward the insulating substrate and applying the external action to the element attachment sheet in that state. In the laminating step, the insulating substrate is formed by laminating the other insulating base material on the one insulating base material.
　上記製造方法において絶縁基材上に搭載するコンデンサ素子は、その厚さ寸法が小さくてシート状のものである。この様なコンデンサ素子は、これを絶縁基材上に搭載するときに高いハンドリング性能を必要とする。このため、絶縁基材上に搭載せんとするコンデンサ素子を個々にハンドリングしたのでは、絶縁基材上にコンデンサ素子を搭載する工程が煩雑になる。 In the above manufacturing method, the capacitor element mounted on the insulating substrate has a small thickness dimension and is in the form of a sheet. Such a capacitor element requires high handling performance when it is mounted on an insulating substrate. For this reason, if the capacitor elements to be mounted on the insulating base material are individually handled, the process of mounting the capacitor elements on the insulating base material becomes complicated.
　上記製造方法によれば、該コンデンサ素子が添付された素子添付シートを用いて絶縁基材上の所定位置にコンデンサ素子が搭載される。このため、コンデンサ素子を個々にハンドリングする必要がなく、絶縁基材上にコンデンサ素子を搭載する工程が簡略化されることになる。 According to the above manufacturing method, the capacitor element is mounted at a predetermined position on the insulating substrate using the element attachment sheet to which the capacitor element is attached. For this reason, it is not necessary to handle the capacitor elements individually, and the process of mounting the capacitor elements on the insulating substrate is simplified.
　上記製造方法の具体的構成において、前記コンデンサ素子は、前記第１電極層が金属箔により形成される一方、前記第２電極層が金属薄膜又は金属箔により形成されており、前記貼着工程では、前記コンデンサ素子を、その前記第１電極層を前記シートの表面の所定領域に面接触させた状態で該シートに貼着する。 In the specific configuration of the manufacturing method, the capacitor element has the first electrode layer formed of a metal foil while the second electrode layer is formed of a metal thin film or a metal foil. The capacitor element is attached to the sheet in a state where the first electrode layer is in surface contact with a predetermined region on the surface of the sheet.
　金属箔からなる第１電極層は、それをシートに貼着した後で剥離した場合でも損傷し難い。従って、上記具体的構成の如く、貼着工程にて第１電極層をシートに貼着した後、剥離工程にてコンデンサ素子をシートから剥離した場合でも、第１電極層には損傷が生じ難い。 The first electrode layer made of metal foil is not easily damaged even if it is peeled off after being attached to a sheet. Therefore, even if the capacitor element is peeled off from the sheet in the peeling step after the first electrode layer is stuck on the sheet in the sticking step as in the above specific configuration, the first electrode layer is hardly damaged. .
　上記製造方法の他の具体的構成において、前記コンデンサ素子の第１電極層は、第２電極層側の表面の一部が該第２電極層によって覆われている。 In another specific configuration of the above manufacturing method, the first electrode layer of the capacitor element has a part of the surface on the second electrode layer side covered with the second electrode layer.
　本発明に係るコンデンサ内蔵基板の製造方法によれば、絶縁基材上にコンデンサ素子を搭載する工程を簡略化することが出来る。 According to the method of manufacturing a capacitor built-in substrate according to the present invention, the process of mounting the capacitor element on the insulating base material can be simplified.
図１は、本発明の一実施形態に係るコンデンサ内蔵基板を示す断面図である。FIG. 1 is a sectional view showing a capacitor built-in substrate according to an embodiment of the present invention. 図２は、該コンデンサ内蔵基板に内蔵されているコンデンサ素子を第２電極層側から見た平面図である。FIG. 2 is a plan view of the capacitor element built in the capacitor built-in substrate as viewed from the second electrode layer side. 図３は、該コンデンサ内蔵基板のインピーダンス特性を示す図である。FIG. 3 is a diagram showing impedance characteristics of the capacitor built-in substrate. 図４は、上記コンデンサ素子の製造方法の誘電体層形成工程を説明する斜視図である。FIG. 4 is a perspective view for explaining a dielectric layer forming step of the method of manufacturing the capacitor element. 図５は、該製造方法のアニール工程を説明する斜視図である。FIG. 5 is a perspective view for explaining an annealing process of the manufacturing method. 図６は、該製造方法のレジスト形成工程を説明する斜視図である。FIG. 6 is a perspective view for explaining a resist forming step of the manufacturing method. 図７は、該製造方法のメッキ工程を説明する斜視図である。FIG. 7 is a perspective view for explaining a plating step of the manufacturing method. 図８は、該メッキ工程の実行後の素子形成用第２シートの状態を説明する平面図である。FIG. 8 is a plan view for explaining the state of the second sheet for element formation after execution of the plating step. 図９は、該製造方法のレジスト剥離工程を説明する平面図である。FIG. 9 is a plan view for explaining a resist stripping step of the manufacturing method. 図１０は、該製造方法の切断工程を説明する平面図である。FIG. 10 is a plan view for explaining a cutting step of the manufacturing method. 図１１は、上記コンデンサ内蔵基板の製造方法の素子搭載工程で実行されるコンデンサ素子の搭載方法の内、貼着工程を説明する斜視図である。FIG. 11 is a perspective view for explaining a sticking step among the capacitor element mounting methods executed in the element mounting step of the method for manufacturing a capacitor built-in substrate. 図１２は、該搭載方法の剥離工程の前段を説明する斜視図である。FIG. 12 is a perspective view for explaining the first stage of the peeling process of the mounting method. 図１３は、該搭載方法の剥離工程の中段を説明する斜視図である。FIG. 13 is a perspective view for explaining the middle stage of the peeling process of the mounting method. 図１４は、該搭載方法の剥離工程の後段を説明する斜視図である。FIG. 14 is a perspective view for explaining the latter stage of the peeling process of the mounting method. 図１５は、上記コンデンサ内蔵基板の製造方法の積層工程を説明する斜視図である。FIG. 15 is a perspective view for explaining a lamination process of the method for manufacturing a capacitor built-in substrate. 図１６は、本発明の第１変形例に係るコンデンサ内蔵基板について、該コンデンサ内蔵基板に内蔵されているコンデンサ素子を第２電極層側から見た平面図である。FIG. 16 is a plan view of the capacitor-embedded substrate according to the first modification of the present invention when the capacitor element built in the capacitor-embedded substrate is viewed from the second electrode layer side. 図１７は、本発明の第２変形例に係るコンデンサ内蔵基板について、該コンデンサ内蔵基板に内蔵されているコンデンサ素子を第２電極層側から見た平面図である。FIG. 17: is the top view which looked at the capacitor | condenser element built in this capacitor | condenser board | substrate from the 2nd electrode layer side about the capacitor | condenser board | substrate concerning the 2nd modification of this invention. 図１８は、本発明の第３変形例に係るコンデンサ内蔵基板を示す断面図である。FIG. 18 is a cross-sectional view showing a capacitor built-in substrate according to a third modification of the present invention. 図１９は、本発明の第４変形例に係るコンデンサ内蔵基板を示す断面図である。FIG. 19 is a cross-sectional view showing a capacitor built-in substrate according to a fourth modification of the present invention. 図２０は、従来のコンデンサ内蔵基板を示した断面図である。FIG. 20 is a cross-sectional view showing a conventional capacitor built-in substrate. 図２１は、従来のコンデンサ搭載基板を示した断面図である。FIG. 21 is a cross-sectional view showing a conventional capacitor mounting board.
　以下、本発明の実施の形態につき、図面に沿って具体的に説明する。 Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
　図１は、本発明の一実施形態に係るコンデンサ内蔵基板を示す断面図である。図１に示す様に、本実施形態のコンデンサ内蔵基板は、第１電極層(11)と第２電極層(12)との間に誘電体層(13)が介在したコンデンサ素子(１)と、絶縁基板(２)とを具え、該絶縁基板(２)内にコンデンサ素子(１)を埋設することにより絶縁基板(２)にコンデンサ素子(１)が内蔵されている。ここで、コンデンサ素子(１)は、その両電極層(11)(12)の表面が絶縁基板(２)の表面と略平行となる姿勢で、絶縁基板(２)内に埋設されている。 FIG. 1 is a cross-sectional view showing a capacitor built-in substrate according to an embodiment of the present invention. As shown in FIG. 1, the capacitor-embedded substrate of this embodiment includes a capacitor element (1) having a dielectric layer (13) interposed between a first electrode layer (11) and a second electrode layer (12). The capacitor element (1) is built in the insulating substrate (2) by embedding the capacitor element (1) in the insulating substrate (2). Here, the capacitor element (1) is embedded in the insulating substrate (2) in such a posture that the surfaces of the electrode layers (11), (12) are substantially parallel to the surface of the insulating substrate (2).
　絶縁基板(２)は、難燃性を有する材料、例えばＦＲ－４（Flame　Retardant　Type　4）の材料から形成されている。ここで、ＦＲ－４の材料は、例えばガラス繊維とエポキシ樹脂の複合材料からなる難燃性の材料である。 The insulating substrate (2) is formed from a material having flame retardancy, for example, a material of FR-4 (Flame Retardant Type 4). Here, the material of FR-4 is a flame retardant material made of, for example, a composite material of glass fiber and epoxy resin.
　コンデンサ素子(１)の第１電極層(11)は、金属箔により形成されている。ここで、金属箔は、銅（Ｃｕ）、ニッケル（Ｎｉ）、アルミニウム（Ａｌ）、白金（Ｐｔ）等、箔を形成することが可能であって且つ電極層となり得る金属材料から形成されている。又、金属箔は、それ単独での取り扱いが可能であり、例えばそれ自体を保持することが可能である。金属箔の厚さ寸法は１μｍ以上であることが好ましい。尚、本実施形態においては、第１電極層(11)を形成する金属箔の金属材料として銅（Ｃｕ）が用いられている。 The first electrode layer (11) of the capacitor element (1) is formed of a metal foil. Here, the metal foil is formed of a metal material that can form a foil and can be an electrode layer, such as copper (Cu), nickel (Ni), aluminum (Al), platinum (Pt), or the like. . Further, the metal foil can be handled by itself, for example, can hold itself. The thickness dimension of the metal foil is preferably 1 μm or more. In the present embodiment, copper (Cu) is used as the metal material of the metal foil forming the first electrode layer (11).
　一方、コンデンサ素子(１)の第２電極層(12)は、金属薄膜により形成されている。ここで、金属薄膜は、誘電体層(13)等の基材の表面に薄く形成された金属膜であり、銅（Ｃｕ）等、薄膜を形成することが可能であって且つ電極層となり得る金属材料から形成されている。従って、金属薄膜は、それ単独での取り扱いが困難であり、基材と一体で取り扱われる。金属薄膜の厚さ寸法は２０μｍ以下であることが好ましい。尚、本実施形態においては、第２電極層(12)を形成する金属薄膜の金属材料として銅（Ｃｕ）が用いられている。 On the other hand, the second electrode layer (12) of the capacitor element (1) is formed of a metal thin film. Here, the metal thin film is a metal film formed thinly on the surface of the base material such as the dielectric layer (13), and a thin film such as copper (Cu) can be formed and can be an electrode layer. It is formed from a metal material. Therefore, the metal thin film is difficult to handle by itself, and is handled integrally with the base material. The thickness dimension of the metal thin film is preferably 20 μm or less. In the present embodiment, copper (Cu) is used as the metal material of the metal thin film that forms the second electrode layer (12).
　図２は、コンデンサ素子(１)を第２電極層(12)側から見た平面図である。図２に示す様に、コンデンサ素子(１)の第１電極層(11)は、第２電極層(12)側の表面(111)（図１の紙面において上面。以下、「上面」という）の一部が該第２電極層(12)によって覆われている。具体的には、第１電極層(11)は略正方形の形状を有する一方、第２電極層(12)は、第１電極層(11)よりも面積の小さい略正方形の形状を有しており、第２電極層(12)は、第１電極層(11)の上面(111)の中央領域を覆っている。 FIG. 2 is a plan view of the capacitor element (1) as seen from the second electrode layer (12) side. As shown in FIG. 2, the first electrode layer (11) of the capacitor element (1) has a surface (111) on the second electrode layer (12) side (upper surface in FIG. 1; hereinafter referred to as “upper surface”). Is covered with the second electrode layer (12). Specifically, the first electrode layer (11) has a substantially square shape, while the second electrode layer (12) has a substantially square shape having a smaller area than the first electrode layer (11). The second electrode layer (12) covers the central region of the upper surface (111) of the first electrode layer (11).
　図１に示す様に本実施形態においては、誘電体層(13)は、第１電極層(11)の上面(111)の内、第２電極層(12)によって覆われている領域(112)上に形成され、第２電極層(12)によって覆われていない領域(113)上には形成されていない。 As shown in FIG. 1, in this embodiment, the dielectric layer (13) is a region (112) covered by the second electrode layer (12) in the upper surface (111) of the first electrode layer (11). ) And is not formed on the region (113) not covered by the second electrode layer (12).
　図１に示す様に、絶縁基板(２)には、第１電極層(11)の上面(111)の内、第２電極層(12)によって覆われていない領域(113)に電気的に接続された第１導電ビア(31)と、第２電極層(12)の第１電極層(11)とは反対側の表面(121)（図１の紙面において上面。以下、「上面」という）に電気的に接続された第２導電ビア(32)とが形成されている。又、両導電ビア(31)(32)は、絶縁基板(２)の表面の内、コンデンサ素子(１)の第２電極層(12)側の表面領域(21)（図１の紙面において上面。以下、「上面」という）に向けて延び、該表面領域(21)に両導電ビア(31)(32)の先端部が露出している。ここで、両導電ビア(31)(32)の形成には、銅（Ｃｕ）等の導電材料が用いられている。 As shown in FIG. 1, the insulating substrate (2) is electrically connected to a region (113) of the upper surface (111) of the first electrode layer (11) that is not covered by the second electrode layer (12). The connected first conductive via (31) and the surface (121) of the second electrode layer (12) on the opposite side of the first electrode layer (11) (upper surface in FIG. 1; hereinafter referred to as “upper surface”) ) Are electrically connected to the second conductive via (32). The conductive vias 31 and 32 are formed on the surface region 21 on the second electrode layer 12 side of the capacitor element 1 on the surface of the insulating substrate 2 (the upper surface in FIG. 1). (Hereinafter referred to as “upper surface”), and the front end portions of both conductive vias (31) and (32) are exposed in the surface region (21). Here, a conductive material such as copper (Cu) is used to form both conductive vias (31) and (32).
　図２に示す様に本実施形態においては、第１電極層(11)の上面(111)の内、第２電極層(12)によって覆われていない領域(113)上の１２箇所に第１導電ビア(31)が形成されると共に、第２電極層(12)の上面(121)上の４箇所に第２導電ビア(32)が形成されており、これらの第１導電ビア(31)～(31)と第２導電ビア(32)～(32)が、図２の紙面において４×４のマトリクス状に配列されている。 As shown in FIG. 2, in the present embodiment, the first electrode layer is formed at 12 locations on the upper surface (111) of the first electrode layer (11) on the region (113) not covered by the second electrode layer (12). Conductive vias (31) are formed, and second conductive vias (32) are formed at four locations on the upper surface (121) of the second electrode layer (12). These first conductive vias (31) (31) and second conductive vias (32) to (32) are arranged in a 4 × 4 matrix on the paper surface of FIG.
　図１に示す様に、絶縁基板(２)の上面(21)には、グランド端子(41)と電源端子(42)とが形成されている。ここで、グランド端子(41)には、絶縁基板(２)の上面(21)に露出した各第１導電ビア(31)の先端部が電気的に接続され、電源端子(42)には、絶縁基板(２)の上面(21)に露出した各第２導電ビア(32)の先端部が電気的に接続されている。従って、グランド端子(41)と電源端子(42)との間には、コンデンサ素子(１)を介して電気的な経路が形成されることになる。 As shown in FIG. 1, a ground terminal (41) and a power supply terminal (42) are formed on the upper surface (21) of the insulating substrate (2). Here, the tip of each first conductive via (31) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected to the ground terminal (41), and the power terminal (42) The tip of each second conductive via (32) exposed on the upper surface (21) of the insulating substrate (2) is electrically connected. Therefore, an electrical path is formed between the ground terminal (41) and the power supply terminal (42) via the capacitor element (1).
　勿論、グランド端子(41)に各第２導電ビア(32)の先端部が接続され、電源端子(42)に各第１導電ビア(31)の先端部が接続されてもよい。 Of course, the tip of each second conductive via (32) may be connected to the ground terminal (41), and the tip of each first conductive via (31) may be connected to the power supply terminal (42).
　上記コンデンサ内蔵基板においては、第１電極層(11)の上面(111)に第２電極層(12)によって覆われていない領域(113)が形成されており、該領域(113)に複数の第１導電ビア(31)～(31)が電気的に接続されている。従って、各第１導電ビア(31)を、第２電極層(12)に電気的に接触させることなく、絶縁基板(２)の上面(21)に向けて延ばして、該上面(21)に第１導電ビア(31)の先端部を露出させることが出来る。よって、従来のコンデンサ内蔵基板、具体的には第１電極層(11)に電気的に接続されるべき導電ビアが、絶縁基板(２)の表面の内、コンデンサ素子(１)の第１電極層(11)側の表面領域(22)（図１の紙面において下面。以下、「下面」という）に引き回されていたコンデンサ内蔵基板（図２０参照）に比べて、本実施形態のコンデンサ内蔵基板（図１）は、前記電気的な経路が短くなり、その結果、コンデンサ内蔵基板に生じるインダクタンスが小さくなる。これにより、高周波領域でのコンデンサ内蔵基板のインピーダンス特性が向上することになる。 In the capacitor built-in substrate, a region (113) not covered with the second electrode layer (12) is formed on the upper surface (111) of the first electrode layer (11), and a plurality of regions (113) are formed in the region (113). The first conductive vias (31) to (31) are electrically connected. Accordingly, each first conductive via (31) extends toward the upper surface (21) of the insulating substrate (2) without being in electrical contact with the second electrode layer (12), and is formed on the upper surface (21). The front end portion of the first conductive via (31) can be exposed. Therefore, the conductive via to be electrically connected to the conventional capacitor-embedded substrate, specifically the first electrode layer (11), is the first electrode of the capacitor element (1) in the surface of the insulating substrate (2). Compared with the capacitor built-in substrate (see FIG. 20) routed to the surface region (22) on the layer (11) side (the lower surface in FIG. 1; hereinafter referred to as the “lower surface”), this embodiment has a built-in capacitor. In the substrate (FIG. 1), the electrical path is shortened, and as a result, the inductance generated in the capacitor built-in substrate is reduced. This improves the impedance characteristics of the capacitor built-in substrate in the high frequency region.
　本願発明者は、本実施形態のコンデンサ内蔵基板について、高周波領域でのインピーダンス特性が向上することをシミュレーションによって確かめた。図３は、シミュレーションによって得られた本実施形態のコンデンサ内蔵基板のインピーダンス特性をグラフ(91)で示した図である。 The inventor of the present application has confirmed by simulation that the impedance characteristics in the high frequency region of the substrate with a built-in capacitor of this embodiment are improved. FIG. 3 is a graph (91) showing the impedance characteristics of the substrate with a built-in capacitor of the present embodiment obtained by simulation.
　尚、図３には、図２１に示す如く従来のコンデンサ搭載基板のインピーダンス特性も、グラフ(92)によって示されている。ここで、従来のコンデンサ搭載基板においては、図２１に示す様に、絶縁基板(304)の複数箇所に、その上面(305)から下面(311)に貫通する一対の導電ビア(314)(315)が形成されると共に、該絶縁基板(304)の下面(311)にチップ状のコンデンサ素子(316)が搭載されている。これにより、絶縁基板(304)の上面(305)に形成されている電源端子(306)とグランド端子(307)との間に、コンデンサ素子(316)を介して電気的な経路が形成されている。 In FIG. 3, the impedance characteristic of the conventional capacitor mounting board as shown in FIG. 21 is also shown by a graph (92). Here, in the conventional capacitor mounting substrate, as shown in FIG. 21, a pair of conductive vias (314) (315) penetrating from the upper surface (305) to the lower surface (311) at a plurality of locations on the insulating substrate (304). ) And a chip-like capacitor element (316) is mounted on the lower surface (311) of the insulating substrate (304). As a result, an electrical path is formed between the power supply terminal (306) and the ground terminal (307) formed on the upper surface (305) of the insulating substrate (304) via the capacitor element (316). Yes.
　図３に示す２つのグラフ(91)(92)を比較することにより、本実施形態のコンデンサ内蔵基板において、高周波領域でのインピーダンス特性が向上していることがわかる。 3. By comparing the two graphs (91) and (92) shown in FIG. 3, it can be seen that the impedance characteristics in the high frequency region are improved in the capacitor built-in substrate of the present embodiment.
　次に、上記コンデンサ素子(１)の製造方法について説明する。 Next, a method for manufacturing the capacitor element (1) will be described.
　図４は、コンデンサ素子(１)の製造方法の誘電体層形成工程を説明する斜視図である。図４に示す様に、誘電体層形成工程では、コンデンサ素子(１)の第１電極層(11)となる金属箔(50)の表面(501)に、成膜装置(71)を用いて誘電体材料の膜を形成することにより、コンデンサ素子(１)の誘電体層(13)を形成する。本実施形態では、銅（Ｃｕ）から形成された１枚の金属箔(50)の表面(501)に、正方形の形状を有する誘電体層(13)が４×４のマトリクス状に形成される。これにより、金属箔(50)の表面(501)に複数の誘電体層(13)が形成された素子形成用第１シート(61)が形成される。 FIG. 4 is a perspective view for explaining a dielectric layer forming step of the method of manufacturing the capacitor element (1). As shown in FIG. 4, in the dielectric layer forming step, a film forming apparatus (71) is used on the surface (501) of the metal foil (50) to be the first electrode layer (11) of the capacitor element (1). By forming a dielectric material film, the dielectric layer (13) of the capacitor element (1) is formed. In this embodiment, a dielectric layer (13) having a square shape is formed in a 4 × 4 matrix on the surface (501) of one metal foil (50) made of copper (Cu). . Thereby, the first sheet for element formation (61) in which a plurality of dielectric layers (13) are formed on the surface (501) of the metal foil (50) is formed.
　図５は、コンデンサ素子(１)の製造方法のアニール工程を説明する斜視図である。アニール工程は、誘電体層形成工程の実行後に実行される工程である。図５に示す様に、アニール工程では、各誘電体層(13)にレーザを照射することにより、該誘電体層(13)にアニール処理を施す。これにより、誘電体層(13)の特性を更に向上させることが出来る。 FIG. 5 is a perspective view for explaining the annealing step of the method for manufacturing the capacitor element (1). An annealing process is a process performed after execution of a dielectric material layer formation process. As shown in FIG. 5, in the annealing step, each dielectric layer (13) is irradiated with a laser to thereby anneal the dielectric layer (13). Thereby, the characteristics of the dielectric layer (13) can be further improved.
　尚、アニール工程は、本発明に係るコンデンサ素子(１)の製造に必須の工程ではなく、誘電体層の特性を更に向上させる場合にのみ、アニール工程を実行してもよい。又、アニール処理には、レーザ照射の他に、マイクロ波加熱、大気又は窒素雰囲気中での加熱（炉などを使用）等の方法を用いることが出来る。 The annealing step is not an essential step for manufacturing the capacitor element (1) according to the present invention, and the annealing step may be performed only when the characteristics of the dielectric layer are further improved. In addition to the laser irradiation, annealing may be performed by a method such as microwave heating, heating in the atmosphere or nitrogen atmosphere (using a furnace or the like), or the like.
　図６は、コンデンサ素子(１)の製造方法のレジスト形成工程を説明する斜視図である。レジスト形成工程は、アニール工程の実行後に実行される工程である。レジスト形成工程では、素子形成用第１シート(61)にマスキング処理を施す。具体的には、図６に示す様に、素子形成用第１シート(61)の露出表面の内、次に実行されるメッキ工程においてメッキを付着させたくない領域にレジスト(52)を形成する。本実施形態では、メッキ工程にて誘電体層(13)の表面(131)にのみメッキを付着させるべく、本工程において、金属箔(50)の表面(501)の内、誘電体層(13)によって覆われていない領域にレジスト(52)を形成する。これにより、素子形成用第２シート(62)が形成される。 FIG. 6 is a perspective view for explaining a resist forming step of the method of manufacturing the capacitor element (1). The resist formation step is a step that is executed after the annealing step. In the resist forming step, a masking process is performed on the first element forming sheet (61). Specifically, as shown in FIG. 6, a resist (52) is formed in the exposed surface of the first element forming sheet (61) in a region where plating is not desired to be applied in the plating process to be executed next. . In the present embodiment, in order to deposit the plating only on the surface (131) of the dielectric layer (13) in the plating step, the dielectric layer (13 The resist (52) is formed in the region not covered with (). Thereby, the second sheet for element formation (62) is formed.
　図７は、コンデンサ素子(１)の製造方法のメッキ工程を説明する斜視図である。メッキ工程は、レジスト形成工程の実行後に実行される工程である。図７に示す様に、メッキ工程では、素子形成用第２シート(62)をメッキ液(72)に浸漬させることにより、素子形成用第２シート(62)に無電解メッキ処理を施す。これにより、図８に示す様に、各誘電体層(13)上に、コンデンサ素子(１)の第２電極層(12)となる金属薄膜(53)が形成される。本実施形態では、無電解メッキ処理用の金属材料として銅（Ｃｕ）が用いられる。 FIG. 7 is a perspective view for explaining a plating step of the method of manufacturing the capacitor element (1). A plating process is a process performed after execution of a resist formation process. As shown in FIG. 7, in the plating step, the element forming second sheet (62) is subjected to electroless plating by immersing the element forming second sheet (62) in a plating solution (72). As a result, as shown in FIG. 8, a metal thin film (53) to be the second electrode layer (12) of the capacitor element (1) is formed on each dielectric layer (13). In the present embodiment, copper (Cu) is used as the metal material for the electroless plating process.
　尚、金属薄膜(53)の形成には、メッキ処理の他に、スパッタリング法、蒸着法、スクリーン印刷法、インクジェット法等の手法を用いることが出来る。 For forming the metal thin film (53), a method such as sputtering, vapor deposition, screen printing, and ink jet can be used in addition to plating.
　図９は、コンデンサ素子(１)の製造方法のレジスト剥離工程を説明する平面図である。レジスト剥離工程は、メッキ工程の実行後に実行される工程である。図９に示す様に、レジスト剥離工程では、金属箔(50)の表面(501)上に形成されているレジスト(52)（図８参照）を剥離し、金属箔(50)の表面(501)からレジスト(52)を除去する。これにより、素子形成用第３シート(63)が形成される。 FIG. 9 is a plan view for explaining the resist stripping step of the method of manufacturing the capacitor element (1). The resist stripping process is a process executed after the plating process. As shown in FIG. 9, in the resist stripping step, the resist (52) (see FIG. 8) formed on the surface (501) of the metal foil (50) is stripped and the surface (501) of the metal foil (50) is removed. ) To remove the resist (52). Thereby, the third sheet for element formation (63) is formed.
　尚、レジスト(52)の剥離には、例えば化学的な手法を用いることが出来る。 For example, a chemical method can be used for removing the resist (52).
　図１０は、コンデンサ素子(１)の製造方法の切断工程を説明する平面図である。切断工程は、レジスト剥離工程の実行後に実行される工程である。図１０に示す様に、切断工程では、素子形成用第３シート(63)に切断加工を施す。具体的には、図１０に示される破線に沿って金属箔(50)を切断することにより、金属箔(50)から第１電極層(11)を形成する。 FIG. 10 is a plan view for explaining a cutting step of the method of manufacturing the capacitor element (1). A cutting process is a process performed after execution of a resist peeling process. As shown in FIG. 10, in the cutting step, the third sheet for element formation (63) is cut. Specifically, the first electrode layer (11) is formed from the metal foil (50) by cutting the metal foil (50) along the broken line shown in FIG.
　このとき、金属箔(50)は、形成される第１電極層(11)の表面の一部が第２電極層(12)によって覆われることとなる様に切断される。具体的には、金属箔(50)は、第１電極層(11)の表面の中央領域が第２電極層(12)によって覆われると共に、第１電極層(11)の形状が略正方形となる様に切断される。 At this time, the metal foil (50) is cut so that a part of the surface of the formed first electrode layer (11) is covered with the second electrode layer (12). Specifically, in the metal foil (50), the central region of the surface of the first electrode layer (11) is covered with the second electrode layer (12), and the shape of the first electrode layer (11) is substantially square. It is cut like this.
　上述した製造方法を実施することによりコンデンサ素子(１)が完成し、上述の如く作製されたコンデンサ素子(１)は、その厚さ寸法が小さくてシート状のものとなる。 The capacitor element (1) is completed by carrying out the manufacturing method described above, and the capacitor element (1) manufactured as described above has a small thickness and a sheet shape.
　次に、上記コンデンサ素子(１)を用いてコンデンサ内蔵基板を作製する方法について説明する。該方法では、先ず、絶縁基板(２)を構成する２枚の絶縁基材(20)(20)（図１５参照）の内、一方の絶縁基材(20)上にコンデンサ素子(１)を搭載する素子搭載工程が実行される。 Next, a method for producing a capacitor built-in substrate using the capacitor element (1) will be described. In this method, first, the capacitor element (1) is placed on one insulating base material (20) of the two insulating base materials (20) and (20) (see FIG. 15) constituting the insulating substrate (2). The element mounting process to be mounted is executed.
　ここで、上記素子搭載工程にて実施されるコンデンサ素子(１)の搭載方法について説明する。 Here, a method of mounting the capacitor element (1) performed in the element mounting process will be described.
　図１１は、コンデンサ素子(１)の搭載方法の貼着工程を説明する斜視図である。図１１に示す様に、貼着工程では、熱や圧力等の外的な作用を与えることによりコンデンサ素子(１)の貼着と剥離とが可能なキャリアシート(80)を用いて、該キャリアシート(80)の表面の内、１又は複数の所定領域(81)にコンデンサ素子(１)を貼着して添付することにより素子添付シート(８)を作製する。このとき、コンデンサ素子(１)は、その第１電極層(11)をキャリアシート(80)の表面の所定領域(81)に面接触させた状態で該キャリアシート(80)に貼着される。ここで、所定領域(81)は、コンデンサ素子(１)が搭載されるべき絶縁基材(20)上の所定位置に対応して設定されている。 FIG. 11 is a perspective view for explaining a sticking process of the mounting method of the capacitor element (1). As shown in FIG. 11, in the adhering step, the carrier sheet (80) capable of adhering and peeling the capacitor element (1) by applying an external action such as heat and pressure is used. The element attachment sheet (8) is produced by attaching and attaching the capacitor element (1) to one or a plurality of predetermined regions (81) of the surface of the sheet (80). At this time, the capacitor element (1) is adhered to the carrier sheet (80) in a state where the first electrode layer (11) is in surface contact with a predetermined region (81) on the surface of the carrier sheet (80). . Here, the predetermined area (81) is set corresponding to a predetermined position on the insulating base material (20) on which the capacitor element (1) is to be mounted.
　図１２～図１４は、コンデンサ素子(１)の搭載方法の剥離工程を説明する斜視図である。剥離工程は、貼着工程の実行後に実行される工程である。 FIGS. 12 to 14 are perspective views for explaining the peeling process of the mounting method of the capacitor element (1). A peeling process is a process performed after execution of a sticking process.
　先ず、図１２に示す様に、剥離工程の前段において、絶縁基材(20)を構成する一対のプリプレグ(201)(201)とコア材(202)とを、該一対のプリプレグ(201)(201)の間にコア材(202)を挟んで積層する。又、プリプレグ(201)上の所定位置に、素子添付シート(８)を、該素子添付シート(８)に添付されているコンデンサ素子(１)を該プリプレグ(201)に向けた姿勢で重ね合わせる。これにより、一対のプリプレグ(201)(201)、コア材(202)、及び素子添付シート(８)からなる積層体(82)が形成される。 First, as shown in FIG. 12, in the preceding stage of the peeling step, the pair of prepregs (201) (201) and the core material (202) constituting the insulating base material (20) are combined with the pair of prepregs (201) ( 201) and sandwiching the core material (202). Further, the element attachment sheet (8) is superposed at a predetermined position on the prepreg (201) with the capacitor element (1) attached to the element attachment sheet (8) in a posture toward the prepreg (201). . Thereby, the laminated body (82) which consists of a pair of prepreg (201) (201), core material (202), and element attachment sheet (8) is formed.
　次に、図１３に示す様に、剥離工程の中段において、積層体(82)に熱と圧力を与えることにより、一対のプリプレグ(201)(201)とコア材(202)とを熱圧着して絶縁基材(20)を形成すると共に、素子添付シート(８)が重なっているプリプレグ(201)の表面に、該素子添付シート(８)に添付されているコンデンサ素子(１)を熱圧着する。このとき、素子添付シート(８)には熱が与えられているので、コンデンサ素子(１)はキャリアシート(80)から剥離し易くなっている。 Next, as shown in FIG. 13, in the middle of the peeling process, by applying heat and pressure to the laminate (82), the pair of prepregs (201) (201) and the core material (202) are thermocompression bonded. The capacitor substrate (1) attached to the element attachment sheet (8) is thermocompression-bonded to the surface of the prepreg (201) on which the element attachment sheet (8) overlaps. To do. At this time, since heat is applied to the element attachment sheet (8), the capacitor element (1) is easily peeled off from the carrier sheet (80).
　その後、図１４に示す様に、剥離工程の後段において、キャリアシート(80)を絶縁基材(20)から引き剥がすことにより、コンデンサ素子(１)をキャリアシート(80)から剥離する。これにより、コンデンサ素子(１)が、絶縁基材(20)上の所定位置に搭載されることになる。 Thereafter, as shown in FIG. 14, the capacitor element (1) is peeled from the carrier sheet (80) by peeling the carrier sheet (80) from the insulating base (20) in the latter stage of the peeling step. As a result, the capacitor element (1) is mounted at a predetermined position on the insulating substrate (20).
　尚、プリプレグ(201)の表面へのコンデンサ素子(１)の接着強度が、キャリアシート(80)への該コンデンサ素子(１)の接着強度より大きい場合には、キャリアシート(80)として、熱剥離性のないシート、例えば粘着性を有するＰＥＴ（ポリエチレンテレフタレート）シート等を用いることが出来る。 When the adhesive strength of the capacitor element (1) to the surface of the prepreg (201) is higher than the adhesive strength of the capacitor element (1) to the carrier sheet (80), the carrier sheet (80) A non-peelable sheet such as a PET (polyethylene terephthalate) sheet having adhesiveness can be used.
　図１５は、コンデンサ内蔵基板を作製する方法の積層工程を説明する斜視図である。積層工程は、素子搭載工程の実行後に実行される工程である。図１５に示す様に、積層工程では、絶縁基材(20)上に、絶縁基板(２)を構成する別の絶縁基材(20)を積層する。これにより、積層された２つの絶縁基材(20)により絶縁基板(２)が形成されることになる。 FIG. 15 is a perspective view for explaining a stacking process of a method for producing a capacitor built-in substrate. A lamination process is a process performed after execution of an element mounting process. As shown in FIG. 15, in the laminating step, another insulating base material (20) constituting the insulating substrate (2) is laminated on the insulating base material (20). Thereby, the insulating substrate (2) is formed by the two insulating base materials (20) laminated.
　その後、図１に示す様に、絶縁基板(２)に、第１導電ビア(31)と第２導電ビア(32)とを形成し、絶縁基板(２)の上面(21)に、グランド端子(41)と電源端子(42)とを形成する。これにより、コンデンサ内蔵基板が完成することになる。 Thereafter, as shown in FIG. 1, a first conductive via (31) and a second conductive via (32) are formed on the insulating substrate (2), and a ground terminal is formed on the upper surface (21) of the insulating substrate (2). (41) and a power supply terminal (42) are formed. As a result, the capacitor built-in substrate is completed.
　上記搭載方法において絶縁基材(20)上に搭載するコンデンサ素子(１)は、その厚さ寸法が小さくてシート状のものである。この様なコンデンサ素子(１)は、これを絶縁基材(20)上に搭載するときに高いハンドリング性能を必要とする。このため、絶縁基材(20)上に搭載せんとするコンデンサ素子(１)を個々にハンドリングしたのでは、絶縁基材(20)上にコンデンサ素子(１)を搭載する素子搭載工程が煩雑になる。 In the mounting method, the capacitor element (1) mounted on the insulating base (20) has a small thickness and is in the form of a sheet. Such a capacitor element (1) requires high handling performance when it is mounted on the insulating substrate (20). For this reason, if the capacitor elements (1) to be mounted on the insulating base material (20) are individually handled, the element mounting process for mounting the capacitor element (1) on the insulating base material (20) is complicated. Become.
　上記搭載方法によれば、コンデンサ素子(１)が添付された素子添付シート(８)を用いて絶縁基材(20)上の所定位置にコンデンサ素子(１)が搭載される。このため、コンデンサ素子(１)を個々にハンドリングする必要がなく、絶縁基材(20)上にコンデンサ素子(１)を搭載する素子搭載工程が簡略化されることになる。 According to the mounting method, the capacitor element (1) is mounted at a predetermined position on the insulating base (20) using the element attachment sheet (8) to which the capacitor element (1) is attached. For this reason, it is not necessary to handle the capacitor elements (1) individually, and the element mounting process for mounting the capacitor elements (1) on the insulating substrate (20) is simplified.
　又、金属箔からなるコンデンサ素子(１)の第１導電層(11)は、それをキャリアシート(80)に貼着した後で剥離した場合でも損傷し難い。従って、上記コンデンサ素子(１)の搭載方法の如く、貼着工程にて第１電極層(11)をキャリアシート(80)に貼着した後、剥離工程にてコンデンサ素子(１)をキャリアシート(80)から剥離した場合でも、第１電極層(11)には損傷が生じ難い。 Also, the first conductive layer (11) of the capacitor element (1) made of metal foil is hardly damaged even when it is peeled off after being stuck on the carrier sheet (80). Therefore, like the mounting method of the capacitor element (1), after the first electrode layer (11) is attached to the carrier sheet (80) in the attaching step, the capacitor element (1) is attached to the carrier sheet in the releasing step. Even when peeled from (80), the first electrode layer (11) is hardly damaged.
　尚、上記コンデンサ内蔵基板の作製に用いるコンデンサ素子(１)の厚さ寸法は、５μｍ以上１００μｍ以下の範囲内であることが好ましい。なぜなら、該厚さ寸法が５μｍより小さい場合、コンデンサ素子(１)のハンドリングが困難になり、又、抵抗が大きくなる等の問題が生じるからである。又、該厚さ寸法が１００μｍより大きい場合、コンデンサ素子(１)の厚さが影響して絶縁基材(20)の表面上に凹凸が形成され、上記積層工程にて絶縁基材(20)上に別の絶縁基材(20)を積層することが困難になるからである。 In addition, it is preferable that the thickness dimension of the capacitor | condenser element (1) used for preparation of the said board | substrate with a built-in capacitor exists in the range of 5 micrometers or more and 100 micrometers or less. This is because when the thickness is smaller than 5 μm, it is difficult to handle the capacitor element (1), and problems such as an increase in resistance occur. Further, when the thickness dimension is larger than 100 μm, the thickness of the capacitor element (1) affects the surface of the insulating base material (20), so that irregularities are formed on the surface of the insulating base material (20). This is because it becomes difficult to laminate another insulating base material (20) thereon.
　図１６は、本発明の第１変形例に係るコンデンサ内蔵基板について、該コンデンサ内蔵基板に内蔵されているコンデンサ素子(１)を第２電極層(12)側から見た平面図である。図１６に示す様に、第１導電ビア(31)が、第１電極層(11)の上面(111)の内、第２電極層(12)によって覆われていない領域(113)上の２４箇所に形成されると共に、第２導電ビア(32)が、第２電極層(12)の上面(121)上の２５箇所に形成され、これらの第１導電ビア(31)～(31)と第２導電ビア(32)～(32)が、図１６の紙面において７×７のマトリクス状に配列されていてもよい。 FIG. 16 is a plan view of the capacitor built-in substrate according to the first modified example of the present invention when the capacitor element (1) built in the capacitor built-in substrate is viewed from the second electrode layer (12) side. As shown in FIG. 16, the first conductive via (31) is located on the upper surface (111) of the first electrode layer (11) over the region (113) not covered by the second electrode layer (12). The second conductive vias (32) are formed at 25 locations on the upper surface (121) of the second electrode layer (12), and the first conductive vias (31) to (31) are formed. The second conductive vias (32) to (32) may be arranged in a 7 × 7 matrix on the paper surface of FIG.
　図１７は、本発明の第２変形例に係るコンデンサ内蔵基板について、該コンデンサ内蔵基板に内蔵されているコンデンサ素子(１)を第２電極層(12)側から見た平面図である。図１７に示す様に、図１６に示すコンデンサ内蔵基板において、コンデンサ素子(１)の第１電極層(11)の上面(111)の４箇所に、誘電体層(13)を介して第２電極層(12)が設けられ、該４箇所に設けられた第２電極層(12)が互いに離間して配置されていてもよい。 FIG. 17 is a plan view of the capacitor-embedded substrate according to the second modification of the present invention when the capacitor element (1) built in the capacitor-embedded substrate is viewed from the second electrode layer (12) side. As shown in FIG. 17, in the substrate with a built-in capacitor shown in FIG. An electrode layer (12) may be provided, and the second electrode layers (12) provided at the four locations may be arranged apart from each other.
　本変形例においては、図１７の紙面において７×７のマトリクス状に配列された導電ビアの内、１行目、４行目、及び７行目に配列された導電ビアと１列目、４列目、及び７列目に配列された導電ビアの合計３３個の導電ビアが第１導電ビア(31)であり、その他の１６個の導電ビアが第２導電ビア(32)である。そして、１６個の第２導電ビア(32)は、上記４箇所に設けられた第２電極層(12)に４個ずつ接続されている。 In this modification, among the conductive vias arranged in a 7 × 7 matrix on the paper surface of FIG. 17, the conductive vias arranged in the first row, the fourth row, and the seventh row, the first column, A total of 33 conductive vias arranged in the row and the seventh row are first conductive vias (31), and the other 16 conductive vias are second conductive vias (32). The 16 second conductive vias (32) are connected to the second electrode layers (12) provided at the four locations, four by four.
　本変形例に係るコンデンサ内蔵基板によれば、第１導電ビア(31)の本数を増やすことが出来、その結果、第１導電ビア(31)には、第２導電ビア(32)との間の距離が最も小さいものが多く存在することになる。よって、コンデンサ内蔵基板に生じるインダクタンスを更に小さくすることが出来る。 According to the substrate with a built-in capacitor according to this modification, the number of the first conductive vias (31) can be increased. As a result, the first conductive via (31) has a gap between the second conductive via (32). There are many things with the smallest distance. Therefore, the inductance generated in the capacitor built-in substrate can be further reduced.
　図１８は、本発明の第３変形例に係るコンデンサ内蔵基板を示す断面図である。図１８に示す様に、図１に示すコンデンサ内蔵基板において、絶縁基板(２)に、コンデンサ素子(１)の第１電極層(11)の第２電極層(12)とは反対側の表面(114)（図１及び図１８の紙面において下面）に電気的に接続された第３導電ビア(33)が形成され、該第３導電ビア(33)が、絶縁基板(２)の下面(22)に向けて延び、該下面(22)に第３導電ビア(33)の先端部が露出していてもよい。 FIG. 18 is a cross-sectional view showing a capacitor built-in substrate according to a third modification of the present invention. As shown in FIG. 18, in the capacitor built-in substrate shown in FIG. 1, the surface of the insulating substrate (2) opposite to the second electrode layer (12) of the first electrode layer (11) of the capacitor element (1). (114) A third conductive via (33) electrically connected to the lower surface (the lower surface in FIG. 1 and FIG. 18) is formed, and the third conductive via (33) is formed on the lower surface of the insulating substrate (2) ( 22) and the tip of the third conductive via (33) may be exposed on the lower surface (22).
　図１９は、本発明の第４変形例に係るコンデンサ内蔵基板を示す断面図である。図１９に示す様に、誘電体層(13)は、第１電極層(11)の上面(111)の内、第２電極層(12)によって覆われている領域(112)上に形成されると共に、第２電極層(12)によって覆われていない領域(113)上にも形成されていてもよい。この場合、第１導電ビア(31)は、誘電体層(13)を貫通して絶縁基板(２)の上面(21)に向けて延びることになる。 FIG. 19 is a cross-sectional view showing a capacitor built-in substrate according to a fourth modification of the present invention. As shown in FIG. 19, the dielectric layer (13) is formed on the upper surface (111) of the first electrode layer (11) on the region (112) covered with the second electrode layer (12). In addition, it may be formed on a region (113) not covered with the second electrode layer (12). In this case, the first conductive via (31) extends through the dielectric layer (13) toward the upper surface (21) of the insulating substrate (2).
　尚、本発明の各部構成は上記実施の形態に限らず、特許請求の範囲に記載の技術的範囲内で種々の変形が可能である。例えば、上記コンデンサ内蔵基板において、コンデンサ素子(１)の第２電極層(12)は、金属箔により形成されていてもよい。又、コンデンサ素子(１)の第１電極層(11)及び第２電極層(12)の形状は略正方形に限定されるものではなく、第１電極層(11)及び第２電極層(12)には様々な形状を採用することが出来る。 The configuration of each part of the present invention is not limited to the above-described embodiment, and various modifications can be made within the technical scope described in the claims. For example, in the capacitor built-in substrate, the second electrode layer (12) of the capacitor element (1) may be formed of a metal foil. Further, the shape of the first electrode layer (11) and the second electrode layer (12) of the capacitor element (1) is not limited to a substantially square shape, but the first electrode layer (11) and the second electrode layer (12). ) Various shapes can be used.
　更に、コンデンサ素子(１)の第１電極層(11)は、絶縁基板(２)内に形成された電源パターンやグランドパターンと一体に形成されていてもよい。 Furthermore, the first electrode layer (11) of the capacitor element (1) may be formed integrally with a power supply pattern or a ground pattern formed in the insulating substrate (2).
　更に又、上記コンデンサ内蔵基板において、第１導電ビア(31)は、絶縁基板(２)内の１箇所にだけ形成されていてもよい。同様に、第２導電ビア(32)は、絶縁基板(２)内の１箇所にだけ形成されていてもよい。 Furthermore, in the capacitor built-in substrate, the first conductive via (31) may be formed only at one location in the insulating substrate (2). Similarly, the second conductive via (32) may be formed only at one place in the insulating substrate (2).
(１)　コンデンサ素子
(11)　第１電極層
(12)　第２電極層
(13)　誘電体層
(２)　絶縁基板
(20)　絶縁基材
(31)　第１導電ビア
(32)　第２導電ビア
(33)　第３導電ビア
(41)　グランド端子
(42)　電源端子
(８)　素子添付シート
(80)　キャリアシート
(81)　所定領域 (1) Capacitor element
(11) First electrode layer
(12) Second electrode layer
(13) Dielectric layer
(2) Insulating substrate
(20) Insulating substrate
(31) First conductive via
(32) Second conductive via
(33) Third conductive via
(41) Ground terminal
(42) Power supply terminal
(8) Element attachment sheet
(80) Carrier sheet
(81) Predetermined area

Claims (3)

  1. 　第１電極層と第２電極層との間に誘電体層が介在した１又複数のコンデンサ素子と、絶縁基板とを具え、該絶縁基板内にコンデンサ素子を埋設することにより絶縁基板にコンデンサ素子が内蔵されたコンデンサ内蔵基板を製造する方法であって、
    　外的な作用を与えることにより前記コンデンサ素子の貼着と剥離とが可能なシートを用いて、該シートの表面の内、１又は複数の所定領域に前記コンデンサ素子を貼着して添付することにより素子添付シートを作製する貼着工程と、
    　前記絶縁基板を構成する２つの絶縁基材の内、一方の絶縁基材上の所定位置に、前記素子添付シートを、該素子添付シートに添付されているコンデンサ素子を前記一方の絶縁基材に向けた姿勢で重ね合わせ、その状態で前記素子添付シートに前記外的な作用を与えることにより、前記コンデンサ素子をシートから剥離して前記一方の絶縁基材上に搭載する剥離工程と、
    　前記一方の絶縁基材上に他方の絶縁基材を積層することにより前記絶縁基板を形成する積層工程
    とを有するコンデンサ内蔵基板の製造方法。     One or a plurality of capacitor elements in which a dielectric layer is interposed between the first electrode layer and the second electrode layer, and an insulating substrate, and the capacitor element is embedded in the insulating substrate, whereby the capacitor element is embedded in the insulating substrate. Is a method of manufacturing a substrate with a built-in capacitor,
    Using a sheet on which the capacitor element can be attached and detached by applying an external action, the capacitor element is attached to one or a plurality of predetermined areas of the surface of the sheet and attached. A sticking step for producing an element attachment sheet by,
    Of the two insulating bases constituting the insulating substrate, the element attaching sheet is placed at a predetermined position on one insulating base, and the capacitor element attached to the element attaching sheet is used as the one insulating base. A peeling step of peeling the capacitor element from the sheet and mounting it on the one insulating base material by superposing in a posture directed and giving the external action to the element attachment sheet in that state,
    A method of manufacturing a capacitor built-in substrate, comprising: a step of forming the insulating substrate by laminating the other insulating substrate on the one insulating substrate.
  2. 　前記コンデンサ素子は、第１電極層が金属箔により形成される一方、前記第２電極層が金属薄膜又は金属箔により形成されており、前記貼着工程では、前記コンデンサ素子を、その前記第１電極層を前記シートの表面の所定領域に面接触させた状態で該シートに貼着する請求項１に記載のコンデンサ内蔵基板の製造方法。 In the capacitor element, the first electrode layer is formed of a metal foil, while the second electrode layer is formed of a metal thin film or a metal foil. In the attaching step, the capacitor element is the first electrode layer. The manufacturing method of the board | substrate with a built-in capacitor | condenser of Claim 1 which sticks to this sheet | seat in the state which made the electrode layer surface-contact the predetermined area | region of the said sheet | seat.
  3. 　前記コンデンサ素子の第１電極層は、第２電極層側の表面の一部が該第２電極層によって覆われている請求項１又は請求項２に記載のコンデンサ内蔵基板の製造方法。 3. The method for manufacturing a capacitor built-in substrate according to claim 1, wherein a part of a surface of the first electrode layer of the capacitor element on a second electrode layer side is covered with the second electrode layer.
PCT/JP2010/071976 2010-01-15 2010-12-08 Method of manufacturing substrate with built-in capacitor WO2011086797A1 (en)

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