WO2011078512A2 - Etchant and electronic device manufacturing method - Google Patents

Etchant and electronic device manufacturing method Download PDF

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Publication number
WO2011078512A2
WO2011078512A2 PCT/KR2010/008941 KR2010008941W WO2011078512A2 WO 2011078512 A2 WO2011078512 A2 WO 2011078512A2 KR 2010008941 W KR2010008941 W KR 2010008941W WO 2011078512 A2 WO2011078512 A2 WO 2011078512A2
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Prior art keywords
semiconductor layer
etchant
electronic device
transition metal
weight
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PCT/KR2010/008941
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French (fr)
Korean (ko)
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WO2011078512A3 (en
Inventor
박귀홍
이기범
조삼영
구병수
최정헌
Original Assignee
㈜동진쎄미켐
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Priority claimed from KR1020100118966A external-priority patent/KR101800803B1/en
Application filed by ㈜동진쎄미켐 filed Critical ㈜동진쎄미켐
Priority to CN201080058576.3A priority Critical patent/CN102666780B/en
Priority to JP2012545844A priority patent/JP2013516064A/en
Publication of WO2011078512A2 publication Critical patent/WO2011078512A2/en
Publication of WO2011078512A3 publication Critical patent/WO2011078512A3/en

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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/08—Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Definitions

  • An etchant and an electronic device manufacturing method using the etchant are provided.
  • a thin film transistor which is a kind of electronic device, is used as a switching element in a flat panel display such as a liquid crystal display or an organic light emitting display.
  • the thin film transistor may have, for example, a structure shown in FIG. 1F.
  • the gate electrode 2 is disposed on the insulating substrate 10
  • the gate insulating layer 3 is disposed on the gate electrode 2, and generally undoped intrinsic on the gate insulating layer 3.
  • Source electrodes 6a and 6b are disposed.
  • the spaced drain / source electrodes 6a, 6b and spaced ohmic contact layers 5a, 5b of FIG. 1F are obtained by sequentially etching the electrode layer 6 and the ohmic contact layer 5 in FIG. 1D. Wet etching is used to etch the electrode layer 6, and dry etching is used to etch the ohmic contact layer 5. Therefore, the manufacturing process is complicated.
  • the conventional etchant has higher etching performance than the ohmic contact layer 5 with respect to the gate insulating layer 3, the insulating substrate 10, the channel layer 4, and the like. Therefore, the wet etching was not applied to the etching of the ohmic contact layer 5.
  • One aspect of the present invention is to provide an etchant having a new composition.
  • Another aspect of the present invention to provide an electronic device manufacturing method using the etchant.
  • Transition metals transition metal salts or mixtures thereof.
  • An etchant comprising; hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof.
  • a method of manufacturing an electronic device comprising selectively etching a doped semiconductor layer disposed between a metal electrode and an intrinsic semiconductor layer of an electronic device with respect to the intrinsic semiconductor layer, wherein the etchant used in the etching step is
  • Transition metals transition metal salts or mixtures thereof.
  • an electronic device manufacturing method including hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof.
  • the etchant according to an aspect of the present invention simplifies the manufacturing process of the electronic device and increases the efficiency of the manufacturing process by selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer. , Reduced production costs, and / or improved performance of electronic devices.
  • FIG. 1A to 1F are cross-sectional views illustrating a thin film transistor manufacturing process according to an exemplary embodiment.
  • FIG. 2 is a scanning electron micrograph of the thin film transistor used in Evaluation Example 1.
  • FIG. 2 is a scanning electron micrograph of the thin film transistor used in Evaluation Example 1.
  • Example 3 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 1;
  • FIG. 4 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 2.
  • FIG. 4 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 2.
  • FIG. 5 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 3.
  • FIG. 5 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 3.
  • FIG. 6 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 4.
  • FIG. 6 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 4.
  • FIG. 7 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 5.
  • FIG. 7 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 5.
  • FIG. 8 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 6.
  • FIG. 9 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 7.
  • FIG. 10 is a scanning electron micrograph of the thin film transistor after etching with the etchant of Example 8.
  • FIG. 11 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 9.
  • FIG. 11 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 9.
  • Example 12 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 10.
  • FIG. 13 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 11.
  • FIG. 14 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 12.
  • FIG. 15 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 13.
  • FIG. 15 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 13.
  • Example 16 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 14.
  • FIG. 17 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 15.
  • FIG. 17 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 15.
  • Example 18 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 16.
  • Intrinsic semiconductor layer channel layer 5, 5a, 5b ... doped semiconductor layer (omic ohmic contact layer)
  • An etchant according to an exemplary embodiment is an etchant for selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer, a transition metal, a transition metal salt or a mixture thereof; And inorganic salts or mixtures thereof including hydrofluoric acid and fluorine.
  • the transition metal ion derived from the transition metal or the salt of the transition metal in the etching solution serves to selectively improve the etching rate for the doped semiconductor layer. Therefore, only the doped semiconductor layer may be selectively etched while suppressing etching of the intrinsic semiconductor layer.
  • the etchant may selectively etch only the doped semiconductor layer while minimizing etching of other layers such as an electrode layer, an electrode insulating layer, and an insulating substrate included in the electronic device.
  • the doped semiconductor layer is hardly etched, but rather an electrode layer, an electrode insulating layer, an insulating substrate, etc. may be etched. .
  • the content of the transition metal, the transition metal salt, or a mixture thereof in the etching solution may be 0.005 to 30% by weight based on the total weight of the etching solution.
  • the content of the transition metal, the transition metal salt or a mixture thereof may be 0.05 to 20% by weight based on the total weight of the etching solution.
  • the content of the transition metal, the transition metal salt or a mixture thereof may be 0.01 to 10% by weight based on the total weight of the etching solution.
  • the content of the inorganic salt containing hydrofluoric acid and fluorine or a mixture thereof in the etching solution may be 0.05 to 30% by weight based on the total weight of the etching solution.
  • the content of the hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof may be 0.05 to 20% by weight based on the total weight of the etching solution.
  • the amount of the hydrofluoric acid, an inorganic salt including fluorine, or a mixture thereof may be 0.05 to 10 wt% based on the total weight of the etching solution.
  • the etchant may include 0.005 to 30% by weight of the transition metal, the transition metal salt or a mixture thereof; 0.05 to 30% by weight of an inorganic salt or a mixture thereof containing hydrofluoric acid and fluorine; And 40 to 99.945% by weight of water.
  • the transition metal in the etchant is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta It may be at least one selected from the group consisting of, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinides.
  • the transition metal may be Cu.
  • the transition metal salt in the etchant is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta It may be a transition metal salt containing ions of at least one metal selected from the group consisting of W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinium elements.
  • the transition metal salt is CuSO 4 , Cu (NO 3 ) 2 , CuO, (CH 3 CO 2 ) 2 Cu, Copper Gluconate, CuCl, CuCl 2 , CuF 2 , Cu (OH) 2 , Cu 2 S, Fe (NO 3 ) 3 , FeSO 4 , Ni (NO 3 ) 2 , NiSO 4 , AgNO 3 , Ag 2 SO 4 , (CH 3 CO 2 ) 2 Co, (CH 3 CO 2 ) 2 Pd, Pd (NO 3) 2, Rh (CH 3 CO 2) 2, may be at least one selected from the group consisting of such as Rh 2 O 3.
  • the transition metal salt may be CuSO 4 .
  • the inorganic salt containing fluorine in the etchant is KF, LiF, NaF, RbF, CsF, MgF 2 , NH 4 F, H 2 SiF 6 , NaHF 2 , NH 4 F, NH 4 HF 2 , NH 4 BF 4 , It may be at least one selected from inorganic salts including fluorine such as KHF 2 , AlF 3 , HBF 4 .
  • the inorganic salt containing fluorine may be used in admixture with hydrofluoric acid.
  • the etching solution may include 0.01 to 10% by weight of the copper or copper salt, 0.05 to 10% by weight of an inorganic salt including hydrofluoric acid or fluorine, and 80 to 99.94% by weight of water.
  • the etchant may include 0.01 to 10% by weight of CuSO 4 , 0.05 to 10% by weight of HF, and 80 to 99.94% by weight of water.
  • the intrinsic semiconductor layer may be amorphous silicon.
  • the doped semiconductor layer may be amorphous silicon doped with an n-type dopant.
  • the doped semiconductor layer may be n + amorphous silicon (n + a-Si: H).
  • the n-type dopant may be a Periodic Table 5A element having more outermost electrons than silicon. For example, it may be P, As, Sb and the like. The content of the n-type dopant may be less than 50 mol%.
  • the electronic device manufactured using the etchant may be a thin film transistor, but is not necessarily limited to the thin film transistor, and any electronic device that may be used in the art may be used.
  • the thin film transistor may have the structure of FIG. 1F, for example.
  • the insulating substrate 10 may be glass, but is not necessarily limited to glass, and may be used as long as the insulating substrate 10 may be used as a substrate in the art, such as polycarbonate and quartz.
  • the gate electrode 2 may be a conductive metal such as molybdenum, aluminum, niobium, or an alloy thereof. However, the gate electrode 2 may be used as long as it is not limited to a metal and may be used as an electrode material in the art.
  • the gate insulating layer 3 may be silicon nitride (SiNx).
  • the gate insulating layer 3 may be used as long as it can be used as an insulating layer of the gate electrode in the art.
  • the semiconductor layer 4 may be amorphous silicon as an undoped intrinsic semiconductor layer, but may be used as long as it is not necessarily limited to amorphous silicon as long as it can be used as an intrinsic semiconductor layer in the art.
  • the semiconductor layer 4 serves as a channel layer in the thin film transistor.
  • the ohmic contact layers 5a and 5b may be n + amorphous silicon as a semiconductor layer doped with an n-type dopant, but are not limited thereto, and may serve as an ohmic contact layer in the art. All ramen can be used.
  • a method of manufacturing an electronic device includes selectively etching a doped semiconductor layer disposed between a metal electrode and an intrinsic semiconductor layer of an electronic device with respect to the intrinsic semiconductor layer.
  • the etchant used may be a transition metal, a transition metal salt or a mixture thereof; And inorganic salts or mixtures thereof including hydrofluoric acid and fluorine.
  • the etching solution used in the preparation method may be 0.005 to 30% by weight of the transition metal, the transition metal salt or a mixture thereof; 0.05 to 30% by weight of an inorganic salt or a mixture thereof containing hydrofluoric acid and fluorine; And 40 to 99.945% by weight of water.
  • the transition metal is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, It may be at least one selected from the group consisting of Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinides.
  • the transition metal may be Cu.
  • the transition metal salt in the etching solution used in the preparation method is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, It may be a transition metal salt containing ions of at least one metal selected from the group consisting of Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinides.
  • the transition metal salt is CuSO 4 , Cu (NO 3 ) 2 , CuO, (CH 3 CO 2 ) 2 Cu, Copper Gluconate, CuCl, CuCl 2 , CuF 2 , Cu (OH) 2 , Cu 2 S, Fe (NO 3 ) 3 , FeSO 4 , Ni (NO 3 ) 2 , NiSO 4 , AgNO 3 , Ag 2 SO 4 , (CH 3 CO 2 ) 2 Co, (CH 3 CO 2 ) 2 Pd, Pd (NO 3 ) 2 It may be one or more selected from the group consisting of Rh (CH 3 CO 2 ) 2 , Rh 2 O 3 and the like.
  • the transition metal salt may be CuSO 4 .
  • the inorganic salt containing fluorine is KF, LiF, NaF, RbF, CsF, MgF 2 , NH 4 F, H 2 SiF 6 , NaHF 2 , NH 4 F, NH 4 HF 2 , NH 4 BF 4 , KHF 2 , AlF 3 , may be one or more selected from inorganic salts containing fluorine, such as HBF 4 may be used in combination with hydrofluoric acid.
  • the etching solution used in the preparation method may include 0.01 to 10% by weight of the copper or copper salt, 0.05 to 10% by weight of inorganic salt containing hydrofluoric acid or fluorine, and 80 to 99.94% by weight of water. .
  • the etching solution used in the preparation method may include 0.01 to 10% by weight of CuSO 4 , 0.05 to 10% by weight of HF, and 80 to 99.94% by weight of water.
  • the intrinsic semiconductor layer may be amorphous silicon.
  • the doped semiconductor layer may be amorphous silicon doped with an n-type dopant.
  • the doped semiconductor layer may be n + amorphous silicon (n + a-Si: H).
  • the n-type dopant may be a Periodic Table 5A element having more outermost electrons than silicon. For example, it may be P, As, Sb and the like. The content of the n-type dopant may be less than 50 mol%.
  • the electronic device manufactured by the electronic device manufacturing method may be a thin film transistor, but is not necessarily limited to the thin film transistor, and any electronic device that may be used in the art may be used.
  • a method of manufacturing a thin film transistor includes disposing a gate electrode on an insulating substrate before the etching step; Sequentially placing an insulating layer, an intrinsic semiconductor layer, and a doped semiconductor layer on the gate electrode; And disposing a drain electrode and a source electrode spaced apart from each other on the doped semiconductor layer.
  • the step of disposing a gate electrode on the insulating substrate may be performed by forming a metal film on the insulating substrate and then etching the metal film.
  • Arranging the insulating layer, the intrinsic semiconductor layer, and the doped semiconductor layer in sequence on the gate electrode may be performed by sequentially forming the layers by sputtering, chemical vapor deposition, physical vapor deposition, or the like. .
  • the disposing the drain electrode and the source electrode spaced apart from each other on the doped semiconductor layer may be performed by forming a metal film on the doped semiconductor layer and partially etching only the metal film.
  • the etching may be performed by wet etching.
  • a metal film 2 is first formed on an insulating substrate 10.
  • the metal film 2 may be an AlNd-based metal film.
  • a molybdenum metal film may be additionally formed to protect the metal film 2, but is not shown in the drawing. Formation of the metal film 2 may be deposited, for example, by a sputtering method.
  • a photoresist film is formed on the entire region of the insulating substrate 10, and then the exposure, development, and etching processes are performed to form the gate electrode 2 as shown in FIG. 1B.
  • a gate line and a gate pad connected to the gate electrode 2 are also formed at the same time, but are not shown in the drawing.
  • the gate insulating layer 3, the intrinsic semiconductor layer 4, and the doped semiconductor layer 5 are sequentially formed in the entire region of the insulating substrate 10. Subsequently, the channel layer 4 is formed on the gate electrode by etching according to a photolithography process. The doped semiconductor layer 5 remains on the channel layer 4.
  • a metal film 6 is deposited on the doped semiconductor layer 5 as shown in FIG. 1D.
  • the metal film 6 is wet etched to form spaced source / drain electrodes 6a and 6b.
  • the etchant of Examples 1 to 16 and Comparative Example 1 according to the etchant composition of the present invention was prepared as shown in Table 1 below.
  • the compositions of Examples 1 to 16 and Comparative Example 1 are shown in Table 1.
  • the transition metal, the transition metal salt or a mixture thereof is referred to as a first component
  • an inorganic salt containing hydrofluoric acid and fluorine or a mixture thereof is referred to as a second component.
  • the first component used in Example 1 was CuSO 4 and the second component was hydrofluoric acid (HF).
  • the first component used in Example 2 was Cu (NO 3 ) 2 and the second component was hydrofluoric acid.
  • the first component used in Example 3 was Fe (NO 3 ) 3 and the second component was hydrofluoric acid.
  • the first component used in Example 4 was AgSO 4 , and the second component was hydrofluoric acid.
  • the first component used in Example 5 was (CH 3 CO 2 ) 2 Cu and the second component was KF.
  • the first component used in Example 6 was CuCl 2 and the second component was LiF.
  • the first component used in Example 7 was CuF 2 and the second component was NaF.
  • the first component used in Example 8 was FeSO and the second component was NH 4 F.
  • the first component used in Example 9 was Ni (NO 3 ) 2 and the second component was H 2 SiF 6 .
  • the first component used in Example 10 was (CH 3 CO 2 ) 2 Co and the second component was NaHF 2 .
  • the first component used in Example 11 was (CH 3 CO 2 ) 2 Pd and the second component was NH 4 HF 2 .
  • the first component used in Example 12 was Pd (NO 3 ) 2 and the second component was NH 4 BF 4 .
  • the first component used in Example 13 was Rh (CH 3 CO 2 ) 2 and the second component was KHF 2 .
  • the first component used in Example 14 was AgNO 3
  • the second component was AlF 3 .
  • the first component used in Example 15 was Cu 2 S and the second component was HBF 4 .
  • the first component used in Example 16 was NiSO 4 and the second component was MgF 2 .
  • Example 1 0.5 0.3 99.2
  • Second component 0.5 0.3 99.2
  • Example 3 3 0.3 96.7
  • Example 4 One 0.3 98.7
  • Example 5 10
  • Example 6 5
  • Example 7 0.05 3 96.95
  • Example 8 2
  • Example 9 5 10
  • Example 10 3 95
  • Example 11 2
  • Example 12 0.5 2 97.5
  • Example 13 0.3 3 96.7
  • Example 14 3
  • Example 15 One 5 94
  • Example 16 One 7 92 Comparative Example 1 0 0.3 99.7
  • a thin film transistor having the structure of FIG. 2 was prepared.
  • Substrate is glass
  • insulating film is silicon nitride (SiNx)
  • intrinsic semiconductor layer is amorphous silicon (a-Si: H)
  • doped semiconductor layer is n + amorphous silicon (n + a-Si: H)
  • source / drain S / D
  • the electrode is molybdenum (Molybdenum).
  • the thin film transistor is etched using the etchant of Examples 1 to 16 and the etchant of Comparative Example 1 is shown in Figures 3 to 18 and 19.
  • FIGS. 3 to 18 are scanning electron micrographs of the thin film transistors after etching using the etchant of Examples 1 to 16, and FIG. 19 is a scanning electron micrograph of the thin film transistors after etching using the etchant of Comparative Example 1 to be.
  • Three photographs in FIGS. 3 to 18 are enlarged views of positions 1, 2, and 3 in FIG. 2.
  • the etchant according to an aspect of the present invention simplifies the manufacturing process of the electronic device and increases the efficiency of the manufacturing process by selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer. , Reduced production costs, and / or improved performance of electronic devices.

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Abstract

Disclosed is an etching fluid for electronic devices, comprising: a transition metal and/or a transition metal salt; and a hydrofluoric acid and/or a fluoride salt. The etchant selectively etches an intrinsic semiconductor layer, in an electronic device which has a doped semiconductor layer situated between metal electrodes and said intrinsic semiconductor layer.

Description

식각액 및 전자소자 제조방법Etching solution and electronic device manufacturing method
식각액 및 상기 식각액을 사용하는 전자소자 제조방법에 관한 것이다.An etchant and an electronic device manufacturing method using the etchant are provided.
전자소자의 일종인 박막트랜지스터(thin film transistor)는 액정표시장치(liquid crystal display) 또는 유기발광표시장치(organic light emitting display) 등과 같은 평판표시장치에서 스위칭 소자로서 사용된다. 박막트랜지스터는 예를 들어 도 1f에 도시된 구조를 가질 수 있다. 도 1f에서 절연기판(10) 상에 게이트 전극(2)이 배치되고, 게이트 전극(2) 상에 게이트 절연층(3)이 배치되고, 게이트 절연층(3) 상에 일반적으로 도핑되지 않은 진성반도체층인 채널층(4)이 배치되고, 상기 채널층(4) 상에 일반적으로 도핑된 반도체층인 오믹콘택층(5a, 5b)이 배치되고, 상기 오믹콘택층(5) 상에 드레인/소스 전극(6a, 6b)이 배치된다.A thin film transistor, which is a kind of electronic device, is used as a switching element in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor may have, for example, a structure shown in FIG. 1F. In FIG. 1F, the gate electrode 2 is disposed on the insulating substrate 10, the gate insulating layer 3 is disposed on the gate electrode 2, and generally undoped intrinsic on the gate insulating layer 3. A channel layer 4, which is a semiconductor layer, is disposed, and ohmic contact layers 5a, 5b, which are generally doped semiconductor layers, are disposed on the channel layer 4, and a drain / on the ohmic contact layer 5 is disposed. Source electrodes 6a and 6b are disposed.
도 1f의 이격된 드레인/소스 전극(6a, 6b) 및 이격된 오믹콘택층(5a, 5b)은 도 1d에서 전극층(6) 및 오믹콘택층(5)을 순차적으로 식각함에 의하여 얻어진다. 전극층(6)의 식각에는 습식 식각이 사용되고, 오믹콘택층(5)의 식각에는 건식 식각이 사용된다. 따라서, 제조 공정이 복잡하다.The spaced drain / source electrodes 6a, 6b and spaced ohmic contact layers 5a, 5b of FIG. 1F are obtained by sequentially etching the electrode layer 6 and the ohmic contact layer 5 in FIG. 1D. Wet etching is used to etch the electrode layer 6, and dry etching is used to etch the ohmic contact layer 5. Therefore, the manufacturing process is complicated.
종래의 식각액은 오믹콘택층(5)보다 게이트 절연층(3), 절연기판(10), 채널층(4) 등에 대하여 더 높은 식각 성능을 나타내었다. 따라서, 오믹콘택층(5)의 식각에 습식 식각이 적용되지 못하였다.The conventional etchant has higher etching performance than the ohmic contact layer 5 with respect to the gate insulating layer 3, the insulating substrate 10, the channel layer 4, and the like. Therefore, the wet etching was not applied to the etching of the ohmic contact layer 5.
본 발명의 한 측면은 새로운 조성을 가지는 식각액을 제공하는 것이다.One aspect of the present invention is to provide an etchant having a new composition.
본 발명의 다른 측면은 상기 식각액을 사용하는 전자소자 제조방법을 제공하는 것이다.Another aspect of the present invention to provide an electronic device manufacturing method using the etchant.
본 발명의 한 측면에 따라According to one aspect of the invention
전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각하는 식각액으로서,An etching solution for selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer,
전이금속, 전이금속염 또는 이들의 혼합물; 및Transition metals, transition metal salts or mixtures thereof; And
불산, 불소를 포함하는 무기염 또는 이들의 혼합물;을 포함하는 식각액이 제공된다.An etchant comprising; hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof.
본 발명의 다른 한 측면에 따라,According to another aspect of the invention,
전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각하는 단계를 포함하는 전자소자 제조방법으로서, 상기 식각 단계에 사용되는 식각액이A method of manufacturing an electronic device comprising selectively etching a doped semiconductor layer disposed between a metal electrode and an intrinsic semiconductor layer of an electronic device with respect to the intrinsic semiconductor layer, wherein the etchant used in the etching step is
전이금속, 전이금속염 또는 이들의 혼합물; 및Transition metals, transition metal salts or mixtures thereof; And
불산, 불소를 포함하는 무기염 또는 이들의 혼합물;을 포함하는 전자소자 제조방법이 제공된다.Provided are an electronic device manufacturing method including hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof.
본 발명의 한 측면에 따른 식각액은 전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각함에 의하여 전자소자 제조공정의 단순화, 제조공정의 효율성 증대, 생산비 절감, 및/또는 전자소자의 성능향상이 가능하다.The etchant according to an aspect of the present invention simplifies the manufacturing process of the electronic device and increases the efficiency of the manufacturing process by selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer. , Reduced production costs, and / or improved performance of electronic devices.
도 1a 내지 1f는 예시적인 일구현예에 따른 박막트랜지스터 제조 공정을 설명하기 위한 단면도이다.1A to 1F are cross-sectional views illustrating a thin film transistor manufacturing process according to an exemplary embodiment.
도 2는 평가예 1에서 사용된 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 2 is a scanning electron micrograph of the thin film transistor used in Evaluation Example 1. FIG.
도 3은 실시예 1의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.3 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 1;
도 4은 실시예 2의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 4 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 2. FIG.
도 5은 실시예 3의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 5 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 3. FIG.
도 6은 실시예 4의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 6 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 4. FIG.
도 7은 실시예 5의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 7 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 5. FIG.
도 8은 실시예 6의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 8 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 6. FIG.
도 9은 실시예 7의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 9 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 7.
도 10은 실시예 8의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 10 is a scanning electron micrograph of the thin film transistor after etching with the etchant of Example 8.
도 11은 실시예 9의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 11 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 9. FIG.
도 12은 실시예 10의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.12 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 10.
도 13은 실시예 11의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 13 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 11. FIG.
도 14은 실시예 12의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 14 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 12. FIG.
도 15은 실시예 13의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 15 is a scanning electron micrograph of a thin film transistor after being etched with the etchant of Example 13. FIG.
도 16은 실시예 14의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.16 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 14.
도 17은 실시예 15의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.FIG. 17 is a scanning electron micrograph of a thin film transistor after etching with an etchant of Example 15. FIG.
도 18은 실시예 16의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.18 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Example 16.
도 19는 비교예 1의 식각액으로 식각된 후의 박막트랜지스터에 대한 주사전자현미경 사진이다.19 is a scanning electron micrograph of a thin film transistor after etching with the etchant of Comparative Example 1.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
2...게이트 전극 3...절연막2 ... gate electrode 3 ... insulation film
4...진성반도체층(채널층) 5, 5a, 5b...도핑된 반도체층(오믹 오믹콘택층)4. Intrinsic semiconductor layer (channel layer) 5, 5a, 5b ... doped semiconductor layer (omic ohmic contact layer)
6...금속층 10...절연기판6 ... metal layer 10 ... insulation substrate
6a, 6b..소스/드레인 전극6a, 6b..source / drain electrodes
이하에서 예시적인 일 구현예에 따른 식각액 및 상기 식각액을 사용하는 전자소자 제조방법에 관하여 더욱 상세히 설명한다.Hereinafter, an etching solution and an electronic device manufacturing method using the etching solution according to an exemplary embodiment will be described in more detail.
예시적인 일 구현예에 따른 식각액은 전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각하는 식각액으로서, 전이금속, 전이금속염 또는 이들의 혼합물; 및 불산, 불소를 포함하는 무기염 또는 이들의 혼합물;을 포함한다.An etchant according to an exemplary embodiment is an etchant for selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer, a transition metal, a transition metal salt or a mixture thereof; And inorganic salts or mixtures thereof including hydrofluoric acid and fluorine.
상기 식각액에서 전이금속 또는 전이금속의 염에서 유래된 전이금속이온은 도핑된 반도체층에 대한 식각 속도를 선택적으로 향상시키는 역할을 한다. 따라서, 상기 진성반도체층에 대한 식각을 억제하면서 상기 도핑된 반도체층만을 선택적으로 식각시킬 수 있다. 상기 식각액은 상기 전자소자에 포함된 전극층, 전극절연층, 절연기판 등의 다른 층들에 대한 식각을 최소화하면서 도핑된 반도체층만을 선택적으로 식각할 수 있다.The transition metal ion derived from the transition metal or the salt of the transition metal in the etching solution serves to selectively improve the etching rate for the doped semiconductor layer. Therefore, only the doped semiconductor layer may be selectively etched while suppressing etching of the intrinsic semiconductor layer. The etchant may selectively etch only the doped semiconductor layer while minimizing etching of other layers such as an electrode layer, an electrode insulating layer, and an insulating substrate included in the electronic device.
이와 달리, 전이금속 또는 전이금속염이 없이 불산 또는 불소 등을 포함하는 종래의 식각액을 사용하면, 상기 도핑된 반도체층이 거의 식각되지 않으며, 오히려 전극층, 전극 절연층, 절연기판 등이 식각될 수 있다.On the contrary, when using a conventional etchant including hydrofluoric acid or fluorine without a transition metal or a transition metal salt, the doped semiconductor layer is hardly etched, but rather an electrode layer, an electrode insulating layer, an insulating substrate, etc. may be etched. .
예를 들어, 상기 식각액에서 상기 전이금속, 전이금속염 또는 이들의 혼합물의 함량은 상기 식각액 총 중량을 기준으로 0.005 내지 30중량%일 수 있다. 예를 들어, 상기 전이금속, 전이금속염 또는 이들의 혼합물의 함량은 상기 식각액 총 중량을 기준으로 0.05 내지 20중량%일 수 있다. 예를 들어, 상기 전이금속, 전이금속염 또는 이들의 혼합물의 함량은 상기 식각액 총 중량을 기준으로 0.01 내지 10중량%일 수 있다.For example, the content of the transition metal, the transition metal salt, or a mixture thereof in the etching solution may be 0.005 to 30% by weight based on the total weight of the etching solution. For example, the content of the transition metal, the transition metal salt or a mixture thereof may be 0.05 to 20% by weight based on the total weight of the etching solution. For example, the content of the transition metal, the transition metal salt or a mixture thereof may be 0.01 to 10% by weight based on the total weight of the etching solution.
예를 들어, 상기 식각액에서 상기 불산, 불소를 포함하는 무기염 또는 이들의 혼합물의 함량은 상기 식각액 총 중량을 기준으로 0.05 내지 30중량%일 수 있다. 예를 들어, 상기 불산, 불소를 포함하는 무기염 또는 이들의 혼합물의 함량은 상기 식각액 총 중량을 기준으로 0.05 내지 20중량%일 수 있다. 예를 들어, 상기 불산, 불소를 포함하는 무기염 또는 이들의 혼합물의 함량은 상기 식각액 총 중량을 기준으로 0.05 내지 10중량%일 수 있다.For example, the content of the inorganic salt containing hydrofluoric acid and fluorine or a mixture thereof in the etching solution may be 0.05 to 30% by weight based on the total weight of the etching solution. For example, the content of the hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof may be 0.05 to 20% by weight based on the total weight of the etching solution. For example, the amount of the hydrofluoric acid, an inorganic salt including fluorine, or a mixture thereof may be 0.05 to 10 wt% based on the total weight of the etching solution.
예를 들어, 상기 식각액은 상기 전이금속, 전이금속염 또는 이들의 혼합물 0.005 내지 30 중량%; 상기 불산, 불소을 포함하는 무기염 또는 이들의 혼합물 0.05 내지 30 중량%; 및 물 40 내지 99.945중량%를 포함할 수 있다.For example, the etchant may include 0.005 to 30% by weight of the transition metal, the transition metal salt or a mixture thereof; 0.05 to 30% by weight of an inorganic salt or a mixture thereof containing hydrofluoric acid and fluorine; And 40 to 99.945% by weight of water.
상기 식각액에서 상기 전이금속은 Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, 란탄족 원소, 및 악티늄족 원소로 이루어진 군에서 선택된 하나 이상일 수 있다. 예를 들어, 상기 전이금속은 Cu일 수 있다.The transition metal in the etchant is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta It may be at least one selected from the group consisting of, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinides. For example, the transition metal may be Cu.
상기 식각액에서 상기 전이금속염은 Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, 란탄족 원소, 및 악티늄족 원소로 이루어진 군에서 선택된 1종 이상의 금속의 이온을 포함하는 전이금속염일 수 있다.The transition metal salt in the etchant is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta It may be a transition metal salt containing ions of at least one metal selected from the group consisting of W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinium elements.
상기 식각액에서 상기 전이금속염은 CuSO4, Cu(NO3)2, CuO, (CH3CO2)2Cu, 구리글루코네이트(Copper Gluconate), CuCl, CuCl2, CuF2, Cu(OH)2, Cu2S, Fe(NO3)3, FeSO4, Ni(NO3)2, NiSO4, AgNO3, Ag2SO4, (CH3C02)2Co, (CH3CO2)2Pd, Pd(NO3)2, Rh(CH3CO2)2, Rh2O3 등으로 이루어진 군에서 선택된 하나 이상일 수 있다. 예를 들어, 상기 전이금속염은 CuSO4일 수 있다.In the etchant, the transition metal salt is CuSO 4 , Cu (NO 3 ) 2 , CuO, (CH 3 CO 2 ) 2 Cu, Copper Gluconate, CuCl, CuCl 2 , CuF 2 , Cu (OH) 2 , Cu 2 S, Fe (NO 3 ) 3 , FeSO 4 , Ni (NO 3 ) 2 , NiSO 4 , AgNO 3 , Ag 2 SO 4 , (CH 3 CO 2 ) 2 Co, (CH 3 CO 2 ) 2 Pd, Pd (NO 3) 2, Rh (CH 3 CO 2) 2, may be at least one selected from the group consisting of such as Rh 2 O 3. For example, the transition metal salt may be CuSO 4 .
상기 식각액에서 상기 불소를 포함하는 무기염은 KF, LiF, NaF, RbF, CsF, MgF2, NH4F, H2SiF6, NaHF2, NH4F, NH4HF2, NH4BF4, KHF2, AlF3, HBF4등의 불소를 포함하는 무기염에서 선택된 하나 이상일 수 있다. 상기 불소를 포함하는 무기염은 불산과 혼합되어 사용될 수 있다.The inorganic salt containing fluorine in the etchant is KF, LiF, NaF, RbF, CsF, MgF 2 , NH 4 F, H 2 SiF 6 , NaHF 2 , NH 4 F, NH 4 HF 2 , NH 4 BF 4 , It may be at least one selected from inorganic salts including fluorine such as KHF 2 , AlF 3 , HBF 4 . The inorganic salt containing fluorine may be used in admixture with hydrofluoric acid.
예를 들어, 상기 식각액은 상기 구리 또는 구리염 0.01 내지 10 중량%, 상기 불산 또는 불소를 포함하는 무기염 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함할 수 있다.For example, the etching solution may include 0.01 to 10% by weight of the copper or copper salt, 0.05 to 10% by weight of an inorganic salt including hydrofluoric acid or fluorine, and 80 to 99.94% by weight of water.
예를 들어, 상기 식각액은 CuSO4 0.01 내지 10 중량%, HF 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함할 수 있다.For example, the etchant may include 0.01 to 10% by weight of CuSO 4 , 0.05 to 10% by weight of HF, and 80 to 99.94% by weight of water.
상기 식각액을 사용하여 제조되는 전자소자에서 상기 진성반도체층이 비정질 실리콘일 수 있다. 또한, 상기 도핑된 반도체층이 n-타입 도판트로 도핑된 비정질 실리콘일 수 있다. 예를 들어, 상기 도핑된 반도체층은 n+ 비정질 실리콘(n+a-Si:H)일 수 있다. 상기 n-타입 도판트는 실리콘보다 최외각 전자가 많은 주기율표 5A족 원소일 수 있다. 예를 들어, P, As, Sb 등일 수 있다. 상기 n-타입 도판트가 도핑되는 함량은 50몰% 미만일 수 있다.In the electronic device manufactured using the etchant, the intrinsic semiconductor layer may be amorphous silicon. In addition, the doped semiconductor layer may be amorphous silicon doped with an n-type dopant. For example, the doped semiconductor layer may be n + amorphous silicon (n + a-Si: H). The n-type dopant may be a Periodic Table 5A element having more outermost electrons than silicon. For example, it may be P, As, Sb and the like. The content of the n-type dopant may be less than 50 mol%.
상기 식각액을 사용하여 제조되는 전자소자는 박막트랜지스터일 수 있으나, 반드시 박막트랜지스터로 한정되지 않으며 당해 기술분야에서 사용될 수 있는 전자소자라면 모두 사용 가능하다.The electronic device manufactured using the etchant may be a thin film transistor, but is not necessarily limited to the thin film transistor, and any electronic device that may be used in the art may be used.
상기 박막트랜지스터는 예를 들어 도 1f의 구조를 가질 수 있다. 도 1f에서 절연기판(10)은 유리일 수 있으나, 반드시 유리로 한정되지 않으며 폴리카보네이트, 수정 등 당해 기술분야에서 기판으로 사용될 수 있는 것이라면 모두 사용 가능하다. 도 1f에서 게이트 전극(2)은 몰리브데늄, 알루미늄, 니오브늄, 이들의 합금 등의 도전성 금속일 수 있으나, 반드시 금속으로 한정되지 않으며 당해 기술 분야에서 전극 재료로 사용될 수 있는 것이라면 모두 사용 가능하다. 도 1f에서 게이트 절연층(3)은 실리콘질화물(SiNx)일 수 있으나, 반드시 이들로 한정되는 것은 아니며 당해 기술분야에서 게이트 전극의 절연층으로 사용될 수 있는 것이라면 모두 사용 가능하다. 도 1f에서 반도체층 (4)은 도핑되지 않은 진성반도체층으로서 비정질 실리콘일 수 있으나, 반드시 비정질 실리콘으로 한정되지 않으면 당해 기술분야에서 진성반도체층으로 사용될 수 있는 것이라면 모두 사용가능하다. 도 1f에서 반도체층(4)은 박막트랜지스터에서 채널층의 역할을 한다. 도 1f에서 오믹콘택층(5a, 5b)는 n-타입 도판트로 도핑된 반도체층으로서 n+비정질실리콘일 수 있으나, 반드시 이것으로 한정되지 않으며 당해 기술분야에서 오믹콘택층으로서 역할을 수행할 수 있는 재료라면 모두 사용 가능하다.The thin film transistor may have the structure of FIG. 1F, for example. In FIG. 1F, the insulating substrate 10 may be glass, but is not necessarily limited to glass, and may be used as long as the insulating substrate 10 may be used as a substrate in the art, such as polycarbonate and quartz. In FIG. 1F, the gate electrode 2 may be a conductive metal such as molybdenum, aluminum, niobium, or an alloy thereof. However, the gate electrode 2 may be used as long as it is not limited to a metal and may be used as an electrode material in the art. . In FIG. 1F, the gate insulating layer 3 may be silicon nitride (SiNx). However, the gate insulating layer 3 may be used as long as it can be used as an insulating layer of the gate electrode in the art. In FIG. 1F, the semiconductor layer 4 may be amorphous silicon as an undoped intrinsic semiconductor layer, but may be used as long as it is not necessarily limited to amorphous silicon as long as it can be used as an intrinsic semiconductor layer in the art. In FIG. 1F, the semiconductor layer 4 serves as a channel layer in the thin film transistor. In FIG. 1F, the ohmic contact layers 5a and 5b may be n + amorphous silicon as a semiconductor layer doped with an n-type dopant, but are not limited thereto, and may serve as an ohmic contact layer in the art. All ramen can be used.
본 발명의 다른 한 측면에 따른 전자소자 제조방법은 전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각하는 단계를 포함하며, 상기 식각 단계에 사용되는 식각액이 전이금속, 전이금속염 또는 이들의 혼합물; 및 불산, 불소을 포함하는 무기염 또는 이들의 혼합물;을 포함한다.According to another aspect of the present invention, a method of manufacturing an electronic device includes selectively etching a doped semiconductor layer disposed between a metal electrode and an intrinsic semiconductor layer of an electronic device with respect to the intrinsic semiconductor layer. The etchant used may be a transition metal, a transition metal salt or a mixture thereof; And inorganic salts or mixtures thereof including hydrofluoric acid and fluorine.
예를 들어, 상기 제조방법에 사용되는 식각액은 상기 전이금속, 전이금속염 또는 이들의 혼합물 0.005 내지 30 중량%; 상기 불산, 불소을 포함하는 무기염 또는 이들의 혼합물 0.05 내지 30 중량%; 및 물 40 내지 99.945중량%를 포함할 수 있다.For example, the etching solution used in the preparation method may be 0.005 to 30% by weight of the transition metal, the transition metal salt or a mixture thereof; 0.05 to 30% by weight of an inorganic salt or a mixture thereof containing hydrofluoric acid and fluorine; And 40 to 99.945% by weight of water.
상기 제조방법에 사용되는 식각액에서 상기 전이금속은 Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, 란탄족 원소, 및 악티늄족 원소로 이루어진 군에서 선택된 하나 이상일 수 있다. 예를 들어, 상기 전이금속은 Cu일 수 있다.In the etching solution used in the preparation method, the transition metal is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, It may be at least one selected from the group consisting of Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinides. For example, the transition metal may be Cu.
상기 제조방법에 사용되는 식각액에서 상기 전이금속염은 Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, 란탄족 원소, 및 악티늄족 원소로 이루어진 군에서 선택된 1종 이상의 금속의 이온을 포함하는 전이금속염일 수 있다.The transition metal salt in the etching solution used in the preparation method is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, It may be a transition metal salt containing ions of at least one metal selected from the group consisting of Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinides.
상기 제조방법에 사용되는 식각액에서 상기 전이금속염은 CuSO4, Cu(NO3)2, CuO, (CH3CO2)2Cu, 구리글루코네이트(Copper Gluconate), CuCl, CuCl2, CuF2, Cu(OH)2, Cu2S, Fe(NO3)3, FeSO4, Ni(NO3)2, NiSO4, AgNO3, Ag2SO4, (CH3C02)2Co, (CH3CO2)2Pd, Pd(NO3)2, Rh(CH3CO2)2, Rh2O3 등으로 이루어진 군에서 선택된 하나 이상일 수 있다. 예를 들어, 상기 전이금속염은 CuSO4일 수 있다.In the etchant used in the preparation method, the transition metal salt is CuSO 4 , Cu (NO 3 ) 2 , CuO, (CH 3 CO 2 ) 2 Cu, Copper Gluconate, CuCl, CuCl 2 , CuF 2 , Cu (OH) 2 , Cu 2 S, Fe (NO 3 ) 3 , FeSO 4 , Ni (NO 3 ) 2 , NiSO 4 , AgNO 3 , Ag 2 SO 4 , (CH 3 CO 2 ) 2 Co, (CH 3 CO 2 ) 2 Pd, Pd (NO 3 ) 2 It may be one or more selected from the group consisting of Rh (CH 3 CO 2 ) 2 , Rh 2 O 3 and the like. For example, the transition metal salt may be CuSO 4 .
상기 제조방법에 사용되는 식각액에서 상기 불소을 포함하는 무기염이 KF, LiF, NaF, RbF, CsF, MgF2, NH4F, H2SiF6, NaHF2, NH4F, NH4HF2, NH4BF4, KHF2, AlF3, HBF4등의 불소를 포함하는 무기염에서 선택된 하나 이상일 수 있으며, 불산과 혼합되어 사용될 수 있다.In the etchant used in the preparation method, the inorganic salt containing fluorine is KF, LiF, NaF, RbF, CsF, MgF 2 , NH 4 F, H 2 SiF 6 , NaHF 2 , NH 4 F, NH 4 HF 2 , NH 4 BF 4 , KHF 2 , AlF 3 , may be one or more selected from inorganic salts containing fluorine, such as HBF 4 may be used in combination with hydrofluoric acid.
예를 들어, 상기 제조방법에 사용되는 식각액은 상기 구리 또는 구리염 0.01 내지 10 중량%, 상기 불산 또는 불소를 포함하는 무기염 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함할 수 있다.For example, the etching solution used in the preparation method may include 0.01 to 10% by weight of the copper or copper salt, 0.05 to 10% by weight of inorganic salt containing hydrofluoric acid or fluorine, and 80 to 99.94% by weight of water. .
예를 들어, 상기 제조방법에 사용되는 식각액은 CuSO4 0.01 내지 10 중량%, HF 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함할 수 있다.For example, the etching solution used in the preparation method may include 0.01 to 10% by weight of CuSO 4 , 0.05 to 10% by weight of HF, and 80 to 99.94% by weight of water.
상기 전자소자 제조방법에서 상기 진성반도체층이 비정질 실리콘일 수 있다. 또한, 상기 도핑된 반도체층이 n-타입 도판트로 도핑된 비정질 실리콘일 수 있다. 예를 들어, 상기 도핑된 반도체층은 n+ 비정질 실리콘(n+a-Si:H)일 수 있다. 상기 n-타입 도판트는 실리콘보다 최외각 전자가 많은 주기율표 5A족 원소일 수 있다. 예를 들어, P, As, Sb 등일 수 있다. 상기 n-타입 도판트가 도핑되는 함량은 50몰% 미만일 수 있다.In the electronic device manufacturing method, the intrinsic semiconductor layer may be amorphous silicon. In addition, the doped semiconductor layer may be amorphous silicon doped with an n-type dopant. For example, the doped semiconductor layer may be n + amorphous silicon (n + a-Si: H). The n-type dopant may be a Periodic Table 5A element having more outermost electrons than silicon. For example, it may be P, As, Sb and the like. The content of the n-type dopant may be less than 50 mol%.
상기 전자소자 제조방법에 의하여 제조되는 전자소자는 박막트랜지스터일 수 있으나, 반드시 박막트랜지스터로 한정되지 않으며 당해 기술분야에서 사용될 수 있는 전자소자라면 모두 사용 가능하다.The electronic device manufactured by the electronic device manufacturing method may be a thin film transistor, but is not necessarily limited to the thin film transistor, and any electronic device that may be used in the art may be used.
상기 전자소자의 일 구현예인 박막트랜지스터의 제조방법은 상기 식각 단계 전에 절연기판 상에 게이트 전극을 배치하는 단계; 상기 게이트 전극 상에 절연층, 진성반도체층 및 도핑된 반도체층을 순차적으로 배치하는 단계; 및 상기 도핑된 반도체층 상에 서로 이격된 드레인 전극 및 소스 전극을 배치하는 단계;를 포함할 수 있다.In one embodiment, a method of manufacturing a thin film transistor includes disposing a gate electrode on an insulating substrate before the etching step; Sequentially placing an insulating layer, an intrinsic semiconductor layer, and a doped semiconductor layer on the gate electrode; And disposing a drain electrode and a source electrode spaced apart from each other on the doped semiconductor layer.
상기 절연기판 상에 게이트 전극을 배치하는 단계는 절연기판 상에 금속막을 형성한 다음 상기 금속막을 식각하여 형성함에 의하여 수행될 수 있다.The step of disposing a gate electrode on the insulating substrate may be performed by forming a metal film on the insulating substrate and then etching the metal film.
상기 게이트 전극 상에 절연층, 진성반도체층 및 도핑된 반도체층을 순차적으로 배치하는 단계는 상기 층들을 순차적으로 스퍼터링, 화학적기상층착, 물리적기상증착, 등의 방법으로 형성시킴에 의하여 수행될 수 있다.Arranging the insulating layer, the intrinsic semiconductor layer, and the doped semiconductor layer in sequence on the gate electrode may be performed by sequentially forming the layers by sputtering, chemical vapor deposition, physical vapor deposition, or the like. .
상기 도핑된 반도체층 상에 서로 이격된 드레인 전극 및 소스 전극을 배치하는 단계는 상기 도핑된 반도체층 상에 금속막을 형성시킨 후 상기 금속막만을 부분적으로 식각시킴에 의하여 수행될 수 있다. 상기 식각은 습식 식각에 의하여 수행될 수 있다.The disposing the drain electrode and the source electrode spaced apart from each other on the doped semiconductor layer may be performed by forming a metal film on the doped semiconductor layer and partially etching only the metal film. The etching may be performed by wet etching.
도 1a 내지 1f를 참조하여 상기 박막트랜지스터의 제조방법의 일 구현예를 구체적으로 설명한다.An embodiment of the method of manufacturing the thin film transistor will be described in detail with reference to FIGS. 1A to 1F.
도 1에서 보여지는 바와 같이, 먼저 절연기판(10) 상에 금속막(2)이 형성된다. 상기 금속막(2)은 AlNd 계열의 금속막일 수 있다. 상기 금속막(2)을 보호하기 위하여 몰리브덴 금속막이 추가적으로 형성될 수 있으나, 도면에는 도시되지 않는다. 상기 금속막(2)의 형성은 예를 들어 스퍼터링 방식으로 증착될 수 있다.As shown in FIG. 1, a metal film 2 is first formed on an insulating substrate 10. The metal film 2 may be an AlNd-based metal film. A molybdenum metal film may be additionally formed to protect the metal film 2, but is not shown in the drawing. Formation of the metal film 2 may be deposited, for example, by a sputtering method.
이어서, 상기 절연기판(10)의 전 영역 상에 포토레지스트막을 형성한 다음, 노광, 현상 및 식각 공정을 진행하여 도 1b에서 보여지는 바와 같이 게이트 전극(2)이 형성된다. 상기 게이트 전극(2)에 연결된 게이트 배선과 게이트 패드도 동시에 형성되나 도면에는 도시되지 않는다.Subsequently, a photoresist film is formed on the entire region of the insulating substrate 10, and then the exposure, development, and etching processes are performed to form the gate electrode 2 as shown in FIG. 1B. A gate line and a gate pad connected to the gate electrode 2 are also formed at the same time, but are not shown in the drawing.
상기 게이트 전극이 형성된 후, 도 1c에 보여지는 바와 같이 상기 절연기판(10)의 전 영역에 게이트 절연막(3), 진성반도체층(4), 도핑된 반도체층(5)이 순차적으로 형성된다. 이어서, 포토리소그라피 공정에 따라 식각하여 상기 게이트 전극 상에 채널층(4)을 형성한다. 상기 채널층(4) 상에는 도핑된 반도체층(5)이 남아 있다.After the gate electrode is formed, as shown in FIG. 1C, the gate insulating layer 3, the intrinsic semiconductor layer 4, and the doped semiconductor layer 5 are sequentially formed in the entire region of the insulating substrate 10. Subsequently, the channel layer 4 is formed on the gate electrode by etching according to a photolithography process. The doped semiconductor layer 5 remains on the channel layer 4.
이어서, 도 1d에 보여지는 바와 같이 상기 도핑된 반도체층(5) 상에 금속막(6)을 증착한다.Subsequently, a metal film 6 is deposited on the doped semiconductor layer 5 as shown in FIG. 1D.
이어서, 도 1e에 보여지는 바와 같이, 상기 금속막(6)을 습식 식각하여 이격된 소스/드레인 전극(6a, 6b)을 형성한다.Subsequently, as shown in FIG. 1E, the metal film 6 is wet etched to form spaced source / drain electrodes 6a and 6b.
이어서, 도 1f에 보여지는 바와 같이 상술한 본 발명의 일 구현예에 따른 식각액을 사용하여 진성반도체층(4)에 대하여 도핑된 반도체층(5)만을 선택적으로 식각하여 진성반도체층(4)이 노출되도록 한다.Subsequently, as shown in FIG. 1F, only the semiconductor layer 5 doped with respect to the intrinsic semiconductor layer 4 is selectively etched using the etchant according to the exemplary embodiment of the present invention described above, thereby forming the intrinsic semiconductor layer 4. To be exposed.
이하 실시예를 들어 본 발명을 더욱 상세히 설명한다. 아래 실시예들에 나타낸 구성은 어디까지나 발명의 이해를 돕기 위함이며 어떠한 경우에도 본 발명의 기술적 범위를 실시예에서 제시한 실시 태양으로 제한하려는 것이 아님을 밝혀 둔다.The present invention will be described in more detail with reference to the following Examples. The configuration shown in the following examples are intended to help the understanding of the invention to the last, and in no case to limit the technical scope of the present invention to the embodiments presented in the examples.
(식각액 조성물 제조)(Etch Composition)
실시예 1 내지 4 및 비교예 1Examples 1 to 4 and Comparative Example 1
본 발명의 식각액 조성물에 따른 실시예 1 내지 16 및 비교예 1의 식각액을 아래 표 1과 같이 제조하였다. 실시예 1 내지 16 및 비교예 1의 조성은 표 1에 나타내었다. 하기 표 1에서 전이금속, 전이금속염 또는 이들의 혼합물을 제 1 성분이라고 하고, 불산, 불소를 포함하는 무기염 또는 이들의 혼합물을 제 2 성분이라고 한다.The etchant of Examples 1 to 16 and Comparative Example 1 according to the etchant composition of the present invention was prepared as shown in Table 1 below. The compositions of Examples 1 to 16 and Comparative Example 1 are shown in Table 1. In Table 1 below, the transition metal, the transition metal salt or a mixture thereof is referred to as a first component, and an inorganic salt containing hydrofluoric acid and fluorine or a mixture thereof is referred to as a second component.
실시예 1에서 사용된 제 1 성분은 CuSO4, 제 2 성분은 불산(HF)이었다. The first component used in Example 1 was CuSO 4 and the second component was hydrofluoric acid (HF).
실시예 2에서 사용된 제 1 성분은 Cu(NO3)2, 제 2 성분은 불산이었다. The first component used in Example 2 was Cu (NO 3 ) 2 and the second component was hydrofluoric acid.
실시예 3에서 사용된 제 1 성분은 Fe(NO3)3, 제 2 성분은 불산이었다. The first component used in Example 3 was Fe (NO 3 ) 3 and the second component was hydrofluoric acid.
실시예 4에서 사용된 제 1 성분은 AgSO4, 제 2 성분은 불산이었다. The first component used in Example 4 was AgSO 4 , and the second component was hydrofluoric acid.
실시예 5에서 사용된 제 1 성분은 (CH3CO2)2Cu, 제 2 성분은 KF이었다.The first component used in Example 5 was (CH 3 CO 2 ) 2 Cu and the second component was KF.
실시예 6에서 사용된 제 1 성분은 CuCl2, 제 2 성분은 LiF이었다.The first component used in Example 6 was CuCl 2 and the second component was LiF.
실시예 7에서 사용된 제 1 성분은 CuF2, 제 2 성분은 NaF이었다.The first component used in Example 7 was CuF 2 and the second component was NaF.
실시예 8에서 사용된 제 1 성분은 FeSO, 제 2 성분은 NH4F이었다.The first component used in Example 8 was FeSO and the second component was NH 4 F.
실시예 9에서 사용된 제 1 성분은 Ni(NO3)2, 제 2 성분은 H2SiF6이었다.The first component used in Example 9 was Ni (NO 3 ) 2 and the second component was H 2 SiF 6 .
실시예 10에서 사용된 제 1 성분은 (CH3C02)2Co, 제 2 성분은 NaHF2이었다.The first component used in Example 10 was (CH 3 CO 2 ) 2 Co and the second component was NaHF 2 .
실시예 11에서 사용된 제 1 성분은 (CH3CO2)2Pd, 제 2 성분은 NH4HF2이었다.The first component used in Example 11 was (CH 3 CO 2 ) 2 Pd and the second component was NH 4 HF 2 .
실시예 12에서 사용된 제 1 성분은 Pd(NO3)2, 제 2 성분은 NH4BF4이었다.The first component used in Example 12 was Pd (NO 3 ) 2 and the second component was NH 4 BF 4 .
실시예 13에서 사용된 제 1 성분은 Rh(CH3CO2)2, 제 2 성분은 KHF2이었다.The first component used in Example 13 was Rh (CH 3 CO 2 ) 2 and the second component was KHF 2 .
실시예 14에서 사용된 제 1 성분은 AgNO3, 제 2 성분은 AlF3이었다.The first component used in Example 14 was AgNO 3 , and the second component was AlF 3 .
실시예 15에서 사용된 제 1 성분은 Cu2S, 제 2 성분은 HBF4이었다.The first component used in Example 15 was Cu 2 S and the second component was HBF 4 .
실시예 16에서 사용된 제 1 성분은 NiSO4, 제 2 성분은 MgF2이었다.The first component used in Example 16 was NiSO 4 and the second component was MgF 2 .
표 1
성분 제 1 성분[중량%] 제 2 성분[중량%] 물[중량%]
실시예 1 0.5 0.3 99.2
실시예 2 0.5 0.3 99.2
실시예 3 3 0.3 96.7
실시예 4 1 0.3 98.7
실시예 5 10 10 80
실시예 6 5 10 80
실시예 7 0.05 3 96.95
실시예 8 2 1 97
실시예 9 5 10 85
실시예 10 3 2 95
실시예 11 2 1 97
실시예 12 0.5 2 97.5
실시예 13 0.3 3 96.7
실시예 14 3 10 87
실시예 15 1 5 94
실시예 16 1 7 92
비교예 1 0 0.3 99.7
Table 1
ingredient First component [% by weight] Second component [% by weight] Water [wt%]
Example 1 0.5 0.3 99.2
Example 2 0.5 0.3 99.2
Example 3 3 0.3 96.7
Example 4 One 0.3 98.7
Example 5 10 10 80
Example 6 5 10 80
Example 7 0.05 3 96.95
Example 8 2 One 97
Example 9 5 10 85
Example 10 3 2 95
Example 11 2 One 97
Example 12 0.5 2 97.5
Example 13 0.3 3 96.7
Example 14 3 10 87
Example 15 One 5 94
Example 16 One 7 92
Comparative Example 1 0 0.3 99.7
평가예 1 : 식각액의 식각 능력 평가Evaluation Example 1 Evaluation of Etching Ability of Etching Liquid
도 2의 구조를 가지는 박막 트랜지스터가 준비되었다. 기판은 유리, 절연막은 실리콘질화물(SiNx), 진성반도체층은 비정질실리콘(a-Si:H), 도핑된 반도체층은 n+비정질 실리콘(n+a-Si:H), 소스/드레인(S/D) 전극은 몰리브데늄(Molybdenum)이다.A thin film transistor having the structure of FIG. 2 was prepared. Substrate is glass, insulating film is silicon nitride (SiNx), intrinsic semiconductor layer is amorphous silicon (a-Si: H), doped semiconductor layer is n + amorphous silicon (n + a-Si: H), source / drain (S / D) The electrode is molybdenum (Molybdenum).
상기 박막 트렌지스트를 상기 실시예 1 내지 16의 식각액 및 비교예 1의 식각액을 사용하여 식각한 결과를 도 3 ~ 18 및 도 19에 나타내었다.The thin film transistor is etched using the etchant of Examples 1 to 16 and the etchant of Comparative Example 1 is shown in Figures 3 to 18 and 19.
도 3 ~ 18은 실시예 1 ~ 16의 식각액을 사용하여 식각한 후의 박막트랜지스터에 대한 주사전자현미경 사진이고, 도 19는 비교예 1의 식각액을 사용하여 식각한 후의 박막트랜지스터에 대한 주사전자현미경 사진이다. 도 3 ~ 18에서 각각 세개의 사진들은 도 2에서 ①, ②, ③의 위치의 확대도이다.3 to 18 are scanning electron micrographs of the thin film transistors after etching using the etchant of Examples 1 to 16, and FIG. 19 is a scanning electron micrograph of the thin film transistors after etching using the etchant of Comparative Example 1 to be. Three photographs in FIGS. 3 to 18 are enlarged views of positions ①, ②, and ③ in FIG. 2.
도 3 ~ 18에 보여지는 바와 같이 실시예 1 ~ 16의 식각액을 사용한 경우에 n+비정질 실리콘만이 선택적으로 식각되어 비정질 실리콘층(a-Si:H)이 노출되었다.As shown in FIGS. 3 to 18, only the n + amorphous silicon was selectively etched when the etchant of Examples 1 to 16 was used to expose the amorphous silicon layer (a-Si: H).
이에 비해, 도 19에 보여지는 바와 같이 비교예 1의 식각액을 사용한 경우에는 n+비정질 실리콘층(n+a-Si:H)이 그대로 유지되었고 대신 절연막이 식각되었다.In contrast, when the etchant of Comparative Example 1 was used as shown in FIG. 19, the n + amorphous silicon layer (n + a-Si: H) was maintained as it was and the insulating film was etched instead.
따라서, 실시에 1 ~ 18의 식각액은 비교예 1에 비하여 선택성이 현저히 향상되었다.Therefore, the etching liquids of Examples 1 to 18 significantly improved selectivity compared to Comparative Example 1.
본 발명의 한 측면에 따른 식각액은 전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각함에 의하여 전자소자 제조공정의 단순화, 제조공정의 효율성 증대, 생산비 절감, 및/또는 전자소자의 성능향상이 가능하다.The etchant according to an aspect of the present invention simplifies the manufacturing process of the electronic device and increases the efficiency of the manufacturing process by selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer. , Reduced production costs, and / or improved performance of electronic devices.

Claims (21)

  1. 전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각하는 식각액으로서,An etching solution for selectively etching the doped semiconductor layer disposed between the metal electrode and the intrinsic semiconductor layer of the electronic device with respect to the intrinsic semiconductor layer,
    전이금속, 전이금속염 또는 이들의 혼합물; 및Transition metals, transition metal salts or mixtures thereof; And
    불산, 불소를 포함하는 무기염 또는 이들의 혼합물;을 포함하는 식각액.An etchant comprising hydrofluoric acid, an inorganic salt containing fluorine, or a mixture thereof.
  2. 제 1 항에 있어서,The method of claim 1,
    상기 전이금속, 전이금속염 또는 이들의 혼합물 0.005 내지 30 중량%;0.005 to 30% by weight of the transition metal, the transition metal salt or a mixture thereof;
    상기 불산, 불소를 포함하는 무기염 또는 이들의 혼합물 0.05 내지 30 중량%; 및0.05 to 30% by weight of the inorganic salt including hydrofluoric acid and fluorine or mixtures thereof; And
    잔량의 물;을 포함하는 식각액.Etch liquid containing a residual amount of water.
  3. 제 1 항에 있어서, 상기 전이금속이 Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, 란탄족 원소, 및 악티늄족 원소로 이루어진 군에서 선택된 1종 이상인 식각액.The method of claim 1, wherein the transition metal is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, At least one etchant selected from the group consisting of Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, lanthanide elements, and actinium elements.
  4. 제 1 항에 있어서, 상기 전이금속염이 CuSO4, Cu(NO3)2, CuO, (CH3CO2)2Cu, 구리글루코네이트(Copper Gluconate), CuCl, CuCl2, CuF2, Cu(OH)2, Cu2S, Fe(NO3)3, FeSO4, Ni(NO3)2, NiSO4, AgNO3, Ag2SO4, (CH3C02)2Co, (CH3CO2)2Pd, Pd(NO3)2, Rh(CH3CO2)2, 및 Rh2O3로 이루어진 군에서 선택된 1종 이상인 식각액.The method of claim 1, wherein the transition metal salt is CuSO 4 , Cu (NO 3 ) 2 , CuO, (CH 3 CO 2 ) 2 Cu, Copper Gluconate, CuCl, CuCl 2 , CuF 2 , Cu (OH ) 2 , Cu 2 S, Fe (NO 3 ) 3 , FeSO 4 , Ni (NO 3 ) 2 , NiSO 4 , AgNO 3 , Ag 2 SO 4 , (CH 3 CO 2 ) 2 Co, (CH 3 CO 2 ) At least one etching solution selected from the group consisting of 2 Pd, Pd (NO 3 ) 2 , Rh (CH 3 CO 2 ) 2 , and Rh 2 O 3 .
  5. 제 1 항에 있어서, 상기 불소를 포함하는 무기염이 KF, LiF, NaF, RbF, CsF, NH4F, NH4FㅇHF, HBF4, 및 H2SiF6로 이루어진 군에서 선택된 1종 이상인 식각액.According to claim 1, wherein the inorganic salt containing fluorine is at least one selected from the group consisting of KF, LiF, NaF, RbF, CsF, NH 4 F, NH 4 FHHF, HBF 4 , and H 2 SiF 6 . Etchant.
  6. 제 1 항에 있어서, 구리 또는 구리염 0.01 내지 10 중량%, 불산 또는 불소를 포함하는 무기염 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함하는 식각액.The etchant according to claim 1, comprising 0.01 to 10% by weight of copper or copper salt, 0.05 to 10% by weight of inorganic salt containing hydrofluoric acid or fluorine, and 80 to 99.94% by weight of water.
  7. 제 1 항에 있어서, CuSO4 0.01 내지 10 중량%, HF 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함하는 식각액.The etchant according to claim 1, comprising 0.01 to 10% by weight of CuSO 4 , 0.05 to 10% by weight of HF, and 80 to 99.94% by weight of water.
  8. 제 1 항에 있어서, 상기 진성반도체층이 비정질 실리콘인 식각액.The etchant of claim 1, wherein the intrinsic semiconductor layer is amorphous silicon.
  9. 제 1 항에 있어서, 상기 도핑된 반도체층이 n-타입 도판트로 도핑된 비정질 실리콘인 식각액.The etchant of claim 1, wherein the doped semiconductor layer is amorphous silicon doped with an n-type dopant.
  10. 제 1 항에 있어서, 상기 전자소자가 박막 트랜지스터인 식각액.The etchant of claim 1, wherein the electronic device is a thin film transistor.
  11. 전자소자의 금속전극과 진성반도체층 사이에 배치된 도핑된 반도체층을 상기 진성반도체층에 대하여 선택적으로 식각하는 단계를 포함하는 전자소자 제조방법으로서, 상기 식각 단계에 사용되는 식각액이A method of manufacturing an electronic device comprising selectively etching a doped semiconductor layer disposed between a metal electrode and an intrinsic semiconductor layer of an electronic device with respect to the intrinsic semiconductor layer, wherein the etchant used in the etching step is
    전이금속, 전이금속염 또는 이들의 혼합물; 및Transition metals, transition metal salts or mixtures thereof; And
    불산, 불소를 포함하는 무기염 또는 이들의 혼합물;을 포함하는 전자소자 제조방법.Fluoric acid, inorganic salts containing fluorine or a mixture thereof; manufacturing method of an electronic device comprising a.
  12. 제 11 항에 있어서, 상기 식각액이The method of claim 11, wherein the etchant
    상기 전이금속, 전이금속염 또는 이들의 혼합물 0.005 내지 30 중량%;0.005 to 30% by weight of the transition metal, the transition metal salt or a mixture thereof;
    상기 불산, 불소를 포함하는 무기염 또는 이들의 혼합물 0.05 내지 30 중량%; 및0.05 to 30% by weight of an inorganic salt or a mixture thereof containing hydrofluoric acid and fluorine; And
    잔량의 물;을 포함하는 전자소자 제조방법.Electronic device manufacturing method comprising a residual amount of water.
  13. 제 11 항에 있어서, 상기 전이금속이 Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, 란탄족 원조, 및 악티늄족 원소로 이루어진 군에서 선택된 1종 이상인 전자소자 제조방법.The method of claim 11, wherein the transition metal is Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Lanthanide Aid, Actinium group element is at least one selected from the group consisting of electronic device manufacturing method.
  14. 제 11 항에 있어서, 상기 전이금속염이 CuSO4, Cu(NO3)2, CuO, (CH3CO2)2Cu, 구리글루코네이트(Copper Gluconate), CuCl, CuCl2, CuF2, Cu(OH)2, Cu2S, Fe(NO3)3, FeSO4, Ni(NO3)2, NiSO4, AgNO3, Ag2SO4, (CH3C02)2Co, (CH3CO2)2Pd, Pd(NO3)2, Rh(CH3CO2)2, 및 Rh2O3로 이루어진 군에서 선택된 1종 이상인 전자소자 제조방법.The method of claim 11, wherein the transition metal salt is CuSO 4 , Cu (NO 3 ) 2 , CuO, (CH 3 CO 2 ) 2 Cu, Copper Gluconate, CuCl, CuCl 2 , CuF 2 , Cu (OH ) 2 , Cu 2 S, Fe (NO 3 ) 3 , FeSO 4 , Ni (NO 3 ) 2 , NiSO 4 , AgNO 3 , Ag 2 SO 4 , (CH 3 CO 2 ) 2 Co, (CH 3 CO 2 ) 2 Pd, Pd (NO 3 ) 2 , Rh (CH 3 CO 2 ) 2 , and Rh 2 O 3 An electronic device manufacturing method of at least one selected from the group consisting of.
  15. 제 11 항에 있어서, 상기 불소를 포함하는 무기염이 KF, LiF, NaF, RbF, CsF, NH4F, NH4FㅇHF, HBF4, 및 H2SiF6로 이루어진 군에서 선택된 1종 이상인 전자소자 제조방법.12. The method according to claim 11, wherein the fluorine-containing inorganic salt is at least one member selected from the group consisting of KF, LiF, NaF, RbF, CsF, NH 4 F, NH 4 FHHF, HBF 4 , and H 2 SiF 6 . Electronic device manufacturing method.
  16. 제 11 항에 있어서, 구리 또는 구리염 0.01 내지 10 중량%, 불산 또는 불소를 포함하는 무기염 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함하는 식각액.The etchant according to claim 11, comprising 0.01 to 10 wt% of copper or copper salt, 0.05 to 10 wt% of inorganic salt including hydrofluoric acid or fluorine, and 80 to 99.94 wt% of water.
  17. 제 11 항에 있어서, CuSO4 0.01 내지 10 중량%, HF 0.05 내지 10 중량%, 및 물 80 내지 99.94 중량%를 포함하는 전자소자 제조방법.The method of claim 11, comprising 0.01 to 10 wt% CuSO 4 , 0.05 to 10 wt% HF, and 80 to 99.94 wt% water.
  18. 제 11 항에 있어서, 상기 진성반도체층이 비정질 실리콘인 전자소자 제조방법.The method of claim 11, wherein the intrinsic semiconductor layer is amorphous silicon.
  19. 제 11 항에 있어서, 상기 도핑된 반도체층이 n-타입 도판트로 도핑된 비정질 실리콘인 전자소자 제조방법.The method of claim 11, wherein the doped semiconductor layer is amorphous silicon doped with an n-type dopant.
  20. 제 11 항에 있어서, 상기 전자소자가 박막 트랜지스터인 전자소자 제조방법.The method of claim 11, wherein the electronic device is a thin film transistor.
  21. 제 20 항에 있어서, 상기 식각 단계 전에The method of claim 20, wherein before the etching step
    절연기판 상에 게이트 전극을 배치하는 단계;Disposing a gate electrode on the insulating substrate;
    상기 게이트 전극 상에 절연층, 진성반도체층 및 도핑된 반도체층을 순차적으로 배치하는 단계; 및Sequentially placing an insulating layer, an intrinsic semiconductor layer, and a doped semiconductor layer on the gate electrode; And
    상기 도핑된 반도체층 상에 서로 이격된 드레인 전극 및 소스 전극을 배치하는 단계;를 포함하는 전자소자 제조방법.Disposing a drain electrode and a source electrode spaced apart from each other on the doped semiconductor layer.
PCT/KR2010/008941 2009-12-24 2010-12-14 Etchant and electronic device manufacturing method WO2011078512A2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
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US6200898B1 (en) * 1999-10-25 2001-03-13 Vanguard International Semiconductor Corporation Global planarization process for high step DRAM devices via use of HF vapor etching
US20020009833A1 (en) * 2000-06-15 2002-01-24 Horng-Chih Lin Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same
US6753606B2 (en) * 2000-03-06 2004-06-22 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
US20060027889A1 (en) * 2004-08-05 2006-02-09 International Business Machines Corporation Isolated fully depleted silicon-on-insulator regions by selective etch

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6200898B1 (en) * 1999-10-25 2001-03-13 Vanguard International Semiconductor Corporation Global planarization process for high step DRAM devices via use of HF vapor etching
US6753606B2 (en) * 2000-03-06 2004-06-22 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
US20020009833A1 (en) * 2000-06-15 2002-01-24 Horng-Chih Lin Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same
US20060027889A1 (en) * 2004-08-05 2006-02-09 International Business Machines Corporation Isolated fully depleted silicon-on-insulator regions by selective etch

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