WO2011066744A1 - 一种偏置控制滤波器及外调制器偏置控制滤波装置 - Google Patents

一种偏置控制滤波器及外调制器偏置控制滤波装置 Download PDF

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Publication number
WO2011066744A1
WO2011066744A1 PCT/CN2010/074324 CN2010074324W WO2011066744A1 WO 2011066744 A1 WO2011066744 A1 WO 2011066744A1 CN 2010074324 W CN2010074324 W CN 2010074324W WO 2011066744 A1 WO2011066744 A1 WO 2011066744A1
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Prior art keywords
switched capacitor
bias control
unit
signal
filter
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PCT/CN2010/074324
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English (en)
French (fr)
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沈剑青
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中兴通讯股份有限公司
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Publication of WO2011066744A1 publication Critical patent/WO2011066744A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/0121—Operation of devices; Circuit arrangements, not otherwise provided for in this subclass
    • G02F1/0123—Circuits for the control or stabilisation of the bias voltage, e.g. automatic bias control [ABC] feedback loops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks

Definitions

  • the present invention relates to the field of communications, and in particular, to a bias control filter and an external modulator bias control filter device.
  • the external modulation mode has the advantages of high rate, large extinction ratio, ⁇ adjustable, and insensitivity to wavelength, and plays an extremely important role in improving the transmission distance and transmission speed of the wavelength division system.
  • the offset operating point position of the external modulator will drift under the influence of temperature changes and device aging, which will affect the modulation performance.
  • the device for bias control of the external modulator consists of a pilot signal generator, a lithium niobate driver, a lithium niobate modulator bias control filter, a preamplifier, and a phase detector integrator, as shown in FIG.
  • the pilot generator generates a pilot signal, which is superimposed by a lithium niobate driver into a normal communication signal at a ratio of 2% to 5%, and then sent to a lithium niobate modulator; the lithium niobate modulator modulates the superimposed signal into an optical signal.
  • the pilot signal is detected, pre-amplification, filter amplification, phase-integration and output-bias control voltage are applied to operate the lithium niobate modulator at a stable bias operating point.
  • the bias control filter extracts the pilot signal from the normal communication signal and performs filtering and amplification. It requires good frequency selection characteristics and low noise figure, and its performance plays an important role in the control accuracy and stability of the modulator bias control.
  • the traditional bias control filter uses a two-stage analog multiple feedback bandpass (MFB) filter to extract and amplify the pilot signal. The structure is shown in Figure 2.
  • the filter frequency depends on the values of resistor R1 R6 and capacitors C1 ⁇ C4. Once the parameters of each component are determined, the filter frequency cannot be changed.
  • the invention with the application number of 200610033896 proposes an analog-to-digital conversion (ADC) analog-to-digital conversion and digital filter based on digital technology to replace the analog band-pass filter, and realize the filtering amplification function in the bias control process.
  • ADC analog-to-digital conversion
  • the analog filter is greatly affected by the discreteness of the device. It is not a problem of mass production, but it also brings disadvantages such as large circuit scale, high cost, high complexity, and high noise of digital circuits. Therefore, it is not the best solution. Summary of the invention
  • the technical problem to be solved by the present invention is to provide a bias control filter and an external modulator bias control filter device to overcome the existing external modulator bias control filter, which cannot achieve both production consistency, productivity, and low efficiency. Defects in the noise figure.
  • the present invention provides a bias control filter, including: a clock generator, a frequency divider, and a switched capacitor filtering unit;
  • the clock generator is configured to: provide a clock signal for the switched capacitor filtering unit and the frequency divider;
  • the frequency divider is configured to: divide the received clock signal to generate a pilot signal; the switched capacitor filtering unit is configured to: input the pilot under the clock signal provided by the clock generator The signal is amplified and filtered and output.
  • the above bias control filter can also have the following features:
  • the switched capacitor filtering unit includes an inverting operational amplifier, a switched capacitor unit and an integrator connected in sequence, and a feedback resistor network;
  • the inverting operational amplifier is configured to: after the input pilot signal is amplified, sent to the switched capacitor unit;
  • the switched capacitor unit is configured to: filter the received pilot signal under a clock signal provided by the clock generator, and send the obtained discrete time signal to the integrator;
  • the integrator is configured to: restore the discrete time signal to a continuous time signal, one channel as a filtered signal output, and the other path to the feedback resistor network;
  • the feedback resistor network is configured to: feed the input signals to the switched capacitor unit and the inverting input of the operational amplifier, respectively.
  • the above bias control filter can also have the following features:
  • the bias control filter includes a multi-stage switched capacitor filtering unit, and the multi-stage switched capacitor
  • the filtering units have the same structure and are connected in series by a capacitor;
  • the clock generator is arranged to provide a clock signal to the switched capacitor filtering unit in the following manner: providing the same clock signal to the multi-stage switched capacitor filtering unit.
  • the above bias control filter can also have the following features:
  • the switched capacitor filter unit includes a two-stage integrator, the feedback resistor network includes two resistors, one of which is coupled to the inverting input terminal and the output terminal of the operational amplifier; the first stage integrator is configured to: The discrete time signal outputted by the switched capacitor unit is reduced to a continuous time signal and then used as a filtered output. One path is fed back to the inverting input of the operational amplifier through another resistor in the resistive feedback network, and the other input is input to the second stage.
  • the second stage integrator is configured to: directly integrate the signal of the data into the switched capacitor unit.
  • the invention also provides an external modulator bias control filtering device, comprising: a lithium niobate driver, a lithium niobate modulator, a preamplifier and a phase detector integrator;
  • bias control filter including a clock generator, a frequency divider, and a switched capacitor filtering unit;
  • the clock generator is configured to: provide a clock signal for the switched capacitor filtering unit and the frequency divider;
  • the frequency divider is configured to: divide a received clock signal, send the generated pilot signal to the phase detector integrator, and superimpose the lithium niobate driver in a ratio of 2% to 5%
  • the switching capacitor filtering unit is configured to: amplify and filter the pilot signal output by the preamplifier after the clock signal provided by the clock generator, and output the pilot signal.
  • the switched capacitor filtering unit comprises an inverting operational amplifier, a switched capacitor unit and an integrator connected in sequence, and a feedback resistor network;
  • the inverting operational amplifier is configured to: after the input signal is amplified, sent to the switched capacitor unit;
  • the switched capacitor unit is configured to: filter the received signal under a clock signal provided by the clock generator, and send the obtained discrete time signal to the integrator;
  • the integrator is configured to: after the discrete time signal is reduced to a continuous time signal, one channel is output as a filtered signal, and the other channel is sent to the feedback resistor network;
  • the feedback resistor network is configured to: feed the input signals to the switched capacitor unit and the inverting input of the operational amplifier, respectively.
  • the external modulator bias control filtering device may further have the following features: the bias control filter includes a multi-stage switched capacitor filtering unit, the multi-stage switched capacitor filtering unit has the same structure, and is connected in series by capacitors.
  • the first-stage switched capacitor filtering unit outputs the filtered pilot signal; the first-stage switched capacitor filtering unit is connected to the pre-amplifier, and the filtered signal outputted by the previous-stage switched capacitor filtering unit is input to the switching capacitor of the subsequent stage through the capacitor.
  • the input end of the unit, the output end of the last stage switched capacitor filter unit is connected to the phase detector integrator; the clock generator is arranged to provide a clock signal to the switched capacitor filter unit in the following manner: filtering the plurality of switches The unit provides the same clock signal.
  • the above external modulator bias control filtering device may also have the following features:
  • the switched capacitor filtering unit includes a two-stage integrator, and the feedback resistor network includes two resistors, one of which is connected to an inverting input end and an output end of the operational amplifier;
  • the first stage integrator is configured to: restore the discrete time signal output by the switched capacitor unit to a continuous time signal and then as a filtered output, and pass back to the inverse of the operational amplifier through another resistor in the resistive feedback network
  • the phase input terminal is input to the second stage integrator; the second stage integrator is configured to: directly integrate the signal of the data into the switched capacitor unit.
  • the advantages of analog filtering and digital filtering are integrated due to the use of the switched capacitor filtering technique, and the frequency stability of the bias control filtering device is balanced.
  • the performance requirements of low noise amplification effectively improve the stability and reliability of the external modulation bias control filter device.
  • FIG. 1 is a block diagram showing the structure of an external modulator bias control device in the prior art
  • FIG. 2 is a circuit diagram of an analog MFB multiple feedback filter in the prior art
  • FIG. 3 is a circuit diagram of a switched capacitor filtering unit according to an embodiment of the present invention.
  • FIG. 5 is a structural block diagram of a bias control filter according to an embodiment of the present invention.
  • FIG. 5 is a structural diagram of applying a bias control filter in a 10G non-return-to-zero (NRZ) external modulator bias control device according to an application example of the present invention
  • FIG. 6 is a detailed implementation circuit of a bias control filter in an application example of the present invention.
  • FIG. 7 and 8 are waveform comparison diagrams of an output of an analog MFB bandpass filter and a bias control filter of the present invention at a normal temperature of 25 ° C and a high temperature of 75 ° C, respectively, in an application example of the present invention.
  • the bias control filter of the present invention is based on the known switched capacitor principle.
  • the core unit is composed of an electric 15 tank Cl, C2 and analog switches Sl, S2 driven by an external clock, as shown in FIG.
  • the analog switches S1 and S2 operate periodically.
  • S1 is closed
  • S2 is open
  • the input signal is charged to the capacitor C1.
  • S2 is closed
  • S1 is turned off
  • C1 is discharged to C2.
  • the duty ratio is 50% to ensure that the capacitor C1 has the same charge and discharge time.
  • the value of the capacitor C1/C2 can be 50, 100, 200.
  • the value of C1/C2 determines the charge distribution ratio of the two capacitors.
  • the center frequency of the switched capacitor unit is independent of the accuracy of the above two capacitors, and is only related to the ratio of the frequency of the clock pulse signal controlling the analog switches S1 and S2 and the capacitance of the two capacitors, namely:
  • c 2 is the filter capacitor
  • / is the frequency of the clock pulse signal.
  • the filter frequency depends only on two capacitors.
  • the ratio of the capacitance of the device is independent of the absolute value of the capacitance of the above two capacitors. This makes it have a very stable center frequency.
  • the capacitance of the two capacitors changes, but the capacitance ratio does not change, so the center frequency is substantially constant, and thus has good temperature stability.
  • the basic idea of the bias control filter provided by the present invention is: including a clock generator, a frequency divider and a switched capacitor filter unit; wherein the clock generator is used to provide a clock signal for the switched capacitor filter unit and the frequency divider; The pilot signal is divided by the received clock signal to generate a pilot signal; the switched capacitor filtering unit is configured to perform amplification and filtering on the input pilot signal under the clock signal provided by the clock generator.
  • the switched capacitor filtering unit includes an inverting operational amplifier (which may be simply referred to as an operational amplifier), a switched capacitor unit and an integrator, which are sequentially connected, and a feedback resistor network;
  • an inverting operational amplifier which may be simply referred to as an operational amplifier
  • a switched capacitor unit and an integrator which are sequentially connected, and a feedback resistor network
  • the inverting operational amplifier is used to amplify the input pilot signal and then send it to the switched capacitor unit; the switched capacitor unit is used for performing switching capacitor filtering on the received pilot signal under the clock signal provided by the clock generator, and filtering
  • the obtained discrete time signal is output to the integrator; the integrator is used to restore the discrete time signal to a continuous time signal, one channel is used as the filtered output, and the other is sent to the feedback resistor network; the feedback resistor network is used to feed the input signal to the switch separately
  • the inverting input of the capacitor unit and the operational amplifier controls the filter gain and Q value of the entire circuit (where the Q value is used to characterize the frequency selection characteristic of the bias control filter).
  • the switched capacitor filter unit included in the bias control filter may have at least two stages, the multi-stage switched capacitor filter unit has the same structure, and the previous stage switched capacitor filter unit
  • the filtered signal outputted by the integrator is input to the inverting input terminal of the inverting operational amplifier in the second-stage switched capacitor filtering unit through the capacitor (ie, the front and rear two-stage switched capacitor filtering unit is connected in series through the capacitor), and the clock generator is A plurality of switching filter units provide the same clock signal.
  • the external modulator bias control filter device using the above bias control filter includes: a bias control filter, a lithium niobate driver, a lithium niobate modulator, a preamplifier, and a phase detector integrator, a bias control filter
  • the clock generator, the frequency divider and the switched capacitor filter unit are further included; wherein the clock generator is used to provide a clock signal for the switched capacitor filter unit and the frequency divider; the frequency divider is configured to divide the received clock signal, and The generated pilot signal is sent to the phase detector integrator all the way, and the other channel is superimposed on the lithium niobate driver in a ratio of 2% to 5%; the switched capacitor filter unit is used in the clock
  • the pilot signal output from the preamplifier is amplified and filtered by the clock signal provided by the generator.
  • the bias control filter includes a multi-stage switched capacitor filtering unit
  • the first-stage switched capacitor filtering unit is connected to the pre-amplifier, and the filtered signal outputted by the previous-stage switched capacitor filtering unit is filtered by the capacitive input to the switching capacitor of the subsequent stage.
  • the input end of the unit, the output end of the last stage switched capacitor filter unit is connected to the phase detector integrator to output the filtered pilot signal.
  • the bias control filter provided in this application example is based on the basic principle of switched capacitor filtering, and is composed of a two-stage series-connected switched capacitor filter unit, a clock generator and a frequency divider.
  • the operational amplifier, switched capacitor unit, integrator and feedback resistor network form a single-stage switched capacitor filter unit. Since the filter gain and Q value of the single-stage switched capacitor filter unit cannot meet the requirements of the offset filter control, two stages of the same structure are required.
  • the switched capacitor filter unit improves the gain and frequency selection characteristics by connecting capacitors in series.
  • the two-stage switched capacitor filter unit is AC-coupled through capacitor C1, as shown in FIG.
  • Each single-stage switched capacitor filtering unit is an analog/digital hybrid discrete-time bandpass filter.
  • the input continuous-time signal is first amplified by an inverting operational amplifier and output to a switched capacitor unit, where the inverting input is The resistor R1 is used to control the input impedance and the amplification factor; the amplified signal enters the switched capacitor unit for filtering, and the analog switch inside the switched capacitor unit is chopped into a discrete time signal and output to the integrator; the integrator will amplify the filtered discrete time signal After being restored to a smooth continuous time signal, the output is divided into two outputs, one is used as the filtered signal output, and the other is fed back to the inverting input terminal of the inverting operational amplifier and the switched capacitor filtering unit through the feedback resistor network to control the Q value of the band pass filtering.
  • Such a circuit structure combines the advantages of low noise of analog filtering and high stability of digital filtering.
  • the Q value and gain parameter of the filter are determined by the resistance parameter in the feedback resistor network, and the filtering frequency is provided by an external clock generator.
  • the clock frequency is determined by the capacitance ratio of the switched capacitor unit, thus ensuring good frequency stability and low noise, balancing the performance of the bias control filter without device dispersion and low noise amplification.
  • the analog MFB bandpass filter in the conventional scheme is a bias control filter composed of a two-stage switched capacitor filter unit, a clock generator and a frequency divider.
  • the clock generator provides the clock required for filtering
  • the pilot signal is generated by an integer multiple of 50, 100, 200, etc.
  • the filter clock and the pilot signal use a homologous clock.
  • the pilot signal also It will drift, and the filtering frequency will also drift with the clock. Therefore, it can cancel the filtering frequency drift caused by the clock frequency variation, further improve the stability of the filtering, and ensure the reliable operation of the external modulator bias control filtering device.
  • Each stage of the switched capacitor filter unit includes a two-stage integrator, and the feedback resistor network includes two resistors, one of which is used to connect the inverse of the operational amplifier. Phase input and output.
  • the first stage integrator is used to restore the discrete time signal outputted by the switched capacitor unit to a continuous time signal and then as a filtered output, one of which is fed back to the inverting input of the operational amplifier through another resistor in the resistive feedback network, and the other input is
  • the second stage integrator is used to integrate the data signal and directly feed back to the switched capacitor unit.
  • the lOGbps tunable optical module is modulated by a lithium niobate externally, and the modulator photodiode detection signal of the optical module is simultaneously connected to the analog MFB multiple feedback filter.
  • the pilot signal is filtered and amplified.
  • the frequency of the pilot signal is 3.4 kHz, and the external clock frequency is 100 times the frequency of the pilot signal, that is, 340 kHz.
  • Gain is the total Q value of the cascaded filter
  • the waveform of the analog MFB multiple feedback filter output measured by an oscilloscope at a normal temperature of 25 ° C and the waveform of the filter output of the present invention are as shown in FIG. It can be seen from the figure that in the normal temperature environment, the waveform outputted by the bias control filter device of the present invention is substantially identical to the filtering effect of the analog MFB multiple feedback filter, and the waveform is clear, but the noise is slightly larger, and the bias control is The filter works normally, demonstrating the effectiveness of the bias control filter proposed by the present invention in the external modulator bias control.
  • the output waveforms of the two filters tested in a 75 ° C high temperature test chamber are shown in FIG. It can be seen from the figure that in the high temperature environment, the waveform of the output of the bias control filter of the present invention is substantially the same as the phase of the waveform output under normal temperature environment, and the waveform is clear, but the phase of the output of the analog MFB multiple feedback filter occurs. Obvious changes, demonstrating the temperature stability of the bias control filter of the present invention is better than the traditional analog MFB The multiple feedback filters are greatly improved, balancing the performance requirements of bias control filter stability and low noise amplification.
  • the bias control filter of the present invention is also applicable to bias control circuits of other modulation methods, such as 40G differential phase keying (DPSK). Modulated optical module, 40G Differential Quadrature Phase-Shift Keying (DQPSK) modulated optical module, etc., but the clock frequency and internal resistance parameter values have some nuances depending on the specific application.
  • DPSK differential phase keying
  • DQPSK Differential Quadrature Phase-Shift Keying
  • the present invention utilizes the switched capacitor filtering technology, combines the advantages of analog filtering and digital filtering, and balances the performance requirements of the frequency control and low noise amplification of the bias control filter device, effectively improving the external
  • the modulation bias controls the stability and reliability of the filtering device.

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Description

一种偏置控制滤波器及外调制器偏置控制滤波装置
技术领域
本发明涉及通讯领域， 尤其涉及一种偏置控制滤波器及外调制器偏置控 制滤波装置。
背景技术
外调制方式具有高速率、 大消光比、 啁啾可调以及对波长不敏感等优点， 对提高波分***的传输距离和传输速度起着极其重要的作用。 但是外调制器 的偏置工作点位置会在温度变化以及器件老化等因素的影响下产生漂移， 进 而影响调制性能。 为此， 对外调制器进行偏置控制的装置由导频信号发生器、 铌酸锂驱动器、铌酸锂调制器偏置控制滤波器、预放大器和鉴相积分器构成， 如图 1所示。 导频发生器产生导频信号， 以 2% ~ 5%的比例由铌酸锂驱动器 叠加到正常通信信号中后发送到铌酸锂调制器； 铌酸锂调制器将该叠加信号 调制成光信号后检测导频信号， 进行预放大、 滤波放大、 鉴相积分后输出偏 置控制电压使铌酸锂调制器工作在稳定的偏置工作点。
偏置控制滤波器从正常通信信号中提取出导频信号后进行滤波放大， 要 求具有良好的频率选择特性和低噪声系数， 其性能对调制器偏置控制的控制 精度和稳定性起重要作用。 传统的偏置控制滤波器使用两级串联的模拟多重 反馈带通（ Multiple Feedback Bandpass, MFB )滤波器进行导频信号的提取放 大， 其结构如图 2所示。 滤波频率取决于电阻 R1 R6和电容 C1~C4的值， 一旦各元件参数确定， 滤波频率就不可更改。 虽然这种滤波放大器在调试良 好的前提下能够正常工作， 但由于它基于传统的模拟电路技术， 滤波特性受 器件离散性、 特别是电容精度的影响较大， 在温度变化的情况下相位延时变 化大， 频率不能动态调节， 调试困难， 不能满足光通信设备大规模生产的要 求。
申请号为 200610033896的发明提出了基于数字技术的模数转换（ Analog to Digital Convert, ADC )釆样量化和数字滤波器以取代模拟带通滤波器， 实 现偏置控制过程中的滤波放大功能，解决了模拟滤波器受器件离散性影响大， 且不能大规模生产的问题， 但同时也带来了电路规模大， 成本、 复杂度高， 数字电路噪声大等缺点， 因此也不是最佳的解决方案。 发明内容
本发明要解决的技术问题是提供一种偏置控制滤波器及外调制器偏置控 制滤波装置， 以克服现有的外调制器偏置控制滤波器不能兼顾生产一致性、 可生产性和低噪声系数的缺陷。
为解决上述问题， 本发明提供了一种偏置控制滤波器， 包括： 时钟发生 器、 分频器及开关电容滤波单元；
所述时钟发生器设置为： 为所述开关电容滤波单元及所述分频器提供时 钟信号；
所述分频器设置为： 对接收到的所述时钟信号进行分频， 生成导频信号； 所述开关电容滤波单元设置为： 在所述时钟发生器提供的时钟信号下对 输入的导频信号进行放大滤波后输出。
上述偏置控制滤波器还可具有以下特征：
所述开关电容滤波单元包括依次相连的反相运算放大器、 开关电容单元 及积分器， 还包括反馈电阻网络；
所述反相运算放大器设置为： 对所述输入的导频信号进行放大后， 发送 到所述开关电容单元；
所述开关电容单元设置为： 在所述时钟发生器提供的时钟信号下对接收 到的导频信号进行滤波， 并将得到的离散时间信号发送给所述积分器；
所述积分器设置为： 将所述离散时间信号还原为连续时间信号后一路作 为滤波信号输出， 另一路传递给所述反馈电阻网络；
所述反馈电阻网络设置为： 将输入的信号分别反馈给所述开关电容单元 和所述运算放大器的反相输入端。
上述偏置控制滤波器还可具有以下特征：
所述偏置控制滤波器是包括多级开关电容滤波单元， 所述多级开关电容 滤波单元具有相同的结构， 且通过电容串联；
所述时钟发生器是设置为以如下方式为所述开关电容滤波单元提供时钟 信号： 为所述多级开关电容滤波单元提供相同的时钟信号。
上述偏置控制滤波器还可具有以下特征：
所述开关电容滤波单元包含两级积分器， 所述反馈电阻网络包含两个电 阻， 其中一个电阻连接所述运算放大器的反相输入端和输出端； 第一级积分器设置为： 将所述开关电容单元输出的离散时间信号还原为 连续时间信号后一路作为滤波输出， 一路通过所述电阻反馈网络中的另一个 电阻反馈到所述运算放大器的反相输入端， 另外一路输入到第二级积分器； 所述第二级积分器设置为： 对数据的信号进行积分后， 直接反馈到所述 开关电容单元。
本发明还提供了一种外调制器偏置控制滤波装置， 包括： 铌酸锂驱动器、 铌酸锂调制器、 预放大器及鉴相积分器；
还包括偏置控制滤波器， 所述偏置控制滤波器包括时钟发生器、 分频器 及开关电容滤波单元；
所述时钟发生器设置为： 为所述开关电容滤波单元及所述分频器提供时 钟信号；
所述分频器设置为： 对接收到的时钟信号进行分频， 将生成的导频信号 发送给所述鉴相积分器， 并以 2% ~ 5%的比例叠加到所述铌酸锂驱动器中； 所述开关电容滤波单元设置为： 在所述时钟发生器提供的时钟信号下对 所述预放大器输出的导频信号进行放大滤波后输出。
上述外调制器偏置控制滤波装置还可具有以下特征： 所述开关电容滤波单元包括依次相连的反相运算放大器、 开关电容单元 及积分器， 还包括反馈电阻网络；
所述反相运算放大器设置为： 对输入的信号进行放大后， 发送到所述开 关电容单元； 所述开关电容单元设置为： 在所述时钟发生器提供的时钟信号下对接收 到的信号进行滤波， 并将得到的离散时间信号发送给所述积分器；
所述积分器设置为： 将所述离散时间信号还原为连续时间信号后一路作 为滤波信号输出， 另一路发送给所述反馈电阻网络；
所述反馈电阻网络设置为： 将输入的信号分别反馈给所述开关电容单元 和所述运算放大器的反相输入端。
上述外调制器偏置控制滤波装置还可具有以下特征： 所述偏置控制滤波器是包括多级开关电容滤波单元， 该多级开关电容滤 波单元具有相同的结构， 且通过电容串联， 由最后一级开关电容滤波单元输 出滤波后的导频信号； 第一级开关电容滤波单元与所述预放大器相连， 前一 级开关电容滤波单元输出的滤波信号通过电容输入到后一级的开关电容滤波 单元的输入端， 最后一级开关电容滤波单元的输出端与鉴相积分器相连； 所述时钟发生器是设置为以如下方式为所述开关电容滤波单元提供时钟 信号： 为该多个开关滤波单元提供相同的时钟信号。
上述外调制器偏置控制滤波装置还可具有以下特征：
所述开关电容滤波单元是包括两级积分器， 所述反馈电阻网络包括两个 电阻， 其中一个电阻连接所述运算放大器的反相输入端和输出端；
第一级积分器设置为： 将所述开关电容单元输出的离散时间信号还原为 连续时间信号后一路作为滤波输出， 一路通过所述电阻反馈网络中的另一个 电阻反馈到所述运算放大器的反相输入端， 另外一路输入到第二级积分器； 所述第二级积分器设置为： 对数据的信号进行积分后， 直接反馈到所述 开关电容单元。
釆用本发明， 与现有的偏置控制滤波技术相比， 由于釆用了开关电容滤 波技术， 综合了模拟滤波和数字滤波的优点， 平衡地兼顾了偏置控制滤波装 置对频率稳定性和低噪声放大的性能要求， 有效地提高了外调制偏置控制滤 波装置的稳定性和可靠性。 附图概述
图 1为现有技术中外调制器偏置控制装置的结构框图；
图 2为现有技术中模拟 MFB多重反馈滤波器的电路图；
图 3为本发明实施例中开关电容滤波单元的电路图；
5 图 4为本发明实施例中偏置控制滤波器的结构框图；
图 5为本发明应用实例中在 10G不归零码（ No Return Zero , NRZ )外调 制器偏置控制装置中应用偏置控制滤波器的结构图；
图 6为本发明应用实例中偏置控制滤波器的详细实施电路；
图 7和图 8为本发明应用实例中分别釆用模拟 MFB带通滤波器和本发明 10 所述偏置控制滤波器在常温 25 °C和高温 75 °C下输出的波形比较图。
本发明的较佳实施方式
下面将结合附图及实施例对本发明的技术方案进行更详细的说明。
本发明所述的偏置控制滤波器基于已知的开关电容原理， 核心单元由电 15 容器 Cl、 C2及由外部时钟驱动的模拟开关 Sl、 S2构成， 如图 3所示。 图中 模拟开关 S1及 S2周期性工作， 在时钟为高电平期间 S1闭合， S2断开， 输 入信号向电容器 C1充电， 在时钟为低电平期间 S2闭合， S1断开， C1向 C2 放电。 占空比为 50 % , 以保证电容器 C1充放电时间相同， 电容器 C1/C2的 值可以取 50、 100、 200 , C1/C2的值决定了两电容器的电荷分配比， 也就决 20 定了时钟与滤波信号的频率比。
通过模拟开关 S1及 S2的周期性开通关断， 输入信号的电荷在两个电容 器中根据电容量相对值的大小进行分配， 从而产生选频效应。 开关电容单元 的中心频率与上述两电容器的精度无关， 而仅与控制模拟开关 S1及 S2的时 钟脉冲信号的频率和两个电容器的电容之比有关， 即：
25 J fO =。 °λ J f elk
2 c2 其中， 为充放电电容， c2为滤波电容， / 为时钟脉冲信号的频率。 在 开关电容滤波电路中， 当时钟脉冲信号稳定时， 滤波频率仅取决于两个电容 器的电容之比， 与上述两电容器的电容绝对值无关。 这就使它具有非常稳定 的中心频率， 当温度变化时， 两电容器的电容改变， 但电容比不变， 因而中 心频率基本不变， 从而具有良好的温度稳定性。
本发明提供的偏置控制滤波器的基本构思是： 包括时钟发生器、 分频器 及开关电容滤波单元； 其中， 时钟发生器用于为开关电容滤波单元及分频器 提供时钟信号； 分频器用于对接收到的时钟信号进行分频， 生成导频信号； 开关电容滤波单元用于在时钟发生器提供的时钟信号下对输入的导频信号进 行放大滤波后输出。
优选地， 开关电容滤波单元中包括依次相连的反相运算放大器（可简称 为运放） 、 开关电容单元及积分器， 还包括反馈电阻网络；
反相运算放大器用于对输入的导频信号进行放大后， 发送到开关电容单 元； 开关电容单元用于在时钟发生器提供的时钟信号下对接收到的导频信号 进行开关电容滤波， 将滤波后得到的离散时间信号输出到积分器； 积分器用 于将离散时间信号还原为连续时间信号后一路作为滤波输出， 另一路发送给 反馈电阻网络； 反馈电阻网络用于将输入的信号分别反馈给开关电容单元和 运算放大器的反相输入端， 以控制整个电路的滤波增益和 Q值（其中， Q值 用于表征该偏置控制滤波器的频率选择特性） 。
此外， 为了保证偏置滤波控制的要求， 该偏置控制滤波器中包括的开关 电容滤波单元可以至少有 2级， 该多级开关电容滤波单元具有相同的结构， 且前一级开关电容滤波单元中的积分器输出的滤波信号经过电容输入到后一 级开关电容滤波单元中的反相运算放大器的反相输入端 （即前后两级开关电 容滤波单元通过电容串联） ， 上述时钟发生器为该多个开关滤波单元提供相 同的时钟信号。
釆用上述偏置控制滤波器的外调制器偏置控制滤波装置中包括： 偏置控 制滤波器、 铌酸锂驱动器、 铌酸锂调制器、 预放大器及鉴相积分器， 偏置控 制滤波器中进一步包括时钟发生器、 分频器及开关电容滤波单元； 其中， 时 钟发生器用于为开关电容滤波单元及分频器提供时钟信号； 分频器用于对接 收到的时钟信号进行分频， 将生成的导频信号一路发送给鉴相积分器， 另一 路以 2% ~ 5%的比例叠加到铌酸锂驱动器中； 开关电容滤波单元用于在时钟 发生器提供的时钟信号下对预放大器输出的导频信号进行放大滤波后输出。 当偏置控制滤波器中包括多级开关电容滤波单元时， 第一级开关电容滤 波单元与预放大器相连， 前一级开关电容滤波单元输出的滤波信号通过电容 输入到后一级的开关电容滤波单元的输入端， 最后一级开关电容滤波单元的 输出端与鉴相积分器相连， 以输出滤波后的导频信号。
下面用本发明的一个应用实例进一步加以说明。
本应用实例提供的偏置控制滤波器基于开关电容滤波的基本原理， 由两 级串联的开关电容滤波单元、 时钟发生器和分频器组成。 运算放大器、 开关 电容单元、 积分器和反馈电阻网络组成单级开关电容滤波单元， 由于单级开 关电容滤波单元的滤波增益和 Q值不能满足偏置滤波控制的要求， 因此需要 两级相同结构的开关电容滤波单元通过电容串联来提高增益和频率选择特 性， 两级开关电容滤波单元间通过电容 C1交流耦合， 如图 4所示。
每个单级的开关电容滤波单元是一个模拟 /数字混合的离散时间带通滤 波器， 输入的连续时间信号首先被反相运算放大器放大后输出到开关电容单 元， 其中， 反相输入端上的电阻 R1用于控制输入阻抗和放大倍数； 放大信号 进入开关电容单元进行滤波， 被开关电容单元内部的模拟开关斩波为离散时 间信号后输出到积分器； 积分器将放大滤波后的离散时间信号还原为平滑的 连续时间信号后分两路输出， 一路作为滤波信号输出， 另一路通过反馈电阻 网络反馈到反相运算放大器的反相输入端和开关电容滤波单元， 以控制带通 滤波的 Q值和滤波增益。 这样的电路结构综合了模拟滤波低噪声和数字滤波 高稳定性的优势， 当电容比固定时， 滤波器 Q值及增益参数由反馈电阻网络 中的电阻参数决定， 滤波频率由外部时钟发生器提供的时钟频率和开关电容 单元的电容比决定， 因此保证了良好的频率稳定度， 同时又具有较低的噪声， 平衡地兼顾了偏置控制滤波器不受器件离散性影响和低噪声放大的性能要 求。
在 10G NRZ外调制器偏置控制滤波装置中应用上述偏置控制滤波器的 电路结构， 如图 5所示。 从图中可以看出， 传统方案中的模拟 MFB带通滤波 器被由两级开关电容滤波单元、 时钟发生器和分频器组成的偏置控制滤波器 所取代。 时钟发生器提供滤波所需要的时钟， 同时由分频器分频 50、 100、 200 等整数倍生成导频信号， 滤波时钟与导频信号使用同源时钟， 时钟频率 发生漂移时导频信号也会漂移， 滤波频率也随时钟漂移， 因此能够抵消时钟 频率变化造成的滤波频率漂移， 进一步提高滤波的稳定性， 保证了外调制器 偏置控制滤波装置的可靠运行。
一种偏置控制滤波器的具体结构如图 6所示， 每一级开关电容滤波单元 中包含两级积分器， 而反馈电阻网络中包含两个电阻， 其中一个电阻用于连 接运算放大器的反相输入端和输出端。 第一级积分器用于将开关电容单元输 出的离散时间信号还原为连续时间信号后一路作为滤波输出， 一路通过电阻 反馈网络中的另一个电阻反馈到运算放大器的反相输入端， 另外一路输入到 第二级积分器； 第二级积分器用于对数据的信号进行积分后， 直接反馈到开 关电容单元。
为了验证本发明所述偏置控制滤波器的有效性， 釆用铌酸锂外调制 lOGbps可调谐光模块进行验证， 将该光模块的调制器光电二极管检测信号同 时接入模拟 MFB多重反馈滤波器和如图 6所示的偏置控制滤波器中，进行导 频信号的滤波放大， 导频信号的频率为 3.4kHz, 外部时钟频率为导频信号频 率的 100 倍， 即 340kHz, 级联滤波总增益为 级联滤波总 Q值为
Figure imgf000010_0001
在 25°C常温下用示波器测量出的模拟 MFB多重反馈滤波器输出的波形 和本发明所述滤波器输出的波形如图 7所示。 从图中可以看出， 在常温环境 下，本发明所述的偏置控制滤波装置输出的波形与模拟 MFB多重反馈滤波器 的滤波效果基本一致， 波形清晰， 只是噪声略微大一些， 偏置控制滤波器工 作正常， 证明了本发明提出的偏置控制滤波器在外调制器偏置控制中的有效 性。
为了考察本发明所述偏置控制滤波器的温度稳定性， 在 75°C高温试验箱 中测试出的两滤波器的输出波形， 如图 8所示。 从图中可以看出， 在高温环 境下， 本发明所述偏置控制滤波器输出的波形与在常温环境下输出的波形相 位基本一致， 波形清晰，但是模拟 MFB多重反馈滤波器输出的相位发生了明 显的变化， 证明了本发明所述偏置控制滤波器的温度稳定性比传统模拟 MFB 多重反馈滤波器有较大提高， 平衡地兼顾了偏置控制滤波器稳定性和低噪声 放大的性能要求。
尽管验证是在 lOGbps NRZ外调制光模块上进行的， 但本发明所述偏置 控制滤波器同样适用于其它调制方式的偏置控制电路， 如 40G差分相移键控 ( Differential Phase Keying, DPSK )调制光模块， 40G 差分正交相移键控 ( Differential Quadrature Phase-Shift Keying, DQPSK )调制光模块等， 只是时 钟频率和内部电阻参数取值根据具体应用有一些细微差别。
当然， 本发明还可有其他多种实施例， 在不背离本发明精神及其实质的 但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业实用性 本发明由于釆用了开关电容滤波技术， 综合了模拟滤波和数字滤波的优 点，平衡地兼顾了偏置控制滤波装置对频率稳定性和低噪声放大的性能要求， 有效地提高了外调制偏置控制滤波装置的稳定性和可靠性。

Claims

权 利 要 求 书
1、 一种偏置控制滤波器， 其包括： 时钟发生器、 分频器及开关电容滤 波单元；
所述时钟发生器设置为： 为所述开关电容滤波单元及所述分频器提供时 钟信号；
所述分频器设置为： 对接收到的所述时钟信号进行分频， 生成导频信号； 所述开关电容滤波单元设置为： 在所述时钟发生器提供的时钟信号下对 输入的导频信号进行放大滤波后输出。
2、 如权利要求 1所述的偏置控制滤波器， 其中，
所述开关电容滤波单元包括依次相连的反相运算放大器、 开关电容单元 及积分器， 还包括反馈电阻网络；
所述反相运算放大器设置为： 对所述输入的导频信号进行放大后， 发送 到所述开关电容单元；
所述开关电容单元设置为： 在所述时钟发生器提供的时钟信号下对接收 到的导频信号进行滤波， 并将得到的离散时间信号发送给所述积分器；
所述积分器设置为： 将所述离散时间信号还原为连续时间信号后一路作 为滤波信号输出， 另一路传递给所述反馈电阻网络；
所述反馈电阻网络设置为： 将输入的信号分别反馈给所述开关电容单元 和所述运算放大器的反相输入端。
3、 如权利要求 1或 2所述的偏置控制滤波器， 其中，
所述偏置控制滤波器是包括多级开关电容滤波单元， 所述多级开关电容 滤波单元具有相同的结构， 且通过电容串联；
所述时钟发生器是设置为以如下方式为所述开关电容滤波单元提供时钟 信号： 为所述多级开关电容滤波单元提供相同的时钟信号。
4、 如权利要求 2所述的偏置控制滤波器， 其中， 所述开关电容滤波单元是包括两级积分器， 所述反馈电阻网络包括两个 电阻， 其中一个电阻连接所述运算放大器的反相输入端和输出端；
第一级积分器设置为： 将所述开关电容单元输出的离散时间信号还原为 连续时间信号后一路作为滤波输出， 一路通过所述电阻反馈网络中的另一个 电阻反馈到所述运算放大器的反相输入端， 另外一路输入到第二级积分器； 所述第二级积分器设置为： 对数据的信号进行积分后， 直接反馈到所述 开关电容单元。
5、 一种外调制器偏置控制滤波装置， 包括： 铌酸锂驱动器、铌酸锂调 制器、 预放大器、 鉴相积分器及偏置控制滤波器；
所述偏置控制滤波器包括时钟发生器、 分频器及开关电容滤波单元； 所述时钟发生器设置为： 为所述开关电容滤波单元及所述分频器提供时 钟信号；
所述分频器设置为： 对接收到的时钟信号进行分频， 将生成的导频信号 发送给所述鉴相积分器， 并以 2% ~ 5%的比例叠加到所述铌酸锂驱动器中； 所述开关电容滤波单元设置为： 在所述时钟发生器提供的时钟信号下对 所述预放大器输出的导频信号进行放大滤波后输出。
6、 如权利要求 5所述的外调制器偏置控制滤波装置， 其中， 所述开关电容滤波单元包括依次相连的反相运算放大器、 开关电容单元 及积分器， 还包括反馈电阻网络；
所述反相运算放大器设置为： 对输入的信号进行放大后， 发送到所述开 关电容单元；
所述开关电容单元设置为： 在所述时钟发生器提供的时钟信号下对接收 到的信号进行滤波， 并将得到的离散时间信号发送给所述积分器；
所述积分器设置为： 将所述离散时间信号还原为连续时间信号后一路作 为滤波信号输出， 另一路发送给所述反馈电阻网络；
所述反馈电阻网络设置为： 将输入的信号分别反馈给所述开关电容单元 和所述运算放大器的反相输入端。
7、 如权利要求 5或 6所述的外调制器偏置控制滤波装置， 其中， 所述偏置控制滤波器是包括多级开关电容滤波单元， 该多级开关滤电容 波单元具有相同的结构， 且通过电容串联， 由最后一级开关电容滤波单元输 出滤波后的导频信号； 第一级开关电容滤波单元与所述预放大器相连， 前一 级开关电容滤波单元输出的滤波信号通过电容输入到后一级的开关电容滤波 单元的输入端， 最后一级开关电容滤波单元的输出端与鉴相积分器相连； 所述时钟发生器是设置为以如下方式为所述开关电容滤波单元提供时钟 信号： 为该多个开关滤波单元提供相同的时钟信号。
8、 如权利要求 6所述的外调制器偏置控制滤波装置， 其中， 所述开关电容滤波单元是包括两级积分器， 所述反馈电阻网络包含两个 电阻， 其中一个电阻连接所述运算放大器的反相输入端和输出端；
第一级积分器设置为： 将所述开关电容单元输出的离散时间信号还原为 连续时间信号后一路作为滤波输出， 一路通过所述电阻反馈网络中的另一个 电阻反馈到所述运算放大器的反相输入端， 另外一路输入到第二级积分器； 所述第二级积分器设置为： 对数据的信号进行积分后， 直接反馈到所述 开关电容单元。
PCT/CN2010/074324 2009-12-03 2010-06-23 一种偏置控制滤波器及外调制器偏置控制滤波装置 WO2011066744A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161249A1 (en) * 2003-02-13 2004-08-19 Fujitsu Limited Optical transmitter
EP1873575A1 (en) * 2006-06-30 2008-01-02 Alcatel Lucent Optical modulation apparatus and method to control it
CN101354515A (zh) * 2008-09-05 2009-01-28 中兴通讯股份有限公司 激光调制器偏置控制方法和装置
CN101777886A (zh) * 2009-12-03 2010-07-14 中兴通讯股份有限公司 一种偏置控制滤波器及外调制器偏置控制滤波装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040161249A1 (en) * 2003-02-13 2004-08-19 Fujitsu Limited Optical transmitter
EP1873575A1 (en) * 2006-06-30 2008-01-02 Alcatel Lucent Optical modulation apparatus and method to control it
CN101354515A (zh) * 2008-09-05 2009-01-28 中兴通讯股份有限公司 激光调制器偏置控制方法和装置
CN101777886A (zh) * 2009-12-03 2010-07-14 中兴通讯股份有限公司 一种偏置控制滤波器及外调制器偏置控制滤波装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MENG ZHI-QIANG ET AL: "Design and Realization of Automatic Tracking Band-Pass Filter Based on LMF 100", JOURNAL OF HUNAN UNIVERSITY (NATURAL SCIENCES), vol. 35, no. 11, November 2008 (2008-11-01), pages 37 - 39 *

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