WO2011021248A1 - Semiconductor substrate, method for production of semiconductor layer, method for production of semiconductor substrate, semiconductor element, luminescent element, display panel, electronic element, solar battery element, and electronic device - Google Patents

Semiconductor substrate, method for production of semiconductor layer, method for production of semiconductor substrate, semiconductor element, luminescent element, display panel, electronic element, solar battery element, and electronic device Download PDF

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Publication number
WO2011021248A1
WO2011021248A1 PCT/JP2009/004002 JP2009004002W WO2011021248A1 WO 2011021248 A1 WO2011021248 A1 WO 2011021248A1 JP 2009004002 W JP2009004002 W JP 2009004002W WO 2011021248 A1 WO2011021248 A1 WO 2011021248A1
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Prior art keywords
semiconductor
layer
substrate
semiconductor layer
graphite
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PCT/JP2009/004002
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French (fr)
Japanese (ja)
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藤岡洋
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国立大学法人東京大学
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Priority to PCT/JP2009/004002 priority Critical patent/WO2011021248A1/en
Priority to CN200980160996.XA priority patent/CN102576653B/en
Priority to KR1020127004218A priority patent/KR101441991B1/en
Priority to JP2011527490A priority patent/JP5545576B2/en
Publication of WO2011021248A1 publication Critical patent/WO2011021248A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02376—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03926—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate comprising a flexible substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a semiconductor substrate, a semiconductor layer manufacturing method, a semiconductor substrate manufacturing method, a semiconductor element, a light emitting element, a display panel, an electronic element, a solar cell element, and an electronic apparatus.
  • a semiconductor such as silicon is grown on a metal substrate and the element is produced, and then a material such as a polymer, glass, or ceramic is adhered to a semiconductor thin film, and then the metal substrate is peeled off.
  • a material such as a polymer, glass, or ceramic is adhered to a semiconductor thin film, and then the metal substrate is peeled off.
  • Such a method has been used, for example, when a semiconductor element is formed on a transparent large-area flexible substrate.
  • the present invention provides a low-cost and highly reproducible semiconductor substrate, a semiconductor layer manufacturing method, a semiconductor substrate manufacturing method, a semiconductor element, a light-emitting element, a display panel, an electronic element, a solar cell element, and An object is to provide electronic equipment.
  • the semiconductor substrate according to the present invention comprises a graphite substrate having heat resistance and flexibility against external force, and a semiconductor layer provided on the graphite substrate and made of silicon.
  • the graphite substrate means a graphite body that is not limited to a plate shape and serves as a base for forming a semiconductor layer.
  • the cost can be reduced by using a method of manufacturing at a high temperature of, for example, 700 degrees Celsius or higher. Since the graphite substrate has flexibility with respect to external force, it can be bent. Thereby, a semiconductor substrate can be obtained at low cost. In addition to this, graphite is not easily oxidized and the reproducibility of the surface treatment is high. As described above, a semiconductor substrate with low cost and high reproducibility can be obtained.
  • the semiconductor substrate includes a polymer obtained by sintering the graphite substrate.
  • the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force.
  • the treatment can be performed at a high temperature of 700 ° C. or more, the treatment can be performed at a high temperature such as a pulse sputtering deposition method, a metal organic vapor phase epitaxy method, or a molecular beam epitaxy method.
  • the semiconductor substrate is not limited to the thickness of the graphite substrate, but is preferably 10 ⁇ m or more and 100 ⁇ m or less. According to the present invention, when the thickness of the graphite substrate is 100 ⁇ m or less, it has extremely excellent flexibility against external force. Moreover, according to this invention, it can be set as the structure which is hard to break with respect to external force because the thickness of a graphite board
  • substrate is 10 micrometers or more.
  • the semiconductor substrate further includes a buffer layer provided between the graphite substrate and the semiconductor layer and including at least one of HfN and ZrN.
  • a buffer layer provided between the graphite substrate and the semiconductor layer and including at least one of HfN and ZrN.
  • the buffer layer including at least one of HfN and ZrN is further provided between the graphite substrate and the semiconductor layer, light can be reflected by the buffer layer.
  • the light absorption efficiency in the said light absorption layer can be raised, for example.
  • the semiconductor substrate further includes a second buffer layer provided between the graphite substrate and the semiconductor layer and containing AlN.
  • the second buffer layer containing AlN is further provided between the graphite substrate and the semiconductor layer, the grain size of the semiconductor layer can be increased.
  • the electrical characteristics of the semiconductor layer can be enhanced.
  • the semiconductor layer is used as a light absorption layer, the light absorption characteristics of the semiconductor layer can also be enhanced.
  • the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is provided on the (0001) plane. According to the present invention, since the graphite substrate has the (0001) plane on the surface and the semiconductor layer is provided on the (0001) plane, the orientation of the semiconductor layer is improved.
  • the method of manufacturing a semiconductor substrate according to the present invention is characterized in that a semiconductor layer made of silicon is grown on a graphite substrate having heat resistance and flexibility against external force.
  • the graphite substrate means a graphite body that is not limited to a plate shape and serves as a base for forming a semiconductor layer.
  • the graphite substrate has a heat resistance of, for example, 700 ° C. or more, a low-cost method such as a pulse sputter deposition method can be used. Since the graphite substrate has flexibility with respect to external force, it can be bent. Thereby, a low-cost semiconductor substrate can be manufactured. In addition to this, graphite is not easily oxidized and the reproducibility of the surface treatment is high. As described above, a semiconductor substrate with low cost and high reproducibility can be manufactured.
  • the semiconductor substrate manufacturing method is characterized in that the semiconductor layer is grown on the graphite substrate containing a sintered polymer.
  • the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force. Since the treatment can be performed at a high temperature, the treatment can be performed at a high temperature such as a pulse sputtering deposition method, a metal organic vapor phase epitaxy method, or a molecular beam epitaxy method.
  • the method for manufacturing a semiconductor substrate does not limit the thickness of the graphite substrate, but preferably the semiconductor layer is grown on the graphite substrate having a thickness of 10 ⁇ m to 100 ⁇ m.
  • the thickness of the graphite substrate is 100 ⁇ m or less, it has extremely excellent flexibility against external force. Further, according to the present invention, since the thickness of the graphite substrate is 10 ⁇ m or more, it is difficult to break against external force. For this reason, the burden at the time of handling of a graphite substrate will be reduced.
  • the method for manufacturing a semiconductor substrate is characterized in that the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is grown on the (0001) plane.
  • the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is grown on the (0001) plane, so that the orientation of the semiconductor layer is enhanced.
  • the method for manufacturing a semiconductor substrate is characterized in that a buffer layer containing at least one of HfN and ZrN is formed on the graphite substrate, and the semiconductor layer is grown on the buffer layer.
  • a buffer layer containing at least one of HfN and ZrN is formed on the graphite substrate, and the semiconductor layer is grown on the buffer layer.
  • the method for manufacturing a semiconductor substrate is characterized in that a second buffer layer containing AlN is formed on the graphite substrate, and the semiconductor layer is grown on the second buffer layer.
  • the grain size of the semiconductor layer can be increased.
  • the electrical characteristics of the semiconductor layer can be enhanced.
  • the semiconductor layer is used as a light absorption layer, the light absorption characteristics of the semiconductor layer can also be enhanced.
  • the manufacturing method is characterized in that after the semiconductor layer is grown, the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated to obtain a layer including the semiconductor layer. .
  • a layer including a semiconductor layer and a layer including at least a part of a graphite substrate are separated to obtain a layer including the semiconductor layer.
  • a quality product can be obtained. For example, a large area exceeding 12 inches in diameter can be easily obtained.
  • what is obtained is not limited to a plate shape, but refers to a structure including a grown semiconductor layer.
  • the layer containing the semiconductor can be obtained by being separated into only a desired semiconductor layer as necessary.
  • the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated, and the separated layer including the semiconductor layer is separated. It arrange
  • substrate is not limited to plate shape, The base body which arrange
  • the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated, and the separated layer including the semiconductor layer is disposed on the second substrate different from the graphite substrate; Therefore, the semiconductor layer can be arranged not only on the graphite substrate but also on another substrate. Thereby, the semiconductor substrate which can be used for a wide use can be manufactured.
  • the graphite substrate includes a layered compound having a predetermined interlayer bonding force, and a force larger than the interlayer bonding force of the graphite substrate is applied between the layers of the layered compound.
  • a force greater than the interlayer bonding force of the graphite substrate including a layered compound having a predetermined interlayer bonding force is applied between the layers to release the interlayer bonding, whereby the layer including the semiconductor layer and the graphite substrate Since the layer is separated into at least a part of the layer, separation can be performed more reliably.
  • the structure of the graphite substrate can be used to separate the layer including the semiconductor layer and the layer including at least a part of the graphite substrate, it can be said that the significance of using the graphite substrate is great. That is, separation of the metal substrate is generally difficult, and there are problems such as dissolution using chemicals. A method that was concerned about adverse environmental impacts was used. Further, the metal surface is oxidized, and there is a problem that the reproducibility of the pretreatment for crystal growth is poor, but such a problem does not occur in the present invention.
  • the layer including the semiconductor layer include a semiconductor layer, a buffer layer, a second buffer layer, and the like, and may include a part of the graphite substrate.
  • the layer including the semiconductor layer when separating the layer including the semiconductor layer, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated from the structural material. It is characterized by doing.
  • the layer including the semiconductor layer when the layer including the semiconductor layer is separated, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated together with the structural material.
  • the semiconductor layer included in the layer including the layer can be prevented from being damaged.
  • a material that transmits visible light is used as the structural material, a structure that is extremely useful as a transparent structure is possible.
  • the layer including the semiconductor layer is disposed together with the structural material.
  • the layer including the semiconductor layer together with the structural material is disposed. Therefore, the layer including the semiconductor layer on the second substrate. Even after the semiconductor layer is disposed, the semiconductor layer can be protected.
  • a material that transmits visible light is used for the second substrate, a very useful structure can be obtained as a transparent structure.
  • the method for producing a semiconductor layer of the present invention is a graphite substrate having heat resistance and flexibility against external force (here, the graphite substrate is not limited to a plate shape, but means a graphite body that forms a base for forming a semiconductor layer) (2), after the semiconductor layer is grown, the layer including the semiconductor layer and the layer including at least part of the graphite substrate are separated to obtain a layer including the semiconductor layer.
  • a layer including a semiconductor layer and a layer including at least a part of a graphite substrate are separated to obtain a layer including the semiconductor layer.
  • a large-area and / or high-quality layer can be obtained. Can do.
  • a large area exceeding 12 inches in diameter can be easily obtained.
  • what is obtained is not limited to a plate shape, but refers to a structure including a grown semiconductor layer.
  • the layer containing the semiconductor can be obtained by being separated into only a desired semiconductor layer as necessary.
  • the method for producing a semiconductor substrate according to the present invention is a graphite substrate having heat resistance and flexibility with respect to external force (here, the graphite substrate is not limited to a plate shape but means a graphite body that forms a base for forming a semiconductor layer)
  • the graphite substrate is not limited to a plate shape but means a graphite body that forms a base for forming a semiconductor layer
  • the layer including the semiconductor layer and the layer including at least part of the graphite substrate are separated, and the separated layer including the semiconductor layer is separated from the graphite substrate.
  • substrate is not limited to plate shape, The base body which arrange
  • the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated, and the separated layer including the semiconductor layer is disposed on the second substrate different from the graphite substrate; Therefore, the semiconductor layer can be arranged not only on the graphite substrate but also on another substrate. Thereby, the semiconductor substrate which can be used for a wide use can be manufactured.
  • the semiconductor substrate manufacturing method is characterized in that the semiconductor layer is made of a group 13 nitride.
  • the semiconductor layer is made of a group 13 nitride.
  • a layer including the semiconductor layer is separated from a layer including at least a part of the graphite substrate, and the separated layer including the semiconductor layer is separated from the graphite substrate. Since they are arranged on different second substrates, the semiconductor layer can be arranged not only on the graphite substrate but also on other substrates. Thereby, the semiconductor substrate which can be used for a wide use can be manufactured.
  • a material that transmits visible light is used for the other substrate material, for example, a very useful structure as a structure of a light emitting element can be realized.
  • the graphite substrate includes a layered compound having a predetermined interlayer bonding force, and a force larger than the interlayer bonding force of the graphite substrate is applied between the layers of the layered compound.
  • the layer including the semiconductor layer and the layer including at least part of the graphite are separated.
  • the layer including the semiconductor layer by releasing the interlayer coupling by applying a force larger than the interlayer coupling force of the graphite substrate including the layered compound having a predetermined interlayer coupling force between the layers; Since the separation into the layer including at least a part of the graphite substrate is performed, the separation can be performed more reliably.
  • the structure of the graphite substrate can be used to separate the layer including the semiconductor layer and the layer including at least a part of the graphite substrate, it can be said that the significance of using the graphite substrate is great. That is, separation of the metal substrate is generally difficult, and there is a problem that it is dissolved using chemicals, and a method that has a concern about adverse effects on the environment has been used. Further, the metal surface is oxidized, and there is a problem that the reproducibility of the pretreatment for crystal growth is poor, but such a problem does not occur in the present invention.
  • the layer including the semiconductor layer include a semiconductor layer, a buffer layer, a second buffer layer, and the like, and may include a part of the graphite substrate.
  • the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated from the structural material. It is characterized by doing.
  • the layer including the semiconductor layer is separated, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated together with the structural material.
  • the semiconductor layer included in the layer including the layer can be prevented from being damaged.
  • a material that transmits visible light is used as the structural material, a structure that is extremely useful as a transparent structure is possible. For example, it is effective in the case of a light emitting element.
  • the layer including the semiconductor layer is disposed together with the structural material.
  • the layer including the semiconductor layer when the layer including the separated semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer together with the structural material is disposed. Therefore, the layer including the semiconductor layer on the second substrate. Even after the semiconductor layer is disposed, the semiconductor layer can be protected.
  • a material that transmits visible light is used for the second substrate, a very useful structure can be obtained as a transparent structure. For example, it is effective in the case of a light emitting element.
  • the semiconductor substrate manufacturing method is characterized in that the semiconductor layer is grown on the graphite substrate containing a sintered polymer.
  • the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force.
  • the treatment can be performed at a high temperature of 700 ° C. or more, the treatment can be performed at a high temperature such as a pulse sputtering deposition method, a metal organic vapor phase epitaxy method, or a molecular beam epitaxy method.
  • the method for manufacturing a semiconductor substrate does not limit the thickness of the graphite substrate, but preferably the semiconductor layer is grown on the graphite substrate having a thickness of 10 ⁇ m to 100 ⁇ m.
  • the thickness of the graphite substrate is 100 ⁇ m or less, it has extremely excellent flexibility against external force. Further, according to the present invention, since the thickness of the graphite substrate is 10 ⁇ m or more, it is difficult to break against external force. For this reason, the burden at the time of handling of a graphite substrate will be reduced.
  • the method for manufacturing a semiconductor substrate is characterized in that the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is grown on the (0001) plane. Since the graphite substrate has a (0001) plane on the surface and grows the semiconductor layer on the (0001) plane, the orientation of the semiconductor layer is improved.
  • the method for manufacturing a semiconductor substrate is characterized in that a buffer layer containing at least one of HfN and ZrN is formed on the graphite substrate, and the semiconductor layer is grown on the buffer layer.
  • a buffer layer containing at least one of HfN and ZrN is formed on the graphite substrate, and the semiconductor layer is grown on the buffer layer.
  • the method for manufacturing a semiconductor substrate is characterized in that a second buffer layer containing AlN is formed on the graphite substrate, and the semiconductor layer is grown on the second buffer layer.
  • the grain size of the semiconductor layer can be increased.
  • the electrical characteristics of the semiconductor layer can be enhanced.
  • the semiconductor layer is used as a light absorption layer, the light absorption characteristics of the semiconductor layer can also be enhanced.
  • a semiconductor device includes the above-described semiconductor substrate. According to the present invention, since a semiconductor substrate with low reproducibility and high reproducibility is provided, an inexpensive and high-quality semiconductor element can be obtained.
  • a light-emitting element according to the present invention includes the above-described semiconductor element. According to the present invention, since a cheap and high-quality semiconductor element is provided, a light-emitting element with good light emission characteristics can be obtained.
  • a display panel according to the present invention includes the light-emitting element described above. According to the present invention, since the light emitting element having good light emission characteristics is provided, a display panel having high display characteristics can be obtained.
  • An electronic device includes the semiconductor device described above. According to the present invention, since an inexpensive and high-quality semiconductor element is provided, an electronic element having high electrical characteristics can be obtained.
  • a solar cell element according to the present invention includes the above-described semiconductor substrate. According to the present invention, since a low-cost and highly reproducible semiconductor substrate is provided, an inexpensive and high-quality solar cell element can be obtained.
  • An electronic device includes at least one of the semiconductor element, the light emitting element, the display panel, the electronic element described above, and the solar cell element. According to the present invention, since at least one of the semiconductor element, the light emitting element, the display panel, the electronic element described above, and the solar cell element is provided, a high-quality electronic device can be obtained. it can.
  • a low-cost and highly reproducible semiconductor substrate a method for manufacturing a semiconductor substrate, a semiconductor element, a light-emitting element, a display panel, an electronic element, a solar cell element, and an electronic device can be provided.
  • the figure which shows the structure of the semiconductor substrate which concerns on embodiment of this invention The graph which shows the light reflectivity of a zirconium nitride. The figure which shows the light reflectance of a zirconium nitride, and the correspondence of a reflective wavelength.
  • the figure which shows the structure of the manufacturing apparatus of the semiconductor substrate which concerns on this embodiment The figure which shows the structure of the manufacturing apparatus of the semiconductor substrate which concerns on this embodiment.
  • FIG. 1 is a diagram showing a configuration of a semiconductor substrate 1 according to the present embodiment.
  • the semiconductor substrate 1 has a structure in which a buffer layer 3 is provided on a graphite substrate 2 and a semiconductor layer 4 is laminated on the buffer layer 3.
  • the semiconductor substrate 1 is mounted on a light emitting element or an electronic element.
  • the semiconductor layer 4 is a semiconductor layer made of, for example, single crystal silicon.
  • the graphite substrate 2 is made of a graphite film produced by sintering a polymer such as polyoxadiazole at about 3000 ° C.
  • the graphite film has a thermal conductivity of about 1700 W / m ⁇ K in the in-plane direction, and the value of this thermal conductivity is about four times that of Cu. Moreover, since it has high heat resistance, it can be processed even at high temperatures. Furthermore, it has a high electric conductivity of about 5 ⁇ 10 ⁇ 5 S / cm in the in-plane direction of the film.
  • the graphite substrate 2 can be formed in a thickness range of, for example, 10 ⁇ m or more and 100 ⁇ m or less.
  • the thickness of the graphite substrate 2 By setting it to 100 ⁇ m or less, it has flexibility with respect to external force. For this reason, it can be bent. Further, by setting the thickness of the graphite substrate 2 to 10 ⁇ m or more, the structure becomes difficult to break against external force. More preferably, the thickness of the graphite substrate 2 can be in the range of 25 ⁇ m or more and 100 ⁇ m or less, which is more difficult to break.
  • the graphite sheet 2 can have a large area of 50 cm 2 or more.
  • the graphite substrate 2 is formed so that the surface in contact with the buffer layer 3 is a (0001) surface.
  • the buffer layer 3 is a layer made of zirconium nitride (ZrN (111)), and is interposed between the (0001) plane of the graphite substrate 2 and the semiconductor layer 4.
  • FIG. 2 is a graph showing the light reflectance of zirconium nitride. The horizontal axis of the graph indicates the wavelength, and the vertical axis of the graph indicates the light reflectance.
  • FIG. 3 is a table showing the correspondence between the light reflectance of zirconium nitride and the wavelength of the light. As shown in FIGS. 2 and 3, the light reflectance at 470 nm that is the wavelength range of blue light in zirconium nitride is 65.6%. Based on this, it can be said that the buffer layer 3 made of zirconium nitride can reflect almost 65% or more of light when irradiated with blue light.
  • FIG. 4A is a diagram showing a configuration of a sputtering apparatus that is a manufacturing apparatus of the buffer layer 3.
  • the sputtering apparatus 10 includes a chamber 11, a substrate heating mechanism 12, a substrate holding unit 13, a sputtering gun 14, a pulse power supply 15, and a control unit 16.
  • the graphite substrate 2 can be heated by the substrate heating mechanism 12 in a state where the graphite substrate 2 is held on the substrate holding unit 13 in the chamber 11.
  • sputter beams are emitted from the plurality of sputter guns 14 toward the graphite substrate 2 while the graphite substrate 2 is held on the substrate holding portion 13.
  • the plurality of sputter guns 14 include, for example, a sputter gun 14a that emits a beam of Ga and Ga alloy, a sputter gun 14b that emits a beam of Al and Al alloy, a sputter gun 14c that emits a beam of In and In alloy, Si and Si A sputter gun 14d for injecting an alloy beam and a sputter gun 14e for injecting an Hf and Hf alloy beam are provided.
  • the type of metal constituting the beam from each of the sputter guns 14a to 14e can be changed as appropriate. Therefore, for example, it may be configured to emit a beam made of Zr, Mg, and these metals.
  • the plurality of sputter guns 14 are each connected to a pulse power supply 15.
  • the pulse power source 15 is a power source that applies a pulse voltage to the sputter gun 14.
  • Pulse power supplies 15a to 15e corresponding to the sputter guns 14a to 14e are provided.
  • the output timing, output period, frequency, amplitude and the like of the pulse voltage output from these pulse power supplies 15a to 15e are controlled by a control unit 16 such as a control computer.
  • FIG. 4B is a diagram illustrating a configuration of an MBE (Molecular Beam Epitaxy) apparatus that is a manufacturing apparatus of the semiconductor layer 4 described above.
  • the MBE apparatus 20 includes a chamber 21, a substrate heating mechanism 22, a substrate holding unit 23, an electron gun 24, and a target holder TH.
  • the graphite substrate 2 can be heated by the substrate heating mechanism 22 in a state where the graphite substrate 2 is held on the substrate holding portion 23 in the chamber 21. Further, an electron beam is emitted from the electron gun 24 toward the target T on the target holder TH while the graphite substrate 2 is held on the substrate holding portion 23.
  • the chamber 21 is provided so that it can be sealed with respect to the outside.
  • the chamber 21 can be depressurized by a turbo molecular pump (not shown). The vacuum in the chamber 21 is maintained by a turbo molecular pump.
  • the chamber 21 has a liquid nitrogen shroud (not shown) on the inner wall surface.
  • the liquid nitrogen shroud adsorbs the residual impurity gas in the chamber 21 on the wall surface.
  • the base pressure of the chamber 21 can be set to about 1 ⁇ 10 ⁇ 10 Torr, for example.
  • a high temperature resistant Ta crucible is used as the target holder.
  • the target T accommodated in the target holder TH is, for example, a solid Si source.
  • the solid Si source is heated by an electron beam emitted from a high-power electron gun to evaporate Si, and the evaporated Si is attached to the graphite substrate 2, thereby allowing Si on the graphite substrate 2.
  • the thin film is grown.
  • the chamber 21 is provided with a reflection high energy electron diffraction (RHEED) apparatus so that the crystallinity of the substrate or the surface of the thin film can be observed.
  • RHEED reflection high energy electron diffraction
  • a PSD method pulse sputter deposition method in which a pulse DC voltage is applied between a substrate and a target
  • the PSD method is significant.
  • argon gas and nitrogen gas are supplied into the chamber 11. After the inside of the chamber 11 reaches a predetermined pressure by argon gas and nitrogen gas, the graphite substrate 2 is held on the substrate holding part 13. After the graphite substrate 2 is held by the substrate holding unit 13, the ambient temperature of the graphite substrate 2 is adjusted by the substrate heating mechanism 12. When the ambient temperature of the graphite substrate 2 is adjusted, the pulse power source 15 is driven to emit a Hf beam from the sputter gun 14 e toward the (0001) plane of the graphite substrate 2.
  • the ejected Hf atoms are supplied onto the graphite substrate 2 with high energy.
  • the nitrogen in the chamber is a nitrogen radical.
  • a large amount of Hf atoms having high energy is supplied onto the (0001) plane of the graphite substrate 2, and the surface of the graphite substrate 2 becomes a metal-rich state.
  • Hf atoms migrate to a stable lattice position.
  • the Hf atoms migrated to a stable lattice position react with the nitrogen radicals activated in the chamber 11 to form a metal nitride (HfN) crystal.
  • HfN metal nitride
  • Each time a pulse voltage is applied, HfN having a stable crystal structure is intermittently deposited. In this way, the buffer layer 3 is formed on the (0001) plane of the graphite substrate 2.
  • a Si thin film is grown on the buffer layer 3.
  • an example in which a Si thin film is grown by the MBE method will be described.
  • the semiconductor thin film is formed on the graphite substrate 2 capable of increasing the area, it can be said that the MBE method is significant.
  • the inside of the chamber 21 is made a base pressure by a turbo molecular pump, and the graphite substrate 2 on which the buffer layer 3 is formed is held on the substrate holding unit 23. Further, the target T is installed on the target holder TH. After placing the graphite substrate 2 and the target T, the ambient temperature of the graphite substrate 2 is adjusted by the heating device 17. After adjusting the ambient temperature of the graphite substrate 2, the electron current of the electron gun 24 is adjusted to irradiate the target T in the target holder TH with an electron beam. The target T irradiated with the electron beam evaporates and adheres to the buffer layer 3 of the graphite substrate 2. In the present embodiment, Si atoms adhere on the buffer layer 3, and a Si thin film grows on the buffer layer 3. This thin film becomes the semiconductor layer 4.
  • the buffer layer 3 and the semiconductor layer 4 formed on the graphite substrate 2 are peeled off.
  • a structural material 5 such as a polymer or glass is disposed on the graphite substrate 2 so as to cover the buffer layer 3 and the semiconductor layer 4.
  • the buffer layer 3 and the semiconductor layer 4 are peeled from the graphite substrate 2 together with the structural material 5 by peeling the structural material 5 from the graphite substrate 2. Since the graphite substrate 2 is a layered compound having a weak interlayer bond, the structural material 5, the buffer layer 3, and the semiconductor layer 4 are easily peeled from the graphite substrate 2. Thus, the buffer layer 3 and the semiconductor layer 4 can be transferred to the structural material 5.
  • the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated to obtain a layer including the semiconductor layer.
  • a large-area and / or high-quality layer can be obtained.
  • a large area exceeding 12 inches in diameter can be easily obtained.
  • what is obtained is not limited to a plate shape, but refers to a structure including a grown semiconductor layer.
  • the layer containing the semiconductor can be obtained by being separated into only a desired semiconductor layer as necessary.
  • the structural material 5, the buffer layer 3 and the semiconductor layer 4 peeled from the graphite substrate 2 are fixed on a second substrate 6 such as a glass substrate, a quartz substrate, or a resin film.
  • a second substrate 6 such as a glass substrate, a quartz substrate, or a resin film.
  • an adhesive or the like can be applied to the buffer layer 3 and can be fixed to the second substrate 6 via the adhesive.
  • it may be fixed by other methods. In this way, the buffer layer 3 and the semiconductor layer 4 can be formed on the second substrate 6.
  • the graphite substrate 2 has heat resistance, the cost can be reduced by using a method of manufacturing at a high temperature. Since the graphite substrate 2 has flexibility with respect to external force, it can be bent. Thereby, the low-cost semiconductor substrate 1 is obtained. In addition to this, graphite is not easily oxidized and the reproducibility of the surface treatment is high. By the above, the semiconductor substrate 1 with high reproducibility can be obtained at low cost.
  • the semiconductor layer 4 is provided on the (0001) plane of the graphite substrate 2 which is a layered compound having a weak interlayer bond, it can be easily peeled off.
  • the graphite constituting the graphite substrate 2 is not easily oxidized and the reproducibility of the surface treatment is high.
  • a semiconductor substrate with low cost and high reproducibility can be manufactured.
  • the buffer layer 3 and the semiconductor layer 4 can be easily peeled off by using the structural material 5, and the buffer layer 3 and the semiconductor layer 4 are disposed on another second substrate 6. The buffer layer 3 and the semiconductor layer 4 can be protected later by the structural material 5.
  • the buffer layer 3 is formed by the pulse sputtering method
  • the semiconductor layer 4 is formed by the MBE method.
  • the present invention is not limited to this.
  • a PLD method pulse laser deposition method
  • PED Pulse electron beam deposition
  • PXD Pulsed Excitation Deposition
  • PXD Pulsed Excitation Deposition
  • a method pulse electron beam deposition
  • the buffer layer 3 made of HfN (111) is formed on the graphite substrate 2.
  • the present invention is not limited to this.
  • the buffer layer 3 made of ZrN (111) is formed. It may be a configuration.
  • the semiconductor layer 4 may be grown directly on the graphite substrate 2 without forming the buffer layer 3, or the semiconductor layer 4 may be stacked (for example, GaN layer / AlN layer / graphite). ).
  • the semiconductor layer 4 is described as an example of growing silicon.
  • the present invention is not limited to this.
  • a group 13 nitride semiconductor may be grown.
  • the group 13 nitride include GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and the like.
  • the general formula InXGaYAl1-XYN (0 ⁇ X ⁇ 1, 0 ⁇ Y) ⁇ 1, 0 ⁇ X + Y ⁇ 1). In this case, it can be formed by using the above method such as a pulse sputtering method.
  • the semiconductor substrate 1 of the present invention has a wide range of applications and can be used for semiconductor elements such as light emitting diodes and semiconductor lasers on an amorphous substrate. Further, it can also be used as a transparent circuit on an amorphous substrate using the semiconductor element.
  • it can be applied to transparent electrodes such as flat panel displays, solar cells, and touch panels. Further, it can be applied to the shielding of electromagnetic waves used for the antireflection film, a film that prevents dust from sticking due to static electricity, an antistatic film, heat ray reflective glass, and ultraviolet reflective glass.
  • Examples of applications include dye-sensitized solar cell electrodes; display panels, organic EL panels, light-emitting elements, light-emitting diodes (LEDs), white LEDs and laser transparent electrodes; surface-emitting laser transparent electrodes; lighting devices; An application that allows light to pass through only a specific wavelength range is also conceivable.
  • Transparent conductive film in liquid crystal display LCD: Liquid Crystal Display
  • Transparent conductive film in color filter portion Transparent conductive film in EL (EL: Electro Luminescence) display
  • Transparent conductive film in plasma display (PDP) PDP optical filter Transparent conductive film for shielding electromagnetic waves; transparent conductive film for shielding near infrared; transparent conductive film for preventing surface reflection; transparent conductive film for improving color reproducibility; transparent conductive film for preventing damage
  • touch panel resistive touch panel; electromagnetic induction touch panel; ultrasonic touch panel; optical touch panel; capacitive touch panel; resistive touch panel for personal digital assistants; Touch panel);
  • Solar cell Amorphous silicon (a-Si) solar cell; Microcrystalline Si thin film solar cell; CIGS solar cell; Dye-sensitized solar cell (DSC); Transparent conductive material; dimming material; dimming mirror; heating element (surface heater, electrothermal glass); electromagnetic wave shielding glass.
  • the present invention the present invention
  • the buffer layer 3 was grown by about 50 nm under the following conditions by pulse sputtering.
  • Target Hf (purity 99wt%) Growth temperature: 1000 ° C
  • Substrate Graphite substrate made of graphite having (0001) plane on its surface
  • Gas flow ratio: N2 / Ar 1: 4
  • the sample was transferred to an MBE apparatus for growing Si, and Si was grown.
  • the output of the electron gun was 8 kV
  • the electron current was 300 mA
  • the growth rate when used at 300 mA was approximately 6 ⁇ / sec.
  • the temperature of the growing graphite substrate 2 was controlled to 900 ° C., and a 3 ⁇ m Si crystal was grown.
  • FIG. 8A is a ⁇ 111> pole figure of electron beam backscatter diffraction.
  • FIG. 8A shows the RHEED image.
  • Si was a good (111) plane crystal as can be seen from the EBSD ⁇ 111> pole figure having clear three-fold rotational symmetry.
  • FIG. 8B it can be seen that a high-quality (111) crystal with a flat surface is grown because the RHEED image is a streak (linear) pattern having a high contrast.
  • Example 2 an AlN layer was formed on the graphite substrate 2 by the method of the above embodiment (pulse sputtering method), and a GaN layer was further formed on the AlN layer.
  • heating was performed at a temperature of about 1000 ° C. to 1200 ° C., and the heating time was about 30 min to 60 min.
  • heating was performed at a temperature of about 650 ° C. to 750 ° C., and the heating time was set to 60 min to 120 min.
  • FIG. 9 is a graph showing measurement results by XRD for the graphite layer and the AlN layer. As shown in the figure, the graphite layer grows in the (002) direction, the AlN layer grows in the (0002) direction, and the AlN layer is recognized to exhibit c-axis orientation.
  • FIG. 10 is an EBSD measurement diagram of the AlN layer. As shown in the figure, it can be seen that many crystals having a grain size of 1 ⁇ m or more are formed in the AlN layer.
  • FIG. 11 is a ⁇ 10-12 ⁇ EBSD pole figure for a portion of the AlN layer. As shown in the figure, a clear pattern is recognized on the apex of the regular hexagon. This shows that the crystallinity of the AlN layer is good.
  • FIG. 12 is a graph showing measurement results by XRD for the graphite layer and the GaN layer. As shown in the figure, the GaN layer grows in the (0002) direction like the AlN layer, and it is recognized that it exhibits c-axis orientation.
  • FIG. 13 is an SEM image of the surface of the GaN layer. As shown in the figure, it can be seen that the surface of the GaN layer has no particularly large irregularities and is formed on a relatively flat surface.
  • FIG. 14 is an EBSD measurement diagram of the GaN layer. As shown in the figure, it is understood that many crystals having a grain size of 1 ⁇ m or more are formed in the GaN layer.
  • FIGS. 15A and 15B are EBSD pole figures of the GaN layer.
  • FIG. 15A is a ⁇ 10-12 ⁇ EBSD pole figure for a part of the GaN layer
  • FIG. 15B is a ⁇ 10-12 ⁇ EBSD pole figure for the other part of the GaN layer.
  • a clear pattern is recognized on the apex of the regular hexagon. This indicates that each grain has high crystallinity.
  • FIG. 16 is a graph showing the results of PL measurement at room temperature of the GaN layer.
  • FIG. 17 is a graph showing the results of PL measurement at room temperature of GaN produced by conventional MOCVD.
  • the vertical axis of the graph is the PL intensity
  • the horizontal axis of the graph is the emission energy.
  • a strong peak is observed when the emission energy is around 3.4 eV. It was 63 meV when the half width of this peak was measured.
  • a strong peak is observed in the vicinity of 3.4 eV for the conventional GaN substrate. It was 66 meV when the half value width of this peak was measured. Comparing the results of FIG. 16 and FIG. 17, it can be seen that the light emission characteristics of the GaN layer obtained in this example are equal to or higher than the light emission characteristics of the conventional GaN substrate.
  • the present invention relates to a low-cost and highly reproducible semiconductor substrate, a method for manufacturing a semiconductor substrate, a semiconductor element, a light emitting element, a display panel, an electronic element, a solar cell element, and an electronic device, and is industrially applicable.

Abstract

A semiconductor substrate (1) comprising: a graphite substrate (2) which has heat resistance and flexibility against an external force; and a semiconductor layer (4) which is arranged on the graphite substrate and comprises silicon.

Description

半導体基板、半導体層の製造方法、半導体基板の製造方法、半導体素子、発光素子、表示パネル、電子素子、太陽電池素子及び電子機器Semiconductor substrate, semiconductor layer manufacturing method, semiconductor substrate manufacturing method, semiconductor element, light emitting element, display panel, electronic element, solar cell element, and electronic device
　本発明は、半導体基板、半導体層の製造方法、半導体基板の製造方法、半導体素子、発光素子、表示パネル、電子素子、太陽電池素子及び電子機器に関する。 The present invention relates to a semiconductor substrate, a semiconductor layer manufacturing method, a semiconductor substrate manufacturing method, a semiconductor element, a light emitting element, a display panel, an electronic element, a solar cell element, and an electronic apparatus.
　基板上に半導体素子を作製する方法として、例えば金属基板上にシリコンなどの半導体を成長・素子作製を行い、その後、ポリマーやガラス、セラミックスといった材料と半導体薄膜を接着し、金属基板を剥離する方法が知られていた。かかる方法は、例えば透明大面積フレキシブル基板に半導体素子を形成する場合などに用いられていた。 As a method for producing a semiconductor element on a substrate, for example, a semiconductor such as silicon is grown on a metal substrate and the element is produced, and then a material such as a polymer, glass, or ceramic is adhered to a semiconductor thin film, and then the metal substrate is peeled off. Was known. Such a method has been used, for example, when a semiconductor element is formed on a transparent large-area flexible substrate.
　しかしながら、金属基板の分離は一般に困難で、化学薬品を使って溶解させるなどの問題があり、環境に対する悪影響が懸念される手法が使われていた。また、金属表面は酸化されており、結晶成長の前処理の再現性が悪いという問題があった。 However, it is generally difficult to separate the metal substrate, and there is a problem that the metal substrate is dissolved by using chemicals, and a method that is concerned about adverse environmental effects has been used. Further, the metal surface is oxidized, and there is a problem that reproducibility of pretreatment for crystal growth is poor.
　上記のような事情に鑑み、本発明は、低コストで再現性の高い半導体基板、半導体層の製造方法、半導体基板の製造方法、半導体素子、発光素子、表示パネル、電子素子、太陽電池素子及び電子機器を提供することを目的とする。 In view of the circumstances as described above, the present invention provides a low-cost and highly reproducible semiconductor substrate, a semiconductor layer manufacturing method, a semiconductor substrate manufacturing method, a semiconductor element, a light-emitting element, a display panel, an electronic element, a solar cell element, and An object is to provide electronic equipment.
　本発明に係る半導体基板は、耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板と、前記グラファイト基板上に設けられ、シリコンからなる半導体層とを備えることを特徴とする。ここで、グラファイト基板とは板状に限定されず半導体層を形成するベースとなるグラファイト体を意味する。 The semiconductor substrate according to the present invention comprises a graphite substrate having heat resistance and flexibility against external force, and a semiconductor layer provided on the graphite substrate and made of silicon. Here, the graphite substrate means a graphite body that is not limited to a plate shape and serves as a base for forming a semiconductor layer.
　本発明によれば、グラファイト基板が耐熱性を有するため、例えば摂氏７００度以上の高温下で製造する手法を用いて低コスト化できる。グラファイト基板が外力に対する可撓性を有するため曲げることも可能となる。これにより、低コストで半導体基板が得られる。これに加えて、グラファイトは酸化されにくく、表面処理の再現性が高い。以上のことにより、低コストで再現性の高い半導体基板を得ることができる。 According to the present invention, since the graphite substrate has heat resistance, the cost can be reduced by using a method of manufacturing at a high temperature of, for example, 700 degrees Celsius or higher. Since the graphite substrate has flexibility with respect to external force, it can be bent. Thereby, a semiconductor substrate can be obtained at low cost. In addition to this, graphite is not easily oxidized and the reproducibility of the surface treatment is high. As described above, a semiconductor substrate with low cost and high reproducibility can be obtained.
　上記の半導体基板は、前記グラファイト基板が焼結されたポリマーを含んでいることを特徴とする。
　本発明によれば、グラファイト基板が焼結されたポリマーを含んでいることとしたので、耐熱性が高く、外力によって容易に曲げることが可能である。例えば摂氏７００度以上の高温下で処理を行うことも可能であるため、パルススパッタ堆積法や有機金属気相成長法、分子線エピタキシー法など高温下で行う処理が可能となる。 The semiconductor substrate includes a polymer obtained by sintering the graphite substrate.
According to the present invention, since the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force. For example, since the treatment can be performed at a high temperature of 700 ° C. or more, the treatment can be performed at a high temperature such as a pulse sputtering deposition method, a metal organic vapor phase epitaxy method, or a molecular beam epitaxy method.
　上記の半導体基板は、前記グラファイト基板の厚さを限定するものではないが、好ましくは１０μｍ以上１００μｍ以下であることを特徴とする。
　本発明によれば、グラファイト基板の厚さが１００μｍ以下であると外力に対して極めて優れた可撓性を有することとなる。また、本発明によれば、グラファイト基板の厚さが１０μｍ以上であることで外力に対して壊れにくい構成とすることができる。 The semiconductor substrate is not limited to the thickness of the graphite substrate, but is preferably 10 μm or more and 100 μm or less.
According to the present invention, when the thickness of the graphite substrate is 100 μm or less, it has extremely excellent flexibility against external force. Moreover, according to this invention, it can be set as the structure which is hard to break with respect to external force because the thickness of a graphite board | substrate is 10 micrometers or more.
　上記の半導体基板は、前記グラファイト基板と前記半導体層との間に設けられ、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を更に備えることを特徴とする。
　本発明によれば、グラファイト基板と半導体層との間に、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を更に備えることとしたので、当該バッファ層によって光を反射することができる。これにより、半導体層を例えば光吸収層等として用いる場合、当該光吸収層における光の吸収効率を高めることができる。 The semiconductor substrate further includes a buffer layer provided between the graphite substrate and the semiconductor layer and including at least one of HfN and ZrN.
According to the present invention, since the buffer layer including at least one of HfN and ZrN is further provided between the graphite substrate and the semiconductor layer, light can be reflected by the buffer layer. Thereby, when using a semiconductor layer as a light absorption layer etc., the light absorption efficiency in the said light absorption layer can be raised, for example.
　上記の半導体基板は、前記グラファイト基板と前記半導体層との間に設けられ、ＡｌＮを含む第２バッファ層を更に備えることを特徴とする。
　本発明によれば、グラファイト基板と半導体層との間に、ＡｌＮを含む第２バッファ層を更に備えることとしたので、半導体層のグレインサイズを増大させることができる。これにより、半導体層の電気的特性を高めることができ、特に半導体層を光吸収層として用いる場合には当該半導体層の光吸収特性についても高めることができる。 The semiconductor substrate further includes a second buffer layer provided between the graphite substrate and the semiconductor layer and containing AlN.
According to the present invention, since the second buffer layer containing AlN is further provided between the graphite substrate and the semiconductor layer, the grain size of the semiconductor layer can be increased. As a result, the electrical characteristics of the semiconductor layer can be enhanced. In particular, when the semiconductor layer is used as a light absorption layer, the light absorption characteristics of the semiconductor layer can also be enhanced.
　上記の半導体基板は、前記グラファイト基板は、（０００１）面を表面に有し、前記半導体層は、前記（０００１）面上に設けられることを特徴とする。
　本発明によれば、グラファイト基板が（０００１）面を表面に有し、半導体層が（０００１）面上に設けられるため、半導体層の配向性が高められることになる。 In the semiconductor substrate, the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is provided on the (0001) plane.
According to the present invention, since the graphite substrate has the (0001) plane on the surface and the semiconductor layer is provided on the (0001) plane, the orientation of the semiconductor layer is improved.
　本発明に係る半導体基板の製造方法は、耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板上に、シリコンからなる半導体層を成長させることを特徴とする。ここで、グラファイト基板とは板状に限定されず半導体層を形成するベースとなるグラファイト体を意味する。 The method of manufacturing a semiconductor substrate according to the present invention is characterized in that a semiconductor layer made of silicon is grown on a graphite substrate having heat resistance and flexibility against external force. Here, the graphite substrate means a graphite body that is not limited to a plate shape and serves as a base for forming a semiconductor layer.
　本発明によれば、グラファイト基板が例えば摂氏７００度以上の耐熱性を有するため、パルススパッタ堆積法などの低コストな手法を用いることができる。グラファイト基板が外力に対する可撓性を有するため曲げることも可能となる。これにより、低コストな半導体基板を製造することができる。これに加えて、グラファイトは酸化されにくく、表面処理の再現性が高い。以上のことにより、低コストで再現性の高い半導体基板を製造することができる。 According to the present invention, since the graphite substrate has a heat resistance of, for example, 700 ° C. or more, a low-cost method such as a pulse sputter deposition method can be used. Since the graphite substrate has flexibility with respect to external force, it can be bent. Thereby, a low-cost semiconductor substrate can be manufactured. In addition to this, graphite is not easily oxidized and the reproducibility of the surface treatment is high. As described above, a semiconductor substrate with low cost and high reproducibility can be manufactured.
　上記の半導体基板の製造方法は、焼結されたポリマーを含む前記グラファイト基板上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、グラファイト基板が焼結されたポリマーを含んでいることとしたので、耐熱性が高く、外力によって容易に曲げることが可能である。高温下で処理を行うことも可能であるため、パルススパッタ堆積法や有機金属気相成長法、分子線エピタキシー法など高温下で行う処理が可能となる。 The semiconductor substrate manufacturing method is characterized in that the semiconductor layer is grown on the graphite substrate containing a sintered polymer.
According to the present invention, since the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force. Since the treatment can be performed at a high temperature, the treatment can be performed at a high temperature such as a pulse sputtering deposition method, a metal organic vapor phase epitaxy method, or a molecular beam epitaxy method.
　上記の半導体基板の製造方法は、前記グラファイト基板の厚さを限定するものではないが、好ましくは厚さが１０μｍ以上１００μｍ以下に形成された前記グラファイト基板上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、グラファイト基板の厚さが１００μｍ以下であるとしたので、外力に対して極めて優れた可撓性を有することとなる。また、本発明によれば、グラファイト基板の厚さが１０μｍ以上であることとしたので、外力に対して壊れにくくなる。このため、グラファイト基板の取り扱い時の負担が軽減されることになる。 The method for manufacturing a semiconductor substrate does not limit the thickness of the graphite substrate, but preferably the semiconductor layer is grown on the graphite substrate having a thickness of 10 μm to 100 μm. Features.
According to the present invention, since the thickness of the graphite substrate is 100 μm or less, it has extremely excellent flexibility against external force. Further, according to the present invention, since the thickness of the graphite substrate is 10 μm or more, it is difficult to break against external force. For this reason, the burden at the time of handling of a graphite substrate will be reduced.
　上記の半導体基板の製造方法は、前記グラファイト基板は、（０００１）面を表面に有し、前記（０００１）面に前記半導体層を成長させることを特徴とする。
　本発明によれば、グラファイト基板が（０００１）面を表面に有し、当該（０００１）面上半導体層を成長させるため、半導体層の配向性が高められることになる。 The method for manufacturing a semiconductor substrate is characterized in that the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is grown on the (0001) plane.
According to the present invention, the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is grown on the (0001) plane, so that the orientation of the semiconductor layer is enhanced.
　上記の半導体基板の製造方法は、前記グラファイト基板上に、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を形成し、前記バッファ層上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、例えば半導体層を光吸収層等として用いる場合、当該光吸収層における光の吸収効率を高めることができる。 The method for manufacturing a semiconductor substrate is characterized in that a buffer layer containing at least one of HfN and ZrN is formed on the graphite substrate, and the semiconductor layer is grown on the buffer layer.
According to the present invention, for example, when a semiconductor layer is used as a light absorption layer or the like, the light absorption efficiency in the light absorption layer can be increased.
　上記の半導体基板の製造方法は、前記グラファイト基板上に、ＡｌＮを含む第２バッファ層を形成し、前記第２バッファ層上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、半導体層のグレインサイズを増大させることができる。これにより、半導体層の電気的特性を高めることができ、特に半導体層を光吸収層として用いる場合には当該半導体層の光吸収特性についても高めることができる。 The method for manufacturing a semiconductor substrate is characterized in that a second buffer layer containing AlN is formed on the graphite substrate, and the semiconductor layer is grown on the second buffer layer.
According to the present invention, the grain size of the semiconductor layer can be increased. As a result, the electrical characteristics of the semiconductor layer can be enhanced. In particular, when the semiconductor layer is used as a light absorption layer, the light absorption characteristics of the semiconductor layer can also be enhanced.
　上記の製造方法は、前記半導体層を成長させた後、当該半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離し、当該半導体層を含む層を得ることを特徴とする。
　本発明によれば、半導体層を含む層と、グラファイト基板の少なくとも一部を含む層とを分離し、当該半導体層を含む層を得るので、例えば半導体ウェハーに用いる材料として大面積および／または高品位のものを得ることができる。例えば直径１２インチを超える大面積のものが容易に得られる。ここにおいては、得られるものは板状に限定されず、成長させた半導体層を含む層で構成されたものをいう。またこの半導体を含む層は必要に応じ所望の半導体層のみに分離されたものを得ることもできる。 The manufacturing method is characterized in that after the semiconductor layer is grown, the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated to obtain a layer including the semiconductor layer. .
According to the present invention, a layer including a semiconductor layer and a layer including at least a part of a graphite substrate are separated to obtain a layer including the semiconductor layer. A quality product can be obtained. For example, a large area exceeding 12 inches in diameter can be easily obtained. Here, what is obtained is not limited to a plate shape, but refers to a structure including a grown semiconductor layer. In addition, the layer containing the semiconductor can be obtained by being separated into only a desired semiconductor layer as necessary.
　上記の半導体基板の製造方法は、前記半導体層を成長させた後、当該半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離し、分離した前記当該半導体層を含む層を前記グラファイト基板とは異なる第２基板上に配置することを特徴とする。ここで、第２基板とは板状に限定されず半導体層を含む層を配置するベース体を意味する。 In the method for manufacturing a semiconductor substrate, after the semiconductor layer is grown, the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated, and the separated layer including the semiconductor layer is separated. It arrange | positions on the 2nd board | substrate different from the said graphite board | substrate. Here, a 2nd board | substrate is not limited to plate shape, The base body which arrange | positions the layer containing a semiconductor layer is meant.
　本発明によれば、半導体層を含む層と、グラファイト基板の少なくとも一部を含む層とを分離し、分離した当該半導体層を含む層をグラファイト基板とは異なる第２基板上に配置することとしたので、グラファイト基板上に限られず他の基板上においても半導体層を配置させることができる。これにより、広い用途に用いることが可能な半導体基板を製造することができる。 According to the present invention, the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated, and the separated layer including the semiconductor layer is disposed on the second substrate different from the graphite substrate; Therefore, the semiconductor layer can be arranged not only on the graphite substrate but also on another substrate. Thereby, the semiconductor substrate which can be used for a wide use can be manufactured.
　上記の半導体基板の製造方法は、前記グラファイト基板は、所定の層間結合力を有する層状化合物を含み、前記グラファイト基板の層間結合力よりも大きい力を前記層状化合物の層間に作用させて前記グラファイト基板の層間結合を解除することで、前記半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離することを特徴とする。
　本発明によれば、所定の層間結合力を有する層状化合物を含むグラファイト基板の当該層間結合力よりも大きい力を層間に作用させて層間結合を解除することで半導体層を含む層とグラファイト基板の少なくとも一部を含む層とに分離することとしたので、より確実に分離することができる。このように、グラファイト基板の構造を利用して半導体層を含む層とグラファイト基板の少なくとも一部を含む層とに分離することができるため、グラファイト基板を用いる意義は大きいといえる。すなわち、金属基板の分離は一般に困難で、化学薬品を使って溶解させるなどの問題があり。環境に対する悪影響が懸念される手法が使われていた。また、金属表面は酸化されており、結晶成長の前処理の再現性が悪いという問題があるが、本発明では、そのような問題は生じない。半導体層を含む層としては、例えば半導体層やバッファ層、第２バッファ層などが含まれ、グラファイト基板の一部が含まれる場合もある。 In the above method for manufacturing a semiconductor substrate, the graphite substrate includes a layered compound having a predetermined interlayer bonding force, and a force larger than the interlayer bonding force of the graphite substrate is applied between the layers of the layered compound. By releasing the interlayer coupling, a layer including the semiconductor layer and a layer including at least a part of the graphite substrate are separated.
According to the present invention, a force greater than the interlayer bonding force of the graphite substrate including a layered compound having a predetermined interlayer bonding force is applied between the layers to release the interlayer bonding, whereby the layer including the semiconductor layer and the graphite substrate Since the layer is separated into at least a part of the layer, separation can be performed more reliably. As described above, since the structure of the graphite substrate can be used to separate the layer including the semiconductor layer and the layer including at least a part of the graphite substrate, it can be said that the significance of using the graphite substrate is great. That is, separation of the metal substrate is generally difficult, and there are problems such as dissolution using chemicals. A method that was concerned about adverse environmental impacts was used. Further, the metal surface is oxidized, and there is a problem that the reproducibility of the pretreatment for crystal growth is poor, but such a problem does not occur in the present invention. Examples of the layer including the semiconductor layer include a semiconductor layer, a buffer layer, a second buffer layer, and the like, and may include a part of the graphite substrate.
　上記の半導体基板の製造方法は、前記半導体層を含む層を分離する際には、所定の構造材を用いて前記半導体層を含む層を保持し前記構造材ごと前記半導体層を含む層を分離することを特徴とする。
　本発明によれば、半導体層を含む層を分離する際には、所定の構造材を用いて半導体層を含む層を保持し構造材ごと半導体層を含む層を分離することとしたので、半導体層を含む層に含まれる半導体層にダメージを与えるのを防ぐことができる。前記構造材に可視光を透過する材料を用いると透明の構造として極めて有用な構造が可能になる。 In the method for manufacturing a semiconductor substrate, when separating the layer including the semiconductor layer, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated from the structural material. It is characterized by doing.
According to the present invention, when the layer including the semiconductor layer is separated, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated together with the structural material. The semiconductor layer included in the layer including the layer can be prevented from being damaged. When a material that transmits visible light is used as the structural material, a structure that is extremely useful as a transparent structure is possible.
　上記の半導体基板の製造方法は、分離した前記半導体層を含む層を前記第２基板上に配置する際には、前記構造材ごと前記半導体層を含む層を配置することを特徴とする。
　本発明によれば、分離した半導体層を含む層を第２基板上に配置する際には、構造材ごと半導体層を含む層を配置することとしたので、第２基板に半導体層を含む層を配置した後も半導体層を保護することができる。前記第２基板に可視光を透過する材料を用いると透明の構造として極めて有用な構造が可能になる。 In the method for manufacturing a semiconductor substrate, when the separated layer including the semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer is disposed together with the structural material.
According to the present invention, when the layer including the separated semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer together with the structural material is disposed. Therefore, the layer including the semiconductor layer on the second substrate. Even after the semiconductor layer is disposed, the semiconductor layer can be protected. When a material that transmits visible light is used for the second substrate, a very useful structure can be obtained as a transparent structure.
　本発明の半導体層の製造方法は、耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板（ここで、グラファイト基板とは板状に限定されず半導体層を形成するベースとなるグラファイト体を意味する。）に、半導体層を成長させた後、当該半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離し、当該半導体層を含む層を得ることを特徴とする。
　本発明によれば、半導体層を含む層と、グラファイト基板の少なくとも一部を含む層とを分離し、当該半導体層を含む層を得るので、例えば大面積および／または高品位のものを得ることができる。例えば直径１２インチを超える大面積のものが容易に得られる。ここにおいては、得られるものは板状に限定されず、成長させた半導体層を含む層で構成されたものをいう。またこの半導体を含む層は必要に応じ所望の半導体層のみに分離されたものを得ることもできる。 The method for producing a semiconductor layer of the present invention is a graphite substrate having heat resistance and flexibility against external force (here, the graphite substrate is not limited to a plate shape, but means a graphite body that forms a base for forming a semiconductor layer) (2), after the semiconductor layer is grown, the layer including the semiconductor layer and the layer including at least part of the graphite substrate are separated to obtain a layer including the semiconductor layer.
According to the present invention, a layer including a semiconductor layer and a layer including at least a part of a graphite substrate are separated to obtain a layer including the semiconductor layer. For example, a large-area and / or high-quality layer can be obtained. Can do. For example, a large area exceeding 12 inches in diameter can be easily obtained. Here, what is obtained is not limited to a plate shape, but refers to a structure including a grown semiconductor layer. In addition, the layer containing the semiconductor can be obtained by being separated into only a desired semiconductor layer as necessary.
　本発明の半導体基板の製造方法は、耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板（ここで、グラファイト基板とは板状に限定されず半導体層を形成するベースとなるグラファイト体を意味する。）に、前記半導体層を成長させた後、当該半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離し、分離した前記当該半導体層を含む層を前記グラファイト基板とは異なる第２基板上に配置することを特徴とする。ここで、第２基板とは板状に限定されず半導体層を含む層を配置するベース体を意味する。 The method for producing a semiconductor substrate according to the present invention is a graphite substrate having heat resistance and flexibility with respect to external force (here, the graphite substrate is not limited to a plate shape but means a graphite body that forms a base for forming a semiconductor layer) After the semiconductor layer is grown, the layer including the semiconductor layer and the layer including at least part of the graphite substrate are separated, and the separated layer including the semiconductor layer is separated from the graphite substrate. Are arranged on different second substrates. Here, a 2nd board | substrate is not limited to plate shape, The base body which arrange | positions the layer containing a semiconductor layer is meant.
　本発明によれば、半導体層を含む層と、グラファイト基板の少なくとも一部を含む層とを分離し、分離した当該半導体層を含む層をグラファイト基板とは異なる第２基板上に配置することとしたので、グラファイト基板上に限られず他の基板上においても半導体層を配置させることができる。これにより、広い用途に用いることが可能な半導体基板を製造することができる。 According to the present invention, the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated, and the separated layer including the semiconductor layer is disposed on the second substrate different from the graphite substrate; Therefore, the semiconductor layer can be arranged not only on the graphite substrate but also on another substrate. Thereby, the semiconductor substrate which can be used for a wide use can be manufactured.
　上記の半導体基板の製造方法は、前記半導体層は、１３族窒化物からなることを特徴とする。
　本発明によれば、１３族窒化物からなる半導体層においても、当該半導体層を含む層と、グラファイト基板の少なくとも一部を含む層とを分離し、分離した半導体層を含む層をグラファイト基板とは異なる第２基板上に配置することとしたので、グラファイト基板上に限られず他の基板上においても半導体層を配置させることができる。これにより、広い用途に用いることが可能な半導体基板を製造することができる。前記他の基板材に可視光を透過する材料を用いると例えば発光素子の構造として極めて有用な構造が可能になる。 The semiconductor substrate manufacturing method is characterized in that the semiconductor layer is made of a group 13 nitride.
According to the present invention, even in a semiconductor layer made of a group 13 nitride, a layer including the semiconductor layer is separated from a layer including at least a part of the graphite substrate, and the separated layer including the semiconductor layer is separated from the graphite substrate. Since they are arranged on different second substrates, the semiconductor layer can be arranged not only on the graphite substrate but also on other substrates. Thereby, the semiconductor substrate which can be used for a wide use can be manufactured. When a material that transmits visible light is used for the other substrate material, for example, a very useful structure as a structure of a light emitting element can be realized.
　上記の半導体基板の製造方法は、前記グラファイト基板は、所定の層間結合力を有する層状化合物を含み、前記グラファイト基板の層間結合力よりも大きい力を前記層状化合物の層間に作用させて前記グラファイト基板の層間結合を解除することで、前記半導体層を含む層と前記グラファイトの少なくとも一部を含む層とを分離することを特徴とする。
　本発明によれば、上記同様、所定の層間結合力を有する層状化合物を含むグラファイト基板の当該層間結合力よりも大きい力を層間に作用させて層間結合を解除することで半導体層を含む層とグラファイト基板の少なくとも一部を含む層とに分離することとしたので、より確実に分離することができる。このように、グラファイト基板の構造を利用して半導体層を含む層とグラファイト基板の少なくとも一部を含む層とに分離することができるため、グラファイト基板を用いる意義は大きいといえる。すなわち、金属基板の分離は一般に困難で、化学薬品を使って溶解させるなどの問題があり、環境に対する悪影響が懸念される手法が使われていた。また、金属表面は酸化されており、結晶成長の前処理の再現性が悪いという問題があるが、本発明では、そのような問題は生じない。半導体層を含む層としては、例えば半導体層やバッファ層、第２バッファ層などが含まれ、グラファイト基板の一部が含まれる場合もある。 In the above method for manufacturing a semiconductor substrate, the graphite substrate includes a layered compound having a predetermined interlayer bonding force, and a force larger than the interlayer bonding force of the graphite substrate is applied between the layers of the layered compound. By releasing the interlayer coupling, the layer including the semiconductor layer and the layer including at least part of the graphite are separated.
According to the present invention, similar to the above, the layer including the semiconductor layer by releasing the interlayer coupling by applying a force larger than the interlayer coupling force of the graphite substrate including the layered compound having a predetermined interlayer coupling force between the layers; Since the separation into the layer including at least a part of the graphite substrate is performed, the separation can be performed more reliably. As described above, since the structure of the graphite substrate can be used to separate the layer including the semiconductor layer and the layer including at least a part of the graphite substrate, it can be said that the significance of using the graphite substrate is great. That is, separation of the metal substrate is generally difficult, and there is a problem that it is dissolved using chemicals, and a method that has a concern about adverse effects on the environment has been used. Further, the metal surface is oxidized, and there is a problem that the reproducibility of the pretreatment for crystal growth is poor, but such a problem does not occur in the present invention. Examples of the layer including the semiconductor layer include a semiconductor layer, a buffer layer, a second buffer layer, and the like, and may include a part of the graphite substrate.
　上記の半導体基板の製造方法は、前記半導体層を含む層を分離する際には、所定の構造材を用いて前記半導体層を含む層を保持し前記構造材ごと前記半導体層を含む層を分離することを特徴とする。
　本発明によれば、半導体層を含む層を分離する際には、所定の構造材を用いて半導体層を含む層を保持し構造材ごと半導体層を含む層を分離することとしたので、半導体層を含む層に含まれる半導体層にダメージを与えるのを防ぐことができる。前記構造材に可視光を透過する材料を用いると透明の構造として極めて有用な構造が可能になる。例えば発光素子の場合には有効である。 In the method for manufacturing a semiconductor substrate, when separating the layer including the semiconductor layer, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated from the structural material. It is characterized by doing.
According to the present invention, when the layer including the semiconductor layer is separated, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated together with the structural material. The semiconductor layer included in the layer including the layer can be prevented from being damaged. When a material that transmits visible light is used as the structural material, a structure that is extremely useful as a transparent structure is possible. For example, it is effective in the case of a light emitting element.
　上記の半導体基板の製造方法は、分離した前記半導体層を含む層を前記第２基板上に配置する際には、前記構造材ごと前記半導体層を含む層を配置することを特徴とする。
　本発明によれば、分離した半導体層を含む層を第２基板上に配置する際には、構造材ごと半導体層を含む層を配置することとしたので、第２基板に半導体層を含む層を配置した後も半導体層を保護することができる。前記第２基板に可視光を透過する材料を用いると透明の構造として極めて有用な構造が可能になる。例えば発光素子の場合には有効である。 In the method for manufacturing a semiconductor substrate, when the separated layer including the semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer is disposed together with the structural material.
According to the present invention, when the layer including the separated semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer together with the structural material is disposed. Therefore, the layer including the semiconductor layer on the second substrate. Even after the semiconductor layer is disposed, the semiconductor layer can be protected. When a material that transmits visible light is used for the second substrate, a very useful structure can be obtained as a transparent structure. For example, it is effective in the case of a light emitting element.
　上記の半導体基板の製造方法は、焼結されたポリマーを含む前記グラファイト基板上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、グラファイト基板が焼結されたポリマーを含んでいることとしたので、耐熱性が高く、外力によって容易に曲げることが可能である。例えば摂氏７００度以上の高温下で処理を行うことも可能であるため、パルススパッタ堆積法や有機金属気相成長法、分子線エピタキシー法など高温下で行う処理が可能となる。 The semiconductor substrate manufacturing method is characterized in that the semiconductor layer is grown on the graphite substrate containing a sintered polymer.
According to the present invention, since the graphite substrate contains the sintered polymer, it has high heat resistance and can be easily bent by an external force. For example, since the treatment can be performed at a high temperature of 700 ° C. or more, the treatment can be performed at a high temperature such as a pulse sputtering deposition method, a metal organic vapor phase epitaxy method, or a molecular beam epitaxy method.
　上記の半導体基板の製造方法は、前記グラファイト基板の厚さを限定するものではないが、好ましくは厚さが１０μｍ以上１００μｍ以下に形成された前記グラファイト基板上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、グラファイト基板の厚さが１００μｍ以下であるとしたので、外力に対して極めて優れた可撓性を有することとなる。また、本発明によれば、グラファイト基板の厚さが１０μｍ以上であることとしたので、外力に対して壊れにくくなる。このため、グラファイト基板の取り扱い時の負担が軽減されることになる。 The method for manufacturing a semiconductor substrate does not limit the thickness of the graphite substrate, but preferably the semiconductor layer is grown on the graphite substrate having a thickness of 10 μm to 100 μm. Features.
According to the present invention, since the thickness of the graphite substrate is 100 μm or less, it has extremely excellent flexibility against external force. Further, according to the present invention, since the thickness of the graphite substrate is 10 μm or more, it is difficult to break against external force. For this reason, the burden at the time of handling of a graphite substrate will be reduced.
　上記の半導体基板の製造方法は、前記グラファイト基板は、（０００１）面を表面に有し、前記（０００１）面に前記半導体層を成長させることを特徴とする。
　グラファイト基板が（０００１）面を表面に有し、当該（０００１）面上半導体層を成長させるため、半導体層の配向性が高められることになる。 The method for manufacturing a semiconductor substrate is characterized in that the graphite substrate has a (0001) plane on the surface, and the semiconductor layer is grown on the (0001) plane.
Since the graphite substrate has a (0001) plane on the surface and grows the semiconductor layer on the (0001) plane, the orientation of the semiconductor layer is improved.
　上記の半導体基板の製造方法は、前記グラファイト基板上に、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を形成し、前記バッファ層上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、半導体層を光吸収層等として用いる場合、当該光吸収層における光の吸収効率を高めることができる。 The method for manufacturing a semiconductor substrate is characterized in that a buffer layer containing at least one of HfN and ZrN is formed on the graphite substrate, and the semiconductor layer is grown on the buffer layer.
According to the present invention, when a semiconductor layer is used as a light absorption layer or the like, the light absorption efficiency in the light absorption layer can be increased.
　上記の半導体基板の製造方法は、前記グラファイト基板上に、ＡｌＮを含む第２バッファ層を形成し、前記第２バッファ層上に、前記半導体層を成長させることを特徴とする。
　本発明によれば、半導体層のグレインサイズを増大させることができる。これにより、半導体層の電気的特性を高めることができ、特に半導体層を光吸収層として用いる場合には当該半導体層の光吸収特性についても高めることができる。 The method for manufacturing a semiconductor substrate is characterized in that a second buffer layer containing AlN is formed on the graphite substrate, and the semiconductor layer is grown on the second buffer layer.
According to the present invention, the grain size of the semiconductor layer can be increased. As a result, the electrical characteristics of the semiconductor layer can be enhanced. In particular, when the semiconductor layer is used as a light absorption layer, the light absorption characteristics of the semiconductor layer can also be enhanced.
　本発明に係る半導体素子は、上記の半導体基板を備えることを特徴とする。
　本発明によれば、低コストで再現性の高い半導体基板を備えるため、安価で良質な半導体素子を得ることができる。 A semiconductor device according to the present invention includes the above-described semiconductor substrate.
According to the present invention, since a semiconductor substrate with low reproducibility and high reproducibility is provided, an inexpensive and high-quality semiconductor element can be obtained.
　本発明に係る発光素子は、上記の半導体素子を備えることを特徴とする。
　本発明によれば、安価で良質な半導体素子を備えるため、発光特性の良い発光素子を得ることができる。 A light-emitting element according to the present invention includes the above-described semiconductor element.
According to the present invention, since a cheap and high-quality semiconductor element is provided, a light-emitting element with good light emission characteristics can be obtained.
　本発明に係る表示パネルは、上記の発光素子を備えることを特徴とする。
　本発明によれば、発光特性の良い発光素子を備えるため、表示特性の高い表示パネルを得ることができる。 A display panel according to the present invention includes the light-emitting element described above.
According to the present invention, since the light emitting element having good light emission characteristics is provided, a display panel having high display characteristics can be obtained.
　本発明に係る電子素子は、上記の半導体素子を備えることを特徴とする。
　本発明によれば、安価で良質な半導体素子を備えるため、電気的特性の高い電子素子を得ることができる。 An electronic device according to the present invention includes the semiconductor device described above.
According to the present invention, since an inexpensive and high-quality semiconductor element is provided, an electronic element having high electrical characteristics can be obtained.
　本発明に係る太陽電池素子は、上記の半導体基板を備えることを特徴とする。
　本発明によれば、低コストで再現性の高い半導体基板を備えるため、安価で良質な太陽電池素子を得ることができる。 A solar cell element according to the present invention includes the above-described semiconductor substrate.
According to the present invention, since a low-cost and highly reproducible semiconductor substrate is provided, an inexpensive and high-quality solar cell element can be obtained.
　本発明に係る電子機器は、上記の半導体素子、上記の発光素子、上記の表示パネル、上記に記載の電子素子及び上記の太陽電池素子のうち少なくとも１つを備えることを特徴とする。
　本発明によれば、上記の半導体素子、上記の発光素子、上記の表示パネル、上記に記載の電子素子及び上記の太陽電池素子のうち少なくとも１つを備えるため、良質な電子機器を得ることができる。 An electronic device according to the present invention includes at least one of the semiconductor element, the light emitting element, the display panel, the electronic element described above, and the solar cell element.
According to the present invention, since at least one of the semiconductor element, the light emitting element, the display panel, the electronic element described above, and the solar cell element is provided, a high-quality electronic device can be obtained. it can.
　本発明によれば、低コストで再現性の高い半導体基板、半導体基板の製造方法、半導体素子、発光素子、表示パネル、電子素子、太陽電池素子及び電子機器を提供することができる。 According to the present invention, a low-cost and highly reproducible semiconductor substrate, a method for manufacturing a semiconductor substrate, a semiconductor element, a light-emitting element, a display panel, an electronic element, a solar cell element, and an electronic device can be provided.
本発明の実施形態に係る半導体基板の構成を示す図。The figure which shows the structure of the semiconductor substrate which concerns on embodiment of this invention. ジルコニウムナイトライドの光反射率を示すグラフ。The graph which shows the light reflectivity of a zirconium nitride. ジルコニウムナイトライドの光反射率と反射波長の対応関係とを示す図。The figure which shows the light reflectance of a zirconium nitride, and the correspondence of a reflective wavelength. 本実施形態に係る半導体基板の製造装置の構成を示す図。The figure which shows the structure of the manufacturing apparatus of the semiconductor substrate which concerns on this embodiment. 本実施形態に係る半導体基板の製造装置の構成を示す図。The figure which shows the structure of the manufacturing apparatus of the semiconductor substrate which concerns on this embodiment. 本実施形態に係る半導体基板の製造過程を示す図。The figure which shows the manufacturing process of the semiconductor substrate which concerns on this embodiment. 同、製造過程図。Same manufacturing process diagram. 同、製造過程図。Same manufacturing process diagram. 本発明の実施例１に係る半導体層の特性を示す図。The figure which shows the characteristic of the semiconductor layer which concerns on Example 1 of this invention. 本発明の実施例１に係る半導体層の特性を示す図。The figure which shows the characteristic of the semiconductor layer which concerns on Example 1 of this invention. 本発明の実施例２に係るグラファイト層及びＡｌＮ層のＸＲＤ測定グラフ。The XRD measurement graph of the graphite layer which concerns on Example 2 of this invention, and an AlN layer. 本実施例に係るＡｌＮ層のＥＢＳＤ測定図。The EBSD measurement figure of the AlN layer concerning a present Example. 本実施例に係るＡｌＮ層のＥＢＳＤ極点図。The EBSD pole figure of the AlN layer concerning a present Example. 本実施例に係るグラファイト層及びＧａＮ層のＸＲＤ測定グラフ。The XRD measurement graph of the graphite layer and GaN layer which concerns on a present Example. 本実施例に係るＧａＮ層の表面のＳＥＭ像。The SEM image of the surface of the GaN layer concerning a present Example. 本実施例に係るＧａＮ層のＥＢＳＤ測定図。The EBSD measurement figure of the GaN layer concerning a present Example. 本実施例に係るＧａＮ層のＥＢＳＤ極点図。The EBSD pole figure of the GaN layer concerning a present Example. 本実施例に係るＧａＮ層のＥＢＳＤ極点図。The EBSD pole figure of the GaN layer concerning a present Example. 本実施例に係るＧａＮ層の室温でのＰＬ測定の結果を示すグラフ。The graph which shows the result of PL measurement at room temperature of the GaN layer concerning a present Example. 従来のＧａＮ層の室温でのＰＬ測定の結果を示すグラフ。The graph which shows the result of PL measurement at the room temperature of the conventional GaN layer.
　本発明の実施の形態を図面に基づき説明する。
　図１は、本実施形態に係る半導体基板１の構成を示す図である。
　同図に示すように、半導体基板１は、グラファイト基板２上にバッファ層３が設けられ、当該バッファ層３上に半導体層４が積層された構成になっている。この半導体基板１は、発光素子や電子素子などに搭載される。本実施形態では、半導体層４は、例えば単結晶シリコンからなる半導体層である。 Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor substrate 1 according to the present embodiment.
As shown in the figure, the semiconductor substrate 1 has a structure in which a buffer layer 3 is provided on a graphite substrate 2 and a semiconductor layer 4 is laminated on the buffer layer 3. The semiconductor substrate 1 is mounted on a light emitting element or an electronic element. In the present embodiment, the semiconductor layer 4 is a semiconductor layer made of, for example, single crystal silicon.
　グラファイト基板２は、ポリオキサジアゾールなどのポリマーを約３０００℃程度で焼結させて作製したグラファイトフィルムからなる。当該グラファイトフィルムは、フィルム面内方向に約１７００Ｗ／ｍ・Ｋ程度の熱伝導率を有しており、この熱伝導率の値はＣｕの４倍程度である。また、耐熱性が高いため、高温下においても処理可能になっている。さらに、フィルム面内方向に５×１０－５Ｓ／ｃｍ程度という高い電気伝導率を有している。
　このグラファイト基板２は、厚さが例えば１０μｍ以上１００μｍ以下の範囲に形成することができる。１００μｍ以下とすることにより、外力に対する可撓性を有することとなる。このため、曲げることができるようになっている。また、グラファイト基板２の厚さを１０μｍ以上とすることにより、外力に対して壊れにくい構成となる。グラファイト基板２の厚さとしてより好ましくは、より壊れにくい２５μｍ以上１００μｍ以下の範囲にすることができる。グラファイトシート２は、５０ｃｍ２以上の大面積化が可能である。グラファイト基板２は、バッファ層３に接する面が、（０００１）面となるように形成されている。 The graphite substrate 2 is made of a graphite film produced by sintering a polymer such as polyoxadiazole at about 3000 ° C. The graphite film has a thermal conductivity of about 1700 W / m · K in the in-plane direction, and the value of this thermal conductivity is about four times that of Cu. Moreover, since it has high heat resistance, it can be processed even at high temperatures. Furthermore, it has a high electric conductivity of about 5 × 10 −5 S / cm in the in-plane direction of the film.
The graphite substrate 2 can be formed in a thickness range of, for example, 10 μm or more and 100 μm or less. By setting it to 100 μm or less, it has flexibility with respect to external force. For this reason, it can be bent. Further, by setting the thickness of the graphite substrate 2 to 10 μm or more, the structure becomes difficult to break against external force. More preferably, the thickness of the graphite substrate 2 can be in the range of 25 μm or more and 100 μm or less, which is more difficult to break. The graphite sheet 2 can have a large area of 50 cm 2 or more. The graphite substrate 2 is formed so that the surface in contact with the buffer layer 3 is a (0001) surface.
　バッファ層３は、ジルコニウムナイトライド（ＺｒＮ（１１１））からなる層であり、グラファイト基板２の（０００１）面と半導体層４との間に介在する。図２は、ジルコニウムナイトライドの光反射率を示すグラフである。グラフの横軸は波長、グラフの縦軸は光反射率を示している。 The buffer layer 3 is a layer made of zirconium nitride (ZrN (111)), and is interposed between the (0001) plane of the graphite substrate 2 and the semiconductor layer 4. FIG. 2 is a graph showing the light reflectance of zirconium nitride. The horizontal axis of the graph indicates the wavelength, and the vertical axis of the graph indicates the light reflectance.
　図３は、ジルコニウムナイトライドの光反射率と当該光の波長との対応関係を示す表である。
　図２及び図３に示すように、ジルコニウムナイトライドにおいて青色光の波長範囲である４７０ｎｍでの光反射率は６５．６％になっている。これをもとにすると、ジルコニウムナイトライドからなるバッファ層３においては、青色光を照射したときにはほぼ６５％以上の光を反射することが可能であるといえる。 FIG. 3 is a table showing the correspondence between the light reflectance of zirconium nitride and the wavelength of the light.
As shown in FIGS. 2 and 3, the light reflectance at 470 nm that is the wavelength range of blue light in zirconium nitride is 65.6%. Based on this, it can be said that the buffer layer 3 made of zirconium nitride can reflect almost 65% or more of light when irradiated with blue light.
　図４Ａは、バッファ層３の製造装置であるスパッタ装置の構成を示す図である。スパッタ装置１０は、チャンバ１１と、基板加熱機構１２と、基板保持部１３と、スパッタガン１４と、パルス電源１５と、制御部１６とを有している。
　このスパッタ装置１０においては、グラファイト基板２をチャンバ１１内の基板保持部１３上に保持させた状態で基板加熱機構１２によって当該グラファイト基板２を加熱することができるようになっている。また、グラファイト基板２が基板保持部１３上に保持された状態で、複数のスパッタガン１４からスパッタビームがグラファイト基板２へ向けて射出されるようになっている。 FIG. 4A is a diagram showing a configuration of a sputtering apparatus that is a manufacturing apparatus of the buffer layer 3. The sputtering apparatus 10 includes a chamber 11, a substrate heating mechanism 12, a substrate holding unit 13, a sputtering gun 14, a pulse power supply 15, and a control unit 16.
In the sputtering apparatus 10, the graphite substrate 2 can be heated by the substrate heating mechanism 12 in a state where the graphite substrate 2 is held on the substrate holding unit 13 in the chamber 11. In addition, sputter beams are emitted from the plurality of sputter guns 14 toward the graphite substrate 2 while the graphite substrate 2 is held on the substrate holding portion 13.
　複数のスパッタガン１４は、例えばＧａ及びＧａ合金のビームを射出するスパッタガン１４ａ、Ａｌ及びＡｌ合金のビームを射出するスパッタガン１４ｂ、Ｉｎ及びＩｎ合金のビームを射出するスパッタガン１４ｃ、Ｓｉ及びＳｉ合金のビームを射出するスパッタガン１４ｄ、Ｈｆ及びＨｆ合金のビームを射出するスパッタガン１４ｅを有している。各スパッタガン１４ａ～１４ｅからのビームを構成する金属の種類については、適宜交換することが可能になっている。したがって、例えばＺｒやＭｇ及びこれらの金属からなるビームを射出できるように構成しても構わない。 The plurality of sputter guns 14 include, for example, a sputter gun 14a that emits a beam of Ga and Ga alloy, a sputter gun 14b that emits a beam of Al and Al alloy, a sputter gun 14c that emits a beam of In and In alloy, Si and Si A sputter gun 14d for injecting an alloy beam and a sputter gun 14e for injecting an Hf and Hf alloy beam are provided. The type of metal constituting the beam from each of the sputter guns 14a to 14e can be changed as appropriate. Therefore, for example, it may be configured to emit a beam made of Zr, Mg, and these metals.
　複数のスパッタガン１４はそれぞれパルス電源１５に接続されている。パルス電源１５は、スパッタガン１４へパルス電圧を印加する電源である。各スパッタガン１４ａ～１４ｅに対応するパルス電源１５ａ～１５ｅが設けられている。これらのパルス電源１５ａ～１５ｅから出力されるパルス電圧の出力タイミングや出力期間、周波数、振幅などは、制御コンピュータなどの制御部１６によって制御されるようになっている。 The plurality of sputter guns 14 are each connected to a pulse power supply 15. The pulse power source 15 is a power source that applies a pulse voltage to the sputter gun 14. Pulse power supplies 15a to 15e corresponding to the sputter guns 14a to 14e are provided. The output timing, output period, frequency, amplitude and the like of the pulse voltage output from these pulse power supplies 15a to 15e are controlled by a control unit 16 such as a control computer.
　図４Ｂは、上記の半導体層４の製造装置であるＭＢＥ（Molecular Beam Epitaxy）装置の構成を示す図である。
　同図に示すように、ＭＢＥ装置２０は、チャンバ２１と、基板加熱機構２２と、基板保持部２３と、電子銃２４と、ターゲットホルダＴＨとを有している。 FIG. 4B is a diagram illustrating a configuration of an MBE (Molecular Beam Epitaxy) apparatus that is a manufacturing apparatus of the semiconductor layer 4 described above.
As shown in the figure, the MBE apparatus 20 includes a chamber 21, a substrate heating mechanism 22, a substrate holding unit 23, an electron gun 24, and a target holder TH.
　このＭＢＥ装置２０においては、グラファイト基板２をチャンバ２１内の基板保持部２３上に保持させた状態で基板加熱機構２２によって当該グラファイト基板２を加熱することができるようになっている。また、グラファイト基板２が基板保持部２３上に保持された状態で、電子銃２４から電子線がターゲットホルダＴＨ上のターゲットＴへ向けて射出されるようになっている。チャンバ２１は、外部に対して密閉可能に設けられている。チャンバ２１内は図示しないターボ分子ポンプなどによって減圧できるようになっている。チャンバ２１の真空はターボ分子ポンプにより維持されるようになっている。 In the MBE apparatus 20, the graphite substrate 2 can be heated by the substrate heating mechanism 22 in a state where the graphite substrate 2 is held on the substrate holding portion 23 in the chamber 21. Further, an electron beam is emitted from the electron gun 24 toward the target T on the target holder TH while the graphite substrate 2 is held on the substrate holding portion 23. The chamber 21 is provided so that it can be sealed with respect to the outside. The chamber 21 can be depressurized by a turbo molecular pump (not shown). The vacuum in the chamber 21 is maintained by a turbo molecular pump.
　また、チャンバ２１は、不図示の液体窒素シュラウドを内部壁面に有している。液体窒素シュラウドは、チャンバ２１内の残留不純物ガスを壁面に吸着させる。チャンバ２１のベースプレッシャーは、例えば１×１０－１０Ｔｏｒｒ程度に設定可能である。ターゲットホルダとしては、例えば耐高温用のＴａ製坩堝が用いられている。ターゲットホルダＴＨ内の中に収められているターゲットＴは、例えば固体Ｓｉソースである。ＭＢＥ装置２０では、この固体Ｓｉソースを高出力電子銃から放出された電子線で加熱することでＳｉを蒸発させ、蒸発させたＳｉをグラファイト基板２に付着させることで、グラファイト基板２上にＳｉの薄膜を成長させる構成となっている。チャンバ２１には反射高エネルギー電子線回折（ＲＨＥＥＤ）装置が設置されており、基板や薄膜表面の結晶性が観察可能になっている。 The chamber 21 has a liquid nitrogen shroud (not shown) on the inner wall surface. The liquid nitrogen shroud adsorbs the residual impurity gas in the chamber 21 on the wall surface. The base pressure of the chamber 21 can be set to about 1 × 10 −10 Torr, for example. As the target holder, for example, a high temperature resistant Ta crucible is used. The target T accommodated in the target holder TH is, for example, a solid Si source. In the MBE apparatus 20, the solid Si source is heated by an electron beam emitted from a high-power electron gun to evaporate Si, and the evaporated Si is attached to the graphite substrate 2, thereby allowing Si on the graphite substrate 2. The thin film is grown. The chamber 21 is provided with a reflection high energy electron diffraction (RHEED) apparatus so that the crystallinity of the substrate or the surface of the thin film can be observed.
　次に、本実施形態に係る半導体基板１を製造する工程を説明する。 Next, a process for manufacturing the semiconductor substrate 1 according to this embodiment will be described.
　まず、バッファ層３の形成工程を説明する。本実施形態では、基板－ターゲット間にパルス直流電圧を印加するＰＳＤ法（パルススパッタ堆積法）を例に挙げて説明する。特に本実施形態では、大面積化が可能なグラファイト基板２上に半導体薄膜を形成するため、ＰＳＤ法を行う意義は大きいといえる。 First, the formation process of the buffer layer 3 will be described. In the present embodiment, a PSD method (pulse sputter deposition method) in which a pulse DC voltage is applied between a substrate and a target will be described as an example. In particular, in this embodiment, since the semiconductor thin film is formed on the graphite substrate 2 capable of increasing the area, it can be said that the PSD method is significant.
　まず、チャンバ１１内にアルゴンガス及び窒素ガスを供給する。アルゴンガス及び窒素ガスによってチャンバ１１内が所定の圧力になった後、グラファイト基板２を基板保持部１３に保持する。グラファイト基板２を基板保持部１３に保持させた後、基板加熱機構１２によって、グラファイト基板２の周囲温度を調節する。グラファイト基板２の周囲温度を調節したら、パルス電源１５を駆動させ、スパッタガン１４ｅからグラファイト基板２の（０００１）面へ向けてＨｆのビームを射出する。 First, argon gas and nitrogen gas are supplied into the chamber 11. After the inside of the chamber 11 reaches a predetermined pressure by argon gas and nitrogen gas, the graphite substrate 2 is held on the substrate holding part 13. After the graphite substrate 2 is held by the substrate holding unit 13, the ambient temperature of the graphite substrate 2 is adjusted by the substrate heating mechanism 12. When the ambient temperature of the graphite substrate 2 is adjusted, the pulse power source 15 is driven to emit a Hf beam from the sputter gun 14 e toward the (0001) plane of the graphite substrate 2.
　パルス電圧が印加されている間、射出されたＨｆ原子は高エネルギーを有した状態でグラファイト基板２上に供給される。グラファイト基板２の表面では、チャンバ内の窒素が窒素ラジカルになっている。グラファイト基板２の（０００１）面上には高エネルギーを有するＨｆ原子が大量に供給され、当該グラファイト基板２の表面は金属リッチの状態になる。 While the pulse voltage is applied, the ejected Hf atoms are supplied onto the graphite substrate 2 with high energy. On the surface of the graphite substrate 2, the nitrogen in the chamber is a nitrogen radical. A large amount of Hf atoms having high energy is supplied onto the (0001) plane of the graphite substrate 2, and the surface of the graphite substrate 2 becomes a metal-rich state.
　金属リッチの状態では、Ｈｆ原子は安定な格子位置にマイグレーションする。安定な格子位置にマイグレーションしたＨｆ原子は、チャンバ１１内で活性化した窒素ラジカルと反応して金属窒化物（ＨｆＮ）の結晶となる。パルス電圧が印加される毎に、結晶構造の安定したＨｆＮが間欠的に堆積されることになる。このようにして、バッファ層３がグラファイト基板２の（０００１）面上に形成される。 In the metal rich state, Hf atoms migrate to a stable lattice position. The Hf atoms migrated to a stable lattice position react with the nitrogen radicals activated in the chamber 11 to form a metal nitride (HfN) crystal. Each time a pulse voltage is applied, HfN having a stable crystal structure is intermittently deposited. In this way, the buffer layer 3 is formed on the (0001) plane of the graphite substrate 2.
　次に、バッファ層３上にＳｉ薄膜を成長させる。本実施形態では、ＭＢＥ法によってＳｉ薄膜を成長させる例に挙げて説明する。特に本実施形態では、大面積化が可能なグラファイト基板２上に半導体薄膜を形成するため、ＭＢＥ法を行う意義は大きいといえる。 Next, a Si thin film is grown on the buffer layer 3. In the present embodiment, an example in which a Si thin film is grown by the MBE method will be described. In particular, in this embodiment, since the semiconductor thin film is formed on the graphite substrate 2 capable of increasing the area, it can be said that the MBE method is significant.
　まず、ターボ分子ポンプによってチャンバ２１内をベースプレッシャーとし、バッファ層３を形成したグラファイト基板２を基板保持部２３に保持させる。また、ターゲットＴをターゲットホルダＴＨ上に設置する。グラファイト基板２及びターゲットＴを配置した後、加熱装置１７によって、グラファイト基板２の周囲温度を調節する。グラファイト基板２の周囲温度を調節した後、電子銃２４の電子電流を調整して、ターゲットホルダＴＨ内のターゲットＴに電子線を照射する。電子線の照射を受けたターゲットＴは、蒸発してグラファイト基板２のバッファ層３上に付着する。本実施形態では、Ｓｉ原子がバッファ層３上に付着し、Ｓｉの薄膜がバッファ層３上に成長する。この薄膜が半導体層４となる。 First, the inside of the chamber 21 is made a base pressure by a turbo molecular pump, and the graphite substrate 2 on which the buffer layer 3 is formed is held on the substrate holding unit 23. Further, the target T is installed on the target holder TH. After placing the graphite substrate 2 and the target T, the ambient temperature of the graphite substrate 2 is adjusted by the heating device 17. After adjusting the ambient temperature of the graphite substrate 2, the electron current of the electron gun 24 is adjusted to irradiate the target T in the target holder TH with an electron beam. The target T irradiated with the electron beam evaporates and adheres to the buffer layer 3 of the graphite substrate 2. In the present embodiment, Si atoms adhere on the buffer layer 3, and a Si thin film grows on the buffer layer 3. This thin film becomes the semiconductor layer 4.
　次に、グラファイト基板２上に形成されたバッファ層３及び半導体層４を剥離する。まず、例えば図５に示すように、バッファ層３及び半導体層４を覆うように、グラファイト基板２上に例えばポリマーやガラス等の構造材５を配置する。次に、図６に示すように、当該構造材５をグラファイト基板２から引き剥がすことによって、構造材５ごとグラファイト基板２からバッファ層３及び半導体層４を剥離する。グラファイト基板２は、層間結合の弱い層状化合物であるため、構造材５、バッファ層３及び半導体層４は、グラファイト基板２から容易に剥離される。このように、バッファ層３及び半導体層４を構造材５に転写することができる。 Next, the buffer layer 3 and the semiconductor layer 4 formed on the graphite substrate 2 are peeled off. First, for example, as shown in FIG. 5, a structural material 5 such as a polymer or glass is disposed on the graphite substrate 2 so as to cover the buffer layer 3 and the semiconductor layer 4. Next, as shown in FIG. 6, the buffer layer 3 and the semiconductor layer 4 are peeled from the graphite substrate 2 together with the structural material 5 by peeling the structural material 5 from the graphite substrate 2. Since the graphite substrate 2 is a layered compound having a weak interlayer bond, the structural material 5, the buffer layer 3, and the semiconductor layer 4 are easily peeled from the graphite substrate 2. Thus, the buffer layer 3 and the semiconductor layer 4 can be transferred to the structural material 5.
　上記により、半導体層を含む層と、グラファイト基板の少なくとも一部を含む層とを分離し、当該半導体層を含む層を得るので、例えば大面積および／または高品位のものを得ることができる。例えば直径１２インチを超える大面積のものが容易に得られる。ここにおいては、得られるものは板状に限定されず、成長させた半導体層を含む層で構成されたものをいう。またこの半導体を含む層は必要に応じ所望の半導体層のみに分離されたものを得ることもできる。 According to the above, the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated to obtain a layer including the semiconductor layer. For example, a large-area and / or high-quality layer can be obtained. For example, a large area exceeding 12 inches in diameter can be easily obtained. Here, what is obtained is not limited to a plate shape, but refers to a structure including a grown semiconductor layer. In addition, the layer containing the semiconductor can be obtained by being separated into only a desired semiconductor layer as necessary.
　次に、図７に示すように、グラファイト基板２から剥離した構造材５、バッファ層３及び半導体層４を例えばガラス基板や石英基板、樹脂フィルムなどの第２基板６上に固定させる。この場合、例えばバッファ層３に接着材などを付与しておき、当該接着材を介して第２基板６に固定させることができる。勿論、他の方法によって固定させることとしても構わない。このようにして、第２基板６上にバッファ層３及び半導体層４を形成することができる。 Next, as shown in FIG. 7, the structural material 5, the buffer layer 3 and the semiconductor layer 4 peeled from the graphite substrate 2 are fixed on a second substrate 6 such as a glass substrate, a quartz substrate, or a resin film. In this case, for example, an adhesive or the like can be applied to the buffer layer 3 and can be fixed to the second substrate 6 via the adhesive. Of course, it may be fixed by other methods. In this way, the buffer layer 3 and the semiconductor layer 4 can be formed on the second substrate 6.
　以上のように、本実施形態によれば、グラファイト基板２が耐熱性を有するため、高温下で製造する手法を用いて低コスト化できる。グラファイト基板２が外力に対する可撓性を有するため曲げることも可能となる。これにより、低コストな半導体基板１が得られる。これに加えて、グラファイトは酸化されにくく、表面処理の再現性が高い。以上のことにより、低コストで再現性の高い半導体基板１を得ることができる。 As described above, according to the present embodiment, since the graphite substrate 2 has heat resistance, the cost can be reduced by using a method of manufacturing at a high temperature. Since the graphite substrate 2 has flexibility with respect to external force, it can be bent. Thereby, the low-cost semiconductor substrate 1 is obtained. In addition to this, graphite is not easily oxidized and the reproducibility of the surface treatment is high. By the above, the semiconductor substrate 1 with high reproducibility can be obtained at low cost.
　また、本実施形態によれば、半導体層４が、層間結合の弱い層状化合物であるグラファイト基板２の（０００１）面上に設けられているため、容易に剥離することができる。これに加えて、グラファイト基板２を構成するグラファイトは酸化されにくく、表面処理の再現性が高い。以上のことにより、低コストで再現性の高い半導体基板を製造することができる。更に、当該構造材５を用いてバッファ層３及び半導体層４を剥離することにより、容易に剥離することができると共に、当該バッファ層３及び半導体層４を別の第２基板６上に配置した後には構造材５によってバッファ層３及び半導体層４を保護することができる。 Moreover, according to this embodiment, since the semiconductor layer 4 is provided on the (0001) plane of the graphite substrate 2 which is a layered compound having a weak interlayer bond, it can be easily peeled off. In addition, the graphite constituting the graphite substrate 2 is not easily oxidized and the reproducibility of the surface treatment is high. As described above, a semiconductor substrate with low cost and high reproducibility can be manufactured. Furthermore, the buffer layer 3 and the semiconductor layer 4 can be easily peeled off by using the structural material 5, and the buffer layer 3 and the semiconductor layer 4 are disposed on another second substrate 6. The buffer layer 3 and the semiconductor layer 4 can be protected later by the structural material 5.
　本発明の技術範囲は上記実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲で適宜変更を加えることができる。
　例えば、上記実施形態では、バッファ層３をパルススパッタ法によって形成し、半導体層４をＭＢＥ法によって形成しているが、これに限られることはなく、例えばＰＬＤ法（パルスレーザ堆積法）やＰＥＤ法（パルス電子線堆積法）を含むＰＸＤ法（Pulsed Excitation Deposition：パルス励起堆積法）有機金属成長法、分子線エピタキシー法、ＣＶＤ法など、他の薄膜形成方法によって形成しても構わない。 The technical scope of the present invention is not limited to the above-described embodiment, and appropriate modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, the buffer layer 3 is formed by the pulse sputtering method, and the semiconductor layer 4 is formed by the MBE method. However, the present invention is not limited to this. For example, a PLD method (pulse laser deposition method) or PED is used. PXD (Pulsed Excitation Deposition) including a method (pulse electron beam deposition) may be formed by other thin film forming methods such as an organic metal growth method, a molecular beam epitaxy method, a CVD method, or the like.
　また、上記実施形態では、グラファイト基板２上にＨｆＮ（１１１）からなるバッファ層３を形成することとしたが、これに限られることは無く、例えばＺｒＮ（１１１）からなるバッファ層３を形成する構成であっても構わない。また、バッファ層３を形成することなく、グラファイト基板２上に直接半導体層４を成長させる構成であっても構わないし、半導体層４を積層する構成（例えば、ＧａＮ層／ＡｌＮ層／グラファイト、など）であっても構わない。 In the above embodiment, the buffer layer 3 made of HfN (111) is formed on the graphite substrate 2. However, the present invention is not limited to this. For example, the buffer layer 3 made of ZrN (111) is formed. It may be a configuration. Alternatively, the semiconductor layer 4 may be grown directly on the graphite substrate 2 without forming the buffer layer 3, or the semiconductor layer 4 may be stacked (for example, GaN layer / AlN layer / graphite). ).
　また、上記実施形態では、半導体層４として、シリコンを成長させる例を挙げて説明したが、これに限られることは無く、例えば１３族窒化物半導体を成長させる構成としても構わない。１３族窒化物としては、例えばＧａＮ（ガリウムナイトライド）、ＡｌＮ（アルミニウムナイトライド）、ＩｎＮ（インジウムナイトライド）などが挙げられ、一般式ＩｎＸＧａＹＡｌ１－Ｘ－ＹＮ（０≦Ｘ≦１、０≦Ｙ≦１、０≦Ｘ＋Ｙ≦１）で表される。この場合、例えばパルススパッタ法など、上記手法を用いて形成することができる。 In the above embodiment, the semiconductor layer 4 is described as an example of growing silicon. However, the present invention is not limited to this. For example, a group 13 nitride semiconductor may be grown. Examples of the group 13 nitride include GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), and the like. The general formula InXGaYAl1-XYN (0 ≦ X ≦ 1, 0 ≦ Y) ≦ 1, 0 ≦ X + Y ≦ 1). In this case, it can be formed by using the above method such as a pulse sputtering method.
　本発明の半導体基板１は適用範囲が広く、非晶質基板上への発光ダイオード、半導体レーザなどの半導体素子などに用いることができる。また、当該半導体素子を用いた非晶質基板上への透明回路としても用いることができる。 The semiconductor substrate 1 of the present invention has a wide range of applications and can be used for semiconductor elements such as light emitting diodes and semiconductor lasers on an amorphous substrate. Further, it can also be used as a transparent circuit on an amorphous substrate using the semiconductor element.
　このほかにも、例えばフラットパネルディスプレイ、太陽電池、タッチパネルなどの透明電極へ適用が考えられる。また、反射防止膜に用いられる電磁波の遮蔽、静電気により埃がつかないようにするフィルム、帯電防止膜、熱線反射ガラス、紫外線反射ガラスへ適用も考えられる。 Other than this, for example, it can be applied to transparent electrodes such as flat panel displays, solar cells, and touch panels. Further, it can be applied to the shielding of electromagnetic waves used for the antireflection film, a film that prevents dust from sticking due to static electricity, an antistatic film, heat ray reflective glass, and ultraviolet reflective glass.
　用途の例として、色素増感太陽電池の電極；ディスプレイパネル、有機ＥＬパネル、発光素子、発光ダイオード（ＬＥＤ）、白色ＬＥＤやレーザの透明電極；面発光レーザの透明電極；照明装置；通信装置；特定の波長範囲だけ光を通すというアプリケーションも考えられる。 Examples of applications include dye-sensitized solar cell electrodes; display panels, organic EL panels, light-emitting elements, light-emitting diodes (LEDs), white LEDs and laser transparent electrodes; surface-emitting laser transparent electrodes; lighting devices; An application that allows light to pass through only a specific wavelength range is also conceivable.
　さらに具体的な用途として次のものを挙げることができる。液晶ディスプレイ（ＬＣＤ：Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ　Ｄｉｓｐｌａｙ）における透明導電膜；カラーフィルタ部における透明導電性膜；ＥＬ（ＥＬ：Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）ディスプレイにおける透明導電性膜；プラズマディスプレイ（ＰＤＰ）における透明導電膜；ＰＤＰ光学フィルタ；電磁波遮蔽のための透明導電膜；近赤外線遮蔽のための透明導電膜；表面反射防止のための透明導電膜；色再現性の向上のための透明導電膜；破損対策のための透明導電膜；光学フィルタ；タッチパネル；抵抗膜式タッチパネル；電磁誘導式タッチパネル；超音波式タッチパネル；光学式タッチパネル；静電容量式タッチパネル；携帯情報端末向け抵抗膜式タッチパネル；ディスプレイと一体化したタッチパネル（インナータッチパネル）；太陽電池；アモルファスシリコン（ａ－Ｓｉ）系太陽電池；微結晶Ｓｉ薄膜太陽電池；ＣＩＧＳ太陽電池；色素増感太陽電池（ＤＳＣ）；電子部品の静電気対策用透明導電材料；帯電防止用透明導電材；調光材料；調光ミラー；発熱体（面ヒーター、電熱ガラス）；電磁波遮蔽ガラス。更に、これらを搭載した携帯電話や情報端末、電子計算機、ＯＡ機器など、種々の電子機器に対しても本発明の適用は可能である。 The following can be listed as more specific uses. Transparent conductive film in liquid crystal display (LCD: Liquid Crystal Display); Transparent conductive film in color filter portion; Transparent conductive film in EL (EL: Electro Luminescence) display; Transparent conductive film in plasma display (PDP); PDP optical filter Transparent conductive film for shielding electromagnetic waves; transparent conductive film for shielding near infrared; transparent conductive film for preventing surface reflection; transparent conductive film for improving color reproducibility; transparent conductive film for preventing damage Optical filter; touch panel; resistive touch panel; electromagnetic induction touch panel; ultrasonic touch panel; optical touch panel; capacitive touch panel; resistive touch panel for personal digital assistants; Touch panel); Solar cell; Amorphous silicon (a-Si) solar cell; Microcrystalline Si thin film solar cell; CIGS solar cell; Dye-sensitized solar cell (DSC); Transparent conductive material; dimming material; dimming mirror; heating element (surface heater, electrothermal glass); electromagnetic wave shielding glass. Furthermore, the present invention can be applied to various electronic devices such as a mobile phone, an information terminal, an electronic computer, and an OA device equipped with these.
（実施例１）
　次に、本発明の実施例を説明する。 Example 1
Next, examples of the present invention will be described.
　本実施例では、半導体層４としてＳｉを用い、バッファ層３としてＨｆＮを用いた例を挙げて説明する。バッファ層３は、パルススパッタ法により、以下の条件で約５０ｎｍ程度成長させた。 In this embodiment, an example in which Si is used as the semiconductor layer 4 and HfN is used as the buffer layer 3 will be described. The buffer layer 3 was grown by about 50 nm under the following conditions by pulse sputtering.
　ターゲット：Ｈｆ（純度９９ｗｔ％）
　成長温度：１０００℃
　基板：　（０００１）面を表面に有するグラファイトからなるグラファイト基板
　成長圧力：３×１０－３Ｔｏｒｒ
　ガス流量比：Ｎ２／Ａｒ＝１：４
　ターゲットバイアス：３００Ｖ
　供給電流：０．３Ａ Target: Hf (purity 99wt%)
Growth temperature: 1000 ° C
Substrate: Graphite substrate made of graphite having (0001) plane on its surface Growth pressure: 3 × 10 −3 Torr
Gas flow ratio: N2 / Ar = 1: 4
Target bias: 300V
Supply current: 0.3A
　グラファイト基板上にバッファ層としてＨｆＮを成長させた後、Ｓｉを成長するためのＭＢＥ装置に試料を搬送し、Ｓｉを成長させた。本実施例では、電子銃の出力は電圧８ｋＶ、電子電流を３００ｍＡとし、３００ｍＡで使用時の成長レートはおよそ６オングストローム／ｓｅｃとした。本実施例では成長中のグラファイト基板２の温度は９００℃となるようにコントロールし、３μｍのＳｉ結晶を成長した。 After growing HfN as a buffer layer on the graphite substrate, the sample was transferred to an MBE apparatus for growing Si, and Si was grown. In this example, the output of the electron gun was 8 kV, the electron current was 300 mA, and the growth rate when used at 300 mA was approximately 6 Å / sec. In this example, the temperature of the growing graphite substrate 2 was controlled to 900 ° C., and a 3 μm Si crystal was grown.
　図８Ａは、電子線後方散乱回折の＜１１１＞極点図である。図８Ａは、そのＲＨＥＥＤ像を示す。図８Ａに示すように、ＥＢＳＤ＜１１１＞極点図が明瞭な３回回転対称性を持っていることから分かる様にＳｉは良質な（１１１）面結晶となった。また、図８Ｂに示すように、ＲＨＥＥＤ像がコントラストの強いストリーク（線状）パターンであることからも表面が平坦で良質な（１１１）結晶が成長していることがわかる。 FIG. 8A is a <111> pole figure of electron beam backscatter diffraction. FIG. 8A shows the RHEED image. As shown in FIG. 8A, Si was a good (111) plane crystal as can be seen from the EBSD <111> pole figure having clear three-fold rotational symmetry. Further, as shown in FIG. 8B, it can be seen that a high-quality (111) crystal with a flat surface is grown because the RHEED image is a streak (linear) pattern having a high contrast.
（実施例２）
　本実施例では、上記実施形態の手法（パルススパッタ法）によってグラファイト基板２上にＡｌＮ層を形成し、当該ＡｌＮ層上にＧａＮ層をさらに形成した。ＡｌＮ成長時には温度１０００℃～１２００℃程度で加熱し、加熱時間を３０ｍｉｎ～６０ｍｉｎ程度とした。ＧａＮ成長時には、温度６５０℃～７５０℃程度で加熱し、加熱時間を６０ｍｉｎ～１２０ｍｉｎとした。 (Example 2)
In this example, an AlN layer was formed on the graphite substrate 2 by the method of the above embodiment (pulse sputtering method), and a GaN layer was further formed on the AlN layer. During the growth of AlN, heating was performed at a temperature of about 1000 ° C. to 1200 ° C., and the heating time was about 30 min to 60 min. During GaN growth, heating was performed at a temperature of about 650 ° C. to 750 ° C., and the heating time was set to 60 min to 120 min.
　また、このようにして作製した半導体基板（ＧａＮ／ＡｌＮ／グラファイト）について、反射型高速電子線回折（ＲＨＥＥＤ）、Ｘ線回折（ＸＲＤ）、走査型電子顕微鏡（ＳＥＭ）、電子線後方散乱回折（ＥＢＳＤ）、フォトルミネッセンス（ＰＬ）の評価法で評価した。 In addition, with respect to the semiconductor substrate (GaN / AlN / graphite) thus produced, reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), scanning electron microscope (SEM), electron beam backscatter diffraction ( EBSD) and photoluminescence (PL) were evaluated.
　図９は、グラファイト層及びＡｌＮ層についてのＸＲＤによる測定結果を示すグラフである。
　同図に示すように、グラファイト層は（００２）方向に成長しており、ＡｌＮ層は（０００２）方向に成長しており、ＡｌＮ層はｃ軸配向性を示していると認められる。 FIG. 9 is a graph showing measurement results by XRD for the graphite layer and the AlN layer.
As shown in the figure, the graphite layer grows in the (002) direction, the AlN layer grows in the (0002) direction, and the AlN layer is recognized to exhibit c-axis orientation.
　図１０はＡｌＮ層のＥＢＳＤ測定図である。
　同図に示すように、ＡｌＮ層には１μｍ以上のグレインサイズを有する結晶が多く形成されていることが分かる。 FIG. 10 is an EBSD measurement diagram of the AlN layer.
As shown in the figure, it can be seen that many crystals having a grain size of 1 μm or more are formed in the AlN layer.
　図１１は、ＡｌＮ層の一部についての｛１０－１２｝ＥＢＳＤ極点図である。
　同図に示すように、正六角形の頂点上に明確なパターンが認められる。このことからＡｌＮ層の結晶性が良好であることが分かる。 FIG. 11 is a {10-12} EBSD pole figure for a portion of the AlN layer.
As shown in the figure, a clear pattern is recognized on the apex of the regular hexagon. This shows that the crystallinity of the AlN layer is good.
　図１２は、グラファイト層及びＧａＮ層についてのＸＲＤによる測定結果を示すグラフである。
　同図に示すように、ＧａＮ層はＡｌＮ層と同様に（０００２）方向に成長しており、ｃ軸配向性を示していると認められる。 FIG. 12 is a graph showing measurement results by XRD for the graphite layer and the GaN layer.
As shown in the figure, the GaN layer grows in the (0002) direction like the AlN layer, and it is recognized that it exhibits c-axis orientation.
　図１３は、ＧａＮ層の表面のＳＥＭ像である。
　同図に示すように、ＧａＮ層の表面には特段に大きな凹凸は見られず、比較的平坦な表面に形成されていることが分かる。 FIG. 13 is an SEM image of the surface of the GaN layer.
As shown in the figure, it can be seen that the surface of the GaN layer has no particularly large irregularities and is formed on a relatively flat surface.
　図１４は、ＧａＮ層のＥＢＳＤ測定図である。
　同図に示すように、ＧａＮ層には１μｍ以上のグレインサイズを有する結晶が多く形成されていることがわかる。 FIG. 14 is an EBSD measurement diagram of the GaN layer.
As shown in the figure, it is understood that many crystals having a grain size of 1 μm or more are formed in the GaN layer.
　図１５Ａ及び１５Ｂは、ＧａＮ層のＥＢＳＤ極点図である。図１５ＡはＧａＮ層の一部分についての｛１０－１２｝ＥＢＳＤ極点図であり、図１５ＢはＧａＮ層の他部分についての｛１０－１２｝ＥＢＳＤ極点図である。
　図１５Ａ及び図１５Ｂに示すように、正六角形の頂点上に明確なパターンが認められる。このことからそれぞれのグレインは高い結晶性を有していることが分かる。 15A and 15B are EBSD pole figures of the GaN layer. FIG. 15A is a {10-12} EBSD pole figure for a part of the GaN layer, and FIG. 15B is a {10-12} EBSD pole figure for the other part of the GaN layer.
As shown in FIGS. 15A and 15B, a clear pattern is recognized on the apex of the regular hexagon. This indicates that each grain has high crystallinity.
　図１６は、ＧａＮ層の室温でのＰＬ測定の結果を示すグラフである。図１７は、従来のＭＯＣＶＤで作製したＧａＮの室温でのＰＬ測定の結果を示すグラフである。両図共に、グラフの縦軸がＰＬ強度であり、グラフの横軸が発光エネルギーである。
　図１６に示すように、本実施例で得られたＧａＮ層については、発光エネルギーが３．４ｅＶ付近において強いピークが認められる。このピークの半値幅を測定したら、６３ｍｅＶであった。また、図１７に示すように、従来のＧａＮ基板については、３．４ｅＶ付近において強いピークが認められる。このピークの半値幅を測定したら、６６ｍｅＶであった。図１６と図１７との結果とを比較すると、本実施例で得られたＧａＮ層の発光特性は、従来のＧａＮ基板の発光特性に比べて同等以上であることが分かる。 FIG. 16 is a graph showing the results of PL measurement at room temperature of the GaN layer. FIG. 17 is a graph showing the results of PL measurement at room temperature of GaN produced by conventional MOCVD. In both figures, the vertical axis of the graph is the PL intensity, and the horizontal axis of the graph is the emission energy.
As shown in FIG. 16, for the GaN layer obtained in this example, a strong peak is observed when the emission energy is around 3.4 eV. It was 63 meV when the half width of this peak was measured. Further, as shown in FIG. 17, a strong peak is observed in the vicinity of 3.4 eV for the conventional GaN substrate. It was 66 meV when the half value width of this peak was measured. Comparing the results of FIG. 16 and FIG. 17, it can be seen that the light emission characteristics of the GaN layer obtained in this example are equal to or higher than the light emission characteristics of the conventional GaN substrate.
　本発明は、低コストで再現性の高い半導体基板、半導体基板の製造方法、半導体素子、発光素子、表示パネル、電子素子、太陽電池素子及び電子機器に係るものであり、産業上適用できる。 The present invention relates to a low-cost and highly reproducible semiconductor substrate, a method for manufacturing a semiconductor substrate, a semiconductor element, a light emitting element, a display panel, an electronic element, a solar cell element, and an electronic device, and is industrially applicable.
１…半導体基板　２…グラファイト基板　３…バッファ層　４…半導体薄膜　５…構造材　６…第２基板 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Graphite substrate 3 ... Buffer layer 4 ... Semiconductor thin film 5 ... Structural material 6 ... 2nd substrate

Claims (33)

  1. 　耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板と、
    　前記グラファイト基板上に設けられ、シリコンからなる半導体層と
    　を備えることを特徴とする半導体基板。     A graphite substrate having heat resistance and flexibility against external force;
    A semiconductor substrate comprising: a semiconductor layer provided on the graphite substrate and made of silicon.
  2. 　前記グラファイト基板は、焼結されたポリマーを含んでいる
    　ことを特徴とする請求項１に記載の半導体基板。     The semiconductor substrate according to claim 1, wherein the graphite substrate includes a sintered polymer.
  3. 　前記グラファイト基板の厚さは１０μｍ以上１００μｍ以下である
    　ことを特徴とする請求項１又は請求項２に記載の半導体基板。     The thickness of the said graphite substrate is 10 micrometers or more and 100 micrometers or less. The semiconductor substrate of Claim 1 or Claim 2 characterized by the above-mentioned.
  4. 　前記グラファイト基板と前記半導体層との間に設けられ、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を更に備える
    　ことを特徴とする請求項１から請求項３のうちいずれか一項に記載の半導体基板。     The semiconductor according to any one of claims 1 to 3, further comprising a buffer layer provided between the graphite substrate and the semiconductor layer and including at least one of HfN and ZrN. substrate.
  5. 　前記グラファイト基板と前記半導体層との間に設けられ、ＡｌＮを含む第２バッファ層を更に備える
    　ことを特徴とする請求項１から請求項４のうちいずれか一項に記載の半導体基板。     The semiconductor substrate according to any one of claims 1 to 4, further comprising a second buffer layer provided between the graphite substrate and the semiconductor layer and containing AlN.
  6. 　前記グラファイト基板は、（０００１）面を表面に有し、
    　前記半導体層は、前記（０００１）面上に設けられる
    　ことを特徴とする請求項１から請求項５のうちいずれか一項に記載の半導体基板。     The graphite substrate has a (0001) surface on the surface,
    The semiconductor substrate according to claim 1, wherein the semiconductor layer is provided on the (0001) plane.
  7. 　耐熱性を有すると共に外力に対する可撓性を有するグラファイト基板上に、シリコンからなる半導体層を成長させる
    　ことを特徴とする半導体基板の製造方法。     A method for producing a semiconductor substrate, comprising: growing a semiconductor layer made of silicon on a graphite substrate having heat resistance and flexibility against external force.
  8. 　焼結されたポリマーを含む前記グラファイト基板上に、前記半導体層を成長させる
    　ことを特徴とする請求項７に記載の半導体基板の製造方法。     The method for producing a semiconductor substrate according to claim 7, wherein the semiconductor layer is grown on the graphite substrate containing a sintered polymer.
  9. 　厚さが１０μｍ以上１００μｍ以下に形成された前記グラファイト基板上に、前記半導体層を成長させる
    　ことを特徴とする請求項７又は請求項８に記載の半導体基板の製造方法。     9. The method of manufacturing a semiconductor substrate according to claim 7, wherein the semiconductor layer is grown on the graphite substrate having a thickness of 10 μm to 100 μm.
  10. 　前記グラファイト基板は、（０００１）面を表面に有し、
    　前記（０００１）面に前記半導体層を成長させる
    　ことを特徴とする請求項７から請求項９のうちいずれか一項に記載の半導体基板の製造方法。     The graphite substrate has a (0001) surface on the surface,
    The method for manufacturing a semiconductor substrate according to claim 7, wherein the semiconductor layer is grown on the (0001) plane.
  11. 　前記グラファイト基板上に、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を形成し、
    　前記バッファ層上に、前記半導体層を成長させる
    　ことを特徴とする請求項７から請求項１０のうちいずれか一項に記載の半導体基板の製造方法。     Forming a buffer layer containing at least one of HfN and ZrN on the graphite substrate;
    The method for manufacturing a semiconductor substrate according to any one of claims 7 to 10, wherein the semiconductor layer is grown on the buffer layer.
  12. 　前記グラファイト基板上に、ＡｌＮを含む第２バッファ層を形成し、
    　前記第２バッファ層上に、前記半導体層を成長させる
    　ことを特徴とする請求項７から請求項１１のうちいずれか一項に記載の半導体基板の製造方法。     Forming a second buffer layer containing AlN on the graphite substrate;
    The method for manufacturing a semiconductor substrate according to any one of claims 7 to 11, wherein the semiconductor layer is grown on the second buffer layer.
  13. 　前記半導体層を成長させた後、当該半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離し、
    　分離した前記半導体層を含む層を前記グラファイト基板とは異なる第２基板上に配置する
    　ことを特徴とする請求項７から請求項１２のうちいずれか一項に記載の半導体基板の製造方法。     After growing the semiconductor layer, separating the layer including the semiconductor layer and the layer including at least a part of the graphite substrate,
    The method for manufacturing a semiconductor substrate according to any one of claims 7 to 12, wherein the separated layer including the semiconductor layer is disposed on a second substrate different from the graphite substrate.
  14. 　前記グラファイト基板は、所定の層間結合力を有する層状化合物を含み、
    　前記グラファイト基板の層間結合力よりも大きい力を前記層状化合物の層間に作用させて前記グラファイト基板の層間結合を解除することで、前記半導体層を含む層と前記グラファイトの少なくとも一部を含む層とを分離する
    　ことを特徴とする請求項１３に記載の半導体基板の製造方法。     The graphite substrate includes a layered compound having a predetermined interlayer bonding force,
    A force greater than the interlayer bonding force of the graphite substrate is applied between the layers of the layered compound to release the interlayer bonding of the graphite substrate, thereby providing a layer including the semiconductor layer and a layer including at least a part of the graphite. The method for manufacturing a semiconductor substrate according to claim 13, wherein the semiconductor substrate is separated.
  15. 　前記半導体層を含む層を分離する際には、所定の構造材を用いて前記半導体層を含む層を保持し前記構造材ごと前記半導体層を含む層を分離する
    　ことを特徴とする請求項１３又は請求項１４に記載の半導体基板の製造方法。     14. When separating the layer including the semiconductor layer, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated together with the structural material. Or the manufacturing method of the semiconductor substrate of Claim 14.
  16. 　分離した前記半導体層を含む層を前記第２基板上に配置する際には、前記構造材ごと前記半導体層を含む層を配置する
    　ことを特徴とする請求項１５に記載の半導体基板の製造方法。     The method for manufacturing a semiconductor substrate according to claim 15, wherein when the separated layer including the semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer is disposed together with the structural material. .
  17. 　耐熱性を有すると共に外力に対する可撓性を有するグラファイトに、半導体層を成長させた後、当該半導体層を含む層と前記グラファイト基板の少なくとも一部を含む層とを分離し、当該半導体層を含む層を得る
    　ことを特徴とする半導体層の製造方法。     A semiconductor layer is grown on graphite having heat resistance and flexibility against external force, and then the layer including the semiconductor layer and the layer including at least a part of the graphite substrate are separated to include the semiconductor layer. A method for producing a semiconductor layer, comprising: obtaining a layer.
  18. 　耐熱性を有すると共に外力に対する可撓性を有するグラファイトに、前記半導体層を成長させた後、当該半導体層を含む層と前記グラファイトの少なくとも一部を含む層とを分離し、分離した前記当該半導体層を含む層を前記グラファイト基板とは異なる第２基板上に配置する
    　ことを特徴とする半導体基板の製造方法。     After the semiconductor layer is grown on graphite having heat resistance and flexibility against external force, the semiconductor layer is separated from the layer including the semiconductor layer and the layer including at least a part of the graphite, and the semiconductor is separated. A method for manufacturing a semiconductor substrate, comprising: arranging a layer including a layer on a second substrate different from the graphite substrate.
  19. 　前記半導体層は、１３族窒化物からなる
    　ことを特徴とする請求項１８に記載の半導体基板の製造方法。     The method for manufacturing a semiconductor substrate according to claim 18, wherein the semiconductor layer is made of a group 13 nitride.
  20. 　前記グラファイト基板は、所定の層間結合力を有する層状化合物を含み、
    　前記グラファイト基板の層間結合力よりも大きい力を前記層状化合物の層間に作用させて前記グラファイト基板の層間結合を解除することで、前記半導体層を含む層と前記グラファイトの少なくとも一部を含む層とを分離する
    　ことを特徴とする請求項１８から請求項１９のうちいずれか一項に記載の半導体基板の製造方法。     The graphite substrate includes a layered compound having a predetermined interlayer bonding force,
    A force greater than the interlayer bonding force of the graphite substrate is applied between the layers of the layered compound to release the interlayer bonding of the graphite substrate, thereby providing a layer including the semiconductor layer and a layer including at least a part of the graphite. The method for manufacturing a semiconductor substrate according to claim 18, wherein the semiconductor substrate is separated.
  21. 　前記半導体層を含む層を分離する際には、所定の構造材を用いて前記半導体層を含む層を保持し前記構造材ごと前記半導体層を含む層を分離する
    　ことを特徴とする請求項１８から請求項２０のうちいずれか一項に記載の半導体基板の製造方法。     19. When separating the layer including the semiconductor layer, the layer including the semiconductor layer is held using a predetermined structural material, and the layer including the semiconductor layer is separated together with the structural material. The manufacturing method of the semiconductor substrate as described in any one of Claim 20.
  22. 　分離した前記半導体層を含む層を前記第２基板上に配置する際には、前記構造材ごと前記半導体層を含む層を配置する
    　ことを特徴とする請求項２１に記載の半導体基板の製造方法。     The method for manufacturing a semiconductor substrate according to claim 21, wherein when the separated layer including the semiconductor layer is disposed on the second substrate, the layer including the semiconductor layer is disposed together with the structural material. .
  23. 　焼結されたポリマーを含む前記グラファイト基板上に、前記半導体層を成長させる
    　ことを特徴とする請求項１８から請求項２２のうちいずれか一項に記載の半導体基板の製造方法。     The method for producing a semiconductor substrate according to any one of claims 18 to 22, wherein the semiconductor layer is grown on the graphite substrate containing a sintered polymer.
  24. 　厚さが１０μｍ以上１００μｍ以下に形成された前記グラファイト基板上に、前記半導体層を成長させる
    　ことを特徴とする請求項１８から請求項２３のうちいずれか一項に記載の半導体基板の製造方法。     The method for manufacturing a semiconductor substrate according to any one of claims 18 to 23, wherein the semiconductor layer is grown on the graphite substrate having a thickness of 10 µm to 100 µm.
  25. 　前記グラファイト基板は、（０００１）面を表面に有し、
    　前記（０００１）面に前記半導体層を成長させる
    　ことを特徴とする請求項１８から請求項２４のうちいずれか一項に記載の半導体基板の製造方法。     The graphite substrate has a (0001) plane on the surface,
    The method for manufacturing a semiconductor substrate according to any one of claims 18 to 24, wherein the semiconductor layer is grown on the (0001) plane.
  26. 　前記グラファイト基板上に、ＨｆＮ及びＺｒＮのうち少なくとも一方を含むバッファ層を形成し、
    　前記バッファ層上に、前記半導体層を成長させる
    　ことを特徴とする請求項１８から請求項２５のうちいずれか一項に記載の半導体基板の製造方法。     Forming a buffer layer containing at least one of HfN and ZrN on the graphite substrate;
    The method for manufacturing a semiconductor substrate according to any one of claims 18 to 25, wherein the semiconductor layer is grown on the buffer layer.
  27. 　前記グラファイト基板上に、ＡｌＮを含む第２バッファ層を形成し、
    　前記第２バッファ層上に、前記半導体層を成長させる
    　ことを特徴とする請求項１８から請求項２６のうちいずれか一項に記載の半導体基板の製造方法。     Forming a second buffer layer containing AlN on the graphite substrate;
    The method for manufacturing a semiconductor substrate according to any one of claims 18 to 26, wherein the semiconductor layer is grown on the second buffer layer.
  28. 　請求項１から請求項７のうちいずれか一項に記載の半導体基板を備えることを特徴とする半導体素子。 A semiconductor element comprising the semiconductor substrate according to any one of claims 1 to 7.
  29. 　請求項２８に記載の半導体素子を備えることを特徴とする発光素子。 A light-emitting element comprising the semiconductor element according to claim 28.
  30. 　請求項２９に記載の発光素子を備えることを特徴とする表示パネル。 A display panel comprising the light-emitting element according to claim 29.
  31. 　請求項３０に記載の半導体素子を備えることを特徴とする電子素子。 An electronic device comprising the semiconductor device according to claim 30.
  32. 　請求項１から請求項７のうちいずれか一項に記載の半導体基板を備えることを特徴とする太陽電池素子。 A solar cell element comprising the semiconductor substrate according to any one of claims 1 to 7.
  33. 　請求項２８に記載の半導体素子、請求項２９に記載の発光素子、請求項３０に記載の表示パネル、請求項３１に記載の電子素子及び請求項３２に記載の太陽電池素子のうち少なくとも１つを備えることを特徴とする電子機器。 At least one of the semiconductor element according to claim 28, the light emitting element according to claim 29, the display panel according to claim 30, the electronic element according to claim 31, and the solar cell element according to claim 32. An electronic device comprising:
PCT/JP2009/004002 2009-08-20 2009-08-20 Semiconductor substrate, method for production of semiconductor layer, method for production of semiconductor substrate, semiconductor element, luminescent element, display panel, electronic element, solar battery element, and electronic device WO2011021248A1 (en)

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