WO2010106810A1 - Equalizer and equalization method - Google Patents
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- WO2010106810A1 WO2010106810A1 PCT/JP2010/001971 JP2010001971W WO2010106810A1 WO 2010106810 A1 WO2010106810 A1 WO 2010106810A1 JP 2010001971 W JP2010001971 W JP 2010001971W WO 2010106810 A1 WO2010106810 A1 WO 2010106810A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
- G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
- G11B20/1012—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom partial response PR(1,2,2,2,1)
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
- G11B20/10212—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter compensation for data shift, e.g. pulse-crowding effects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10268—Improvement or modification of read or write signals bit detection or demodulation methods
- G11B20/10287—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors
- G11B20/10296—Improvement or modification of read or write signals bit detection or demodulation methods using probabilistic methods, e.g. maximum likelihood detectors using the Viterbi algorithm
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
- G11B2220/2541—Blu-ray discs; Blue laser DVR discs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
- G11B2220/2562—DVDs [digital versatile discs]; Digital video discs; MMCDs; HDCDs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
- G11B2220/2579—HD-DVDs [high definition DVDs]; AODs [advanced optical discs]
Definitions
- the present invention relates to an equalizer, and more particularly to an equalizer and an equalization method for equalizing nonlinear distortion.
- the disk control circuit rotates the optical disk at a predetermined rotation speed, and the optical pickup reads a reproduction signal recorded on the optical disk.
- the reproduction signal is amplified by a preamplifier and then amplified to a predetermined amplitude by an AGC circuit or the like.
- the reproduction signal is A / D converted, waveform equalized by a linear waveform equalization circuit, and then decoded by Viterbi decoding.
- image data and music data recorded on the optical disc are reproduced.
- a nonlinear waveform equalization circuit is used to reduce nonlinear distortion.
- a neural network is used to realize a nonlinear waveform equalization circuit (see, for example, Patent Document 1).
- a training signal is recorded at a predetermined location on the optical disc, and a coefficient in the neural network is determined using an output corresponding to the training signal as a teacher signal. Therefore, since the training signal is recorded in advance on the optical disc, the utilization efficiency of the optical disc is reduced. In addition, since the coefficient is fixed after the learning operation is finished, it is difficult to follow the fluctuation of the reproduction waveform characteristic in the plane of the optical disc. Furthermore, there are power fluctuations and the like depending on the recorder that records data on the optical disc, but it is also difficult to follow them. For this reason, it is required to adaptively reduce the linear distortion without using a training signal as well as adaptively reducing the non-linear distortion of the reproduction signal caused by the improvement of the recording density and the recording power fluctuation.
- the present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique for reducing non-linear distortion of a reproduction signal caused by improvement in recording density, recording power fluctuation or the like without a training signal.
- an equalizer sequentially linearly equalizes a signal to be processed and linearly equalizes a signal that is linearly equalized in the linear equalization unit.
- the temporary determination unit may execute a temporary determination according to the partial response rule. In this case, the provisional determination according to the partial response rule is executed, so that the partial response process can be handled.
- a delay unit that delays the signal that is nonlinearly equalized in the nonlinear equalizer may be further provided.
- the delay unit executes delay over a period corresponding to the difference between the processing delay in the temporary determination unit and the processing delay in the nonlinear equalization unit, and the nonlinear equalization unit performs the temporary determination in the signal delayed in the delay unit and the temporary determination unit.
- a plurality of coefficients may be derived based on the difference from the signal. In this case, since the delay is executed over a period corresponding to the difference between the processing delay in the provisional determination unit and the processing delay in the nonlinear equalization unit, the timing of the delayed signal and the provisionally determined signal can be matched.
- the non-linear equalization unit may newly derive a plurality of coefficients when the difference becomes larger than the threshold value. In this case, since a plurality of coefficients are newly derived when divergence is detected, deterioration of equalization characteristics can be suppressed.
- Another aspect of the present invention is an equalization method.
- an input signal is sequentially linearly equalized, a linearly equalized signal is sequentially provisionally determined, a plurality of coefficients are derived using the provisionally determined signal as a teacher signal, and a plurality of coefficients are included. And sequentially performing nonlinear equalization on the linearly equalized signal.
- the equalizer includes an input unit that sequentially inputs a signal to be processed, a linear equalization unit that sequentially linearly equalizes the signal input at the input unit, and an input that is performed in parallel with the linear equalization in the linear equalization unit.
- An adaptive nonlinear equalization unit that sequentially performs nonlinear equalization on the input signal, an addition unit that adds the nonlinear equalization signal in the adaptive nonlinear equalization unit, and the linear equalization signal in the linear equalization unit, and addition
- a provisional determination unit that sequentially provisionally determines signals added in the unit.
- the adaptive nonlinear equalization unit derives a plurality of coefficients using the signal provisionally determined by the provisional determination unit as a teacher signal, and performs nonlinear equalization based on the plurality of coefficients.
- linear equalization and non-linear equalization are performed in parallel, the equalization signals from both are added, and the result of provisional determination of the addition signal is used as a teacher signal, so that no training signal is used.
- a coefficient for nonlinear equalization can be derived.
- the multi-stage tap included in the linear equalization unit and the multi-stage tap in the adaptive nonlinear equalization unit may be shared. In this case, since multistage taps are shared, an increase in circuit scale can be suppressed.
- the temporary determination unit may execute a temporary determination according to the partial response rule. In this case, the provisional determination according to the partial response rule is executed, so that the partial response process can be handled.
- a determination unit that determines convergence of a plurality of coefficients in the adaptive nonlinear equalization unit may be further provided.
- the adder outputs the signal linearly equalized by the linear equalizer to the temporary determiner until convergence is determined by the determiner, and after the convergence is determined by the determiner, the added signal is temporarily determined. You may output to a part. In this case, since the nonlinear equalized signal is not output to the provisional determination unit until the nonlinear equalization coefficient is converged, deterioration of the accuracy of the provisional determination can be suppressed.
- a linear delay unit may further include a first delay unit that delays the linearly equalized signal, and a second delay unit that delays the nonlinear equalized signal in the adaptive nonlinear equalization unit.
- the first delay unit executes a delay over a period according to the processing delay in the temporary determination unit
- the second delay unit executes a delay over a period according to the processing delay in the temporary determination unit
- the adaptive nonlinear equalization unit The linear equalization unit derives a plurality of coefficients based on the difference between the sum of the signal delayed in the first delay unit and the signal delayed in the second delay unit and the signal provisionally determined in the temporary determination unit.
- An addition unit that adds a signal that is linearly equalized in the linear equalization unit and a signal that is nonlinearly equalized in the adaptive nonlinear equalization unit, and a delay unit that delays the signal output from the addition unit may be further provided.
- the delay unit performs a delay over a period corresponding to the processing delay in the provisional determination unit, and the adaptive nonlinear equalization unit is based on a difference between the signal delayed in the delay unit and the signal provisionally determined in the provisional determination unit.
- the plurality of coefficients may be derived, and the linear equalization unit may perform the linear equalization using the plurality of coefficients, and may use a fixed value as the plurality of coefficients. In this case, since the coefficient for linear equalization is a fixed value, the stability of the equalization process can be improved.
- the adaptive nonlinear equalization unit may newly derive a plurality of coefficients when detecting the divergence of the plurality of coefficients. In this case, since a plurality of coefficients are newly derived when divergence is detected, deterioration of equalization characteristics can be suppressed.
- Still another aspect of the present invention is an equalization method.
- the step of linearly equalizing the input signal, the step of sequentially nonlinearly equalizing the input signal in parallel with the linear equalization, and the nonlinear equalized signal and the linearly equalized signal are added.
- a step of tentatively determining the added signals sequentially.
- a plurality of coefficients are derived using the temporarily determined signal as a teacher signal, and nonlinear equalization is executed based on the plurality of coefficients.
- the present invention it is possible to reduce the non-linear distortion of the reproduction signal caused by the improvement of the recording density, the recording power fluctuation or the like without the training signal.
- FIG. 6 is a diagram illustrating a configuration of a path memory unit in FIG. 5. It is a figure which shows the data structure of the table memorize
- Embodiment 1 of the present invention reproduces a signal recorded on a recording medium such as an optical disc, equalizes a reproduced signal (hereinafter referred to as “reproduced signal”) by a partial response method, and equalizes the signal.
- the present invention relates to a playback apparatus for decoding (hereinafter referred to as “equalized signal”).
- equalized signal As described above, as the recording capacity of the optical disk increases, the influence of nonlinear distortion that cannot be removed by the linear waveform equalizer increases. In order to remove the nonlinear distortion, a neural network as a nonlinear equalizer is effective, but it is necessary to learn and converge with a training signal. Therefore, in order to reduce the non-linear distortion of the reproduction signal without the training signal, the reproduction apparatus according to the present embodiment executes the following processing.
- the playback device arranges a linear waveform equalizer in series before the nonlinear waveform equalizer.
- the reproduction apparatus inputs an equalized signal from a linear waveform equalizer (hereinafter referred to as “linear equalized signal”) to a nonlinear waveform equalizer, and then receives an equalized signal (hereinafter referred to as a nonlinear waveform equalizer). , Referred to as “nonlinear equalized signal”) to the Viterbi decoder.
- the linear equalization signal is also input to the temporary determination unit, and is temporarily determined by the temporary determination unit.
- the provisionally determined signal (hereinafter referred to as “temporary determination signal”) is input to the linear waveform equalizer and the nonlinear waveform equalizer as a teacher signal.
- the linear waveform equalizer and the nonlinear waveform equalizer perform equalization processing by deriving tap coefficients based on the teacher signal.
- a neural network is used for the nonlinear equalizer, but according to the above configuration, the neural network is learned without using a training signal.
- a linear equalization signal, a non-linear equalization signal, and a temporary determination signal are used for derivation of tap coefficients in the linear waveform equalizer and the non-linear waveform equalizer.
- the output timing is different from the provisional determination signal. Therefore, in order to match these timings, the playback device delays the linear equalization signal and the nonlinear equalization signal in order to derive the tap coefficient.
- FIG. 1 shows the configuration of a playback apparatus 100 according to Embodiment 1 of the present invention.
- the playback device 100 includes an optical disc 10, an optical disc drive unit 12, an optical pickup 14, a preamplifier unit 16, an AGC unit 18, a PLL (Phase Locked Loop) unit 20, an A / D conversion unit 22, a processing unit 24, and a control unit 26.
- an optical disc 10 an optical disc drive unit 12
- an optical pickup 14 includes an optical pickup 14
- a preamplifier unit 16 an AGC unit 18, a PLL (Phase Locked Loop) unit 20, an A / D conversion unit 22, a processing unit 24, and a control unit 26.
- PLL Phase Locked Loop
- the optical disc 10 is a recording medium configured to be detachable from the playback device 100.
- the optical disk 10 corresponds to various types such as CD, DVD, BD, and HD DVD.
- the optical disk 10 is particularly targeted for a case where the nonlinear distortion is large enough to affect reproduction.
- the optical disk drive unit 12 is a motor for rotating the optical disk 10 at a predetermined rotation speed.
- the optical pickup 14 reads a signal to be processed from the optical disc 10 and performs photoelectric conversion and amplification on the signal. The resulting signal corresponds to the “reproduction signal” described above.
- the optical pickup 14 outputs a reproduction signal to the preamplifier unit 16.
- the preamplifier unit 16 amplifies the reproduction signal
- the AGC unit 18 amplifies the reproduction signal from the preamplifier unit 16 to a predetermined amplitude.
- the AGC unit 18 outputs the amplified reproduction signal to the PLL unit 20, and the PLL unit 20 detects a clock from the reproduction signal.
- the A / D converter 22 performs analog / digital conversion of the reproduction signal based on the clock detected by the PLL unit 20.
- the processing unit 24 performs equalization processing and decoding processing on the reproduction signal (hereinafter also referred to as “reproduction signal”) analog / digital converted by the A / D conversion unit 22. Details of the processing unit 24 will be described later.
- This configuration can be realized in terms of hardware by a CPU, memory, or other LSI of any computer, and in terms of software, it can be realized by a program loaded in the memory, but here it is realized by their cooperation.
- Draw functional blocks Accordingly, those skilled in the art will understand that these functional blocks can be realized in various forms by hardware only, software only, or a combination thereof.
- FIG. 2 shows the configuration of the processing unit 24.
- the processing unit 24 includes a linear equalization unit 44, a first delay unit 32, a provisional determination unit 30, a nonlinear equalization unit 46, a second delay unit 34, a first addition unit 40, a second addition unit 42, and a Viterbi decoding unit 38. including.
- the signal includes a linear equalization error signal 300, a non-linear equalization error signal 302, and a provisional determination signal 306.
- the reproduction signal sampled for each bit clock in the A / D conversion unit 22 in FIG. 1 is sequentially input to the linear equalization unit 44.
- the linear equalizer 44 sequentially performs linear equalization on the input reproduction signal.
- the linear equalization unit 44 is configured by a transversal filter, delays the reproduction signal by a multistage tap, multiplies the output from the multistage tap and a plurality of tap coefficients, and adds the multiplication results.
- the addition result corresponds to the linear equalization signal described above.
- the linear equalization unit 44 receives the linear equalization error signal 300 from the first addition unit 40 described later, and derives a plurality of tap coefficients based on the linear equalization error signal 300.
- an adaptive algorithm such as a LMS (Least Mean Square) algorithm is used to derive a plurality of tap coefficients.
- the linear equalization unit 44 outputs a linear equalization signal to the first delay unit 32, the provisional determination unit 30, and the non-linear equalization unit 46.
- the non-linear equalization unit 46 receives the linear equalization signal from the linear equalization unit 44 and sequentially performs non-linear equalization on the linear equalization signal.
- the nonlinear equalization unit 46 is configured by a neural network. The result of nonlinear equalization in the nonlinear equalization unit 46 corresponds to the aforementioned nonlinear equalization signal. Further, the nonlinear equalization unit 46 receives the nonlinear equalization error signal 302 from the second addition unit 42 described later, and based on the nonlinear equalization error signal 302, a plurality of taps used in the neural network. Deriving coefficients.
- the non-linear equalization unit 46 uses the temporary determination signal as the teacher signal. It can be said that a plurality of coefficients are derived.
- the nonlinear equalization unit 46 outputs the nonlinear equalization signal to the second delay unit 34 and the Viterbi decoding unit 38.
- the Viterbi decoding unit 38 receives the nonlinear equalization signal from the nonlinear equalization unit 46 and executes Viterbi decoding on the nonlinear equalization signal.
- the Viterbi decoding unit 38 has a branch metric calculation circuit that calculates a branch metric from a non-linear equalization signal, a path metric calculation circuit that calculates a path metric by accumulating the branch metrics every clock, and a path metric is minimized.
- a path memory for selecting and storing the data series as the most probable candidate series.
- the path memory stores a plurality of candidate sequences, and selects candidate sequences according to a selection signal from the path metric calculation circuit. In addition, the selected candidate series is output as a data series.
- the provisional determination unit 30 receives the linear equalization signal from the linear equalization unit 44 and executes Viterbi decoding on the linear equalization signal to sequentially provisionally determine the linear equalization signal.
- the provisional determination unit 30 is configured in the same manner as the Viterbi decoding unit 38.
- the path memory stores a plurality of candidate series, and temporary determination is executed according to the partial response rule based on the selection signal from the path metric calculation circuit. More specifically, the provisional determination unit 30 provisionally determines the output level for a predetermined input bit when the partial response equalization is normally performed, and the provisional determination signal indicates the level temporarily determined for the input bit. Output as 306.
- the temporary determination unit 30 and the Viterbi decoding unit 38 are configured to have different path memory lengths. For example, when the path memory length of the Viterbi decoding unit 38 is 64 bits, the path memory length of the temporary determination unit 30 is 24 bits or 32 bits.
- the first delay unit 32 receives the linear equalization signal from the linear equalization unit 44.
- the first delay unit 32 delays the linear equalization signal and then outputs the delayed linear equalization signal (hereinafter referred to as “linear equalization signal” or “delay signal”) to the first addition unit 40.
- the first delay unit 32 executes the delay over a period corresponding to the processing delay in the provisional determination unit 30. That is, the timing of the provisional determination signal 306 output from the provisional determination unit 30 and the linear equalization signal from the linear equalization unit 44 are matched in the first addition unit 40.
- the first delay unit 32 is configured by, for example, a latch circuit driven by a bit clock.
- the first addition unit 40 receives the linear equalization signal and the temporary determination signal 306 from the first delay unit 32.
- the first addition unit 40 generates a linear equalization error signal 300 based on the difference between the linear equalization error and the provisional determination signal 306. For example, the linear equalization error signal 300 is derived by subtracting the provisional determination signal 306 from the linear equalization error. The first addition unit 40 outputs the linear equalization error signal 300 to the linear equalization unit 44.
- the second delay unit 34 inputs the nonlinear equalization signal from the nonlinear equalization unit 46.
- the second delay unit 34 delays the nonlinear equalized signal and then outputs the delayed nonlinear equalized signal (hereinafter referred to as “nonlinear equalized signal” or “delayed signal”) to the second adder 42.
- the second delay unit 34 executes the delay over a period corresponding to the difference between the processing delay in the provisional determination unit 30 and the processing delay in the nonlinear equalization unit 46.
- the second adder 42 generates a non-linear equalization error signal 302 based on the difference between the non-linear equalization signal from the second delay unit 34 and the provisional determination signal 306.
- the non-linear equalization error signal 302 is derived by subtracting the provisional determination signal 306 from the non-linear equalization signal sum.
- the second addition unit 42 outputs the non-linear equalization error signal 302 to the non-linear equalization unit 46.
- the non-linear equalization unit 46 derives a plurality of coefficients based on the non-linear equalization error signal 302. That is, the nonlinear equalizer 46 uses the temporary determination signal 306 as a teacher signal. Further, the non-linear equalization unit 46 calculates an integrated value that is a sum obtained by successively adding the square values of the non-linear equalization error signal 302, thereby converging a plurality of tap coefficients in the non-linear equalization unit 46. To monitor. That is, the non-linear equalization unit 46 determines the convergence of a plurality of tap coefficients when the non-linear equalization error signal 302 changes from a state where the integrated value is larger than a threshold value to a small state.
- the nonlinear equalization unit 46 newly derives a plurality of tap coefficients.
- FIG. 3 shows the configuration of the linear equalization unit 44.
- the linear equalization unit 44 includes a multistage tap 50 and a linear processing unit 52.
- the multistage tap 50 includes a first delay tap 54a, a second delay tap 54b, a third delay tap 54c, and an Nth delay tap 54n, which are collectively referred to as a delay tap 54.
- the linear processing unit 52 includes a first multiplication unit 56a, a second multiplication unit 56b, a third multiplication unit 56c, an N + 1 multiplication unit 56n + 1, a tap coefficient derivation unit 58, and an integration unit 60, which are collectively referred to as a multiplication unit 56.
- the multistage tap 50 is formed by serially connecting a plurality of delay taps 54. More specifically, the first delay tap 54a inputs the reproduction signal, and outputs the reproduction signal after delay. The second delay tap 54b receives the reproduction signal from the first delay tap 54a, and outputs the reproduction signal after delay. The third delay tap 54c to the Nth delay tap 54n perform the same processing. An input portion and an output portion to the delay tap 54 are output signals from the multistage tap 50. For example, when four delay taps 54 are arranged, there are five output signals. These output signals are output to the multiplication unit 56.
- the multiplication unit 56 inputs the output signal from the delay tap 54 and also receives the tap coefficient from the tap coefficient deriving unit 58.
- the tap coefficient is derived in association with each output signal.
- the multiplier 56 multiplies the output signal and the tap coefficient.
- the multiplication unit 56 outputs each multiplication result to the integration unit 60.
- the accumulating unit 60 adds the multiplication results from the multiplying unit 56 one after another to obtain an accumulated value as an addition result.
- the integrated value as the addition result corresponds to the above-described linear equalization signal.
- the integrating unit 60 outputs a linear equalization signal.
- the tap coefficient deriving unit 58 receives the linear equalization error signal 300.
- the tap coefficient deriving unit 58 controls a plurality of tap coefficients using the linear equalization error signal 300 and the multiplication result of the multiplication unit 56 so that the reproduction signal matches the partial response characteristic.
- the tap coefficient is derived by using an adaptive algorithm such as the LMS algorithm so that the linear equalization error signal 300 is controlled to be small. Since the LMS algorithm is a known technique, the description thereof is omitted here.
- FIG. 4 shows the configuration of the nonlinear equalization unit 46.
- the nonlinear equalization unit 46 includes a multistage tap 70 and a nonlinear processing unit 72.
- the multistage tap 70 includes a first delay tap 74a, a second delay tap 74b, and an Nth delay tap 74n, which are collectively referred to as a delay tap 74.
- the nonlinear processing unit 72 includes an eleventh multiplication unit 76aa, a twelfth multiplication unit 76ab, a first M multiplication unit 76am, a twenty-first multiplication unit 76ba, a twenty-second multiplication unit 76bb, a second M multiplication unit 76bm, (N + 1) 1 multiplier 76 (n + 1) a, (N + 1) 2 multiplier 76 (n + 1) b, (N + 1) M multiplier 76 (n + 1) m, and first integrator 78a collectively referred to as integrator 78.
- a 1-multiplier 82a, a second multiplier 82b, an M-th multiplier 82m, an integrator 84, a function calculator 86, and a tap coefficient derivation unit 88 are included.
- the non-linear equalization unit 46 is configured by a three-layer perceptron type neural network as shown in the figure.
- the input layer corresponds to the multistage tap 70
- the hidden layer corresponds to the function calculation unit 80
- the output layer corresponds to the function calculation unit 86.
- the multistage tap 70 is formed by serially connecting a plurality of delay taps 74. More specifically, the first delay tap 74a receives a linear equalization signal and outputs a linear equalization signal after delaying.
- the second delay tap 74b receives the linear equalization signal from the first delay tap 74a, and outputs the linear equalization signal after the delay.
- the Nth delay tap 74n also performs the same process.
- An input portion and an output portion to the delay tap 74 are output signals from the multistage tap 70. These output signals are output to the multiplier 76.
- the multiplication unit 76 multiplies the output signal from the multistage tap 70 and the tap coefficient from the tap coefficient deriving unit 88. More specifically, the IJ multiplication unit 76ij multiplies the i-th output signal S (i) from the top of the multistage tap 70 by the tap coefficient W1 (i, j), thereby obtaining a multiplication result U (i , J).
- the accumulating unit 78 performs accumulating by sequentially adding the multiplication results in the multiplying unit 76. More specifically, the J-th integrating unit 78j adds the multiplication results U (1, j), U (2, j), U (3, j),..., U (n + 1, j). To generate an integration result V (j).
- the function calculation unit 80 calculates a sigmoid function on the integration result V (j) in the integration unit 78.
- the integration result V (j) is input to x in Expression 1.
- the calculation result in the J-th function calculation unit 80j is denoted as X (j), and the calculation result corresponds to the output from the hidden layer.
- the multiplication unit 82 multiplies the calculation result in the function calculation unit 80 and the tap coefficient from the tap coefficient derivation unit 88. Specifically, the J-th multiplication unit 82j generates a multiplication result Y (j) by multiplying the calculation result X (j) in the J-th function calculation unit 80j by the tap coefficient W2 (j). .
- the accumulating unit 84 performs an accumulation by sequentially adding the multiplication results in the multiplying unit 82.
- the multiplication results in all the multiplication units 82 are integrated, and an integration result Z is generated.
- the function calculation unit 86 calculates a sigmoid function on the integration result in the integration unit 84.
- the integration result Z is input to x in Equation 1.
- the calculation result of the function calculation unit 86 corresponds to the output from the output layer, and corresponds to the above-described nonlinear equalization signal.
- the tap coefficient deriving unit 88 derives tap coefficients W1 (i, j) and W2 (j) used in the multiplying unit 76 and the multiplying unit 82. A random value or a value close to that after convergence is set as the initial value of W1 (i, j) and W2 (j). Further, the tap coefficient deriving unit 88 updates W1 (i, j) and W2 (j) by the LMS algorithm similarly to the tap coefficient deriving unit 58 of FIG. Here, learning of W1 (i, j) and W2 (j) is performed by back propagation.
- A corresponds to the linear equalization signal
- D corresponds to the provisional determination signal 306. That is, AD corresponds to the error signal 302 for nonlinear equalization.
- the tap coefficient deriving unit 88 controls W1 (i, j) and W2 (j) so that E is minimized.
- the result of back propagation at the output layer is shown as follows.
- ( ⁇ E) / ( ⁇ Y (j)) f ′ (Y (j)) ⁇ 2 (AD) (Formula 3)
- the tap coefficient deriving unit 88 updates the tap coefficient W2 (j) as follows.
- W2 (j) W2 (j) old ⁇ ⁇ ( ⁇ E) / ( ⁇ W2 (j)) (Formula 4)
- W2 (j) old indicates the tap coefficient W2 (j) at the previous timing.
- the tap coefficient deriving unit 88 updates the tap coefficient W1 (i, j) as follows.
- W1 (i, j) W1 (i, j) old ⁇ ⁇ ( ⁇ E) / ( ⁇ W1 (i, j)) (Formula 6)
- W1 (i, j) old indicates the tap coefficient W1 (i, j) at the previous timing.
- FIG. 5 shows a configuration of the provisional determination unit 30.
- the provisional determination unit 30 includes a branch metric calculation unit 90, a path memory unit 92, and a specifying unit 96. Further, the selection signal SEL is included as a signal.
- the branch metric calculation unit 90 performs branch metric calculation and path metric calculation based on a linear equalization signal from a linear equalization unit 44 (not shown). Therefore, the branch metric calculation unit 90 includes the aforementioned branch metric calculation circuit and path metric calculation circuit.
- the partial response method is applied in the present embodiment, but before the configuration of the provisional determination unit 30 is described, here, state transition in the partial response method will be described.
- FIG. 6 shows a state transition when the temporary determination unit 30 corresponds to a partial response (1, 2, 2, 2, 1).
- the partial response (1, 2, 2, 2, 1) the amplitude falls within a range of ⁇ 4.
- 10 states from S0 to S9 are defined according to the values included in the combination.
- the state transitions as shown in the figure according to the next input bit value. For example, when a bit value “1” is input to the state S0, a transition to the state S1 is made.
- a value such as “x / y” is shown in the arrows connecting the states, where x indicates an input bit value and y indicates a new bit value added to the original state.
- the temporary decision value for 5 bits is shown.
- FIG. 7 shows a state transition when the provisional determination unit 30 corresponds to a partial response (1, 2, 2, 2, 1).
- FIG. 7 shows a state at two consecutive timings, and each state is the same as FIG.
- FIG. 8 shows the configuration of the branch metric calculation unit 90.
- the branch metric calculation unit 90 includes a first addition unit 110a, a second addition unit 110b, a third addition unit 110c, a fourth addition unit 110d, a fifth addition unit 110e, a sixth addition unit 110f, which are collectively referred to as an addition unit 110.
- SEL0 a 0th selection signal SEL0, a first selection signal SEL1, a second selection signal SEL2, a seventh selection signal SEL7, an eighth selection signal SEL8, and a ninth selection signal SEL9, which are collectively referred to as a selection signal SEL.
- the addition unit 110 subtracts a predetermined target value from the linear equalization signal.
- the square circuit 112 calculates the square value of the subtraction result in the addition unit 110.
- the ACS circuit 114 performs a metric operation on the square from the square circuit 112 by addition, comparison, and selection. Further, the ACS circuit 114 outputs a 0th selection signal SEL0, a first selection signal SEL1, a second selection signal SEL2, a seventh selection signal SEL7, an eighth selection signal SEL8, and a ninth selection signal SEL9 as a result of the metric calculation. To do. There is also a square value that is not input to the ACS circuit 114 due to the partial response characteristic. The adder 116 adds such a square value. Returning to FIG.
- the path memory unit 92 receives the selection signal SEL from the branch metric calculation unit 90 and stores a path corresponding to the selection signal SEL.
- FIG. 9 shows the configuration of the path memory unit 92.
- the path memory unit 92 includes an eleventh memory 120aa, a twelfth memory 120ab, a thirteenth memory 120ac, a fourteenth memory 120ad, a fifteenth memory 120ae, a sixteenth memory 120af, a seventeenth memory 120ag, and an eighteenth memory.
- one path is stored in the L + 1 memory 120, and 10 types of paths are stored so as to correspond to each of the 10 types of states shown in FIGS.
- the selection unit 122 selects one of the paths according to the selection signal SEL.
- the selected path corresponds to the survival path.
- the majority decision unit 124 inputs bit values stored in the (L + 1) th memory 120 (l + 1) a to the (L + 1) th memory 120 (l + 1) j, respectively, and executes the majority decision.
- the majority decision unit 124 outputs the selection result.
- the specifying unit 96 inputs the selection value from the majority decision unit 124 (not shown) and holds the selection value in a latch.
- the specifying unit 96 selects one combination from selection values corresponding to five timings including past selection values.
- the combination is updated by removing the oldest selection value from the combination.
- FIG. 10 shows the data structure of the table stored in the specifying unit 96.
- memory value column 200 b (k) column 202, b (k-1) column 204, b (k-2) column 206, b (k-3) column 208, b (k-4) column.
- 210 and a provisional determination output column 212 are included.
- b (k) corresponds to the most recently input selection value
- b (k ⁇ 1) corresponds to the selection value input at the previous timing
- b (k ⁇ 4) This corresponds to the selection value input at the previous four timings. As described above, these are held by the latch.
- the b (k) column 202 to the b (k-4) column 210 combinations of values that the selection values held in the latch can take are shown.
- the memory value column 200 memory values corresponding to possible values are shown, and in the temporary determination output column 212, temporary determination values corresponding to possible values are shown. For example, if the content of the path memory is “00000”, the temporary determination value “ ⁇ 4” is associated, and if “00001”, the temporary determination value “ ⁇ 3” is associated.
- the specifying unit 96 specifies a provisional determination value corresponding to the combination while referring to the table shown in FIG.
- the specifying unit 96 outputs the temporary determination value as the temporary determination signal 306.
- FIG. 11 is a flowchart showing a procedure for deriving coefficients in the nonlinear equalization unit 46.
- the nonlinear equalization unit 46 continues to derive the magnitude of the nonlinear equalization error signal 302 even after the magnitude of the nonlinear equalization error signal 302 has converged.
- the nonlinear equalization unit 46 newly derives a tap coefficient (S42). If the size does not become larger than the threshold value (N in S40), the process is terminated.
- FIG. 12A shows a histogram of signals equalized by a conventional linear waveform equalizer.
- the bit error rate at this time is 1.1 ⁇ 10 ⁇ 2 .
- FIG. 12B shows a histogram of signals equalized by the playback apparatus 100.
- the target value at this time is 9 values of partial response (1, 2, 2, 2, 1) as described above. Further, the bit error rate at this time is 1.5 ⁇ 10 ⁇ 4 . It is estimated that the characteristic deterioration in the conventional linear waveform equalizer is due to the fact that the waveform does not converge to the Viterbi target value because the waveform includes a nonlinear component.
- the result of provisional determination of the linear equalization signal is used as the teacher signal, so that the provisional determination signal can be used as the teacher signal instead of the training signal.
- the temporary determination signal is used as the teacher signal instead of the training signal
- a coefficient for nonlinear equalization can be derived without using the training signal.
- the coefficient for nonlinear equalization is derived without using the training signal, nonlinear equalization can be performed without using the training signal.
- a coefficient for nonlinear equalization is derived without using a training signal, nonlinear distortion of a reproduction signal caused by improvement in recording density, recording power fluctuation, or the like can be reduced without a training signal.
- provisional judgment is executed according to the partial response rule, so it can support partial response processing.
- the delay is executed over a period corresponding to the difference between the processing delay in the provisional determination unit and the processing delay in the nonlinear equalization unit, the timing of the nonlinear equalization signal and the provisional determination signal can be matched.
- the timing of the nonlinear equalization signal and the provisional determination signal are matched, it is possible to improve the estimation accuracy of tap coefficients for nonlinear equalization. Further, since a plurality of coefficients are newly derived when the divergence of the non-linear equalization error signal is detected, deterioration of the equalization characteristics can be suppressed.
- the second embodiment of the present invention reproduces a signal recorded on a recording medium such as an optical disk, equalizes the reproduced signal (hereinafter referred to as “reproduced signal”) using a partial response method, and equalizes the signal.
- the present invention relates to a playback apparatus for decoding (hereinafter referred to as “equalized signal”).
- the recording capacity of the optical disk increases, the influence of nonlinear distortion that cannot be removed by the linear waveform equalizer increases.
- a neural network as a nonlinear equalizer is effective, but it is necessary to learn and converge with a training signal. Therefore, in order to reduce the non-linear distortion of the reproduction signal without the training signal, the reproduction apparatus according to the present embodiment executes the following processing.
- the playback device has a linear waveform equalizer and a nonlinear waveform equalizer arranged in parallel, and inputs a playback signal to both.
- the reproducing apparatus includes an equalized signal from a linear waveform equalizer (hereinafter referred to as “linear equalized signal”) and an equalized signal from a nonlinear waveform equalizer (hereinafter referred to as “nonlinear equalized signal”).
- the synthesized signal hereinafter referred to as “addition signal” is input to the Viterbi decoder.
- the Viterbi decoder functions as a provisional determination unit of the present invention that sequentially provisionally determines the addition signal.
- a signal provisionally determined by the Viterbi decoder (hereinafter referred to as “provisional determination signal”) is input as a teacher signal to the linear waveform equalizer and the nonlinear waveform equalizer.
- the linear waveform equalizer and the nonlinear waveform equalizer perform equalization processing by deriving tap coefficients based on the teacher signal. For example, since the neural network is used for the nonlinear equalizer, the neural network is learned without using the training signal.
- the reproducing apparatus further performs the following operation. Execute the process.
- the nonlinear waveform equalizer requires a longer period for tap coefficient convergence than the linear waveform equalizer.
- the playback device monitors the learning convergence state of the neural network, and if convergence is not confirmed, the linear equalization signal is used instead of the addition signal. Is output to the Viterbi decoder.
- a linear equalization signal, a non-linear equalization signal, and a temporary determination signal are used for derivation of tap coefficients in the linear waveform equalizer and the non-linear waveform equalizer.
- the output timing is different from the provisional determination signal. Therefore, in order to match these timings, the playback device delays the linear equalized signal and the nonlinear equalized signal. Examples of the present invention will be described below.
- FIG. 13 shows the configuration of the processing unit 24.
- the processing unit 24 includes an equalization processing unit 1030, a first delay unit 1032, a second delay unit 1034, an addition unit 1036, a Viterbi decoding unit 1038, an equalization error generation unit 1040, and a determination unit 1042.
- the equalization processing unit 1030 includes a linear equalization unit 1044 and a non-linear equalization unit 1046. Also, the equalization error generation unit 1040 and the non-linear equalization unit 1046 are grouped with the adaptive non-linear equalization unit 1048. Further, the signal includes a linear equalization error signal 1300, a non-linear equalization error signal 1302, and a provisional determination signal 1306.
- the Viterbi decoding unit 1038 functions as a temporary determination unit of the present invention that sequentially determines the signals added by the addition unit 1036.
- a temporary determination unit may be provided separately from the Viterbi decoding unit 1038. It doesn't matter.
- the reproduction signal sampled for each bit clock in the A / D conversion unit 22 in FIG. 1 is sequentially input to the linear equalization unit 1044 and the non-linear equalization unit 1046.
- the linear equalizer 1044 sequentially performs linear equalization on the input reproduction signal.
- the linear equalization unit 1044 is configured by a transversal filter, delays the reproduction signal by a multistage tap, multiplies the output from the multistage tap and a plurality of tap coefficients, and adds the multiplication results.
- the addition result corresponds to the linear equalization signal described above.
- the linear equalization unit 1044 receives a linear equalization error signal 1300 from an equalization error generation unit 1040 described later, and derives a plurality of tap coefficients based on the linear equalization error signal 1300.
- an adaptive algorithm such as a LMS (Least Mean Square) algorithm is used to derive a plurality of tap coefficients.
- the linear equalization unit 1044 outputs the linear equalization signal to the equalization error generation unit 1040 via
- the non-linear equalization unit 1046 sequentially performs non-linear equalization on the reproduction signal in parallel with the linear equalization in the linear equalization unit 1044.
- the nonlinear equalization unit 1046 is configured by a neural network.
- the result of nonlinear equalization in the nonlinear equalization unit 1046 corresponds to the aforementioned nonlinear equalization signal.
- the nonlinear equalization unit 1046 receives a nonlinear equalization error signal 1302 from an equalization error generation unit 1040, which will be described later, and based on the nonlinear equalization error signal 1302, a plurality of signals used in the neural network.
- a tap coefficient is derived.
- the non-linear equalization error signal 1302 is generated by the difference between the sum of the delay signal from the first delay unit 1032 and the delay signal from the second delay unit 1034 and the provisional determination signal. It can be said that the nonlinear equalization unit 1046 derives a plurality of coefficients using the temporary determination signal as a teacher signal. The nonlinear equalization unit 1046 outputs the nonlinear equalization signal to the equalization error generation unit 1040 via the second delay unit 1034 and directly to the addition unit 1036 without passing through the second delay unit 1034.
- the first delay unit 1032 receives the linear equalization signal from the linear equalization unit 1044.
- the first delay unit 1032 delays the linear equalization signal and then outputs the delayed linear equalization signal (hereinafter referred to as “linear equalization signal” or “delayed signal”) to the equalization error generation unit 1040.
- the first delay unit 1032 executes a delay over a period corresponding to the processing delay for provisional determination in the Viterbi decoding unit 1038. That is, the first delay unit 1032 uses the provisional determination signal 1306 output from the Viterbi decoding unit 1038 after reaching the Viterbi decoding unit 1038 from the linear equalization unit 1044 and the linear equalization signal from the linear equalization unit 1044. Timing is adjusted.
- the first delay unit 1032 is constituted by, for example, a latch circuit driven by a bit clock.
- the second delay unit 1034 receives the nonlinear equalization signal from the nonlinear equalization unit 1046.
- the second delay unit 1034 delays the nonlinear equalization signal, and then outputs the delayed nonlinear equalization signal (hereinafter referred to as “nonlinear equalization signal” or “delayed signal”) to the equalization error generation unit 1040.
- the second delay unit 1034 executes a delay over a period corresponding to the processing delay for provisional determination in the Viterbi decoding unit 1038.
- the addition unit 1036 receives the linear equalization signal from the linear equalization unit 1044 and the non-linear equalization signal from the non-linear equalization unit 1046.
- the adder 1036 generates an addition signal by adding the linear equalization signal and the nonlinear equalization signal.
- Adder 1036 outputs the addition signal to Viterbi decoder 1038.
- the Viterbi decoding unit 1038 receives the addition signal from the addition unit 1036 and performs Viterbi decoding on the addition signal.
- the Viterbi decoding unit 1038 includes a branch metric calculation circuit that calculates a branch metric from the addition signal, a path metric calculation circuit that calculates a path metric by accumulating the branch metrics for each clock, and a data sequence that minimizes the path metric And a path memory that selects and stores them as the most probable candidate series.
- the path memory stores a plurality of candidate sequences, and selects candidate sequences according to a selection signal from the path metric calculation circuit. In addition, the selected candidate series is output as a data series.
- the Viterbi decoding unit 1038 sequentially provisionally determines the addition signal by executing provisional determination on the data series stored in the path memory according to the partial response rule. That is, the Viterbi decoding unit 1038 performs a partial response provisional determination operation using a predetermined number of bits for one of the candidate sequences stored in the path memory. Specifically, the Viterbi decoding unit 1038 tentatively determines the output level for a predetermined input bit when the partial response equalization is normally performed, and the tentative determination signal indicates the level temporarily determined for the input bit. The result is output to the equalization error generation unit 1040 as 1306.
- the provisional determination is not limited to the final result of the path memory, but may be made for a candidate series in the middle of the path memory. For example, if the path memory length is 64 bits, provisional determination may be made for one of the 24th and 32nd bit candidate series.
- the equalization error generation unit 1040 receives the linear equalization signal from the first delay unit 1032, the nonlinear equalization signal from the second delay unit 1034, and the provisional determination signal 1306 from the Viterbi decoding unit 1038. As mentioned above, the timing of these signals is correct.
- the equalization error generation unit 1040 generates a linear equalization error signal 1300 based on the difference between the sum of the linear equalization error and the nonlinear equalization signal and the provisional determination signal 1306. For example, after the sum of the linear equalization error and the non-linear equalization signal is calculated, the provisional determination signal 1306 is subtracted from the sum to derive the linear equalization error signal 1300.
- the equalization error generation unit 1040 generates a non-linear equalization error signal 1302 based on the difference between the sum of the linear equalization error and the non-linear equalization signal and the provisional determination signal 1306. For example, after the sum of the linear equalization error and the nonlinear equalization signal is calculated, the provisional determination signal 1306 is subtracted from the sum to derive the nonlinear equalization error signal 1302.
- the equalization error generation unit 1040 outputs the linear equalization error signal 1300 to the linear equalization unit 1044, and outputs the nonlinear equalization error signal 1302 to the nonlinear equalization unit 1046.
- the nonlinear equalizer 1046 updates the tap coefficients of the neural network based on the error signal 1302 for nonlinear equalization, but the operation of the nonlinear equalizer 1046 is unstable until the tap coefficients converge. become. As a result, there is a high possibility that the data series output from the Viterbi decoding unit 1038 is erroneous. Therefore, it is not preferable to input the addition signal to the Viterbi decoding unit 1038 before convergence. In order to cope with this, the determination unit 1042 determines convergence of a plurality of tap coefficients in the nonlinear equalization unit 1046. More specifically, the determination unit 1042 adds up the square values of the nonlinear equalization error signal 1302 by adding them over a predetermined period.
- the determination unit 1042 compares the integrated value with a threshold value, and determines that the integrated value is converged if the integrated value is equal to or less than the threshold value. On the other hand, if the integrated value is larger than the threshold value, the determination unit 1042 determines that the convergence has not occurred.
- the determination unit 1042 outputs the determination result to the addition unit 1036 and the equalization error generation unit 1040. The determination result indicates whether or not it has converged.
- the adding unit 1036 does not output the above addition signal to the Viterbi decoding unit 1038 until the determination unit 1042 determines convergence, that is, when it is determined that convergence has not occurred, the linear equalization unit 1044
- the linear equalized signal is output to the Viterbi decoding unit 1038.
- the adder 1036 outputs the added signal to the Viterbi decoder 1038 as described above after the convergence is determined by the determination unit 1042.
- the linear equalized signal is output to the Viterbi decoding unit 1038 until the neural network converges, and the added signal is output to the Viterbi decoding unit 1038 after the neural network converges.
- adverse effects due to the nonlinear equalized signal are reduced.
- the equalization error generation unit 1040 does not use the nonlinear equalization signal until the convergence is determined by the determination unit 1042, and performs linear equalization based on the difference between the linear equalization signal and the provisional determination signal 1306. An error signal 1300 is generated. Also, the equalization error generation unit 1040 causes the linear equalization unit 1044 to derive a plurality of tap coefficients based on the linear equalization error signal 1300. On the other hand, the equalization error generation unit 1040 operates as described above after the determination unit 1042 determines convergence. Further, the equalization error generation unit 1040 performs non-linear equalization based on the difference between the sum of the linear equalization signal and the non-linear equalization signal and the provisional determination signal 1306 regardless of the determination result from the determination unit 1042.
- the determination unit 1042 determines that the integrated value that is the sum of the square values of the nonlinear equalization error signal 1302 becomes larger than the threshold value again. It is determined that the tap coefficient is divergent. At this time, the determination unit 1042 causes the nonlinear equalization unit 1046 to newly derive a plurality of tap coefficients. Note that the non-linear equalization unit 1046 may only stop updating the plurality of tap coefficients when the value becomes equal to or less than the predetermined convergence value.
- an addition signal of the linear equalization signal and the non-linear equalization signal may be output to the Viterbi decoding unit 1038 from the beginning, or the non-linear equalization error signal may be output.
- the convergence of 1302 is equal to or less than the threshold value, it may be determined that the convergence has occurred after a predetermined time.
- FIG. 14 shows the configuration of the linear equalization unit 1044.
- the linear equalization unit 1044 includes a multistage tap 1050 and a linear processing unit 1052.
- the multistage tap 1050 includes a first delay tap 1054a, a second delay tap 1054b, a third delay tap 1054c, and an Nth delay tap 1054n, which are collectively referred to as a delay tap 1054.
- the linear processing unit 1052 includes a first multiplication unit 1056a, a second multiplication unit 1056b, a third multiplication unit 1056c, an (N + 1) th multiplication unit 1056n + 1, a tap coefficient derivation unit 1058, and an accumulation unit 1060, which are collectively referred to as a multiplication unit 1056.
- the multi-stage tap 1050 is formed by connecting a plurality of delay taps 1054 serially. More specifically, the first delay tap 1054a inputs the reproduction signal, and outputs the reproduction signal after delay. The second delay tap 1054b receives the reproduction signal from the first delay tap 1054a, and outputs the reproduction signal after delay. The third delay tap 1054c to the Nth delay tap 1054n perform the same processing. An input portion and an output portion to the delay tap 1054 are output signals from the multistage tap 1050. For example, when four delay taps 1054 are arranged, there are five output signals. These output signals are output to the multiplication unit 1056.
- Multiplier 1056 receives the output signal from delay tap 1054 and also receives the tap coefficient from tap coefficient deriving section 1058. Here, the tap coefficient is derived in association with each output signal. Multiplier 1056 multiplies the output signal and the tap coefficient. Multiplication unit 1056 outputs each multiplication result to integration unit 1060. The accumulating unit 1060 adds the multiplication results from the multiplying unit 1056 one after another to obtain an accumulated value as an addition result. The integrated value as the addition result corresponds to the above-described linear equalization signal. The integrating unit 1060 outputs a linear equalization signal. The tap coefficient deriving unit 1058 receives the linear equalization error signal 1300.
- the tap coefficient deriving unit 1058 controls the plurality of tap coefficients using the linear equalization error signal 1300 and the multiplication result of the multiplication unit 1056 so that the reproduction signal matches the partial response characteristic.
- the tap coefficient is derived by using an adaptive algorithm such as the LMS algorithm so that the linear equalization error signal 1300 is controlled to be small. Since the LMS algorithm is a known technique, the description thereof is omitted here.
- FIG. 15 shows the configuration of the nonlinear equalization unit 1046.
- the non-linear equalization unit 1046 includes a multistage tap 1070 and a non-linear processing unit 1072.
- the multistage tap 1070 includes a first delay tap 1074a, a second delay tap 1074b, and an Nth delay tap 1074n, which are collectively referred to as a delay tap 1074.
- the nonlinear processing unit 1072 includes an eleventh multiplication unit 1076aa, a twelfth multiplication unit 1076ab, a first M multiplication unit 1076am, a twenty-first multiplication unit 1076ba, a twenty-second multiplication unit 1076bb, a second M multiplication unit 1076bm, (N + 1) 1 multiplier 1076 (n + 1) a, (N + 1) 2 multiplier 1076 (n + 1) b, (N + 1) M multiplier 1076 (n + 1) m, and first integrator 1078a collectively referred to as integrator 1078 , A second summation unit 1078b, an Mth summation unit 1078m, a first function computation unit 1080a collectively referred to as a function computation unit 1080, a second function computation unit 1080b, an Mth function computation unit 1080m, and a multiplication unit 1082. 1 multiplier 1082a, 2nd multiplier 1082b, Mth multiplier 1082m, integrator 1084, function calculator
- the non-linear equalization unit 1046 is configured by a three-layer perceptron type neural network as illustrated.
- the input layer corresponds to the multistage tap 1070
- the hidden layer corresponds to the function calculation unit 1080
- the output layer corresponds to the function calculation unit 1086.
- the multistage tap 1070 is formed by serially connecting a plurality of delay taps 1074. More specifically, the first delay tap 1074a inputs the reproduction signal, and outputs the reproduction signal after delay.
- the second delay tap 1074b receives the reproduction signal from the first delay tap 1074a, and outputs the reproduction signal after delay.
- the Nth delay tap 1074n performs the same process.
- An input part and an output part to the delay tap 1074 are output signals from the multistage tap 1070. These output signals are output to the multiplier 1076.
- Multiplier 1076 multiplies the output signal from multistage tap 1070 and the tap coefficient from tap coefficient deriving section 1088. Specifically, the IJ multiplication unit 1076ij multiplies the i-th output signal S (i) from the top of the multistage tap 1070 by the tap coefficient W1 (i, j), thereby obtaining a multiplication result U (i , J).
- the accumulating unit 1078 performs an accumulation by sequentially adding the multiplication results in the multiplying unit 1076. More specifically, the J-th integrating unit 1078j adds the multiplication results U (1, j), U (2, j), U (3, j),..., U (n + 1, j). By integrating, an integration result V (j) is generated.
- the function calculation unit 1080 calculates a sigmoid function on the integration result V (j) in the integration unit 1078.
- the integration result V (j) is input to x in Expression 7.
- the calculation result in the J-th function calculation unit 1080j is denoted as X (j), and the calculation result corresponds to the output from the hidden layer.
- the multiplication unit 1082 multiplies the calculation result in the function calculation unit 1080 and the tap coefficient from the tap coefficient derivation unit 1088. Specifically, the J-th multiplication unit 1082j generates a multiplication result Y (j) by multiplying the calculation result X (j) in the J-th function calculation unit 1080j by the tap coefficient W2 (j). .
- the accumulating unit 1084 performs accumulation in which the multiplication results in the multiplying unit 1082 are added one after another. Here, the multiplication results in all the multiplication units 1082 are added and integrated, and an integration result Z is generated.
- the function calculation unit 1086 calculates a sigmoid function on the integration result in the integration unit 1084. Here, the integration result Z is input to x in Expression 7.
- the calculation result of the function calculation unit 1086 corresponds to the output from the output layer, and corresponds to the above-described nonlinear equalization signal.
- A corresponds to the sum of the linear equalization signal and the nonlinear equalization signal
- D corresponds to the provisional determination signal 1306. That is, AD corresponds to the error signal 1302 for nonlinear equalization.
- the tap coefficient deriving unit 1088 controls W1 (i, j) and W2 (j) so that E is minimized.
- the result of back propagation at the output layer is shown as follows.
- ( ⁇ E) / ( ⁇ Y (j)) f ′ (Y (j)) ⁇ 2 (AD) (Equation 9)
- the tap coefficient deriving unit 1088 updates the tap coefficient W2 (j) as follows.
- W2 (j) W2 (j) old ⁇ ⁇ ( ⁇ E) / ( ⁇ W2 (j)) (Equation 10)
- W2 (j) old indicates the tap coefficient W2 (j) at the previous timing.
- the tap coefficient deriving unit 1088 updates the tap coefficient W1 (i, j) as follows.
- W1 (i, j) W1 (i, j) old ⁇ ⁇ ( ⁇ E) / ( ⁇ W1 (i, j)) (Equation 12)
- W1 (i, j) old indicates the tap coefficient W1 (i, j) at the previous timing.
- FIG. 16 shows the configuration of the Viterbi decoding unit 1038.
- the Viterbi decoding unit 1038 includes a branch metric calculation unit 1090, a path memory unit 1092, a majority decision unit 1094, and a specification unit 1096.
- the signal includes a selection signal SEL and a bit signal 1304.
- the branch metric calculation unit 1090 executes branch metric calculation and path metric calculation based on a linear equalized signal or an addition signal (hereinafter collectively referred to as “addition signal”) from an addition unit 1036 (not shown). Therefore, the branch metric calculation unit 1090 includes the aforementioned branch metric calculation circuit and path metric calculation circuit.
- the partial response method is applied in the present embodiment, but before the configuration of the Viterbi decoding unit 1038 is described, state transition in the partial response method will be described here.
- FIG. 17 shows a state transition when the Viterbi decoding unit 1038 corresponds to a partial response (1, 2, 2, 2, 1).
- the partial response (1, 2, 2, 2, 1) the amplitude falls within a range of ⁇ 4.
- 10 states from S0 to S9 are defined according to the values included in the combination.
- the state transitions as shown in the figure according to the next input bit value. For example, when a bit value “1” is input to the state S0, a transition to the state S1 is made.
- a value such as “x / y” is shown in the arrows connecting the states, where x indicates an input bit value and y indicates a new bit value added to the original state.
- the temporary decision value for 5 bits is shown.
- FIG. 18 shows a state transition when the Viterbi decoding unit 1038 corresponds to a partial response (1, 2, 2, 2, 1).
- FIG. 18 shows a state at two consecutive timings, and each state is the same as FIG.
- FIG. 19 shows the configuration of the branch metric calculation unit 1090.
- the branch metric calculation unit 1090 includes a first addition unit 1110a, a second addition unit 1110b, a third addition unit 1110c, a fourth addition unit 1110d, a fifth addition unit 1110e, a sixth addition unit 1110f, which are collectively referred to as an addition unit 1110.
- SEL0 a 0th selection signal SEL0, a first selection signal SEL1, a second selection signal SEL2, a seventh selection signal SEL7, an eighth selection signal SEL8, and a ninth selection signal SEL9, which are collectively referred to as a selection signal SEL.
- the addition unit 1110 subtracts a predetermined target value from the addition signal.
- the square circuit 1112 calculates the square value of the subtraction result in the adder 1110.
- the ACS circuit 1114 performs a metric operation by addition, comparison, and selection on the square from the square circuit 1112. Further, the ACS circuit 1114 outputs the 0th selection signal SEL0, the first selection signal SEL1, the second selection signal SEL2, the seventh selection signal SEL7, the eighth selection signal SEL8, and the ninth selection signal SEL9 as the result of the metric calculation. To do. There is also a square value that is not input to the ACS circuit 1114 due to the partial response characteristic. An addition unit 1116 adds the square value.
- FIG. 20 shows the configuration of the path memory unit 1092.
- the path memory unit 1092 receives the selection signal SEL from the branch metric calculation unit 1090 and stores a path corresponding to the selection signal SEL.
- FIG. 20 shows the configuration of the path memory unit 1092.
- the path memory unit 1092 includes an eleventh memory 1120aa, a twelfth memory 1120ab, a thirteenth memory 1120ac, a fourteenth memory 1120ad, a fifteenth memory 1120ae, a sixteenth memory 1120af, a seventeenth memory 1120ag, and an eighteenth memory.
- one path is stored in the L + 1 memory 1120, and ten types of paths are stored so as to correspond to each of the ten types shown in FIGS.
- the selection unit 1122 selects one of the paths according to the selection signal SEL.
- the selected path corresponds to the survival path.
- the majority decision unit 1124 inputs bit values stored in the (L + 1) th memory 1120 (l + 1) a to the (L + 1) th memory 1120 (l + 1) j, and executes majority decision.
- the bit value selected by the majority vote corresponds to the decoding result.
- the majority decision unit 1124 outputs the decryption result. Note that the bit value stored in the memory 1120 during the pass is output as a bit signal 1304.
- the bit signal 1304 includes 10 bit values corresponding to the same timing among the 10 types of paths.
- the majority decision unit 1094 receives the bit signal 1304 and executes a majority decision on the 10 bit values included in the bit signal 1304.
- the majority decision unit 1094 outputs the bit value selected by the majority decision (hereinafter referred to as “selected value”) to the identification unit 1096.
- the specifying unit 1096 receives the selection value from the majority decision unit 1094 and holds the selection value in a latch. Here, the specifying unit 1096 selects one combination from selection values corresponding to five timings including past selection values. When a new selection value is input to the specifying unit 1096, the combination is updated by removing the oldest selection value from the combination.
- FIG. 21 shows the data structure of the table stored in the specifying unit 1096.
- memory value column 1200 b (k) column 1202, b (k-1) column 1204, b (k-2) column 1206, b (k-3) column 1208, b (k-4) column. 1210 and a provisional determination output column 1212 are included.
- b (k) corresponds to the most recently input selection value
- b (k ⁇ 1) corresponds to the selection value input at the previous timing
- b (k ⁇ 4) This corresponds to the selection value input at the previous four timings. As described above, these are held by the latch.
- combinations of values that the selection value held in the latch can take are shown.
- the memory value column 1200 shows memory values corresponding to possible values
- the temporary determination output column 1212 shows temporary determination values corresponding to possible values. For example, if the content of the path memory is “00000”, the temporary determination value “ ⁇ 4” is associated, and if “00001”, the temporary determination value “ ⁇ 3” is associated.
- the specifying unit 1096 specifies the provisional determination value corresponding to the combination while referring to the table shown in FIG.
- the identifying unit 1096 outputs the temporary determination value as the temporary determination signal 1306.
- FIG. 22 is a flowchart showing the adding procedure in the adding unit 1036.
- the determination unit 1042 receives the nonlinear equalization error signal 1302 and derives the magnitude of the nonlinear equalization error signal 1302. If the magnitude of the non-linear equalization error signal 1302 does not converge within the threshold (N in S1010), the determination unit 1042 causes the addition unit 1036 to output a linear equalization signal (S1012). On the other hand, if the magnitude of the nonlinear equalization error signal 1302 has converged within the threshold value (Y in S1010), the determination unit 1042 causes the addition unit 1036 to output an addition signal (S1014).
- FIG. 23 is a flowchart showing a generation procedure in the equalization error generation unit 1040.
- the determination unit 1042 receives the nonlinear equalization error signal 1302 and derives the magnitude of the nonlinear equalization error signal 1302. If the magnitude of the non-linear equalization error signal 1302 does not converge within the threshold value (N in S20), the equalization error generation unit 1040 determines the difference between the delay signal from the first delay unit 1032 and the provisional determination signal 1306. Is output as an error signal 1300 for linear equalization to the linear equalization unit 1044 (S22).
- the equalization error generation unit 1040 uses the difference between the sum of the delay signal from the first delay unit 1032 and the delay signal from the second delay unit 1034 and the provisional determination signal 1306 as a non-linear equalization error signal 1302. It outputs to the nonlinear equalization part 1046 (S24).
- the equalization error generation unit 1040 and the delay signal from the first delay unit 1032 and the second delay unit 1034 The difference between the sum of the delay signal and the provisional determination signal 1306 is output to the linear equalization unit 1044 as the linear equalization error signal 1300 (S26).
- the equalization error generation unit 1040 uses the difference between the sum of the delay signal from the first delay unit 1032 and the delay signal from the second delay unit 1034 and the provisional determination signal 1306 as a non-linear equalization error signal 1302. It outputs to the nonlinear equalization part 1046 (S28).
- FIG. 24 is a flowchart showing a coefficient derivation procedure in the nonlinear equalization unit 1046.
- the determination unit 1042 continuously derives the magnitude of the nonlinear equalization error signal 1302 even after the magnitude of the nonlinear equalization error signal 1302 has converged.
- the linear equalization unit 1044 causes the nonlinear equalization unit 1046 to derive a new tap coefficient (S42). If the size does not become larger than the threshold value (N in S40), the process is terminated.
- linear equalization and nonlinear equalization are performed in parallel, and the linear equalization signal and the nonlinear equalization signal are added, and the result of provisional determination of the addition signal is used as a teacher signal.
- the temporary determination signal can be used as the teacher signal instead of the training signal.
- a coefficient for nonlinear equalization can be derived without using the training signal.
- nonlinear equalization can be performed without using the training signal.
- a coefficient for nonlinear equalization is derived without using a training signal, nonlinear distortion of a reproduction signal caused by improvement in recording density, recording power fluctuation, or the like can be reduced without a training signal.
- provisional judgment is executed according to the partial response rule, so it can support partial response processing.
- the nonlinear equalization signal is not output to the Viterbi decoding unit until the nonlinear equalization coefficient is converged, deterioration of the accuracy of the provisional determination signal can be suppressed.
- the deterioration of the accuracy of the provisional determination signal until the nonlinear equalization coefficient is converged is suppressed, the deterioration of the accuracy of the equalization processing can be suppressed even at the initial stage of the processing.
- the nonlinear equalization signal is not used to derive the coefficient for linear equalization until the nonlinear equalization coefficient is converged, deterioration of the derivation accuracy of the coefficient can be suppressed.
- deterioration in the derivation accuracy of the coefficient for linear equalization until the nonlinear equalization coefficient is converged is suppressed, deterioration in the accuracy of the equalization process can be suppressed even at the initial stage of the process. .
- a plurality of coefficients are newly derived when the divergence of the non-linear equalization error signal is detected, deterioration of the equalization characteristics can be suppressed.
- the third embodiment of the present invention relates to a reproducing apparatus in which a linear waveform equalizer and a nonlinear waveform equalizer are arranged in parallel. Both the linear waveform equalizer and the nonlinear waveform equalizer have multi-stage taps.
- the multistage tap is shared by the linear waveform equalizer and the nonlinear waveform equalizer.
- the playback apparatus 100 and the processing unit 24 according to the third embodiment are the same type as those in FIGS. Here, the difference from the second embodiment will be mainly described.
- FIG. 25 shows a configuration of the equalization processing unit 1030 according to the third embodiment of the present invention.
- the equalization processing unit 1030 includes a linear processing unit 1052, a non-linear processing unit 1072, and a multistage tap 1130.
- the multistage tap 1130 includes a first delay tap 1132a, a second delay tap 1132b, a third delay tap 1132c, and an Nth delay tap 1132n, which are collectively referred to as a delay tap 1132.
- the multistage tap 1130 is configured in the same manner as the multistage tap 1050 included in the linear equalization unit 1044 in FIG. 14 and the multistage tap 1070 included in the nonlinear equalization unit 1046 in FIG. 15, and a plurality of delay taps 1132 are serially connected. It is connected. That is, the multistage tap 1130 is shared by the linear equalization unit and the nonlinear equalization unit.
- the output from the multistage tap 1130 is output to the linear processing unit 1052 and also to the nonlinear processing unit 1072.
- the linear processing unit 1052 is the same as the configuration shown in FIG. 14, and the nonlinear processing unit 1072 is the same as the configuration shown in FIG. Here, these descriptions are omitted.
- the multistage tap is shared in linear equalization and nonlinear equalization, an increase in circuit scale can be suppressed.
- multistage taps performing the same processing are shared in linear equalization and nonlinear equalization, it is possible to suppress deterioration in processing accuracy with respect to linear equalization and nonlinear equalization.
- the circuit scale can be reduced while suppressing the accuracy of equalization processing.
- both the linear equalization unit 44 and the non-linear equalization unit 46 use a plurality of tap coefficients, and derive a plurality of tap coefficients adaptively.
- the present invention is not limited to this.
- the nonlinear equalizer 46 may adaptively derive a plurality of tap coefficients, and the linear equalizer 44 may use a fixed value as the plurality of tap coefficients. That is, the linear equalization unit 44 does not have to adaptively derive a plurality of tap coefficients.
- the first addition unit 40 does not output the linear equalization error signal 300 to the linear equalization unit 44. According to this modification, since the coefficient for linear equalization is a fixed value, the processing can be simplified.
- each of the linear equalization unit 1044 and the nonlinear equalization unit 1046 uses a plurality of tap coefficients and adaptively derives the plurality of tap coefficients.
- the present invention is not limited to this.
- the nonlinear equalizer 1046 may adaptively derive a plurality of tap coefficients, and the linear equalizer 1044 may use a fixed value as the plurality of tap coefficients. That is, the linear equalization unit 1044 may not derive a plurality of tap coefficients adaptively.
- FIG. 26 shows the configuration of the processing unit 24 according to a modification of the present invention.
- the processing unit 24 includes a delay unit 1140 as compared with FIG. Here, it demonstrates centering on the difference with FIG.
- the adder 1036 adds the linear equalized signal from the linear equalizer 1044 and the nonlinear equalized signal from the nonlinear equalizer 1046.
- the delay unit 1140 delays the signal output from the equalization error generation unit 1040.
- the delay unit 1140 performs a delay over a period corresponding to the processing delay in the Viterbi decoding unit 1038.
- the equalization error generation unit 1040 generates a non-linear equalization error signal 1302 based on the difference between the signal delayed in the delay unit 1140 and the provisional determination signal 1306 from the Viterbi decoding unit 1038, and performs non-linear equalization
- the unit 1046 derives a plurality of coefficients based on the non-linear equalization error signal 1302. According to this modification, since the coefficient for linear equalization is a fixed value, the stability of the equalization process can be improved. In addition, since the coefficient for linear equalization is a fixed value, the processing can be simplified.
- optical discs 10 optical discs, 12 optical disc drive units, 14 optical pickups, 16 preamplifier units, 18 AGC units, 20 PLL units, 22 A / D conversion units, 24 processing units, 26 control units, 30 temporary determination units, 32 first delay units, 34 second delay unit, 38 Viterbi decoding unit, 40 first addition unit, 42 second addition unit, 44 linear equalization unit, 46 non-linear equalization unit, 100 playback device.
- the present invention it is possible to reduce the non-linear distortion of the reproduction signal caused by the improvement of the recording density, the recording power fluctuation or the like without the training signal.
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Abstract
Description
本発明を具体的に説明する前に、まず概要を述べる。本発明の実施例1は、光ディスク等の記録媒体に記録されている信号を再生し、再生した信号(以下、「再生信号」という)をパーシャルレスポンス方式にて等化するととともに、等化した信号(以下、「等化信号」という)を復号する再生装置に関する。前述のごとく、光ディスクの記録容量が高まるにつれ、線形波形等化器では除去しきれない非線形歪の影響が大きくなっている。非線形歪を除去するためには、非線形等化器としてのニューラルネットが有効であるが、トレーニング信号によって学習、収束させる必要がある。そこで、再生信号の非線形歪をトレーニング信号なしで低減するために、本実施例に係る再生装置は次の処理を実行する。 Example 1
Before describing the present invention specifically, an outline will be given first.
f(x)=(1-exp(-αx))/(1+exp(-αx)) (式1)
ここで、式1のxに積算結果V(j)が入力される。ここでは、第J関数演算部80jでの演算結果をX(j)と示し、当該演算結果が隠れ層からの出力に相当する。 The
f (x) = (1−exp (−αx)) / (1 + exp (−αx)) (Formula 1)
Here, the integration result V (j) is input to x in
E=(A-D)2 (式2) The tap
E = (AD) 2 (Formula 2)
(∂E)/(∂Y(j))=f’(Y(j))×2(A-D) (式3)
タップ係数導出部88は、タップ係数W2(j)を次のように更新する。
W2(j)=W2(j)old-ε×(∂E)/(∂W2(j)) (式4) Here, A corresponds to the linear equalization signal, and D corresponds to the
(∂E) / (∂Y (j)) = f ′ (Y (j)) × 2 (AD) (Formula 3)
The tap
W2 (j) = W2 (j) old −ε × (∂E) / (∂W2 (j)) (Formula 4)
(∂E)/(∂U(i,j))=
f’(U(i,j))×(∂E)/(∂Y(j))×W2(j) (式5)
タップ係数導出部88は、タップ係数W1(i,j)を次のように更新する。
W1(i,j)=
W1(i,j)old-ε×(∂E)/(∂W1(i,j)) (式6)
ここで、W1(i,j)oldは、ひとつ前のタイミングにおけるタップ係数W1(i,j)を示す。 Here, W2 (j) old indicates the tap coefficient W2 (j) at the previous timing. On the other hand, back propagation in the hidden layer is shown as follows.
(∂E) / (∂U (i, j)) =
f ′ (U (i, j)) × (∂E) / (∂Y (j)) × W2 (j) (Formula 5)
The tap
W1 (i, j) =
W1 (i, j) old −ε × (∂E) / (∂W1 (i, j)) (Formula 6)
Here, W1 (i, j) old indicates the tap coefficient W1 (i, j) at the previous timing.
本発明を具体的に説明する前に、まず概要を述べる。本発明の実施例2は、光ディスク等の記録媒体に記録されている信号を再生し、再生した信号(以下、「再生信号」という)をパーシャルレスポンス方式にて等化するととともに、等化した信号(以下、「等化信号」という)を復号する再生装置に関する。前述のごとく、光ディスクの記録容量が高まるにつれ、線形波形等化器では除去しきれない非線形歪の影響が大きくなっている。非線形歪を除去するためには、非線形等化器としてのニューラルネットが有効であるが、トレーニング信号によって学習、収束させる必要がある。そこで、再生信号の非線形歪をトレーニング信号なしで低減するために、本実施例に係る再生装置は次の処理を実行する。 (Example 2)
Before describing the present invention specifically, an outline will be given first. The second embodiment of the present invention reproduces a signal recorded on a recording medium such as an optical disk, equalizes the reproduced signal (hereinafter referred to as “reproduced signal”) using a partial response method, and equalizes the signal. The present invention relates to a playback apparatus for decoding (hereinafter referred to as “equalized signal”). As described above, as the recording capacity of the optical disk increases, the influence of nonlinear distortion that cannot be removed by the linear waveform equalizer increases. In order to remove the nonlinear distortion, a neural network as a nonlinear equalizer is effective, but it is necessary to learn and converge with a training signal. Therefore, in order to reduce the non-linear distortion of the reproduction signal without the training signal, the reproduction apparatus according to the present embodiment executes the following processing.
f(x)=(1-exp(-αx))/(1+exp(-αx))…(式7)
ここで、式7のxに積算結果V(j)が入力される。ここでは、第J関数演算部1080jでの演算結果をX(j)と示し、当該演算結果が隠れ層からの出力に相当する。
f (x) = (1−exp (−αx)) / (1 + exp (−αx)) (Expression 7)
Here, the integration result V (j) is input to x in
E=(A-D)2…(式8) Tap
E = (AD) 2 (Formula 8)
(∂E)/(∂Y(j))=f’(Y(j))×2(A-D)…(式9)
タップ係数導出部1088は、タップ係数W2(j)を次のように更新する。
W2(j)=W2(j)old-ε×(∂E)/(∂W2(j))…(式10) Here, A corresponds to the sum of the linear equalization signal and the nonlinear equalization signal, and D corresponds to the
(∂E) / (∂Y (j)) = f ′ (Y (j)) × 2 (AD) (Equation 9)
The tap
W2 (j) = W2 (j) old −ε × (∂E) / (∂W2 (j)) (Equation 10)
(∂E)/(∂U(i,j))=
f’(U(i,j))×(∂E)/(∂Y(j))×W2(j)…(式11)
タップ係数導出部1088は、タップ係数W1(i,j)を次のように更新する。
W1(i,j)=
W1(i,j)old-ε×(∂E)/(∂W1(i,j))…(式12)
ここで、W1(i,j)oldは、ひとつ前のタイミングにおけるタップ係数W1(i,j)を示す。 Here, W2 (j) old indicates the tap coefficient W2 (j) at the previous timing. On the other hand, back propagation in the hidden layer is shown as follows.
(∂E) / (∂U (i, j)) =
f ′ (U (i, j)) × (∂E) / (∂Y (j)) × W2 (j) (Equation 11)
The tap
W1 (i, j) =
W1 (i, j) old −ε × (∂E) / (∂W1 (i, j)) (Equation 12)
Here, W1 (i, j) old indicates the tap coefficient W1 (i, j) at the previous timing.
本発明の実施例3は、実施例2と同様に、線形波形等化器と非線形波形等化器とを並列に配置した再生装置に関する。線形波形等化器と非線形波形等化器とは、いずれも多段タップを備える。実施例3に係る再生装置では、回路規模を減少させるために、線形波形等化器と非線形波形等化器とにおいて、多段タップが共通化される。実施例3に係る再生装置100、処理部24は、図1、図13と同様のタイプである。ここでは、実施例2との差異を中心に説明する。 (Example 3)
As in the second embodiment, the third embodiment of the present invention relates to a reproducing apparatus in which a linear waveform equalizer and a nonlinear waveform equalizer are arranged in parallel. Both the linear waveform equalizer and the nonlinear waveform equalizer have multi-stage taps. In the reproducing apparatus according to the third embodiment, in order to reduce the circuit scale, the multistage tap is shared by the linear waveform equalizer and the nonlinear waveform equalizer. The
Claims (15)
- 処理対象の信号を順次線形等化する線形等化部と、
前記線形等化部において線形等化した信号を順次仮判定する仮判定部と、
前記仮判定部において仮判定した信号を教師信号として複数の係数を導出するとともに、複数の係数をもとに、前記線形等化部において線形等化した信号を順次非線形等化する非線形等化部と、
を備えることを特徴とする等化器。 A linear equalization unit that sequentially linearly equalizes the signal to be processed;
A provisional determination unit that sequentially provisionally determines signals linearly equalized in the linear equalization unit;
A non-linear equalization unit for deriving a plurality of coefficients using the signal provisionally determined by the temporary determination unit as a teacher signal and sequentially non-linear equalizing the signal linearly equalized by the linear equalization unit based on the plurality of coefficients When,
An equalizer comprising: - 前記仮判定部は、パーシャルレスポンス規則にしたがって仮判定を実行することを特徴とする請求項1に記載の等化器。 The equalizer according to claim 1, wherein the temporary determination unit performs a temporary determination according to a partial response rule.
- 前記非線形等化部において非線形等化した信号を遅延させる遅延部をさらに備え、
前記遅延部は、前記仮判定部における処理遅延と前記非線形等化部における処理遅延との差異に応じた期間にわたって遅延を実行し、
前記非線形等化部は、前記遅延部において遅延した信号と前記仮判定部において仮判定した信号との差異をもとに、複数の係数を導出することを特徴とする請求項1または2に記載の等化器。 A delay unit that delays the signal that is nonlinearly equalized in the nonlinear equalizer;
The delay unit executes a delay over a period according to a difference between a processing delay in the temporary determination unit and a processing delay in the nonlinear equalization unit,
3. The non-linear equalization unit derives a plurality of coefficients based on a difference between a signal delayed by the delay unit and a signal provisionally determined by the temporary determination unit. Equalizer. - 前記非線形等化部は、差異がしきい値よりも大きくなった場合に、複数の係数を新たに導出することを特徴とする請求項3に記載の等化器。 4. The equalizer according to claim 3, wherein the nonlinear equalizer newly derives a plurality of coefficients when the difference becomes larger than a threshold value.
- 入力した信号を順次線形等化するステップと、
線形等化した信号を順次仮判定するステップと、
仮判定した信号を教師信号として複数の係数を導出するとともに、複数の係数をもとに、線形等化した信号を順次非線形等化するステップと、
を備えることを特徴とする等化方法。 Sequentially equalizing the input signal, and
Sequentially and temporarily determining linearly equalized signals;
A step of deriving a plurality of coefficients using the provisionally determined signal as a teacher signal and sequentially nonlinearly equalizing the linearly equalized signal based on the plurality of coefficients;
An equalization method comprising: - 入力した信号を順次線形等化するステップと、
線形等化した信号を順次仮判定するステップと、
仮判定した信号を教師信号として複数の係数を導出するとともに、複数の係数をもとに、線形等化した信号を順次非線形等化するステップと、
をコンピュータに実行させるためのプログラム。 Sequentially equalizing the input signal, and
Sequentially and temporarily determining linearly equalized signals;
A step of deriving a plurality of coefficients using the provisionally determined signal as a teacher signal and sequentially nonlinearly equalizing the linearly equalized signal based on the plurality of coefficients;
A program that causes a computer to execute. - 処理対象の信号を順次入力する入力部と、
前記入力部において入力した信号を順次線形等化する線形等化部と、
前記線形等化部における線形等化に並行して、前記入力部において入力した信号を順次非線形等化する適応非線形等化部と、
前記適応非線形等化部において非線形等化した信号と、前記線形等化部において線形等化した信号とを加算する加算部と、
前記加算部において加算した信号を順次仮判定する仮判定部とを備え、
前記適応非線形等化部は、前記仮判定部において仮判定した信号を教師信号として複数の係数を導出するとともに、複数の係数をもとに、非線形等化を実行することを特徴とする等化器。 An input unit for sequentially inputting signals to be processed;
A linear equalization unit that sequentially linearly equalizes the signal input in the input unit;
In parallel with the linear equalization in the linear equalization unit, an adaptive nonlinear equalization unit that sequentially nonlinearly equalizes the signal input in the input unit;
An adder that adds a signal that is nonlinearly equalized in the adaptive nonlinear equalizer and a signal that is linearly equalized in the linear equalizer;
A temporary determination unit that sequentially determines the signals added in the addition unit sequentially,
The adaptive nonlinear equalization unit derives a plurality of coefficients using the signal provisionally determined by the provisional determination unit as a teacher signal, and performs nonlinear equalization based on the plurality of coefficients vessel. - 前記線形等化部に含まれた多段タップと、前記適応非線形等化部における多段タップとが、共通化されていることを特徴とする請求項7に記載の等化器。 The equalizer according to claim 7, wherein the multistage tap included in the linear equalization unit and the multistage tap in the adaptive nonlinear equalization unit are shared.
- 前記仮判定部は、パーシャルレスポンス規則にしたがって仮判定を実行することを特徴とする請求項7または8に記載の等化器。 The equalizer according to claim 7 or 8, wherein the temporary determination unit executes a temporary determination according to a partial response rule.
- 前記適応非線形等化部における複数の係数の収束を判定する判定部をさらに備え、
前記加算部は、前記判定部において収束が判定されるまでの間、前記線形等化部において線形等化した信号を前記仮判定部へ出力し、前記判定部において収束が判定された後、加算した信号を前記仮判定部へ出力することを特徴とする請求項7から9のいずれかに記載の等化器。 A determination unit for determining convergence of a plurality of coefficients in the adaptive nonlinear equalization unit;
The addition unit outputs a signal linearly equalized by the linear equalization unit to the provisional determination unit until convergence is determined by the determination unit. After the convergence is determined by the determination unit, the addition is performed. The equalizer according to claim 7, wherein the received signal is output to the provisional determination unit. - 前記線形等化部において線形等化した信号を遅延させる第1遅延部と、
前記適応非線形等化部において非線形等化した信号を遅延させる第2遅延部とをさらに備え、
前記第1遅延部は、前記仮判定部における処理遅延に応じた期間にわたって遅延を実行し、
前記第2遅延部は、前記仮判定部における処理遅延に応じた期間にわたって遅延を実行し、
前記適応非線形等化部は、前記第1遅延部において遅延した信号と前記第2遅延部において遅延した信号との和と、前記仮判定部において仮判定した信号との差異をもとに、複数の係数を導出し、
前記線形等化部は、複数の係数を使用して線形等化を実行しており、前記判定部において収束が判定されるまでの間、前記第1遅延部において遅延した信号と前記仮判定部において仮判定した信号との差異をもとに、複数の係数を導出し、前記判定部において収束が判定された後、前記第1遅延部において遅延した信号と前記第2遅延部において遅延した信号との和と、前記仮判定部において仮判定した信号との差異をもとに、複数の係数を導出することを特徴とする請求項10に記載の等化器。 A first delay unit that delays a signal linearly equalized in the linear equalization unit;
A second delay unit that delays the signal that is nonlinearly equalized in the adaptive nonlinear equalization unit,
The first delay unit executes a delay over a period according to the processing delay in the temporary determination unit,
The second delay unit executes a delay over a period according to the processing delay in the temporary determination unit,
The adaptive nonlinear equalization unit includes a plurality of signals based on a difference between a sum of a signal delayed in the first delay unit and a signal delayed in the second delay unit, and a signal temporarily determined in the temporary determination unit. The coefficient of
The linear equalization unit performs linear equalization using a plurality of coefficients, and the signal delayed in the first delay unit and the provisional determination unit until convergence is determined by the determination unit. A plurality of coefficients are derived on the basis of the difference from the signal temporarily determined in step, and after the convergence is determined in the determination unit, the signal delayed in the first delay unit and the signal delayed in the second delay unit 11. The equalizer according to claim 10, wherein a plurality of coefficients are derived based on a difference between the sum of and a signal provisionally determined by the provisional determination unit. - 前記線形等化部において線形等化した信号と前記適応非線形等化部において非線形等化した信号とを加算する加算部と、
前記加算部から出力した信号を遅延させる遅延部とをさらに備え、
前記遅延部は、前記仮判定部における処理遅延に応じた期間にわたって遅延を実行し、
前記適応非線形等化部は、前記遅延部において遅延した信号と、前記仮判定部において仮判定した信号との差異をもとに、複数の係数を導出し、
前記線形等化部は、複数の係数を使用して線形等化を実行しており、かつ複数の係数として固定値を使用することを特徴とする請求項7から10のいずれかに記載の等化器。 An adder for adding the signal linearly equalized in the linear equalizer and the signal nonlinearly equalized in the adaptive nonlinear equalizer;
A delay unit that delays the signal output from the adding unit;
The delay unit executes a delay over a period according to the processing delay in the temporary determination unit,
The adaptive nonlinear equalization unit derives a plurality of coefficients based on a difference between the signal delayed in the delay unit and the signal temporarily determined in the temporary determination unit,
11. The linear equalization unit performs linear equalization using a plurality of coefficients, and uses a fixed value as the plurality of coefficients, etc. Generator. - 前記適応非線形等化部は、複数の係数の発散を検出した場合に、複数の係数を新たに導出することを特徴とする請求項7から12のいずれかに記載の等化器。 13. The equalizer according to claim 7, wherein the adaptive nonlinear equalization unit newly derives a plurality of coefficients when detecting divergence of the plurality of coefficients.
- 入力した信号を順次線形等化するステップと、
線形等化に並行して、入力した信号を順次非線形等化するステップと、
非線形等化した信号と線形等化した信号とを加算するステップと、
加算した信号を順次仮判定するステップとを備え、
前記非線形等化するステップは、仮判定した信号を教師信号として複数の係数を導出するとともに、複数の係数をもとに、非線形等化を実行することを特徴とする等化方法。 Sequentially equalizing the input signal, and
In parallel with linear equalization, sequentially performing nonlinear equalization on the input signal;
Adding a non-linear equalized signal and a linear equalized signal;
The provisionally determining the added signal sequentially,
The non-linear equalization step includes deriving a plurality of coefficients using the provisionally determined signal as a teacher signal and performing non-linear equalization based on the plurality of coefficients. - 入力した信号を順次線形等化するステップと、
線形等化に並行して、入力した信号を順次非線形等化するステップと、
非線形等化した信号と線形等化した信号とを加算するステップと、
加算した信号を順次仮判定するステップとを備え、
前記非線形等化するステップは、仮判定した信号を教師信号として複数の係数を導出するとともに、複数の係数をもとに、非線形等化を実行することをコンピュータに実行させるためのプログラム。 Sequentially equalizing the input signal; and
In parallel with linear equalization, sequentially performing nonlinear equalization on the input signal;
Adding a non-linear equalized signal and a linear equalized signal;
The provisionally determining the added signals sequentially,
The non-linear equalization step is a program for deriving a plurality of coefficients using the provisionally determined signal as a teacher signal and causing the computer to execute non-linear equalization based on the plurality of coefficients.
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