WO2010100958A1 - 表示装置 - Google Patents
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- WO2010100958A1 WO2010100958A1 PCT/JP2010/050078 JP2010050078W WO2010100958A1 WO 2010100958 A1 WO2010100958 A1 WO 2010100958A1 JP 2010050078 W JP2010050078 W JP 2010050078W WO 2010100958 A1 WO2010100958 A1 WO 2010100958A1
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- display device
- potential
- wiring
- storage node
- light
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/042—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by opto-electronic means
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
- G02F1/13312—Circuits comprising photodetectors for purposes other than feedback
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
Definitions
- the present invention relates to a display device with a photosensor having a photodetection element such as a photodiode or phototransistor, and more particularly to a display device having a photosensor in a pixel region.
- a photodetection element such as a photodiode or phototransistor
- a display device with a photosensor that can detect the brightness of external light or capture an image of an object close to the display by providing a photodetection element such as a photodiode in the pixel.
- a display device with an optical sensor is assumed to be used as a display device for bidirectional communication or a display device with a touch panel function.
- Patent Document 1 In a conventional display device with an optical sensor, when forming known components such as signal lines, scanning lines, TFTs (Thin Film Transistors), and pixel electrodes in an active matrix substrate by a semiconductor process, simultaneously on the active matrix substrate A photodiode or the like is built in (see Patent Document 1 and Non-Patent Document 1).
- known components such as signal lines, scanning lines, TFTs (Thin Film Transistors), and pixel electrodes in an active matrix substrate by a semiconductor process, simultaneously on the active matrix substrate A photodiode or the like is built in (see Patent Document 1 and Non-Patent Document 1).
- FIG. 59 An example of a conventional optical sensor (Patent Documents 2 and 3) formed on an active matrix substrate is shown in FIG.
- the conventional optical sensor shown in FIG. 59 includes a photodiode D1, a capacitor C2, and a thin film transistor M2.
- a wiring RST for supplying a reset signal is connected to the anode of the photodiode D1.
- One of the electrodes of the capacitor C2 and the gate of the thin film transistor M2 are connected to the cathode of the photodiode D1.
- the drain of the thin film transistor M2 is connected to the wiring VDD, and the source is connected to the wiring OUT.
- the other electrode of the capacitor C2 is connected to a wiring RWS for supplying a read signal.
- a sensor output V PIX corresponding to the amount of light received by the photodiode D1 can be obtained by supplying a reset signal to the wiring RST and a read signal to the wiring RWS at predetermined timings.
- the low level (for example, ⁇ 7 V) of the reset signal is set to V RST.
- the reset signal high level (for example, 0 V) is set to V RST.
- the low level (for example, 0 V) of the read signal is set to V RWS.
- the high level of the read signal (for example, 15V) is set to V RWS. H , respectively.
- a high level reset signal V RST When H is supplied, the photodiode D1 is forward-biased, and the potential V INT of the gate of the thin film transistor M2 is expressed by the following equation (1).
- V INT V RST. H -V F (1)
- V F is the forward voltage of the photodiode D1. Since V INT at this time is lower than the threshold voltage of the thin film transistor M2, the thin film transistor M2 is in a non-conductive state in the reset period.
- the reset signal is low level VRST.
- a photocurrent integration period (sensing period, T INT period shown in FIG. 60) starts.
- a photocurrent proportional to the amount of light incident on the photodiode D1 flows out of the capacitor C2, and discharges the capacitor C2.
- the potential V INT of the gate of the thin film transistor M2 at the end of the integration period is expressed by the following equation (2).
- V INT V RST. H ⁇ V F ⁇ V RST ⁇ C PD / C T ⁇ I PHOTO ⁇ T INT / C T (2)
- ⁇ V RST is the pulse height of the reset signal (V RST.H ⁇ V RST.L )
- I PHOTO is the photocurrent of the photodiode D 1
- T INT is the length of the integration period That's it.
- CPD is the capacitance of the photodiode D1.
- C T is the sum of the capacitance of the capacitor C2, the capacitance C PD of the photodiode D1, a capacitor C TFT of the thin-film transistor M2. Even during the integration period, since V INT is lower than the threshold voltage of the thin film transistor M2, the thin film transistor M2 is in a non-conductive state.
- charge injection occurs in the capacitor C2.
- the gate potential V INT of the thin film transistor M2 is expressed by the following equation (3).
- V INT V RST. H ⁇ V F ⁇ V RST ⁇ C PD / C T ⁇ I PHOTO ⁇ T INT / C T + ⁇ V RWS ⁇ C INT / C T (3) ⁇ V RWS is the pulse height (V RWS.H ⁇ V RWS.L ) of the read signal.
- V INT of the gate of the thin film transistor M2 becomes higher than the threshold voltage, so that the thin film transistor M2 becomes conductive, and the source follower amplifier together with the bias thin film transistor M3 provided at the end of the wiring OUT in each column.
- the sensor output voltage V PIX from the thin film transistor M2 is proportional to the integrated value of the photocurrent of the photodiode D1 during the integration period.
- the waveform indicated by the solid line represents a change in the potential V INT when the light incident on the photodiode D1 is small, and the waveform indicated by the broken line represents the light at the saturation level incident on the photodiode D1.
- the change in potential V INT in the case is shown.
- ⁇ V SIG in FIG. 60 is a potential difference proportional to the amount of light incident on the photodiode D1.
- ⁇ V INT is the amount by which the potential V INT is pushed up when a read signal is applied to the optical sensor from the wiring RWS in the read period.
- the potential of the storage node at the end of the storage period when the illuminance is different (for example, in a dark state and when light of a saturation level is incident).
- the difference is equal to the difference in potential of the storage node after being pushed up in the reading period in each case.
- V INT1 the potential of the storage node at the end of the storage period in the dark state
- V INT2 the potential of the storage node at the end of the storage period when light of a saturation level is incident
- V INT3 The potential of the storage node after the push-up in the readout period in the dark state
- V INT4 the storage node after the push-up in the readout period when saturated level light is incident
- V INT3 -V INT4 the potential difference after the push-up (V INT3 -V INT4 ) is larger than the potential difference (V INT1 -V INT2 ) of the storage node due to the difference in illuminance on the light receiving surface at the end of the integration period.
- a display device is a display device including a photosensor in a pixel region of an active matrix substrate, and the photosensor receives a light detection element;
- a sensing period includes a reset signal wiring that supplies a reset signal to the photosensor, a readout signal wiring that supplies a readout signal to the photosensor, and a period from when the reset signal is supplied to when the readout signal is supplied.
- a storage node whose potential changes according to the amount of light received by the light detection element during a sensing period; an amplification element that amplifies the potential of the storage node according to the read signal; and a potential amplified by the amplification element And a sensor switching element for reading out to the output wiring as a sensor circuit output.
- the potential difference after the push-up is higher than the potential difference of the storage node due to the difference in illuminance on the light receiving surface at the end of the integration period.
- the readout period in the dark state is larger than the potential difference between the potential of the storage node at the end of the storage period in the dark state and the potential of the storage node at the end of the storage period in the case where light of saturation level is incident.
- the potential difference between the potential of the storage node after the push-up and the potential of the storage node after the push-up during the readout period when light of a saturation level is incident becomes larger.
- FIG. 1 is a block diagram showing a schematic configuration of a display device according to an embodiment of the present invention.
- FIG. 2 is an equivalent circuit diagram showing a configuration of one pixel in the display device according to the first embodiment of the present invention.
- FIG. 3 is a CV characteristic diagram of a capacitor provided in the photosensor according to the first embodiment.
- FIG. 4 is a timing chart showing the waveform of the drive signal and the potential change of the storage node in the photosensor according to the first embodiment.
- FIG. 5 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 6 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 7 is an enlarged view of a region where the capacitor C1 is formed.
- FIG. 8 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- FIG. 9 is a waveform diagram showing a change in the potential V INT of the storage node from the end of the integration period to the reading period.
- FIG. 10A is a schematic cross-sectional view illustrating charge transfer when the potential of the gate electrode is lower than the threshold voltage in the capacitor C1.
- FIG. 10A is a schematic cross-sectional view showing the movement of charges when the potential of the gate electrode is higher than the threshold voltage in the capacitor C1.
- FIG. 11 is a timing chart showing sensing timing of the display device according to the first embodiment.
- FIG. 12 is a circuit diagram showing the internal configuration of the sensor pixel readout circuit.
- FIG. 13 is a waveform diagram showing the relationship among the readout signal, the sensor output, and the output of the sensor pixel readout circuit.
- FIG. 14 is an equivalent circuit diagram showing a schematic configuration of the sensor column amplifier.
- FIG. 15 is an equivalent circuit diagram of the photosensor according to the second embodiment.
- FIG. 16 is a waveform diagram of a reset signal and a readout signal supplied to the photosensor according to the second embodiment.
- FIG. 17 is a plan view illustrating an example of a planar structure of the photosensor according to the second embodiment.
- FIG. 18 is an enlarged view of a region where the capacitor C1 is formed in FIG.
- FIG. 19 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the second embodiment.
- FIG. 20 is an equivalent circuit diagram of the photosensor according to the third embodiment.
- FIG. 21 is a plan view illustrating an example of a planar structure of the photosensor according to the third embodiment.
- FIG. 22 is an enlarged view of a region where the capacitor C1 is formed in FIG.
- FIG. 23 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the third embodiment.
- FIG. 24 is an equivalent circuit diagram of the photosensor according to the fourth embodiment.
- FIG. 25 is a plan view illustrating an example of a planar structure of the photosensor according to the fourth embodiment.
- FIG. 26 is an enlarged view of a region where the p-channel TFT is formed in FIG.
- FIG. 27 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the fourth embodiment.
- FIG. 28 is an equivalent circuit diagram of the p-channel TFT of the photosensor according to the fourth embodiment.
- FIG. 29 is a waveform diagram showing the influence of parasitic capacitance and leakage current on the potential of the storage node.
- FIG. 30 is a plan view illustrating an example of a planar structure of a modification of the photosensor according to the fourth embodiment.
- FIG. 31 is an enlarged view of a region where the p-channel TFT is formed in FIG.
- FIG. 32 is an equivalent circuit diagram of the p-channel TFT of FIG.
- FIG. 33 is an equivalent circuit diagram of an optical sensor according to the fifth embodiment.
- FIG. 34 is a plan view showing an example of a planar structure of an optical sensor according to the fifth embodiment.
- FIG. 35 is an enlarged view of a region where an amplifying element (n-channel TFT) is formed in the fifth embodiment.
- FIG. 36 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the fifth embodiment.
- FIG. 37 is an equivalent circuit diagram of an n-channel TFT as an amplifying element in the fifth embodiment.
- FIG. 38 is a plan view showing an example of a planar structure of a modification of the photosensor according to the fifth embodiment.
- FIG. 39 is a schematic cross-sectional view showing the connection relationship of each region in the amplifying element in the modification of FIG. FIG.
- FIG. 40 is an equivalent circuit diagram of the n-channel TFT of FIG.
- FIG. 41 is an equivalent circuit diagram of an optical sensor according to the sixth embodiment.
- FIG. 42 is a plan view illustrating an example of a planar structure of the photosensor according to the sixth embodiment.
- FIG. 43 is an enlarged view of a region where the amplifying element (photodiode D2) is formed in the sixth embodiment.
- FIG. 44 is a schematic cross-sectional view showing the connection relationship between the regions in the photosensor according to Embodiment 6.
- FIG. 45 is an equivalent circuit diagram of a photodiode as an amplifying element in the sixth embodiment.
- FIG. 46 is an equivalent circuit diagram of the photosensor according to the first modification example of the sixth embodiment.
- FIG. 47 is a plan view showing an example of a planar structure of an optical sensor according to a first modification of the sixth embodiment.
- FIG. 48 is an equivalent circuit diagram of an optical sensor according to a second modification of the sixth embodiment.
- FIG. 49 is a plan view illustrating an example of a planar structure of an optical sensor according to a second modification of the sixth embodiment.
- FIG. 50 is an equivalent circuit diagram of the photosensor according to the seventh embodiment.
- FIG. 51 is a plan view showing an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 52A is a circuit diagram showing a state of charge injection when a series capacitor CSER is combined with a configuration in which the amplifying element is a variable capacitor.
- FIG. 52B is a circuit diagram showing a state of charge injection when a series capacitor CSER is combined with a configuration in which the amplifying element is a p-channel TFT.
- FIG. 53 is an equivalent circuit diagram of an optical sensor according to the eighth embodiment.
- FIG. 54 is a plan view showing an example of a planar structure of an optical sensor according to the eighth embodiment.
- FIG. 55 is an equivalent circuit diagram of an optical sensor according to the ninth embodiment.
- FIG. 56 is a plan view showing an example of a planar structure of an optical sensor according to the ninth embodiment.
- FIG. 57 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 58 is a plan view showing an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 59 is an equivalent circuit diagram showing an example of a conventional photosensor formed on an active matrix substrate.
- FIG. 60 is a timing chart showing the waveform of the drive signal and the potential change of the storage node in the conventional photosensor
- a display device is a display device including a photosensor in a pixel region of an active matrix substrate, wherein the photosensor receives a light detection element and resets the photosensor.
- a reset signal wiring for supplying a signal, a readout signal wiring for supplying a readout signal to the optical sensor, and a period from when the reset signal is supplied until the readout signal is supplied are defined as a sensing period.
- a storage node whose potential changes according to the amount of light received by the light detection element, an amplification element that amplifies the potential of the storage node according to the readout signal, and a potential amplified by the amplification element as a sensor circuit output It is the structure provided with the sensor switching element for reading to an output wiring.
- the potential difference after the push-up is higher than the potential difference of the storage node due to the difference in the illuminance on the light receiving surface at the end of the integration period.
- the readout period in the dark state is larger than the potential difference between the potential of the storage node at the end of the storage period in the dark state and the potential of the storage node at the end of the storage period in the case where light of saturation level is incident.
- the potential difference between the potential of the storage node after the push-up and the potential of the storage node after the push-up during the readout period when light of a saturation level is incident becomes larger.
- this potential difference amplification function is not limited to the case of a dark state and the case where light of a saturation level is incident, but is established between arbitrary illuminances. Thereby, it is possible to provide a display device having an optical sensor with high sensitivity.
- a variable capacitor can be used as the amplifying element.
- the variable capacitor for example, a MOS capacitor including the read signal wiring, an insulating film, and a p-type semiconductor region formed in a silicon film can be used.
- a MOS capacitor including a gate electrode of the sensor switching element, an insulating film, and an n-type semiconductor region formed in a silicon film can be used. According to the former configuration, since the read signal wiring can be used as the gate electrode of the variable capacitor, there is an advantage that it is not necessary to provide a wiring or a contact for connecting the read signal wiring and the gate electrode. .
- a p-channel thin film transistor can be used as the amplifying element.
- the p-channel thin film transistor a channel region is formed in a wide portion of the silicon film connecting the photodetecting element and the storage node, and a gate electrode of the p-channel thin film transistor is provided so as to overlap the wide portion. It is preferable to adopt the configuration described above. This is because according to this configuration, the boundary length can be shortened, and the reduction of the dynamic range due to parasitic capacitance and leakage current can be prevented.
- an n-channel thin film transistor may be used as the amplifying element.
- a diode having a gate electrode on a channel may be used as the amplifying element. According to this configuration, the boundary length can be shortened.
- a light-shielding film provided on the opposite side of the light-receiving surface with respect to the light detection element, and a series capacitance is formed with respect to the parasitic capacitance between the light-shielding film and the light detection element
- an electrode provided to face the light-shielding film, and the electrode is electrically connected to the readout wiring.
- the pixel region includes a plurality of the light detection elements, the plurality of light detection elements are connected in parallel, and the amplification element is connected to a light detection element at a terminal of the plurality of light detection elements.
- a connected configuration is preferable.
- the sensor switching element is a three-terminal switching element, a gate electrode of the three terminals is connected to the storage node, and one of the remaining two terminals of the three terminals is the output wiring. It is preferable to have a configuration connected to According to this configuration, since the number of sensor switching elements is sufficient, the circuit configuration of the optical sensor can be simplified.
- the display device may further include a reset switching element for the sensor switching element.
- the amplifying element has a threshold potential at which the amplifying element is switched on / off between a low level potential and a high level potential of the readout signal.
- the display device may be implemented as a liquid crystal display device further including a counter substrate facing the active matrix substrate and a liquid crystal sandwiched between the active matrix substrate and the counter substrate. .
- the display device according to the present invention is implemented as a liquid crystal display device.
- the display device according to the present invention is not limited to the liquid crystal display device, and is an active matrix.
- the present invention can be applied to any display device using a substrate.
- the display device according to the present invention includes a touch panel display device that performs an input operation by detecting an object close to the screen by using an optical sensor, and a display for bidirectional communication including a display function and an imaging function. Use as a device is assumed.
- each drawing referred to below shows only the main members necessary for explaining the present invention in a simplified manner among the constituent members of the embodiment of the present invention for convenience of explanation. Therefore, the display device according to the present invention can include arbitrary constituent members that are not shown in the drawings referred to in this specification. Moreover, the dimension of the member in each figure does not represent the dimension of an actual structural member, the dimension ratio of each member, etc. faithfully.
- FIG. 1 is a block diagram showing a schematic configuration of an active matrix substrate 100 provided in a liquid crystal display device according to an embodiment of the present invention.
- an active matrix substrate 100 includes a pixel region 1, a display gate driver 2, a display source driver 3, a sensor column driver 4, a sensor row driver 5, and a buffer amplifier 6 on a glass substrate.
- the FPC connector 7 is provided at least.
- a signal processing circuit 8 for processing an image signal captured by a light detection element (described later) in the pixel region 1 is connected to the active matrix substrate 100 via the FPC connector 7 and the FPC 9. .
- the above-described constituent members on the active matrix substrate 100 can be formed monolithically on the glass substrate by a semiconductor process. Or it is good also as a structure which mounted the amplifier and drivers among said structural members on the glass substrate by COG (Chip On Glass) technique etc., for example. Alternatively, it is conceivable that at least a part of the constituent members shown on the active matrix substrate 100 in FIG. 1 is mounted on the FPC 9.
- the active matrix substrate 100 is bonded to a counter substrate (not shown) having a counter electrode formed on the entire surface, and a liquid crystal material is sealed in the gap.
- the pixel area 1 is an area where a plurality of pixels are formed in order to display an image.
- an optical sensor for capturing an image is provided in each pixel in the pixel region 1.
- FIG. 2 is an equivalent circuit diagram showing the arrangement of pixels and photosensors in the pixel region 1 of the active matrix substrate 100.
- one pixel is formed by picture elements of three colors R (red), G (green), and B (blue), and one pixel composed of these three picture elements includes 1
- Two light sensors are provided.
- the pixel region 1 includes pixels arranged in a matrix of M rows ⁇ N columns and photosensors arranged in a matrix of M rows ⁇ N columns. As described above, the number of picture elements is M ⁇ 3N.
- the pixel region 1 has gate lines GL and source lines COL arranged in a matrix as wiring for the pixels.
- the gate line GL is connected to the display gate driver 2.
- the source line COL is connected to the display source driver 3.
- the gate lines GL are provided in M rows in the pixel region 1.
- three source lines COL are provided for each pixel in order to supply image data to the three picture elements in one pixel.
- a thin film transistor (TFT) M1 is provided as a pixel switching element at the intersection of the gate line GL and the source line COL.
- the thin film transistor M1 provided in each of the red, green, and blue picture elements is denoted as M1r, M1g, and M1b.
- the thin film transistor M1 has a gate electrode connected to the gate line GL, a source electrode connected to the source line COL, and a drain electrode connected to a pixel electrode (not shown).
- a liquid crystal capacitor CLC is formed between the drain electrode of the thin film transistor M1 and the counter electrode (VCOM).
- the auxiliary capacitance C LS is formed between the drain electrode and the TFTCOM.
- the pixel driven by the thin film transistor M1r connected to the intersection of one gate line GLi and one source line COLrj is provided with a red color filter corresponding to this pixel.
- red image data is supplied from the display source driver 3 via the source line COLrj, it functions as a red picture element.
- a picture element driven by the thin film transistor M1g connected to the intersection of the gate line GLi and the source line COLgj is provided with a green color filter so as to correspond to the picture element, and a display source is provided via the source line COLgj.
- green image data is supplied from the driver 3, it functions as a green picture element.
- the pixel driven by the thin film transistor M1b connected to the intersection of the gate line GLi and the source line COLbj is provided with a blue color filter so as to correspond to this pixel, and the display source is connected via the source line COLbj.
- blue image data is supplied from the driver 3, it functions as a blue picture element.
- one photosensor is provided for each pixel (three picture elements) in the pixel region 1.
- the arrangement ratio of the pixels and the photosensors is not limited to this example and is arbitrary.
- one photosensor may be arranged for each picture element, or one photosensor may be arranged for a plurality of pixels.
- the optical sensor includes a photodiode D1 as a light detecting element, a capacitor C1 (amplifying element), and a thin film transistor M2.
- the capacitor C1 that functions as an amplifying element is a variable capacitor.
- the source line COLr also serves as the wiring VDD for supplying the constant voltage V DD from the sensor column driver 4 to the photosensor. Further, the source line COLg also serves as the sensor output wiring OUT.
- a wiring RST as a reset signal wiring for supplying a reset signal is connected to the anode of the photodiode D1.
- One electrode of the capacitor C1 and the gate of the thin film transistor M2 are connected to the cathode of the photodiode D1.
- the drain of the thin film transistor M2 is connected to the wiring VDD, and the source is connected to the wiring OUT.
- a connection point (storage node) between the cathode of the photodiode D1, one of the electrodes of the capacitor C1, and the gate of the thin film transistor M2 is denoted as INT.
- the other electrode of the capacitor C1 is connected to a wiring RWS as a readout signal wiring for supplying a readout signal.
- the sensor row driver 5 sequentially selects a set of wirings RSTi and RWSi shown in FIG. 2 at a predetermined time interval t row . As a result, the rows of photosensors from which signal charges are to be read out in the pixel region 1 are sequentially selected.
- the drain of a thin film transistor M3, which is an insulated gate field effect transistor, is connected to the end of the wiring OUT.
- the drain of the thin film transistor M3 is connected to the output wiring SOUT, and the drain potential V SOUT of the thin film transistor M3 is output to the sensor column driver 4 as an output signal from the photosensor.
- the source of the thin film transistor M3 is connected to the wiring VSS.
- the gate of the thin film transistor M3 is connected to a reference voltage power source (not shown) via the reference voltage wiring VB.
- FIG. 3 is a CV characteristic diagram of the capacitor C1.
- the horizontal axis represents the interelectrode voltage V CAP of the capacitor C1
- the vertical axis represents the capacitance.
- the capacitor C1 has a constant capacitance while the interelectrode voltage V CAP is small, but has a characteristic that the capacitance changes sharply before and after the threshold value of the interelectrode voltage V CAP. . Therefore, the characteristics of the capacitor C1 can be dynamically changed by the potential of the read signal from the wiring RWS.
- the photosensor according to the present embodiment can amplify and read out the potential change of the storage node in the integration period T INT as shown in FIG.
- the example in FIG. 4 is merely an embodiment, but the low level V RST. L is ⁇ 1.4V, and the reset signal high level V RST. H is 0V. Further, the low level V RWS. L is -3V, read signal high level V RWS. H is 12V. Also in FIG. 4, the waveform indicated by the solid line represents the change in the potential V INT when light is incident on the photodiode D1, and the waveform indicated by the broken line is the case where light at the saturation level is incident on the photodiode D1. Represents a change in the potential V INT , and ⁇ V SIG is a potential difference proportional to the amount of light incident on the photodiode D1. As is clear from a comparison between the conventional example shown in FIG.
- the potential change of the storage node in the integration period T INT when the light of the saturation level is incident is smaller than the conventional photosensor, the potential of the storage node is amplified and read out during the readout period (while the potential of the readout signal is at the high level V RWS.H ).
- V INT V RST. H- V F (4)
- V F is the forward voltage of the photodiode D1. Since V INT at this time is lower than the threshold voltage of the thin film transistor M2, the thin film transistor M2 is in a non-conductive state in the reset period.
- the reset signal is low level VRST.
- the photocurrent integration period T INT
- a photocurrent proportional to the amount of light incident on the photodiode D1 flows into the capacitor C1, and the capacitor C1 is discharged.
- the potential V INT at the connection point INT at the end of the integration period T INT is expressed by the following equation (5).
- V INT V RST. H ⁇ V F ⁇ V RST ⁇ C PD / C T -I PHOTO ⁇ t INT / C T (5)
- ⁇ V RST is the pulse height (V RST.H -V RST.L ) of the reset signal
- I PHOTO is the photocurrent of the photodiode D 1
- t INT is the length of the integration period That's it.
- CPD is the capacitance of the photodiode D1.
- C TOTAL is the capacitance of the entire optical sensor circuit, that is, the total capacitance of the connection point INT, and is the sum of the capacitance C INT of the capacitor C1, the capacitance C PD of the photodiode D1, and the capacitance C TFT of the thin film transistor M2. . Even during the integration period, since V INT is lower than the threshold voltage of the thin film transistor M2, the thin film transistor M2 is in a non-conductive state.
- the readout period starts by the rise of the readout signal supplied to the wiring RWS.
- charge injection occurs in the capacitor C1.
- the output signal voltage from the output wiring SOUT from the drain of the thin film transistor M3 corresponds to an amplified value of the photocurrent of the photodiode D1 during the integration period. The principle will be described later.
- the initialization by the reset pulse, the integration of the photocurrent in the integration period, and the reading of the sensor output in the reading period are periodically performed as one cycle.
- FIG. 5 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 6 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 7 is an enlarged view of a region where the capacitor C1 is formed.
- FIG. 8 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- the optical sensor according to the present embodiment includes a capacitor C1 that is a variable capacitor as an amplifying element.
- the capacitor C1 is a p-channel MOS capacitor.
- the thin film transistor M2 is provided in the region between the source lines COLg and COLb, and one set of the capacitor C1 and the photodiode D1 is provided on both sides thereof.
- the capacitor C1 and the photodiode D1 are provided.
- a configuration may be provided in which only one set is provided.
- the photosensor according to this embodiment includes a thin film transistor M2 in a region between the source lines COLg and COLb.
- the photodiode D1 is a lateral structure PIN diode in which a p-type semiconductor region 102p, an i-type semiconductor region 102i, and an n-type semiconductor region 102n are formed in series on a base silicon film.
- the p-type semiconductor region 102p serves as the anode of the photodiode D1, and is connected to the wiring RST via the wiring 108 and the contacts 109 and 110.
- the n-type semiconductor region 102n serves as the cathode of the photodiode D1, and is connected to the gate electrode 101 of the thin film transistor M2 through the silicon film extension 107, the contacts 105 and 106, and the wiring 104.
- the wirings RST and RWS are formed of the same metal as the gate electrode 101 of the thin film transistor M2 in the same process. Further, the wirings 104 and 108 are formed of the same metal as the source line COL in the same process. On the back surface of the photodiode D1, a light shielding film 113 for preventing backlight light from entering the sensor is provided.
- the capacitor C1 is formed by the wide portion 111 formed in the wiring RWS, the extending portion 107 of the silicon film, and the insulating film (not shown) disposed therebetween. Is formed. That is, the wide portion 111 having the same potential as the wiring RWS functions as the gate electrode of the capacitor C1.
- a region 112 shown in FIG. 7 is a p + region formed by doping a n-type silicon film with a p-type impurity such as boron. Since the wide portion 111 functions as a mask when doping with p-type impurities, as shown in FIG. 8, the extended portion 107 becomes a p + region, and the silicon film below the wide portion 111 has an n ⁇ region.
- FIG. 9 is a waveform diagram showing a change in the potential V INT of the storage node from the end of the integration period to the reading period.
- a waveform w1 indicated by a solid line represents a change in the potential V INT when light is incident on the photodiode D1
- a waveform w2 indicated by a broken line is a potential when light is incident on the photodiode D1. It represents a change in V INT .
- the read signal supplied from the wiring RWS is low level V RWS.
- a time to start rising from the L, the time t 2 the read signal is at a high level V RWS. Time to reach H.
- Time t S is the time when the thin film transistor M2 is turned on and the sensor output is sampled.
- Time t 1 is the time when the read signal reaches the threshold voltage V off of the capacitor C1. That is, the operating characteristics of the capacitor C1 change depending on the magnitude relationship between the potential supplied from the wiring RWS to the wide portion 111 and the threshold voltage Voff .
- Time t 1 ′ is the time when the read signal reaches the threshold voltage V off of the capacitor C1 in the case of the waveform w2 (when light enters the photodiode D1).
- FIGS. 10A and 10B are schematic cross-sectional views showing the difference in charge movement due to the potential of the gate electrode (wide portion 111) in capacitor C1.
- capacitor C1 is always on, after time t 1 is turned off. That is, while the potential of the wiring RWS is equal to or lower than the threshold voltage V off , the movement of the charge Q inj below the gate electrode (wide portion 111) occurs as shown in FIG. 10A, but the potential of the wiring RWS decreases to the threshold voltage V off . If it exceeds, the movement of the charge Q inj under the gate electrode (wide portion 111) is eliminated as shown in FIG. 10B.
- the potential of the read signal supplied from the wiring RWS is high level V RWS.
- the potential V INT of the storage node at sample time t s after reaching the H (t s) is as shown in the following equation (6). Note that ⁇ V INT shown in FIG. 4 corresponds to a difference between V INT (t 0 ) and V INT (t s ), and is equal to Q inj / C INT .
- ⁇ V SIG (t 0 ) at the end of the integration period is amplified to ⁇ V SIG (t 1 ).
- the potential difference after the push-up becomes larger than the potential difference of the storage node due to the difference in the illuminance on the light receiving surface at the end of the integration period.
- the readout period in the dark state is larger than the potential difference between the potential of the storage node at the end of the storage period in the dark state and the potential of the storage node at the end of the storage period in the case where light of saturation level is incident.
- the source lines COLr and COLg are shared as the optical sensor wirings VDD and OUT, and therefore, as shown in FIG. It is necessary to distinguish the timing for inputting the image data signal for display from the timing for reading the sensor output.
- the sensor output is read out using the horizontal blanking period or the like after the input of the display image data signal in the horizontal scanning period.
- HSYNC in FIG. 11 indicates a horizontal synchronization signal.
- the sensor column driver 4 includes a sensor pixel readout circuit 41, a sensor column amplifier 42, and a sensor column scanning circuit 43.
- An output wiring SOUT (see FIG. 2) that outputs the sensor output V SOUT from the pixel region 1 is connected to the sensor pixel readout circuit 41.
- the sensor pixel readout circuit 41 outputs the peak hold voltage V Sj of the sensor output V SOUTj to the sensor column amplifier 42.
- V COUT is output to the buffer amplifier 6.
- FIG. 12 is a circuit diagram showing an internal configuration of the sensor pixel readout circuit 41.
- FIG. 13 is a waveform diagram showing the relationship among the readout signal, the sensor output, and the output of the sensor pixel readout circuit.
- the read signal is at the high level V RWS.
- V RWS When it becomes H , when the thin film transistor M2 is turned on, a source follower amplifier is formed by the thin film transistors M2 and M3, and the sensor output V SOUT is accumulated in the sample capacitor C SAM of the sensor pixel readout circuit 41. As a result, the read signal is low level V RWS.
- the output voltage V S from the sensor pixel readout circuit 41 to the sensor column amplifier 42 remains at the peak value of the sensor output V SOUT during the selection period (t row ) of the row even after becoming L , as shown in FIG. Is held at a level equal to.
- each column amplifier is composed of thin film transistors M6 and M7.
- the buffer amplifier 6 further amplifies V COUT output from the sensor column amplifier 42 and outputs the amplified signal to the signal processing circuit 8 as a panel output (photosensor signal) V out .
- the sensor column scanning circuit 43 may scan the optical sensor columns one by one as described above, but is not limited thereto, and may be configured to interlace scan the optical sensor columns. Further, the sensor column scanning circuit 43 may be formed as a multi-phase driving scanning circuit such as a four-phase.
- the display device obtains a panel output VOUT corresponding to the amount of light received by the photodiode D1 formed for each pixel in the pixel region 1.
- the panel output VOUT is sent to the signal processing circuit 8, A / D converted, and stored in a memory (not shown) as panel output data. That is, the same number of panel output data as the number of pixels (number of photosensors) in the pixel region 1 is stored in this memory.
- the signal processing circuit 8 performs various signal processing such as image capture and touch area detection using the panel output data stored in the memory.
- the same number of panel output data as the number of pixels (number of photosensors) in the pixel region 1 is accumulated in the memory of the signal processing circuit 8.
- the number of pixels is not necessarily limited due to restrictions such as memory capacity. It is not necessary to store the same number of panel output data.
- the wide portion 111 of the wiring RWS since the wide portion 111 of the wiring RWS also serves as the gate electrode of the capacitor C1, for example, a contact (see FIG. 21 in the third embodiment is more than that in the third embodiment described later).
- the wide portion 111 of the wiring RWS is arranged to shield the storage node INT from the source line COL. Therefore, for example, as in a third embodiment to be described later, there is an advantage that noise interference from the source line COL to the storage node INT can be suppressed as compared with a configuration in which the source line COL is arranged above the storage node INT. is there.
- FIG. 15 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 16 is a waveform diagram of a reset signal and a readout signal supplied to the photosensor according to the present embodiment.
- FIG. 17 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 18 is an enlarged view of a region where the capacitor C1 is formed.
- FIG. 19 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- the optical sensor according to the present embodiment is different from the first embodiment in that the capacitor C1 is an n-channel MOS capacitor.
- the photodiode D1 is connected in the opposite direction to that of the first embodiment. That is, the cathode of the photodiode D1 is connected to the wiring RST, and the anode is connected to the storage node INT.
- the thin film transistor M2 for reading is a p-channel TFT.
- the high level and low level potentials of the reset signal and the read signal are opposite to those of the first embodiment.
- a p-type semiconductor region 102p, an i-type semiconductor region 102i, and an n-type semiconductor region 102n are arranged in series on a base silicon film.
- the n-type semiconductor region 102n (cathode) is connected to the wiring RST through the wiring 108 and the contacts 109 and 110.
- the p-type semiconductor region 102p (anode) is connected to the gate electrode 101 of the thin film transistor M2 through the silicon film extension 107, the contacts 105 and 106, and the wiring 104.
- a capacitor C1 is formed by the wide portion 111 formed in the wiring RWS, the extending portion 107 of the silicon film, and the insulating film (not shown) disposed therebetween. ing. That is, the wide portion 111 having the same potential as the wiring RWS functions as the gate electrode of the capacitor C1.
- the region 112 shown in FIG. 18 is an n + region formed by doping an n-type silicon film with an n-type impurity such as phosphorus. Since the wide portion 111 functions as a mask when doping with n-type impurities, as shown in FIG. 19, the extended portion 107 becomes an n + region, and the silicon film below the wide portion 111 has an n ⁇ region.
- the potential relationship is reversed from that of the first embodiment. Therefore, the potential change of the storage node V INT during the integration period and the readout period is shown in the first embodiment.
- FIG. 9 is upside down. Therefore, also with the optical sensor of this embodiment, the potential difference after the push-up becomes larger than the potential difference of the storage node due to the difference in illuminance on the light receiving surface at the end of the integration period.
- the readout period in the dark state is larger than the potential difference between the potential of the storage node at the end of the storage period in the dark state and the potential of the storage node at the end of the storage period in the case where light of saturation level is incident.
- FIG. 20 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 21 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 22 is an enlarged view of a region where the capacitor C1 is formed.
- FIG. 23 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- the equivalent circuit diagram of the photosensor according to this embodiment is the same as that of the first embodiment. However, as shown in FIGS. 21 to 23, the structure of the capacitor C1 is different.
- the wiring from the gate electrode 101 of the thin film transistor M2 extends to above the n-type semiconductor region 102n of the photodiode D1, and is connected via the contacts 115 and 116. It is connected to the n-type semiconductor region 102n.
- the wiring from the gate electrode 101 of the thin film transistor M2 extends to the upper layer of the capacitor C1 and functions as the gate electrode 121 of the capacitor C1.
- the capacitor C1 is formed by the gate electrode 121, the silicon film 117, and the insulating film (not shown) disposed therebetween.
- the gate electrode 121 is at the same potential (V INT ) as the storage node INT.
- the region 112 shown in FIG. 22 is an n + region formed by doping an n-type silicon film with an n-type impurity such as phosphorus. Since the gate electrode 121 functions as a mask when doping with n-type impurities, the silicon film below the gate electrode 121 forms an n ⁇ region as shown in FIG.
- the optical sensor of the present embodiment is driven by the reset signal and readout signal shown in FIG. 4 in the first embodiment, and the potential change of the storage node V INT during the integration period and the readout period is shown in FIG. As shown in FIG. Therefore, also with the optical sensor of this embodiment, the potential difference after the push-up becomes larger than the potential difference of the storage node due to the difference in illuminance on the light receiving surface at the end of the integration period.
- the readout period in the dark state is larger than the potential difference between the potential of the storage node at the end of the storage period in the dark state and the potential of the storage node at the end of the storage period in the case where light of saturation level is incident.
- FIG. 24 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 25 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 26 is an enlarged view of a region where an amplifying element (p-channel TFT) is formed.
- FIG. 27 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- FIG. 28 is an equivalent circuit diagram of a p-channel TFT as an amplifying element.
- the optical sensor according to the present embodiment uses a p-channel TFT (thin film transistor M4) as an amplifying element instead of the variable capacitor C1 described in the first to third embodiments. It was.
- the drive signal and operation of the photosensor of this embodiment using the thin film transistor M4 as an amplifying element are the same as those described with reference to FIGS. 4 and 9 in the first embodiment. Therefore, the photosensor according to this embodiment can also amplify and read out the potential V INT of the storage node.
- the optical sensor according to the present embodiment also has the first feature in that the wide portion 111 of the wiring RWS extends to a position covering the entire width of the wiring 107. It is different from the embodiment. With this configuration, the optical sensor according to the present embodiment has an advantage that the boundary length is shorter than that of the optical sensor according to the first embodiment.
- the boundary length means the length of the boundary between the amplifying element and the storage node INT.
- the capacitor C ⁇ b> 1 is formed by the overlap of the extending part 107 of the silicon film and the wide part 111 of the wiring RWS. Therefore, in the first embodiment, as shown in FIG. 7, the boundary between the amplifying element and the storage node INT is indicated by the thick line B, and the outer edge of the wide portion 111 of the wiring RWS is the extended portion 107 of the silicon film. It is the part that overlaps. In other words, in the first embodiment, the sum of the length of LCAP shown in FIG.
- the portion where the wide portion 111 of the wiring RWS and the extending portion 107 of the silicon film overlap functions as an amplifying element.
- the width W TFT (that is, the width of the extended portion 107) is twice the boundary length.
- the boundary length is because the width W TFT extending portions 107 of the silicon film, it is possible to shorten the boundary length without increasing the layout area.
- the read signal supplied from the wiring RWS is low level V RWS. L to high level V RWS.
- V RWS low level
- V RWS high level
- V off high level
- the potential V INT of the storage node is constant until the sampling time t S after the read signal of the wiring RWS reaches the threshold voltage V off at the time t 1 .
- the potential V INT of the storage node rises due to the parasitic capacitance between the amplification element and the storage node. to continue.
- the potential of the read signal is high level V RWS. Also from the time t 2 when reaching H to the sampling time t S , the potential V INT of the storage node continues to rise due to the leakage current. As described above, the increase in the potential V INT of the storage node after time t 1 is not preferable because the potential amplification effect is reduced. In order to suppress the rise in the potential V INT due to time t 1 since the parasitic capacitance and leakage current, it is preferable boundary length of the amplifying element is short.
- the optical sensor according to the fourth embodiment can suppress the increase in the potential V INT due to the parasitic capacitance and the leakage current after the time t 1 in that the boundary length of the amplifying element is short. This is more advantageous than the optical sensor according to the embodiment.
- the width of the extending portion 107 of the silicon film is narrowed, and the extending portion 107 is provided with an amplifying element.
- the structure in which a wide portion 107a for securing the width W CAP, while ensuring the effective area of the amplification device it is possible to further shorten the construction of the boundary length W TFT.
- an equivalent circuit diagram of a p-channel TFT as an amplifying element is as shown in FIG.
- the configuration according to this modified example as compared with the structure shown in FIGS. 24 to 28, since the boundary length can be further shortened, the rise in the potential V INT caused by the parasitic capacitance and leakage current after time t 1 Can be further reduced. Thereby, an optical sensor with a wider dynamic range can be realized.
- FIG. 33 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 34 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 35 is an enlarged view of a region where an amplifying element (n-channel TFT) is formed.
- FIG. 36 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- FIG. 37 is an equivalent circuit diagram of an n-channel TFT as an amplifying element.
- the optical sensor of this embodiment uses an n-channel TFT (thin film transistor M4) as an amplifying element instead of the n-channel MOS capacitor described in the second embodiment.
- the driving signal of the photosensor of this embodiment using an n-channel TFT as an amplifying element is the same as that described with reference to FIG. 16 in the second embodiment.
- the drive signal of the embodiment has the high level and low level potentials reversed. According to the drive signal, the photosensor of the present embodiment can amplify and read out the potential V INT of the storage node as described with reference to FIG. 9 in the first embodiment.
- the photodiode D1 is connected in the opposite direction to that of the fourth embodiment. That is, the cathode of the photodiode D1 is connected to the wiring RST and is connected to the n-channel TFT. Further, the thin film transistor M2 for reading is a p-channel TFT.
- the optical sensor according to the present embodiment is different from the second embodiment in that the wide portion 111 of the wiring RWS extends to a position covering the entire width of the wiring 107. Is different.
- the optical sensor according to the present embodiment has the advantage that the boundary length is shorter than that of the optical sensor according to the second embodiment, as described in the fourth embodiment with comparison with the first embodiment. That is, the boundary length of the photosensor according to the second embodiment is L CAP + 2 ⁇ W CAP as shown in FIG. On the other hand, boundary length of the photosensor according to the present embodiment, as shown in FIG. 35, the width W TFT extending portions 107.
- the boundary length is because it is twice the width W TFT extending portions 107 of the silicon film, it is possible to shorten the boundary length without increasing the layout area.
- the optical sensor according to the present embodiment can suppress an increase in the potential V INT caused by the parasitic capacitance and the leakage current after the time t 1 in that the boundary length of the amplifying element is short. It is more advantageous than the optical sensor according to the embodiment.
- the width of the extending portion 107 of the silicon film is reduced, and the extended portion 107 is provided with a wide portion 107a.
- the configuration according to this modified example as shown in FIG.
- the boundary length can be further shortened, the rise in the potential V INT caused by the parasitic capacitance and leakage current after time t 1 Can be further reduced. Thereby, an optical sensor with a wider dynamic range can be realized.
- FIG. 41 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 42 is a plan view illustrating an example of a planar structure of the photosensor according to the present embodiment.
- FIG. 43 is an enlarged view of a region where the amplifying element (photodiode D2) is formed.
- FIG. 44 is a schematic cross-sectional view showing the connection relationship of each region in the photosensor according to the present embodiment.
- FIG. 45 is an equivalent circuit diagram of a photodiode as an amplifying element.
- the optical sensor according to this embodiment is different from the above-described embodiments in that the photodiode D2 is used as an amplifying element.
- the photodiode D2 used here is a photodiode having a gate electrode on a channel.
- the photodiode D2 is provided with a gate electrode over the channel region, so that the readout period is pushed up by the capacitance between the gate and the photodiode.
- the photosensor according to this embodiment includes a photodiode D2 that functions as an amplifying element. As shown in FIGS.
- the cathode (n-type semiconductor region 107n) of the photodiode D2 is connected to the cathode (n-type semiconductor region 102n) of the photodiode D1, and the anode (p-type semiconductor region) of the photodiode D2. 107p) is connected to the storage node INT.
- the potential V INT of the storage node can be amplified and read by the reset signal and the read signal shown in FIG. 4 in the first embodiment. .
- the configuration according to the present embodiment has the following two advantages as compared with the configuration using the p-channel TFT as an amplifying element as in the fourth embodiment.
- the first advantage is that the boundary length is even shorter. That is, in the photosensor according to the present embodiment, as shown in FIG. 43, since the boundary B exists only in the p + region side, boundary length is the width W TFT extending portions 107 of the silicon film. Therefore, in that it is possible to further suppress the rise in the potential V INT due to time t 1 since the parasitic capacitance and leakage currents, it is advantageous than the optical sensor according to a fourth embodiment.
- the second advantage is that the cathode (n-type semiconductor region 102n) of the photodiode D1 and the cathode (n-type semiconductor region 107n) of the photodiode D2 are connected, so that the cathode (n-type semiconductor region 102n) of the photodiode D1. ) In the p-type semiconductor region is easier to connect than in the fourth embodiment.
- FIG. 46 is an equivalent circuit diagram of the photosensor according to the first modification example of the present embodiment.
- FIG. 47 is a plan view showing an example of a planar structure of the photosensor according to the first modification.
- the optical sensor according to the first modification of the present embodiment has a configuration in which a reset thin film transistor M5 is added.
- the anode (p-type semiconductor region 102p) of the photodiode D1 is connected to the wiring VSS for supplying a predetermined DC potential via the wiring 108 and the contacts 109 and 110.
- the gate electrode 131 of the resetting thin film transistor M3 extends from the wiring RST. According to the configuration according to the first modification, as compared with the configuration in which the reset is performed via the photodiode D2 as illustrated in FIGS. 41 and 42, the reset thin film transistor M3 connected to the storage node INT. This has the advantage that the storage node can be reset more reliably.
- FIG. 48 is an equivalent circuit diagram of the photosensor according to the second modification example of the present embodiment.
- FIG. 49 is a plan view showing an example of a planar structure of an optical sensor according to the second modification.
- the anode (p-type semiconductor region 102p) of the photodiode D1 is different from the first modification in that it is connected to the wiring RST that supplies the reset signal. Yes.
- the layout area of the photosensor can be reduced as compared with the first modified example.
- FIG. 50 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 51 is a plan view showing an example of a planar structure of the photosensor according to the present embodiment.
- the light shielding film 113 provided on the back surface of the photodiode D1 is provided.
- the capacitor C SER is formed by extending to a position facing the wiring RWS and using the light shielding film 113, the wiring RWS, and an insulating film (not shown) therebetween. That is, the photosensor according to the present embodiment uses a p-channel TFT (thin film transistor M4) as an amplifying element, as in the fourth embodiment.
- the capacitor CSER functions as a series capacitor for the capacitors Cc and Ca between the light shielding film 113 and the photodiode D1. For this reason, only C INT can be increased without increasing C INT ′ in the equation (6) described in the first embodiment, and the amplification effect at the time of reading can be improved.
- the effect of improving the amplification effect at the time of reading by providing the capacitor CSER in this way uses a p-channel TFT as an amplifying element as in this embodiment, rather than a configuration using a variable capacitor as an amplifying element. Conspicuous in configuration.
- the capacitor CSER when the capacitor CSER is combined with the configuration in which the variable capacitor C1 is used as the amplifying element (the first embodiment), the potential V INT of the storage node at the time of reading is the capacitor C1. Is affected not only by the charge ⁇ Q C from the capacitor C, but also by the charge Q S injected from the capacitor C SER . Therefore, in this configuration, the presence of the capacitor CSER reduces the amplification effect at the time of reading.
- an optical sensor in which a capacitor CSER is combined with a configuration using a p-channel TFT as an amplifying element is effective in obtaining a high amplification effect.
- FIG. 53 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 54 is a plan view showing an example of a planar structure of the photosensor according to the present embodiment.
- a photodiode D1 and a capacitor C3 are respectively formed in parallel over a plurality of pixel regions.
- the capacitor C3 is a normal (not variable) capacitor.
- reading is performed from four photodiodes D1 using one reading thin film transistor M2.
- the number of photodiodes D1 to be read is not limited to this.
- a p-channel TFT (thin film transistor M4) is formed as an amplifying element in the pixel region closest to the reading transistor M2, and a normal (non-variable) capacitor C3 is formed in the other pixel region.
- a normal (non-variable) capacitor C3 is formed in the other pixel region.
- the photocurrent can be increased by connecting a plurality of photodiodes D1 in parallel.
- the amplifying element closest to the reading thin film transistor M2 in the plurality of photodiodes D1
- the potential of the storage node can be amplified and read.
- an optical sensor with high sensitivity can be realized without deteriorating the S / N ratio.
- the boundary length can be shortened as compared with the case where a variable capacitor is used as described above. Thereby, the amplification effect can be further improved.
- FIG. 55 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 56 is a plan view showing an example of a planar structure of the photosensor according to the present embodiment.
- the photodiode D1 and the capacitor C3 are respectively formed in parallel over a plurality of pixel regions.
- the capacitor C3 is a normal (not variable) capacitor.
- reading is performed from four photodiodes D1 by one reading thin film transistor M2.
- the number of photodiodes D1 to be read is not limited to this.
- a photodiode D2 as an amplifying element is provided in the pixel region closest to the thin film transistor M2 for reading, and a normal pixel is provided in the other pixel regions.
- a capacitor C3 (not variable) is formed.
- a reset thin film transistor M5 is formed in a pixel region adjacent to the readout thin film transistor M2.
- the photocurrent can be increased by connecting a plurality of photodiodes D1 in parallel. Further, by arranging the amplifying element (photodiode D2) in the plurality of photodiodes D1 closest to the thin film transistor M2 for reading, the potential of the storage node can be amplified and read. Thereby, an optical sensor with high sensitivity can be realized without deteriorating the S / N ratio. Further, by using the photodiode D2 as the amplifying element, as described above, the boundary length can be shortened as compared with the case where the variable capacitor is used. Thereby, the amplification effect can be further improved.
- FIG. 57 is an equivalent circuit diagram of the photosensor according to the present embodiment.
- FIG. 58 is a plan view showing an example of a planar structure of the photosensor according to the present embodiment.
- the photosensor according to the present embodiment has a configuration in which a reset thin film transistor M5 is added to the photosensor according to the first embodiment.
- a gate electrode 131 of the reset thin film transistor M5 extends from the wiring RST.
- the potential of the storage node can be amplified and read out in the same manner as the photosensor according to the first embodiment. Thereby, an optical sensor with high sensitivity can be realized without deteriorating the S / N ratio.
- the configuration in which the thin film transistor M5 for reset is provided in this way is the second embodiment, the third embodiment, the fourth embodiment, the fifth embodiment, and the seventh embodiment.
- This embodiment can also be applied to the eighth embodiment and the eighth embodiment, and has the same effects as described in the respective embodiments.
- the configuration in which the wirings VDD and OUT connected to the photosensor are shared with the source line COL is exemplified.
- this configuration there is an advantage that the pixel aperture ratio is high.
- the optical sensor wiring VDD and OUT may be provided separately from the source line COL.
- the optical sensor wiring can be driven separately from the source line COL, so that the sensor circuit output data is read regardless of the pixel display timing. There is an advantage that you can.
- transistors M3, M6, and M7 provided in an IC chip may be used instead of the thin film transistors M3, M6, and M7 formed on the active matrix substrate.
- the present invention is industrially applicable as a display device having an optical sensor in a pixel region of an active matrix substrate.
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Abstract
Description
式(1)において、VFはフォトダイオードD1の順方向電圧である。このときのVINTは薄膜トランジスタM2の閾値電圧より低いので、薄膜トランジスタM2はリセット期間において非導通状態となっている。
式(2)において、ΔVRSTは、リセット信号のパルスの高さ(VRST.H-VRST.L)であり、IPHOTOは、フォトダイオードD1の光電流、TINTは、積分期間の長さである。CPDは、フォトダイオードD1の容量である。CTは、コンデンサC2の容量、フォトダイオードD1の容量CPDと、薄膜トランジスタM2の容量CTFTとの総和である。積分期間においても、VINTが薄膜トランジスタM2の閾値電圧より低いので、薄膜トランジスタM2は非導通状態となっている。
+ΔVRWS・CINT/CT …(3)
ΔVRWSは、読み出し信号のパルスの高さ(VRWS.H-VRWS.L)である。これにより、薄膜トランジスタM2のゲートの電位VINTが閾値電圧よりも高くなるので、薄膜トランジスタM2は導通状態となり、各列において配線OUTの端部に設けられているバイアス用の薄膜トランジスタM3と共に、ソースフォロアアンプとして機能する。すなわち、薄膜トランジスタM2からのセンサ出力電圧VPIXは、積分期間におけるフォトダイオードD1の光電流の積分値に比例する。
最初に、図1および図2を参照しながら、本発明の第1の実施形態にかかる液晶表示装置が備えるアクティブマトリクス基板の構成について説明する。
式(4)において、VFはフォトダイオードD1の順方向電圧である。このときのVINTは薄膜トランジスタM2の閾値電圧より低いので、薄膜トランジスタM2はリセット期間において非導通状態となっている。
-IPHOTO・tINT/CT …(5)
式(5)において、ΔVRSTは、リセット信号のパルスの高さ(VRST.H-VRST.L)であり、IPHOTOは、フォトダイオードD1の光電流、tINTは、積分期間の長さである。CPDはフォトダイオードD1の容量である。CTOTALは、光センサ回路全体の容量、すなわち、接続点INTの総容量であり、コンデンサC1の容量CINTと、フォトダイオードD1の容量CPDと、薄膜トランジスタM2の容量CTFTとの総和である。積分期間においても、VINTが薄膜トランジスタM2の閾値電圧より低いので、薄膜トランジスタM2は非導通状態となっている。
以下、本発明の第2の実施形態について説明する。第1の実施形態において説明した構成と同様の機能を有する構成については、第1の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第3の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第4の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第5の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第6の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第7の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第8の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第9の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
以下、本発明の第10の実施形態について説明する。前述の各実施形態において説明した構成と同様の機能を有する構成については、前述の実施形態と同じ参照符号を付記し、その詳細な説明を省略する。
2 ディスプレイゲートドライバ
3 ディスプレイソースドライバ
4 センサカラム(column)ドライバ
41 センサ画素読み出し回路
42 センサカラムアンプ
43 センサカラム走査回路
5 センサロウ(row)ドライバ
6 バッファアンプ
7 FPCコネクタ
8 信号処理回路
9 FPC
100 アクティブマトリクス基板
Claims (14)
- アクティブマトリクス基板の画素領域に光センサを備えた表示装置であって、
前記光センサが、
入射光を受光する光検出素子と、
当該光センサへリセット信号を供給するリセット信号配線と、
当該光センサへ読み出し信号を供給する読み出し信号配線と、
前記リセット信号が供給されてから前記読み出し信号が供給されるまでの間をセンシング期間とし、センシング期間に前記光検出素子で受光された光量にしたがって電位が変化する蓄積ノードと、
前記読み出し信号に応じて、前記蓄積ノードの電位を増幅する増幅素子と、
前記増幅素子で増幅された電位をセンサ回路出力として出力配線へ読み出すためのセンサスイッチング素子とを備えたことを特徴とする表示装置。 - 前記増幅素子が可変コンデンサである、請求項1に記載の表示装置。
- 前記可変コンデンサが、前記読み出し信号配線と、絶縁膜と、シリコン膜に形成されたp型半導体領域とを含むMOSコンデンサである、請求項2に記載の表示装置。
- 前記可変コンデンサが、前記センサスイッチング素子のゲート電極と、絶縁膜と、シリコン膜に形成されたn型半導体領域とを含むMOSコンデンサである、請求項2に記載の表示装置。
- 前記増幅素子がpチャネル薄膜トランジスタである、請求項1に記載の表示装置。
- 前記pチャネル薄膜トランジスタにおいて、前記光検出素子と前記蓄積ノードとを接続するシリコン膜の幅広部にチャネル領域が形成され、前記幅広部にオーバーラップするように当該pチャネル薄膜トランジスタのゲート電極が設けられている、請求項5に記載の表示装置。
- 前記増幅素子がnチャネル薄膜トランジスタである、請求項1に記載の表示装置。
- 前記増幅素子が、チャネル上にゲート電極を備えたダイオードである、請求項1に記載の表示装置。
- 前記光検出素子に対してその受光面とは反対側に設けられた遮光膜と、
前記遮光膜と前記光検出素子との寄生容量に対して直列容量を形成するように、前記遮光膜に対向して設けられた電極とを備え、
前記電極が前記読み出し配線に電気的に接続されている、請求項1~8のいずれか一項に記載の表示装置。 - 前記画素領域に複数の前記光検出素子を備え、
前記複数の光検出素子が並列に接続され、
前記複数の光検出素子の末端の光検出素子に前記増幅素子が接続された、請求項1~9のいずれか一項に記載の表示装置。 - 前記センサスイッチング素子が三端子スイッチング素子であり、
前記三端子のうちのゲート電極が前記蓄積ノードに接続され、
前記三端子のうちの残りの二端子の一方が、前記出力配線へ接続された、請求項1~10のいずれか一項に記載の表示装置。 - 前記センサスイッチング素子のリセット用スイッチング素子をさらに備えた、請求項1~11のいずれか一項に記載の表示装置。
- 前記増幅素子が、前記読み出し信号のローレベル電位とハイレベル電位との間に、当該増幅素子のオン/オフが切り替わる閾値電位を有する、請求項1~12のいずれか一項に記載の表示装置。
- 前記アクティブマトリクス基板に対向する対向基板と、
前記アクティブマトリクス基板と対向基板との間に挟持された液晶とをさらに備えた、請求項1~13のいずれか一項に記載の表示装置。
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EP10748556.7A EP2392964A4 (en) | 2009-03-02 | 2010-01-07 | DISPLAY DEVICE |
US13/254,422 US8772699B2 (en) | 2009-03-02 | 2010-01-07 | Display device having a photosensor |
RU2011139956/28A RU2011139956A (ru) | 2009-03-02 | 2010-01-07 | Устройство отображения |
JP2011502676A JP5421355B2 (ja) | 2009-03-02 | 2010-01-07 | 表示装置 |
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US9106191B2 (en) * | 2012-05-02 | 2015-08-11 | Adaptive I/O Technologies, Inc. | Diode enhanced amplifier circuits and methods thereof |
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CN102341749A (zh) | 2012-02-01 |
EP2392964A1 (en) | 2011-12-07 |
RU2011139956A (ru) | 2013-04-10 |
US8772699B2 (en) | 2014-07-08 |
US20110315860A1 (en) | 2011-12-29 |
JPWO2010100958A1 (ja) | 2012-09-06 |
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