WO2010098026A1 - キャパシタの製造方法、キャパシタ製造装置、キャパシタ製造プログラム及び記録媒体 - Google Patents
キャパシタの製造方法、キャパシタ製造装置、キャパシタ製造プログラム及び記録媒体 Download PDFInfo
- Publication number
- WO2010098026A1 WO2010098026A1 PCT/JP2010/000853 JP2010000853W WO2010098026A1 WO 2010098026 A1 WO2010098026 A1 WO 2010098026A1 JP 2010000853 W JP2010000853 W JP 2010000853W WO 2010098026 A1 WO2010098026 A1 WO 2010098026A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- capacitor
- defect
- capacitor cell
- manufacturing
- forming
- Prior art date
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 250
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000007547 defect Effects 0.000 claims abstract description 109
- 239000010409 thin film Substances 0.000 claims abstract description 41
- 239000010408 film Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000002245 particle Substances 0.000 claims abstract description 15
- 230000002950 deficient Effects 0.000 claims description 51
- 238000001514 detection method Methods 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 18
- 238000003860 storage Methods 0.000 claims description 13
- 230000008859 change Effects 0.000 claims description 12
- 239000003550 marker Substances 0.000 claims description 12
- 230000010365 information processing Effects 0.000 claims description 11
- 235000012431 wafers Nutrition 0.000 description 31
- 230000015572 biosynthetic process Effects 0.000 description 19
- 238000005530 etching Methods 0.000 description 12
- 238000005259 measurement Methods 0.000 description 12
- 238000004458 analytical method Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- 239000010407 anodic oxide Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000008439 repair process Effects 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910003781 PbTiO3 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910010252 TiO3 Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000001552 radio frequency sputter deposition Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G7/00—Capacitors in which the capacitance is varied by non-mechanical means; Processes of their manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/43—Electric condenser making
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/43—Electric condenser making
- Y10T29/435—Solid dielectric type
Definitions
- the present invention relates to a capacitor manufacturing method, a capacitor manufacturing apparatus, a capacitor manufacturing program, and a recording medium for manufacturing a thin film capacitor.
- a mounting board on which a semiconductor element is mounted has a large number of capacitors mounted around an LSI (Large Scale Integration) in order to prevent noise.
- LSI Large Scale Integration
- a voltage drop ⁇ V corresponding to the following equation (1) is generated by the resistance R and the inductance L existing in the wiring between the power supply and the LSI.
- the sign of L is ⁇ (minus) because the induced electromotive force is generated so as to cancel out the instantaneously generated current. Therefore, the voltage drop ⁇ V increases as the R, L, load variation di of the wiring increases and the variation time dt decreases.
- the clock frequency of LSI has become high speed exceeding several hundred MHz. That is, the rise time t r of the pulse waveform in the digital circuit becomes varying time dt equivalent load, since the time t r rise as the clock frequency increases becomes short, the voltage drop ⁇ V increases.
- FIG. 15 shows the structure of the interposer type capacitor described in Patent Document 3.
- a silicon substrate 100 has a first through hole 120a filled with a conductor.
- a lower electrode 140, a high dielectric film 160, and an upper electrode 180 are stacked on the support 110 to form a capacitor.
- the lower electrode 140 of the capacitor is connected to the electrode pad 240a and the bump electrode 280a through a conductor in the through hole 120a.
- the bump electrode 280a is connected to the power line of the circuit board.
- the lower electrode 140 is connected to the power line of the LSI via the electrode pad 210a.
- the upper electrode 180 of the capacitor is connected to the electrode pad 240b and the bump electrode 280b through a conductor in the through hole 120b.
- the bump electrode 280b is connected to the ground line of the circuit board.
- the upper electrode 180 is connected to the ground line of the LSI via the electrode pad 210b.
- the electrode pads 210a, 210b, 240a and 240b are formed on the protective films 200 and 220.
- a method of measuring a resistance change is disclosed as a method of detecting a defect in a semiconductor device wiring or diffusion part (for example, Patent Document 8), and OBIRCH (Optical Beam Induced Resistance Change) or the like is actually used.
- OBIRCH Optical Beam Induced Resistance Change
- OBIRCH has been used for failure analysis of semiconductor devices and finished capacitors, but can also be used to detect a short circuit between the upper electrode and the lower electrode of the capacitor.
- Patent Documents 1 to 8 have a problem that the frequency of occurrence of defects increases when a large-area thin film capacitor is formed.
- a capacitor using an anodic oxide film as a dielectric has a problem that a high capacity cannot be obtained due to a low dielectric constant.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a capacitor manufacturing method, a capacitor manufacturing apparatus, a program, and a recording medium that solve the above-described problems and manufacture a thin film capacitor with a high yield. .
- the method of manufacturing a capacitor according to the present invention includes a film forming step of forming a capacitor by forming a lower electrode, a thin film dielectric, and an upper electrode on a substrate, and a particle portion and the lower portion before dividing the capacitor into capacitor cells.
- a capacitor manufacturing apparatus includes a defect detection unit that detects a defect of a capacitor before being divided into capacitor cells, and a defect removal unit that removes the defect.
- the capacitor includes a substrate, a lower electrode, and a thin film.
- the defect portion includes a particle portion and an electrical short circuit portion between the lower electrode and the upper electrode.
- the program of the present invention includes a process of forming a capacitor by forming a lower electrode, a thin film dielectric, and an upper electrode on a substrate, and a particle portion, a lower electrode, and an upper electrode before dividing the capacitor into capacitor cells.
- a computer is caused to execute processing for detecting a defective portion including an electrical short circuit portion therebetween and processing for removing the defective portion.
- the recording medium of the present invention is a computer-readable recording medium on which the above program is recorded.
- a thin film capacitor can be manufactured with a high yield.
- FIG. 1 shows an example of a method for manufacturing a thin film capacitor according to Embodiment 1 of the present invention.
- the thin film capacitor according to this embodiment includes an upper electrode 1, a thin film dielectric 2, a lower electrode 3, and a substrate 4.
- Pt, Ru, TiN, Au, etc. are suitable for the material of the upper electrode 1, for example. However, it is not limited to these materials.
- the material of the thin film dielectric 2 is preferably a compound containing a perovskite structure having a high dielectric constant, for example.
- a compound containing a perovskite structure a part of Sr in SrTiO3 and SrTiO3 is substituted with Ba (Sr, Ba) TiO3 or PbTiO3 or BaTiO3 as a skeleton and a part of Pb and Ba sites (A sites) are Sr and Ca.
- a composite perovskite compound in which the average valence of the A site is divalent by substituting with La or the like is preferable.
- a composite perovskite compound in which a part of Ti (B site) is substituted with Mg, W, Nb, Zr, Ni, Zn, etc. to make the average valence of the B site tetravalent can also be applied.
- the thin film dielectric 2 is not limited to these materials.
- the manufacturing method of the thin film dielectric 2 is not limited, the sputtering method, the CVD (Chemical Vapor Deposition) method, the sol-gel method, or the like is preferable.
- the material of the lower electrode 3 is preferably a metal or alloy having excellent adhesion to the substrate 4 and less diffusion to the thin film dielectric 2.
- an active metal such as Ti, Cr, Ta, and Mo from the insulating substrate side, Pt
- a high barrier metal such as Ru, TiN, or Au.
- the substrate 4 is preferably a substrate 4 having a high surface smoothness in order to form a thin film capacitor, and a semiconductor substrate such as Si or GaAs or an insulating substrate such as glass, sapphire, ceramics, or resin is suitable.
- a semiconductor substrate such as Si or GaAs
- an insulating substrate such as glass, sapphire, ceramics, or resin
- step (Embodiment 1) In the present embodiment, an example of a method for manufacturing a thin film capacitor will be described with reference to FIG.
- a lower electrode 3, a thin film dielectric 2, and an upper electrode 1 having a MIM (Metal Insulation Metal) structure are formed on a substrate 4.
- step (c) of FIG. 1 it is detected whether there is a defect portion such as the particle portion 5 or an electrical short-circuit portion between the upper electrode 1 and the lower electrode 3 on the entire wafer surface.
- a detection method is not limited, OBIRCH etc. are suitable, for example.
- the particle portion may be detected optically, it is preferable to use resistance change measurement under a laser scan such as OBIRCH in order to detect an electrical short circuit portion.
- resistance measurement as shown in step (b) of FIG. 1, it is necessary to form a portion exposing the lower electrode 3 at the end of the wafer for probing.
- step (d) of FIG. 1 in the wafer state, the defective portion such as the particle portion 5 specified in the step (b) or the electrical short circuit portion between the upper electrode 1 and the lower electrode 3 is removed. Remove locally.
- the removal method is not limited, but mechanical processing such as laser, ion beam, electron beam, wet etching, drill or sandblasting can be used. In particular, laser processing is preferably used.
- FIG. 2 shows an example of a method for manufacturing a thin film capacitor according to the present embodiment.
- step S201 when the MIM is formed, it is first determined whether or not to perform probing (step S201). When probing is performed (step S201 / YES), the wafer edge is processed to expose the lower electrode 3 (step S202). When probing is not performed (step S201 / NO) and after processing the wafer edge in step S202, capacitor defects are detected (step S203). Capacitor defect detection is performed using resistance change measurement under a laser scan such as OBIRCH.
- step S204 it is determined from the detection result in step S203 whether or not the capacitor is defective (step S204). If the capacitor is defective (step S204 / YES), the defective portion is locally removed by etching (step S205). Then, the process proceeds to step S203, and the processes in steps S203 to S205 are repeated until there is no defective portion. On the other hand, when there is no defective part (step S204 / NO), the process proceeds to manufacture of a capacitor cell.
- FIG. 3 shows an example of a method in which the detected defective portions are stored once and the stored defective portions are collectively removed locally.
- step S301 when the MIM is formed, it is first determined whether or not to perform probing (step S301).
- step S301 / YES When probing is performed (step S301 / YES), the wafer edge is processed to expose the lower electrode 3 (step S302).
- step S303 capacitor defect detection is performed (step S303).
- Capacitor defect detection is performed using resistance change measurement under a laser scan such as OBIRCH.
- the defect detection in step S303 is different from the defect detection in step S202 in that defect detection of all capacitors is performed at once and defect part information such as position data of the defect part is stored (step S304).
- step S303 When the defect detection in step S303 is completed, the defect portion is locally removed by etching based on the defect portion information stored in step S304 (step SS305). And it shifts to manufacture of a capacitor cell.
- the defect is locally removed before dividing the capacitor cell into capacitor cells. It can be manufactured.
- FIG. 4 shows an example of defect analysis in a wafer state after MIM film formation of a thin film capacitor according to Embodiment 2 of the present invention.
- 5 and 6 show an example of forming a thin film capacitor cell according to this embodiment.
- FIG. 7 shows an example of a method for manufacturing a thin film capacitor according to this embodiment.
- FIG. 4 shows an example in which an MIM capacitor is formed on the entire surface of the wafer and an electrical short circuit portion 6 between the upper electrode 1 and the lower electrode 3 is detected.
- FIG. 5 shows the capacitor cell position in the case where the mask is aligned with the wafer center of the capacitor shown in FIG.
- the capacitor cell position to be formed is optimized based on the position of the short circuit portion 6, and a mask is formed at the optimized position.
- a capacitor cell is manufactured.
- FIG. 6 shows an example in which a capacitor cell is manufactured by aligning a mask at an optimized position. Unlike the case shown in FIG. 5, when the capacitor cell is manufactured by aligning the mask with the position optimized using the formed alignment mark 12, the short-circuit portion 6 does not exist in the modified capacitor cell formation position 11.
- the short circuit portion 6 does not exist in the capacitor cell formation position 11 (capacitor cell) located inside the capacitor chip outer peripheral position 10 after the mask position optimization has been described.
- the short circuit portion exists. Even in this case, the short-circuit portion in the capacitor cell can be reduced (minimized), and the yield of the capacitor can be improved.
- it is effective to form the alignment mark 12 in order to align the mask with the optimized position.
- step S701 it is first determined whether or not to perform probing.
- step S701 / YES the wafer end is processed to expose the lower electrode 3 (step S702).
- step S703 the defect detection of the capacitor is performed (step S703), and the defect part information such as the position data of the detected defect part is stored.
- Step S704 the defect detection of the capacitor in step S703 is performed by using resistance change measurement under a laser scan such as OBIRCH.
- step S703 When the defect detection in step S703 is completed, the position of the capacitor cell in the wafer is optimized so that there is no defect in the capacitor cell based on the defect information stored in step S704 (step S705). . And it shifts to manufacture of a capacitor cell.
- a defect-free capacitor can be formed by identifying a defective portion after MIM film formation on a wafer and optimizing a capacitor cell position that is a position for forming a capacitor cell. That is, the yield of thin film capacitor manufacturing can be improved.
- FIG. 8 shows Embodiment 3 of the present invention.
- FIG. 8 shows an example in which a short-circuit portion exists in the capacitor cell even after the capacitor cell position is optimized and the mask position is optimized as in the second embodiment.
- FIG. 9 shows a capacitor manufacturing method in the case of FIG. With reference to FIG. 8 and FIG. 9, an example of a method for manufacturing a capacitor in the case where a defective portion exists in the capacitor cell formation position even when the mask position is optimized will be described.
- step S901 it is first determined whether or not to perform probing (step S901).
- step S901 / YES the wafer edge is processed to expose the lower electrode 3 (step S902).
- step S903 the defect detection of the capacitor is performed (step S903), and the defect information such as the position data of the detected defect is stored.
- Step S904 the defect detection of the capacitor in step S903 is performed by using resistance change measurement under a laser scan such as OBIRCH.
- step S903 When the defect detection in step S903 is completed, based on the defect part information stored in step S904, the defect in the capacitor cell is minimized so that the number of defect parts is minimized.
- the capacitor cell position is optimized (step S905).
- step S906 it is determined whether or not a defective portion exists in the capacitor cell formation position. If there is a defect in the capacitor cell (step S906 / YES), the defective part is locally removed by etching (step S907). FIG. 8 shows the defect 13 thus removed by etching. Thereafter, the process proceeds to manufacture of a capacitor cell. On the other hand, when there is no defect (step S906 / NO), the process proceeds to the manufacture of a capacitor cell, as in the second embodiment. Thus, if the partial removal of the short-circuit portion shown in FIG. 1 is performed only on the portion corresponding to the inside of the capacitor cell, the defective capacitor cell can be eliminated.
- the defect portion is identified after the MIM film is formed on the wafer, the capacitor cell position is optimized, and only the defect portion existing in the capacitor cell after the capacitor cell position optimization is removed, Capacitors free from defects can be easily formed. That is, the yield of thin film capacitor manufacturing can be improved.
- the capacitor manufacturing apparatus 20 includes a defect detection unit 21 and an etching unit 22.
- the defective part detection part 21 detects defective parts, such as a short circuit and a particle.
- the etching unit 22 is a defect removal unit that locally etches and removes a defect when the defect detection unit 21 detects the defect.
- the capacitor manufacturing apparatus 20 according to the present embodiment is an apparatus in which the defect detection unit and the defect part removal unit are incorporated.
- the capacitor manufacturing apparatus 20 shown in FIG. 11 includes a defect part information storage unit 23 and an information processing unit 24 in addition to the configuration of the capacitor manufacturing apparatus 20 shown in FIG.
- the defect part information storage part 23 stores information such as position data of the defect part detected by the defect part detection part 21.
- the information processing unit 24 performs the optimization process of the capacitor formation position based on the information on the defective part stored in the defective part information storage unit 23.
- information on the defective part detected by the defective part detection unit 21 is temporarily stored in the defective part information storage unit 23, and a capacitor cell is formed by the information processing unit 24 based on the stored information. Optimize position.
- the capacitor manufacturing apparatus 20 optimizes the capacitor formation position, and even if the mask position is optimized, if the defect portion exists in the capacitor cell formation position, the etching portion 22 localizes the defect portion. Etch away.
- the defect detection unit 21 is not limited, and optical inspection or the like can be applied. However, it is preferable to specify a defect location such as a short circuit by resistance change measurement by OBIRCH analysis.
- the etching part 22 is not limited, laser processing is suitable. Although these devices can be used to detect and remove the defective portion after the capacitor cell is formed, it is preferable to repair the defective portion in the wafer state because the process time can be shortened.
- the present embodiment it is possible to manufacture a capacitor having no defective portion in a short manufacturing time. Further, it becomes possible to locally remove the defective portion of the thin film capacitor after the MIM film is formed in the wafer state, and it is possible to improve the yield even in the case of a large area capacitor.
- the capacitor manufacturing apparatus 20 includes a defective part detection unit 21, a defective part information storage unit 23, an information processing unit 24, and a marker unit 25.
- the marker part 25 forms an alignment mark.
- the capacitor manufacturing apparatus 20 shown in FIG. 13 includes an etching unit 22 in addition to the configuration of the capacitor manufacturing apparatus 20 shown in FIG. Therefore, if there is a defective portion in the capacitor cell even after the capacitor cell position is optimized, the defective portion can be removed. Thereby, the yield of the capacitor cell can be further improved as compared with the capacitor manufacturing apparatus shown in FIG.
- the defect detection unit 21 is not limited, and an optical inspection or the like can be applied. However, it is preferable to specify a defect location such as a short circuit by resistance change measurement by OBIRCH analysis.
- the formation of the alignment mark by the marker unit 25 is not limited, but laser processing is preferably used.
- the etching part 22 is not limited, laser processing is suitable.
- the capacitor cell position is automatically optimized based on the defect portion identification of the thin film capacitor after the MIM film is formed in the wafer state, and the alignment mark is formed. It is possible to improve the yield. Further, based on the defect portion identification of the thin film capacitor after MIM film formation in the wafer state, the capacitor cell position can be automatically optimized, the alignment mark can be formed, and the defect portion in the capacitor cell can be locally removed. Capacitor defects can be almost eliminated. This makes it possible to improve the yield of large-area capacitors even on wafers including defective portions such as particle portions or electrical short-circuit portions between the upper electrode and the lower electrode.
- a 4-inch silicon wafer on which a thermal oxide film having a thickness of 200 nm was formed as the substrate 4 was used, and the lower electrode 3 was obtained by depositing Ti and Ru in this order from the wafer side by DC magnetron sputtering at room temperature.
- the film thicknesses of Ti and Ru were 50 nm and 100 nm, respectively.
- SrTiO 3 (STO) added with 5% Mn as a thin film dielectric 2 was formed to a thickness of 100 nm at 400 ° C. by RF sputtering.
- Ru was formed into a film with a thickness of 100 nm at room temperature by DC magnetron sputtering.
- the room temperature indicates a room temperature in a state where the apparatus or the like is not driven.
- the upper electrode 1 and the thin film dielectric 2 were etched to a probing terminal at a size of 1 mm 2 at the edge of the wafer. Further, the OBIRCH analysis is performed by probing between the lower electrode 3 and the upper electrode 1 on the entire surface of the wafer to identify a short-circuited portion between the lower electrode 3 and the upper electrode 1, and the identified short-circuited portion is locally detected by a laser. Removed. Although it is considered that particles were present in the short-circuit portion, only the removal of the upper electrode 1 and the thin film dielectric 2 and the damage to the lower electrode were observed after the laser processing. There were 18 laser-processed locations. After the laser processing, the resistance measurement between the lower electrode and the upper electrode was performed again, and it was confirmed that there was no short circuit across the entire wafer surface.
- the capacitor manufacturing apparatus 20 includes a defect information storage unit 23, an information processing unit 24, an infrared scanning unit 26, a current measurement unit 27, a processing laser unit 28, a laser marker unit 29, and a control unit 30. .
- the capacitor manufacturing apparatus 20 uses OBIRCH as the defect detection unit 21 of the capacitor device described with reference to FIG.
- the same MIM as in the above example was formed on a 4-inch wafer, and alignment optimization and defect repair were performed using the apparatus shown in FIG. As a result, there were 15 short-circuited locations detected by OBIRCH, and 2 locations where laser processing was performed for repair after optimization of the capacitor cell position, and alignment marks were formed by the laser marker after optimization of the capacitor cell position.
- the capacitor manufacturing apparatus 20 includes an infrared scanning unit 26 and a current measuring unit 27 as the defect detection unit 21, a processing laser unit 28 as the etching unit 22, and a laser marker unit 29 as the marker unit 25. Further, an example in which the control unit 30 manufactures a capacitor cell by controlling the defect information storage unit 23, the information processing unit 24, the infrared scanning unit 26, the current measurement unit 27, the processing laser unit 28, and the laser marker unit 29. Although shown, it is not limited to this.
- processing shown in the flowcharts of each figure can be executed by the CPU by a program.
- a computer-readable recording medium for recording the program a semiconductor storage unit, an optical and / or magnetic storage unit, or the like can be used.
- the present invention is not limited to the above-described capacitor manufacturing method, capacitor manufacturing apparatus, program, and recording medium, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.
- the present invention can be applied to manufacture of a capacitor using a thin film capacitor, and a thin film capacitor can be manufactured with a high yield.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
図15において、シリコン基板100は内部に導電体が充填された第1のスルーホール120aを有する。基板100を支持体110として、支持体110上には下部電極140と高誘電体膜160と上部電極180とが積層されてキャパシタを形成する。キャパシタの下部電極140はスルーホール120a内の導電体を介して電極パッド240aおよびバンプ電極280aに接続される。バンプ電極280aは回路基板の電源ラインに接続される。また、下部電極140は電極パッド210aを介してLSIの電源ラインに接続される。キャパシタの上部電極180はスルーホール120b内の導電体を介して電極パッド240bおよびバンプ電極280bに接続される。バンプ電極280bは回路基板のグランドラインに接続される。また、上部電極180は電極パッド210bを介してLSIのグランドラインに接続される。電極パッド210a、210b,240aおよび240bは保護膜200および220上に形成される。
図1は、本発明の実施形態1に係る薄膜キャパシタの製造方法例を示す。図示するように、本実施形態に係る薄膜キャパシタは、上部電極1、薄膜誘電体2、下部電極3、および基板4を有している。上部電極1の材質は、例えば、Pt、Ru、TiN、Au等が好適である。しかしながら、これらの材質に限定されるものではない。
本実施形態では、薄膜キャパシタの製造方法例について、図1を用いて説明する。初めに、図1の工程(a)に示すように、基板4にMIM(Metal Insulation Metal)構造となる下部電極3、薄膜誘電体2、上部電極1を成膜する。次に、図1の工程(c)に示すように、ウエハ全面において、パーティクル部5、又は上部電極1と下部電極3間の電気的短絡部等の欠陥部が存在するかを検出する。検出方法は限定されないが、例えば、OBIRCH等が好適である。光学的にパーティクル部を検出しても良いが、電気的短絡部を検出するにはOBIRCH等のレーザスキャン下での抵抗変化測定を利用するのが好ましい。抵抗測定では、図1の工程(b)に示すように、プロービングするためにウエハの端部において下部電極3を露出する部分を形成する必要がある。
図4は、本発明の実施形態2に係る薄膜キャパシタのMIM成膜後のウエハ状態における欠陥部分析例を示す。図5及び図6は、本実施形態に係る薄膜キャパシタセルの形成例を示す。
図7は、本実施形態に係る薄膜キャパシタの製造方法例を示す。次に、薄膜薄膜キャパシタの製造方法例について、図4~図7を用いて説明する。
そこで、本実施形態に係る薄膜キャパシタの製造方法では、図4に示す短絡部6を検出した後、短絡部6の位置に基づいて形成するキャパシタセル位置を最適化し、最適化した位置にマスクを合わせてキャパシタセルを製造する。
図6は、最適化した位置にマスクを合わせてキャパシタセルを製造した例を示す。図5に示す場合とは異なり、形成したアライメントマーク12を用いて最適化した位置にマスクを合わせてキャパシタセルを製造した場合、短絡部6は修正したキャパシタセル形成位置11内に存在しない。この例ではマスク位置最適化後にキャパシタチップ外周位置10の内部に位置するキャパシタセル形成位置11(キャパシタセル)内に短絡部6が存在しない場合を挙げて説明したが、短絡部が存在してしまう場合においても、キャパシタセル内の短絡部を減少(最小化)することができ、キャパシタの歩留を向上することができる。また、上述したキャパシタの製造方法において、マスクを最適化後の位置に合わせるためにアライメントマーク12を形成することが有効である。
図8は、本発明の実施形態3を示す。この図8は、上記実施形態2と同様にキャパシタセル位置を最適化し、マスク位置を最適化した後にも、キャパシタセル内に短絡部が存在する例を示す。図9は、図8の場合におけるキャパシタ製造方法を示す。図8及び図9を参照して、マスク位置を最適化した場合にもキャパシタセル形成位置内に欠陥部が存在する場合のキャパシタの製造方法例について説明する。
次に、本発明の実施形態4に係るキャパシタ製造装置について説明する。図10及び図11は、本実施形態に係るキャパシタ製造装置の概略構成例を示す。図10に示すように、本実施形態に係るキャパシタ製造装置20は、欠陥部検出部21、エッチング部22、を備えている。欠陥部検出部21は、短絡やパーティクル等の欠陥部を検出する。エッチング部22は、欠陥部検出部21が欠陥部を検出すると、その欠陥部を局所的にエッチングして除去する欠陥部除去部である。このように、本実施形態に係るキャパシタ製造装置20は、欠陥検出部と欠陥部除去部とを組み込んだ装置である。
図12及び図13は、本発明の実施形態5に係るキャパシタ製造装置の概略構成例を示す。図12に示すように、本実施形態に係るキャパシタ製造装置20は、欠陥部検出部21、欠陥部情報記憶部23、情報処理部24、マーカ部25、を備えている。マーカ部25は、アライメントマークを形成する。このキャパシタ製造装置を使用することにより、ウエハ状態において予めキャパシタセルを形成した後に不良となる部分を特定し、形成するキャパシタセルの位置を最適化することにより、キャパシタの歩留を向上することができる。
2 薄膜誘電体
3 下部電極
4 基板
6 短絡部
7 キャパシタチップ外周
8 キャパシタ形成予定位置
9 アライメントマーク形成予定位置
10 キャパシタチップ外周
11 キャパシタ形成位置
12 アライメントマーク
13 欠陥
14 MIM成膜ウエハ
20 欠陥部検出装置
21 欠陥部検出部
22 エッチング部
23 欠陥部情報記憶部
24 情報処理部
25 マーカ部
26 赤外線走査部
27 電流計測部
28 加工レーザ部
29 レーザマーカ部
30 制御部
100 基板
110 支持体
120a、120b スルーホール
140 下部電極
160 高誘電体膜
180 上部電極
200 保護膜
220 保護膜
210a、210b 電極パッド
240a、240b 電極パッド
280a、280b バンプ電極
Claims (25)
- 基板に下部電極と薄膜誘電体と上部電極とを成膜してキャパシタを形成する成膜工程と、
前記キャパシタをキャパシタセルに分割する前に、パーティクル部と前記下部電極及び前記上部電極間の電気的短絡部とを含む欠陥部を検出する欠陥部検出工程と、
前記欠陥部を除去する欠陥部除去工程と、
を有するキャパシタの製造方法。 - 前記欠陥検出工程により検出された欠陥部の情報を記憶する欠陥部情報記憶工程をさらに有する請求項1記載のキャパシタの製造方法。
- 前記キャパシタセルを形成する位置であるキャパシタセル位置を調整するキャパシタセル位置調整工程をさらに有する請求項1又は2に記載のキャパシタの製造方法。
- 前記キャパシタセル位置調整工程により調整されたキャパシタセル位置にキャパシタセルを形成するためのマークを形成するマーク形成工程をさらに有する請求項3記載のキャパシタの製造方法。
- 前記マーク形成工程は、レーザ加工を用いてマークを形成する請求項4記載のキャパシタの製造方法。
- 前記欠陥部除去工程は、前記キャパシタセル位置を調整した後のキャパシタセル内の前記欠陥部を除去する請求項3から5の何れか1項に記載のキャパシタの製造方法。
- 前記キャパシタセル位置調整工程は、前記キャパシタセルに含まれる前記欠陥部が最小となるように、前記キャパシタセル位置を調整する請求項3から6の何れか1項に記載のキャパシタの製造方法。
- 前記欠陥部除去工程は、レーザ加工を用いて前記欠陥部を除去する請求項1から7の何れか1項に記載のキャパシタの製造方法。
- 前記欠陥部検出工程は、前記基板全面をレーザ走査し、前記下部電極及び前記上部電極間の抵抗変化測定により欠陥部を検出する請求項1から8の何れか1項に記載のキャパシタの製造方法。
- キャパシタセルへの分割前のキャパシタの欠陥部を検出する欠陥部検出部と、
前記欠陥部を除去する欠陥部除去部とを有し、
前記キャパシタは、基板上に積層された下部電極と薄膜誘電体と上部電極とによって形成され、
前記欠陥部は、パーティクル部と前記下部電極及び前記上部電極間の電気的短絡部とを含むキャパシタ製造装置。 - 前記欠陥部検出部により検出された欠陥部の情報を記憶する欠陥部情報記憶部をさらに有し、
前記欠陥部除去部は、前記欠陥部情報記憶部に記憶された欠陥部の情報に基づいて欠陥部を除去する請求項10記載のキャパシタ製造装置。 - 前記キャパシタセルを形成する位置であるキャパシタセル位置を調整する情報処理部をさらに有する請求項10又は11に記載のキャパシタ製造装置。
- 前記情報処理部により調整されたキャパシタセル位置にキャパシタセルを形成するためのマークを形成するマーカ部をさらに有する請求項12記載のキャパシタ製造装置。
- 前記マーカ部は、レーザ加工である請求項13記載のキャパシタ製造装置。
- 前記欠陥部除去部は、前記情報処理部によりキャパシタセル位置を調整した場合に、前記キャパシタセル内に存在する前記欠陥部を除去する請求項12から14の何れか1項に記載のキャパシタ製造装置。
- 前記情報処理部は、前記キャパシタセルに含まれる前記欠陥部が最小となるように、前記キャパシタセル位置を調整する請求項12から15の何れか1項に記載のキャパシタ製造装置。
- 前記欠陥部除去部は、レーザ加工である請求項10から16の何れか1項に記載のキャパシタ製造装置。
- 前記欠陥部検出部は、前記基板全面をレーザ走査し、前記下部電極及び前記上部電極間の抵抗変化測定により欠陥部を検出する請求項10から17の何れか1項に記載のキャパシタ製造装置。
- 基板に下部電極と薄膜誘電体と上部電極とを成膜してキャパシタを形成する処理と、
前記キャパシタをキャパシタセルに分割する前に、パーティクル部と前記下部電極及び前記上部電極間の電気的短絡部とを含む欠陥部を検出する処理と、
前記欠陥部を除去する処理と、
をコンピュータに実行させるプログラム。 - 検出された前記欠陥部の情報を記憶する処理をコンピュータに実行させる請求項19記載のプログラム。
- 前記キャパシタセルを形成する位置であるキャパシタセル位置を調整する処理をコンピュータに実行させる請求項19又は20に記載のプログラム。
- 調整された前記キャパシタセル位置にキャパシタセルを形成するためのマークを形成する処理をコンピュータに実行させる請求項21記載のプログラム。
- 前記除去する処理は、前記キャパシタセル位置を調整した後のキャパシタセル内の前記欠陥部を除去するようにコンピュータに実行させる請求項21又は22に記載のプログラム。
- 前記調整する処理は、前記キャパシタセルに含まれる前記欠陥部を最小とするように、前記キャパシタセル位置を調整することをコンピュータに実行させる請求項21から23の何れか1項に記載のプログラム。
- 請求項19から24の何れか1項に記載のプログラムを記録したコンピュータ読み取り可能な記録媒体。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011501474A JP5348238B2 (ja) | 2009-02-25 | 2010-02-12 | キャパシタの製造方法、キャパシタ製造装置、キャパシタ製造プログラム及び記録媒体 |
CN201080008852.5A CN102326248B (zh) | 2009-02-25 | 2010-02-12 | 电容器制造方法、电容器制造装置 |
US13/203,018 US8621730B2 (en) | 2009-02-25 | 2010-02-12 | Capacitor producing method for producing thin-film capacitors eliminating defects |
EP10745913A EP2402987A1 (en) | 2009-02-25 | 2010-02-12 | Capacitor fabrication method, capacitor fabricating device, capacitor fabricating program, and recording medium |
US14/081,163 US20140068905A1 (en) | 2009-02-25 | 2013-11-15 | Capacitor producing method, capacitor producing device, and capacitor producing program |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009042210 | 2009-02-25 | ||
JP2009-042210 | 2009-02-25 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/203,018 A-371-Of-International US8621730B2 (en) | 2009-02-25 | 2010-02-12 | Capacitor producing method for producing thin-film capacitors eliminating defects |
US14/081,163 Division US20140068905A1 (en) | 2009-02-25 | 2013-11-15 | Capacitor producing method, capacitor producing device, and capacitor producing program |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010098026A1 true WO2010098026A1 (ja) | 2010-09-02 |
Family
ID=42665243
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/000853 WO2010098026A1 (ja) | 2009-02-25 | 2010-02-12 | キャパシタの製造方法、キャパシタ製造装置、キャパシタ製造プログラム及び記録媒体 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8621730B2 (ja) |
EP (1) | EP2402987A1 (ja) |
JP (1) | JP5348238B2 (ja) |
CN (1) | CN102326248B (ja) |
WO (1) | WO2010098026A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013004853A (ja) * | 2011-06-20 | 2013-01-07 | Mitsubishi Shindoh Co Ltd | フィルムコンデンサ用金属蒸着フィルムの製造方法 |
JP2020088093A (ja) * | 2018-11-21 | 2020-06-04 | 三菱電機株式会社 | 半導体チップの製造方法および半導体ウェハ |
CN117066793A (zh) * | 2023-09-18 | 2023-11-17 | 扬州日精电子有限公司 | 一种可翻转调节的薄膜电容器生产用焊接装置及其使用方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20130046847A (ko) * | 2011-10-28 | 2013-05-08 | 삼성디스플레이 주식회사 | 표시기판 및 표시기판의 수리 방법 |
JP6158468B2 (ja) * | 2011-11-08 | 2017-07-05 | 富士電機株式会社 | 半導体装置の故障位置解析方法及び装置 |
CN105321836B (zh) * | 2015-10-19 | 2018-06-26 | 上海华力微电子有限公司 | Mim电容器的测试结构和测试方法 |
EP3217428B1 (de) * | 2016-03-07 | 2022-09-07 | Infineon Technologies AG | Mehrfachsubstrat sowie verfahren zu dessen herstellung |
KR20180079157A (ko) * | 2016-12-29 | 2018-07-10 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
CN116030047B (zh) * | 2023-03-24 | 2023-05-30 | 四川中星电子有限责任公司 | 一种电容器工艺过程中识别掩膜合格的方法 |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10200071A (ja) * | 1997-01-09 | 1998-07-31 | Fujitsu Ltd | 半導体装置及び欠陥検出方法 |
JPH11154734A (ja) * | 1997-11-21 | 1999-06-08 | Advantest Corp | 薄膜コンデンサの形成方法 |
JP2001033886A (ja) | 1999-05-17 | 2001-02-09 | Noritsu Koki Co Ltd | フィルム供給装置 |
JP2002008942A (ja) | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | コンデンサ装置、コンデンサ装置の製造方法及びコンデンサ装置が実装されたモジュール |
JP2003060041A (ja) * | 2001-08-08 | 2003-02-28 | Murata Mfg Co Ltd | Mimキャパシタの製造方法 |
JP2003069185A (ja) | 2001-08-29 | 2003-03-07 | Hitachi Ltd | キャパシタを内蔵した回路基板 |
JP3465464B2 (ja) | 1996-02-06 | 2003-11-10 | 富士通株式会社 | 半導体チップキャリヤ |
JP2005033195A (ja) | 2003-06-20 | 2005-02-03 | Ngk Spark Plug Co Ltd | コンデンサ及びコンデンサの製造方法 |
JP2005123250A (ja) | 2003-10-14 | 2005-05-12 | Fujitsu Ltd | インターポーザ及びその製造方法並びに電子装置 |
JP2006253631A (ja) | 2005-02-14 | 2006-09-21 | Fujitsu Ltd | 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法 |
JP2007206444A (ja) * | 2006-02-02 | 2007-08-16 | Sony Corp | 欠陥修正手法の表示方法 |
JP2007281376A (ja) * | 2006-04-11 | 2007-10-25 | Sony Corp | 配線基板の製造方法、ディスプレイ装置の製造方法、及び配線基板の製造装置 |
JP2008041757A (ja) | 2006-08-02 | 2008-02-21 | Nec Electronics Corp | 半導体検査装置および半導体検査方法 |
JP2008164881A (ja) * | 2006-12-28 | 2008-07-17 | Hitachi Displays Ltd | 表示装置およびその製造方法 |
JP2009042210A (ja) | 2007-07-13 | 2009-02-26 | Fujifilm Corp | 表面プラズモン共鳴測定用チップ |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3402448A (en) * | 1966-05-04 | 1968-09-24 | Bunker Ramo | Thin film capacitor and method of adjusting the capacitance thereof |
US3649488A (en) * | 1969-11-07 | 1972-03-14 | Bell Telephone Labor Inc | Electrochemical etching technique for charting and curing defects in thin film capacitors |
US4749454A (en) * | 1986-11-17 | 1988-06-07 | Solarex Corporation | Method of removing electrical shorts and shunts from a thin-film semiconductor device |
DE69133410T2 (de) * | 1990-03-08 | 2005-09-08 | Fujitsu Ltd., Kawasaki | Schichtstruktur mit einem Kontaktloch für Flossenkondensatoren in Drams und Verfahren zur Herstellung derselben |
US5817533A (en) * | 1996-07-29 | 1998-10-06 | Fujitsu Limited | High-yield methods of fabricating large substrate capacitors |
JP2001338836A (ja) | 2000-03-24 | 2001-12-07 | Sumitomo Metal Ind Ltd | コンデンサ付き接続部材、その接続構造と製造方法 |
US6344964B1 (en) * | 2000-07-14 | 2002-02-05 | International Business Machines Corporation | Capacitor having sidewall spacer protecting the dielectric layer |
US9064785B2 (en) | 2007-07-20 | 2015-06-23 | Freesacle Semiconductor, Inc. | Electronic device including a capacitor and a process of forming the same |
-
2010
- 2010-02-12 US US13/203,018 patent/US8621730B2/en not_active Expired - Fee Related
- 2010-02-12 EP EP10745913A patent/EP2402987A1/en not_active Withdrawn
- 2010-02-12 CN CN201080008852.5A patent/CN102326248B/zh not_active Expired - Fee Related
- 2010-02-12 WO PCT/JP2010/000853 patent/WO2010098026A1/ja active Application Filing
- 2010-02-12 JP JP2011501474A patent/JP5348238B2/ja not_active Expired - Fee Related
-
2013
- 2013-11-15 US US14/081,163 patent/US20140068905A1/en not_active Abandoned
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3465464B2 (ja) | 1996-02-06 | 2003-11-10 | 富士通株式会社 | 半導体チップキャリヤ |
JPH10200071A (ja) * | 1997-01-09 | 1998-07-31 | Fujitsu Ltd | 半導体装置及び欠陥検出方法 |
JPH11154734A (ja) * | 1997-11-21 | 1999-06-08 | Advantest Corp | 薄膜コンデンサの形成方法 |
JP2001033886A (ja) | 1999-05-17 | 2001-02-09 | Noritsu Koki Co Ltd | フィルム供給装置 |
JP2002008942A (ja) | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | コンデンサ装置、コンデンサ装置の製造方法及びコンデンサ装置が実装されたモジュール |
JP2003060041A (ja) * | 2001-08-08 | 2003-02-28 | Murata Mfg Co Ltd | Mimキャパシタの製造方法 |
JP2003069185A (ja) | 2001-08-29 | 2003-03-07 | Hitachi Ltd | キャパシタを内蔵した回路基板 |
JP2005033195A (ja) | 2003-06-20 | 2005-02-03 | Ngk Spark Plug Co Ltd | コンデンサ及びコンデンサの製造方法 |
JP2005123250A (ja) | 2003-10-14 | 2005-05-12 | Fujitsu Ltd | インターポーザ及びその製造方法並びに電子装置 |
JP2006253631A (ja) | 2005-02-14 | 2006-09-21 | Fujitsu Ltd | 半導体装置及びその製造方法、キャパシタ構造体及びその製造方法 |
JP2007206444A (ja) * | 2006-02-02 | 2007-08-16 | Sony Corp | 欠陥修正手法の表示方法 |
JP2007281376A (ja) * | 2006-04-11 | 2007-10-25 | Sony Corp | 配線基板の製造方法、ディスプレイ装置の製造方法、及び配線基板の製造装置 |
JP2008041757A (ja) | 2006-08-02 | 2008-02-21 | Nec Electronics Corp | 半導体検査装置および半導体検査方法 |
JP2008164881A (ja) * | 2006-12-28 | 2008-07-17 | Hitachi Displays Ltd | 表示装置およびその製造方法 |
JP2009042210A (ja) | 2007-07-13 | 2009-02-26 | Fujifilm Corp | 表面プラズモン共鳴測定用チップ |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013004853A (ja) * | 2011-06-20 | 2013-01-07 | Mitsubishi Shindoh Co Ltd | フィルムコンデンサ用金属蒸着フィルムの製造方法 |
JP2020088093A (ja) * | 2018-11-21 | 2020-06-04 | 三菱電機株式会社 | 半導体チップの製造方法および半導体ウェハ |
JP7209513B2 (ja) | 2018-11-21 | 2023-01-20 | 三菱電機株式会社 | 半導体チップの製造方法および半導体ウェハ |
CN117066793A (zh) * | 2023-09-18 | 2023-11-17 | 扬州日精电子有限公司 | 一种可翻转调节的薄膜电容器生产用焊接装置及其使用方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5348238B2 (ja) | 2013-11-20 |
EP2402987A1 (en) | 2012-01-04 |
CN102326248A (zh) | 2012-01-18 |
US20140068905A1 (en) | 2014-03-13 |
JPWO2010098026A1 (ja) | 2012-08-30 |
US20110302753A1 (en) | 2011-12-15 |
CN102326248B (zh) | 2014-06-25 |
US8621730B2 (en) | 2014-01-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5348238B2 (ja) | キャパシタの製造方法、キャパシタ製造装置、キャパシタ製造プログラム及び記録媒体 | |
US7981761B2 (en) | Method of manufacturing semiconductor device having MIM capacitor | |
US20060228855A1 (en) | Capacitor with co-planar electrodes | |
CN105321953B (zh) | 用于压电层布置的制造方法和相应的压电层布置 | |
JP2007149730A (ja) | 薄膜キャパシタ、実装基板、実装基板の製造方法、半導体装置、および半導体装置の製造方法 | |
US9257497B2 (en) | Metal-insulator-metal (MIM) capacitor techniques | |
JP2017204630A (ja) | 薄膜キャパシター及びその製造方法 | |
JP5263528B2 (ja) | キャパシタ構造体及びその製造方法 | |
US20140017872A1 (en) | Method for fabricating a metal-insulator-metal capacitor | |
JP6446877B2 (ja) | 薄膜キャパシタ | |
US20070293014A1 (en) | Method for forming metal-insulator-metal capacitor of semiconductor device | |
JP2005086091A (ja) | 半導体装置 | |
CN107045917B (zh) | 电子部件 | |
US6693017B1 (en) | MIMcap top plate pull-back | |
CN102110638A (zh) | 解决半导体器件在制作过程中放电缺陷的方法及结构 | |
JP2008085291A (ja) | コンデンサ及び高周波部品 | |
JP4973023B2 (ja) | 薄膜キャパシタ及びその製造方法 | |
JP5016210B2 (ja) | 圧電薄膜積層トランス及びその製造方法 | |
JP2008251889A (ja) | キャパシタの製造方法 | |
CN108122894B (zh) | 改善mim电容器电弧放电缺陷的方法 | |
US9590027B2 (en) | Method for fabricating an integrated-passives device with a MIM capacitor and a high-accuracy resistor on top | |
US20210335992A1 (en) | Capacitor with mim | |
US7105451B2 (en) | Method for manufacturing semiconductor device | |
JP5686366B2 (ja) | 誘電体構造体、及びその製造方法 | |
Thomason et al. | High capacitance density thin film integrated tantalum pentoxide decoupling capacitors |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201080008852.5 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10745913 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011501474 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13203018 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2010745913 Country of ref document: EP |