WO2010095295A1 - 抵抗記憶素子およびその使用方法 - Google Patents
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- WO2010095295A1 WO2010095295A1 PCT/JP2009/065633 JP2009065633W WO2010095295A1 WO 2010095295 A1 WO2010095295 A1 WO 2010095295A1 JP 2009065633 W JP2009065633 W JP 2009065633W WO 2010095295 A1 WO2010095295 A1 WO 2010095295A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/30—Resistive cell, memory material aspects
- G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
Definitions
- the present invention relates to a resistance memory element and a method for using the same, and particularly to a resistance memory element including an element body made of an oxide semiconductor and a method for using the same.
- the resistance memory element includes an element body having a resistance memory characteristic, and this element body exhibits a relatively high resistance in an initial state, for example, but changes to a low resistance state when a voltage of a predetermined value or more is applied, Even if the voltage is removed, this low resistance state is retained (stored). On the other hand, if a voltage higher than the specified value is applied to the element body in the low resistance state in the reverse direction, it returns to the high resistance state and this voltage is removed. Even so, the high resistance state is maintained (stored).
- Such a resistance memory element can be switched between a low resistance state and a high resistance state by applying a voltage equal to or higher than a threshold value in each of the positive direction and the reverse direction. It is possible to memorize it.
- the resistance memory element can be used not only as a so-called resistance memory element but also as a switching element.
- Resistive memory elements change the easiness of electrons exceeding the barrier due to changes in the depletion layer thickness of the Schottky barrier, or the trapping or emission of electrons to the interface between the electrode and the semiconductor element or the bulk level. This is considered to change between a high resistance state and a low resistance state.
- bipolar voltages of different polarities
- one of the problems is the resistance retention characteristic, because resistance switching is caused by trapping or emission of electrons at the interface or bulk level. Especially, the stability in the low resistance state is poor, and the temperature rise or time There is a problem that the resistance switches to a high resistance state as time passes.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2006-324447
- Patent Document 1 proposes a technique for improving resistance memory characteristics. That is, in Patent Document 1, an oxide semiconductor (for example, Nb: SrTiO 3 ) has a structure sandwiched between a first electrode (for example, a Pt electrode) that can form a Schottky barrier and another second electrode. In the resistance memory element, a structure of Pt / Nb: SrTiO 3 / insulating film / electrode is adopted.
- the insulating film functions as a barrier that suppresses the emission of electrons from the interface trap in the oxide semiconductor, thereby suppressing the probability of trapping or emitting electrons from the interface, and as a result. They are trying to improve data retention characteristics (resistance memory effect).
- an object of the present invention is to provide a resistance memory element that can satisfy the above-described demand and a method for using the same.
- the present invention includes an element body and at least one pair of electrodes facing each other through at least a part of the element body, and a switching voltage in the first direction is applied between the pair of electrodes. , At least a portion of the element body positioned between the pair of electrodes is reduced in resistance, and then the switching voltage in the first direction is removed, and at least a portion of the low resistance state positioned between the pair of electrodes is removed.
- a switching voltage in the second direction opposite to the first direction is applied between the pair of electrodes, at least a part of the element body positioned between the pair of electrodes becomes highly resistive, After that, even if the switching voltage in the second direction is removed, it is first directed to the resistance memory element that is located between the pair of electrodes and retains at least a part of the high resistance state. In order to solve It is characterized in that.
- the element body has a composition represented by the general formula: Ti 1-x M x O 2 (M is at least one of Fe, Co, Ni, and Cu. 0.005 ⁇ x ⁇ 0.05). It is characterized by comprising an oxide semiconductor having
- the oxide semiconductor is preferably a polycrystal.
- At least one of the pair of electrodes is made of a material that is Schottky bonded to the element body.
- the resistance memory element according to the present invention can be advantageously used for impedance matching.
- the resistance memory element in a second aspect, includes an element body and first and second electrodes provided so as to be in contact with the element body.
- the first electrode includes:
- the second electrode is made of a material that can form a Schottky barrier capable of exhibiting rectification and resistance change characteristics in the interface region, and the second electrode has a more ohmic contact with the element body than the first electrode.
- the element body has the general formula: Ti 1-x M x O 2 (M is at least one of Fe, Co, Ni and Cu. 0.005 ⁇ x ⁇ 0.05) It is characterized by comprising an oxide semiconductor having a composition represented by
- the second electrode is made of a material that can provide a more ohmic contact with the element body than the first electrode” means that the second electrode is bonded to the element body. This means that the second electrode is made of a material that can obtain a junction closer to the ohmic characteristics than the junction of the first electrode to the element body.
- the present invention is also directed to a method of using the resistance memory element according to the second aspect.
- the method of using a resistance memory element according to the present invention includes the steps of realizing a low resistance state of the resistance memory element by applying a first voltage pulse having a first polarity between the first and second electrodes, And applying a second voltage pulse having a second polarity opposite to the first polarity between the first and second electrodes to realize a high resistance state of the resistance memory element. .
- the method of using the resistance memory element according to the present invention is the first polarity or the second polarity between the first and second electrodes, and the first voltage pulse and the second voltage pulse. Providing at least one intermediate resistance state indicative of a resistance value between the low resistance state and the high resistance state by applying at least one intermediate voltage pulse having an energy between preferable.
- a pulse having an intermediate value between the first voltage pulse and the second voltage pulse is preferably used for at least one selected from a pulse width, a pulse amplitude, and the number of pulse applications. It is done.
- the preferred usage method as described above enables the resistance memory element to be used as a multi-value memory.
- a resistance memory element having a large resistance change rate and an excellent resistance memory effect can be obtained.
- the reason can be assumed as follows.
- the present inventor speculated that stabilizing the trapping or emission of electrons at the interface or bulk level is important for improving the resistance switching characteristics and the resistance memory characteristics. It was considered that the characteristics can be improved and stabilized by adding a transition metal to TiO 2 and thereby forming a level in the band gap of TiO 2 .
- the resistance memory effect when the oxide semiconductor constituting the element body is a polycrystalline body, the resistance memory effect, particularly the resistance holding characteristic in a low resistance state can be further improved.
- the grain boundary in the polycrystal acts.
- providing a discontinuous structure that traps electrons, such as grain boundaries, and facilitating the generation of electron traps and oxygen vacancies helps the resistance in the low resistance state to increase with time. It is speculated that there is.
- the above-described effect of increasing the resistance change rate appears more remarkably.
- the resistance memory element according to the present invention When the resistance memory element according to the present invention is used for impedance matching, a large impedance change can be realized with low power consumption.
- a step of realizing a low resistance state of the resistance memory element by applying a first voltage pulse having a first polarity between the first and second electrodes; Performing a step of realizing a high resistance state of the resistance memory element by applying a second voltage pulse having a second polarity opposite to the first polarity between the first and second electrodes. And applying at least one intermediate voltage pulse having a first polarity or a second polarity and having an energy between the first voltage pulse and the second voltage pulse between the first and second electrodes. Accordingly, if the step of realizing at least one intermediate resistance state, which indicates a resistance value between the low resistance state and the high resistance state, is performed, the resistance memory is realized while realizing excellent memory characteristics. It is possible to multi-value of resistance child gives.
- the resistance memory element according to the present invention achieves a large rate of change in resistance and has a good memory characteristic. Therefore, when this is used, a plurality of resistance states (multi-values) can be stabilized. For example, it can be used as a multi-value memory device or an analog memory device.
- a plurality of resistance states can be held by cells of the same size.
- the cell size can be increased.
- the resistance value can be continuously changed by changing the width and amplitude of the applied voltage pulse instead of the discrete value, it can be used for analog purposes.
- FIG. 1 is a cross-sectional view schematically showing a resistance memory element according to an embodiment of the present invention. It is a figure which shows the electric current-voltage characteristic of the resistive memory element which concerns on the sample 14 in the range of this invention calculated
- FIG. It is a figure which shows the resistance holding characteristic in the room temperature of the resistance memory element which concerns on the sample 32 outside the range of this invention calculated
- FIG. It is a figure which shows the resistance holding characteristic of the low resistance state of the resistance memory element which concerns on the sample 32 outside the range of this invention calculated
- FIG. 1st application aspect of the voltage pulse applied to the resistance memory element in Experimental example 3 shows the state of resistance change of a resistive memory element when a voltage pulse is applied in the aspect shown in FIG.
- FIG. It is a figure which shows the state of resistance change of a resistive memory element when a voltage pulse is applied in the aspect shown in FIG. It is a figure which shows the 1st application aspect of the voltage pulse applied to the resistance memory element in Experimental example 4.
- FIG. It is a figure which shows the state of resistance change of a resistive memory element when a voltage pulse is applied in the aspect shown in FIG.
- FIG. It is a figure which shows the 2nd application aspect of the voltage pulse applied to the resistance memory element in Experimental example 4.
- FIG. It is a figure which shows the state of resistance change of a resistive memory element when a voltage pulse is applied in the aspect shown in FIG.
- the resistance memory element 1 includes an element body 2 and at least a pair of electrodes 3 and 4 facing each other with at least a part of the element body 2.
- the resistance memory element 1 has a capacitor structure in which a thin film-like element body 2 is formed on a substrate-like lower electrode 4 and a thin-film upper electrode 3 is further formed thereon. ing.
- the resistance memory element 1 when a switching voltage in the first direction is applied between the pair of electrodes 3 and 4, at least a part of the element body 2 positioned between the pair of electrodes 3 and 4 is reduced in resistance, Thereafter, even when the switching voltage in the first direction is removed, the low resistance state of the element body 2 is maintained, while the switching voltage in the second direction opposite to the first direction is interposed between the pair of electrodes 3 and 4. Is applied, the resistance of at least a part of the element body 2 positioned between the pair of electrodes 3 and 4 becomes high, and the high resistance of the element body 2 is removed even if the switching voltage in the second direction is removed thereafter. The state is maintained.
- the element body 2 is represented by the general formula: Ti 1-x M x O 2 (M is at least one transition metal of Fe, Co, Ni and Cu. 0.005 ⁇ x ⁇ 0.05). It consists of an oxide semiconductor having a composition.
- the thin film to be the element body 2 can be formed by using, for example, a PLD (Pulse Laser Deposition) method using a target having a predetermined composition.
- a PLD Pulse Laser Deposition
- ArF or KrF excimer laser or the like is used as the laser, but the laser is not limited thereto.
- the laser conditions at the time of film formation are as follows: energy is 0.1 to 3 J / cm 2 , frequency is 1 to 10 Hz, temperature is 400 to 700 ° C., and vacuum is 0.1 Torr to 1 ⁇ 10 ⁇ 5 Torr (O 2 flowing Is possible.
- MOCVD Metal Organic Chemical Vapor Deposition
- RF sputtering method RF sputtering method
- MOD Metal Organic deposition
- the above-mentioned target has the same general formula as Ti 2 to be obtained: Ti 1-x M x O 2 (M is at least one of Fe, Co, Ni and Cu. 0.005 ⁇ x ⁇ 0.05), which is prepared by, for example, a solid phase reaction method. That is, a high-purity TiO 2 powder is used as a raw material, and each powder of Co 3 O 4 , Fe 2 O 3 , NiO and CuO is used as necessary, and weighed to have a predetermined composition. Add ethanol in a mortar and mix thoroughly. After drying, a binder is added, fired using a high-pressure press and a mold, and then molded. The target can be obtained by degreasing the obtained molded product and firing in the air for 4 hours while applying a temperature of 1100 ° C. to 1200 ° C.
- the upper electrode 3 is made of a material that can form a Schottky barrier that can exhibit rectification and resistance change characteristics in the interface region with the element body 2. Therefore, as the material of the upper electrode 3, for example, Pt having a work function larger than that of the TiO 2 material which is the main component of the element body 2 is advantageously used. Note that not only Pt but also a noble metal such as Au, Ag, and Pd, an oxide that exhibits metal conduction such as SrRuO 3 , an organic conductor such as PEDOT: PSS, nitriding, and the like can be used as long as a Schottky junction can be formed. A physical conductor or the like may be used.
- the lower electrode 4 may be made of a material that can provide a more ohmic contact with the element body 2 than the upper electrode 3, but is preferably made of a material that can provide an ohmic contact.
- a material having a work function smaller than or equal to that of the TiO 2 material which is the main component of the element body 2 is used.
- the lower electrode 4 is made of Nb: SrTiO 3 . Further, depending on the device formation process, even if a metal having a large work function is used, it is possible to obtain a junction close to an ohmic junction.
- Nb SrTiO 3
- a noble metal electrode or the like can be used. These are used alone or in a structure in which, for example, a Ti electrode as an ohmic electrode is formed on the element body of the present invention, and a Pt electrode for preventing oxidation of the Ti electrode is formed thereon.
- a Schottky barrier is formed on the upper electrode 3, and an electrode capable of obtaining ohmic characteristics or almost ohmic characteristics is used for the lower electrode 4.
- a Schottky barrier may be formed.
- the resistance memory element 1 may have a planar structure in which two electrodes 3 and 4 are formed side by side on a TiO 2 -based thin film to be the element body 2 instead of the capacitor structure as in the illustrated embodiment.
- the element body 2 may be provided by a bulk body instead of a thin film.
- electrons are controlled by controlling the oxygen partial pressure during film formation.
- an element that acts as a donor is added to control the carrier concentration. May be.
- Example 1 A ceramic target (diameter: 20 mm, thickness 5 mm) represented by the general formula: Ti 1-x M x O 2 (M is any one of Cr, Mn, Co, Fe, Ni and Cu) is produced by a solid phase reaction method. did. As raw materials, high-purity TiO 2 , Mn 3 O 4 , Cr 2 O 3 , Co 3 O 4 , Fe 2 O 3 , NiO and CuO powders are used, and the predetermined composition shown in Table 1 is obtained. After weighed, ethanol was added in an agate mortar and mixed to mix well.
- a binder was added, fired using a high-pressure press and a mold, and then molded to have a diameter of about 20 mm and a thickness of about 5 mm.
- the molded body was degreased and then fired in the air at a temperature of 1100 ° C. for 4 hours to obtain a target.
- an Nb0.5 at% doped SrTiO 3 (100) single crystal substrate (manufactured by Furuuchi Chemical Co., Ltd.) was prepared as a lower electrode capable of obtaining an approximately ohmic junction with the TiO 2 thin film serving as the element body.
- a Ti 1-x M x O 2 thin film having a thickness of about 100 nm was formed on the substrate as a base body by the PLD method.
- a laser a “Compex110” ArF excimer laser manufactured by Lambda Physics was used, and the generated laser light was condensed and incident on a target to produce a thin film.
- the energy was 1 J / cm 2
- the frequency was 10 Hz
- the temperature was 600 ° C.
- the degree of vacuum was 0.1 Torr (O 2 flowing).
- the composition analysis of the thin film produced as described above was performed by fluorescent X-ray measurement or the like, it was confirmed that the thin film had substantially the same composition as the target used for the production in all samples.
- an upper electrode made of Pt having a diameter of 300 ⁇ m was formed on the thin film by DC sputtering using a metal mask.
- an extraction electrode 5 made of In—Ga is formed on the lower electrode 4, and a W probe 6 is brought into contact with the extraction electrode 5.
- a current-voltage generator 7 was connected between the extraction electrode 5 and the upper electrode 3 to evaluate the current-voltage characteristics, and the resistance holding characteristics at room temperature and 100 ° C. were evaluated.
- an “R6246A” current / voltage generator manufactured by Advantest Corporation was used as the current / voltage generator 7, as the current / voltage generator 7, an “R6246A” current / voltage generator manufactured by Advantest Corporation was used.
- sample 32 is a comparative example.
- Samples 1 to 31 had a structure of Pt / TiO 2 / Nb: SrTiO 3 / In—Ga.
- Pt / Nb SrTiO 3 / In Those having the structure of -Ga were prepared. Therefore, the samples 1 to 31 are to evaluate the characteristics at the interface between Pt and TiO 2, and the sample 32 are to evaluate the characteristics at the interface between Pt and Nb: SrTiO 3 .
- the voltage applied to the resistance memory element is expressed as follows: -X (V) ⁇ 0V ⁇ Y (V) ⁇ 0V ⁇ -X (V) (X and Y are arbitrary voltage values)
- the current flowing through the resistance memory element was measured while sweeping.
- the voltage that gives the largest change in polarity for switching from the low resistance state to the high resistance state is defined as the “estimated voltage”.
- the resistance change rate at Resistance change rate [%] (resistance value in high resistance state ⁇ resistance value in low resistance state) / resistance value in low resistance state ⁇ 100 Based on the formula of The result is shown in the column of “resistance change rate” in Table 1.
- the resistance holding characteristic evaluation as an index of the resistance memory effect, after switching to each of the high resistance state and the low resistance state, the resistance is measured for 10 hours at a voltage of 2 V every 10 seconds, and the time change of the resistance is measured.
- the resistance stability was evaluated by measuring at room temperature and at 100 ° C. More specifically, as illustrated in FIG. 3 for the sample 32, a resistance value in the low resistance state and a resistance value in the high resistance state are drawn by drawing a straight line from logarithmic plots (Log vs. Log) of the resistance value and time. Was defined as the resistance holding time, and this resistance holding time was determined. The result is shown in the “resistance holding time” column of Table 1. In FIG. 3, “LRS” indicates a low resistance state, “HRS” indicates a high resistance state, and “RT” indicates room temperature. . Further, in FIG. 4 described later, “100C” indicates 100 ° C. These also apply in the other figures and Table 1.
- the resistance holding time obtained as described above is only for observing the tendency of the resistance memory effect, and does not indicate the actual resistance memory effect time, but it is sufficient for relative comparison. It is considered a factor.
- the sample 1 having a TiO 2 thin film to which no transition metal is added has a small resistance change rate of less than 100%, and even if it is a transition metal, Cr and Mn are added respectively. Also in Samples 2 to 6 and Samples 7 to 11, the resistance change rate was as small as less than 100%.
- samples 12 to 31 having TiO 2 thin films to which any one of Co, Fe, Ni and Cu as transition metals was added showed a resistance change rate of 1000% or more. That is, in samples 12 to 15, 17 to 20, 22 to 25, and 27 to 30 in which the amount x of Co, Fe, Ni, or Cu as a transition metal satisfies the condition of x ⁇ 0.05, a resistance of 1000% or more The rate of change is shown.
- the time dependency of the resistance change in the low resistance state increased.
- the resistance holding time was 91 days, which was extremely shorter than the resistance holding time at room temperature of 8 ⁇ 10 + 9 days.
- Sample 13 having a TiO 2 thin film in which any one of Co, Fe, Ni and Cu as transition metals is added in a range where the addition amount x satisfies the condition of 0.005 ⁇ x ⁇ 0.05.
- the resistance value in the low resistance state of Sample 14 tends to change with time, but even at 100 ° C.
- an extremely long resistance holding time could be realized. This can be confirmed from the resistance holding time shown in Table 1.
- the additive-free TiO 2 thin film defects such as oxygen vacancies are easily generated, and even if an electrode having a large work function to be a Schottky junction is used, a good Schottky barrier is not formed, and a leakage current is large and small. Only the rate of resistance change is shown.
- the added transition metal forms a level or compensates for defects, so that a good Schottky barrier can be obtained.
- Mn and Cr show only a small resistance change rate. This is considered to be because the interface state and the amount of defects that cause the resistance change are excessively lowered, but the clear cause is not well understood at present.
- Co, Fe, Ni, and Cu a good Schottky barrier is formed, and a large resistance change rate can be realized.
- the resistance memory element according to the present invention As described above, by using the resistance memory element according to the present invention, as is apparent from Table 1, it is possible to realize excellent resistance holding characteristics in the actual operating temperature region (room temperature or higher), It becomes possible to remarkably improve the resistance holding characteristic in the low resistance state, which has been a problem of the Schottky barrier resistance switching element.
- the resistance memory element according to the present invention can be advantageously applied as, for example, an impedance switching element because a large resistance change rate can be obtained.
- An embodiment in which the resistance memory element according to the present invention is used as an impedance switching element will be described below.
- a PIN diode type switching element or an FET transistor type switching element is generally used as the switching element of the RF signal circuit.
- the RF signal circuit is turned on / off by turning on the low resistance state when applying a forward bias and turning off the high resistance state when applying a reverse bias. is doing.
- the RF signal circuit is turned on / off by turning on the low resistance state when the gate voltage is applied and turning off the high resistance state when the gate voltage is not applied. is doing.
- the resistance memory element as the Schottky junction device according to the present invention when used, the impedance can be changed at the same time as the resistance changes, and it can be used as an impedance switching element as in the case of the PIN diode. can do. Furthermore, since the resistance memory element according to the present invention has a resistance memory function, it is not necessary to continue to apply a voltage after switching to the low resistance state, so that power consumption can be reduced. . Therefore, it is possible to solve the problem of power consumption, which is a drawback of the PIN diode type, and the problem that it is necessary to continue to apply a voltage in order to maintain the on state, which is a disadvantage of both the PIN diode type and the FET transistor type. it can.
- a conventionally known junction resistance change element such as SrTiO 3 / SrRuO 3 has insufficient resistance change rate and resistance memory characteristics. .
- the resistance memory element according to the present invention by adding a transition metal to TiO 2, by forming a level within the band gap of TiO 2, a large resistance change ratio, excellent impedance switching elements of the resistance memory characteristic Can be realized.
- An experimental example carried out to confirm this will be described below.
- the “added element”, “added amount”, and “resistance change rate” shown in Table 1 are listed again, and in particular, the correlation between the resistance change rate and the impedance change rate is easily understood. Yes. Further, in Table 2, when the impedance change rate is 0%, it means that the impedance change rate is almost 0%, and precisely, it means 5% or less.
- the resistance memory characteristic was not good in the sample 32 as the comparative example, but a relatively large resistance change characteristic of 8500% was realized.
- the impedance characteristic evaluation result of this sample 32 is shown in FIG. According to the sample 32, a large resistance change rate can be realized with the DC resistance, but the difference between the impedance in the high resistance state and the impedance in the low resistance state is small, and the difference becomes smaller as the frequency becomes higher. It was. As shown in Table 2, at a frequency of 10 kHz, the impedance change rate was very small at 50%.
- the impedance characteristics of the sample 14 are shown in FIG. 7 on behalf of the samples 13 to 15, 18 to 20, 23 to 25, and 28 to 30 within the scope of the present invention.
- the difference in impedance becomes smaller due to the problem of the capacitance component, but there is a very large difference in the low frequency region.
- the impedance change rate was 7750%, which was a very large value.
- the impedance change rate at a frequency of 10 kHz exceeded 3000% while realizing a large resistance change rate, A large impedance change rate was achieved.
- the sample 32 as the comparative example almost the same large resistance change rate is obtained as compared with the samples 13 to 15, 18 to 20, 23 to 25, and 28 to 30 within the scope of the present invention.
- the impedance change rate was as small as 50%.
- the impedance (Z) is not only the resistance component (R) but also the capacitance component (C) and the inductance component (L), and samples 13 to 15 within the scope of the present invention.
- the resistance change rate is large, but also the resistance of the low resistance state is lower than that of the sample 32, so that the influence of the C component is reduced. It is estimated that a large impedance change rate was obtained.
- the resistance memory characteristic contributes greatly. If the resistance memory characteristic is poor, the resistance in the low resistance state immediately rises, so that the impedance change rate is also considered to be small.
- the resistance memory element according to the present invention not only can a large resistance change rate and excellent resistance memory characteristics be realized, but also a large impedance change rate can be realized. It can be advantageously used not only as a memory device but also as an impedance switching element.
- the resistance memory element manufactured in this experimental example has a limited frequency band in which the impedance can be changed, but the characteristics are improved on the high-frequency side by reducing the capacitance due to the fine structure of the oxide semiconductor constituting the element body. It can be expected that it can be used as an impedance switching element with low power consumption in a wider frequency band.
- the resistance memory element by using the resistance memory element according to the present invention, not only two states such as a high resistance state and a low resistance state, that is, two values such as “0” and “1”, but also a high resistance state and a low resistance state. At least one intermediate resistance state, preferably a plurality of intermediate resistance states, can be realized in between.
- Migration is considered as a candidate for the origin of resistance change.
- a transition metal is added, as in the case of the compound semiconductor constituting the element body included in the resistance memory element according to the present invention, this forms an interface and a bulk level, and thus the number of states that can trap electrons increases.
- a change in valence which eliminates the charge imbalance created by the migrated defects, and as a result, is considered to have achieved excellent memory characteristics.
- Multi-leveling is considered to be realized by changing the degree of electron trapping or migration by applying voltage pulses.
- the magnitude of the switching voltage that is, the pulse amplitude is set to ⁇ 5V.
- the resistance value was measured while gradually increasing the pulse width in the range of 100 ns to 100 ⁇ s.
- the voltage at the time of measurement is shown as “Read voltage” in FIG.
- the pulse amplitude is fixed to +5 V as shown in FIG.
- the resistance value was measured while gradually increasing the pulse width in the range of 100 ns to 100 ⁇ s. More specifically, as shown in FIG. (6) Measure the initial resistance state (LRS) three times, (7) Next, after applying one pulse voltage having a pulse amplitude of +5 V and a pulse width of 100 ns, the resistance value in the first intermediate resistance state (MRS1) is measured three times.
- the pulse width is fixed to 100 ⁇ s as shown in FIG.
- the resistance value was measured while gradually increasing the pulse amplitude in the range of + 2V to + 5V. More specifically, as shown in FIG. (6) Measure the initial resistance state (LRS) three times, (7) Next, after one pulse voltage having a pulse width of 100 ⁇ s and a pulse amplitude of +2 V is applied, the resistance value in the first intermediate resistance state (MRS1) is measured three times.
- the resistance value is changed stepwise, but instead of changing the resistance value stepwise, switching to a desired resistance value is performed at once, so that a predetermined pulse width, pulse amplitude, or pulse is changed.
- a use mode in which a pulse voltage having the number of application times is applied is also possible.
- the voltage pulse to be applied has a reverse polarity, even when going from the low resistance state to the high resistance state, or returning to the low resistance state, conversely, even while going from the high resistance state to the low resistance state, It can also be returned to a high resistance state.
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Abstract
Description
一般式:Ti1-xMxO2(Mは、Cr、Mn、Co、Fe、NiおよびCuのいずれか)で示されるセラミックターゲット(直径:20mm、厚み5mm)を固相反応法で作製した。原料としては、高純度のTiO2、Mn3O4、Cr2O3、Co3O4、Fe2O3、NiOおよびCuOの各粉末を用い、表1に示した所定の組成になるように秤量した後、メノウ乳鉢でエタノールを加えて十分混ざるように混合した。次に、乾燥させた後、バインダを添加し、高圧プレス機および金型を用いて焼成した後、直径が約20mm、厚みが約5mmになるように成形した。この成形体を、脱脂した後、1100℃の温度で大気中において4時間焼成し、ターゲットを得た。
抵抗変化率[%]=(高抵抗状態の抵抗値-低抵抗状態の抵抗値)/低抵抗状態の抵抗値×100
の式に基づいて算出した。その結果が表1の「抵抗変化率」の欄に示されている。
図3において、「LRS」は低抵抗状態、「HRS」は高抵抗状態を示し、「RT」は室温を示している。また、後述する図4において、「100C」は100℃を示すものである。これらのことは、他の図面および表1においても当てはまる。
実験例2では、前述の実験例1において作製した試料を用いて高抵抗状態と低抵抗状態におけるインピーダンスの周波数特性評価を行なった。
インピーダンス変化率[%]=(高抵抗状態のインピーダンス-低抵抗状態のインピーダンス)/低抵抗状態のインピーダンス×100
の式に基づいて算出した。その結果が表2に示されている。なお、表2では、表1に示した「添加元素」、「添加量」および「抵抗変化率」を再び掲載し、特に、抵抗変化率とインピーダンス変化率との相関が把握しやすいようにしている。また、表2において、インピーダンス変化率が0%のものは、ほぼ0%であるという意味であり、正確には、5%以下のものをいう。
実験例3では、実験例1において作製した試料14に係る抵抗記憶素子を用いて多値化についての評価を行なった。
(1)初期抵抗状態(HRS)を3回測定し、
(2)次いで、パルス振幅が-5Vで、パルス幅が100nsのパルス電圧を1発印加した後、第1の中間抵抗状態(MRS1)の抵抗値を3回測定し、
(3)次いで、パルス幅を1μsとより長くしたパルス電圧を1発印加した後、第2の中間抵抗状態(MRS2)の抵抗値を3回測定し、
(4)次いで、パルス幅を10μsとより長くしたパルス電圧を1発印加した後、第3の中間抵抗状態(MRS3)の抵抗値を3回測定し、
(5)次いで、パルス幅を100μsとより長くしたパルス電圧を1発印加した後、低抵抗状態(LRS)の抵抗値を3回測定した。
(6)初期抵抗状態(LRS)を3回測定し、
(7)次いで、パルス振幅が+5Vで、パルス幅が100nsのパルス電圧を1発印加した後、第1の中間抵抗状態(MRS1)の抵抗値を3回測定し、
(8)次いで、パルス幅を1μsとより長くしたパルス電圧を1発印加した後、第2の中間抵抗状態(MRS2)の抵抗値を3回測定し、
(9)次いで、パルス幅を10μsとより長くしたパルス電圧を1発印加した後、第3の中間抵抗状態(MRS3)の抵抗値を3回測定し、
(10)次いで、パルス幅を100μsとより長くしたパルス電圧を1発印加した後、高抵抗状態(HRS)の抵抗値を3回測定した。
実験例4では、実験例3の場合と同様、実験例1において作製した試料14に係る抵抗記憶素子を用いて多値化についての評価を行なった。実験例3と異なるのは、パルス電圧の印加態様である。
(1)初期抵抗状態(HRS)を3回測定し、
(2)次いで、パルス幅が100μsで、パルス振幅が-1Vのパルス電圧を1発印加した後、第1の中間抵抗状態(MRS1)の抵抗値を3回測定し、
(3)次いで、パルス振幅を-2Vと絶対値でより大きくしたパルス電圧を1発印加した後、第2の中間抵抗状態(MRS2)の抵抗値を3回測定し、
(4)次いで、パルス振幅を-3Vと絶対値でより大きくしたパルス電圧を1発印加した後、第3の中間抵抗状態(MRS3)の抵抗値を3回測定し、
(5)次いで、パルス振幅を-4Vと絶対値でより大きくしたパルス電圧を1発印加した後、低抵抗状態(LRS)の抵抗値を3回測定した。
(6)初期抵抗状態(LRS)を3回測定し、
(7)次いで、パルス幅が100μsで、パルス振幅が+2Vのパルス電圧を1発印加した後、第1の中間抵抗状態(MRS1)の抵抗値を3回測定し、
(8)次いで、パルス振幅を+3Vとより大きくしたパルス電圧を1発印加した後、第2の中間抵抗状態(MRS2)の抵抗値を3回測定し、
(9)次いで、パルス振幅を+4Vとより大きくしたパルス電圧を1発印加した後、第3の中間抵抗状態(MRS3)の抵抗値を3回測定し、
(10)次いで、パルス振幅を+5Vとより大きくしたパルス電圧を1発印加した後、高抵抗状態(HRS)の抵抗値を3回測定した。
2 素体
3,4 電極
Claims (9)
- 素体と、前記素体の少なくとも一部を介して対向する少なくとも1対の電極とを備え、前記1対の電極間に第1方向のスイッチング電圧を印加したとき、前記素体の、前記1対の電極間に位置する少なくとも一部が低抵抗化し、その後、前記第1方向のスイッチング電圧を除去しても、前記1対の電極間に位置する少なくとも一部の低抵抗状態が保持され、他方、前記1対の電極間に第1方向とは逆の第2方向のスイッチング電圧を印加したとき、前記素体の、前記1対の電極間に位置する少なくとも一部が高抵抗化し、その後、前記第2方向のスイッチング電圧を除去しても、前記1対の電極間に位置する少なくとも一部の高抵抗状態が保持される抵抗記憶素子であって、
前記素体は、一般式:Ti1-xMxO2(Mは、Fe、Co、NiおよびCuのうちの少なくとも1種。0.005≦x≦0.05)で示される組成を有する酸化物半導体からなる、
抵抗記憶素子。 - 前記酸化物半導体は多結晶体である、請求項1に記載の抵抗記憶素子。
- 前記1対の電極の少なくとも一方は、前記素体とショットキー接合される材料からなる、請求項1または2に記載の抵抗記憶素子。
- インピーダンス整合用に用いられる、請求項1ないし3のいずれかに記載の抵抗記憶素子。
- 素体と、前記素体に接触するように設けられた、第1および第2の電極とを備え、
前記第1の電極は、前記素体との界面領域において整流性と抵抗変化特性とを発現し得るショットキー障壁を形成し得る材料からなり、
前記第2の電極は、前記第1の電極と比較して、前記素体に対してよりオーミックな接合が得られる材料からなり、
前記素体は、一般式:Ti1-xMxO2(Mは、Fe、Co、NiおよびCuのうちの少なくとも1種。0.005≦x≦0.05)で示される組成を有する酸化物半導体からなる、
抵抗記憶素子。 - 請求項5に記載の抵抗記憶素子を使用する方法であって、
前記第1および第2の電極間に第1極性の第1の電圧パルスを印加することによって、当該抵抗記憶素子の低抵抗状態を実現するステップと、
前記第1および第2の電極間に前記第1極性とは逆の第2極性の第2の電圧パルスを印加することによって、当該抵抗記憶素子の高抵抗状態を実現するステップと
を備える、抵抗記憶素子の使用方法。 - 前記第1および第2の電極間に、前記第1極性または前記第2極性であって、前記第1の電圧パルスと前記第2の電圧パルスとの間のエネルギーを有する少なくとも1つの中間電圧パルスを印加することによって、前記低抵抗状態と前記高抵抗状態との間の抵抗値を示す、少なくとも1つの中間抵抗状態を実現するステップをさらに備える、請求項6に記載の抵抗記憶素子の使用方法。
- 前記中間電圧パルスは、パルス幅、パルス振幅およびパルス印加回数から選ばれる少なくとも1種について、前記第1の電圧パルスと前記第2の電圧パルスとの中間の値を有する、請求項7に記載の抵抗記憶素子の使用方法。
- 多値化メモリーとして使用される、請求項7または8に記載の抵抗記憶素子の使用方法。
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Patent Citations (3)
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JPH10135715A (ja) * | 1996-11-01 | 1998-05-22 | Matsushita Electric Ind Co Ltd | 超伝導信号処理装置 |
JP2007235139A (ja) * | 2006-02-27 | 2007-09-13 | Samsung Electronics Co Ltd | 二つの酸化層を利用した不揮発性メモリ素子 |
JP2008310859A (ja) * | 2007-06-12 | 2008-12-25 | Toshiba Corp | 情報記録再生装置 |
Cited By (2)
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JP2012060072A (ja) * | 2010-09-13 | 2012-03-22 | Sharp Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2013008884A (ja) * | 2011-06-27 | 2013-01-10 | National Institute Of Advanced Industrial & Technology | 抵抗変化型不揮発性メモリ素子 |
Also Published As
Publication number | Publication date |
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CN102326253A (zh) | 2012-01-18 |
JPWO2010095295A1 (ja) | 2012-08-16 |
CN102326253B (zh) | 2014-06-25 |
US20120092919A1 (en) | 2012-04-19 |
US8542520B2 (en) | 2013-09-24 |
JP5459515B2 (ja) | 2014-04-02 |
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