WO2010088142A3 - Method and apparatus for performing abstraction-refinement using a lower-bound-distance - Google Patents

Method and apparatus for performing abstraction-refinement using a lower-bound-distance Download PDF

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Publication number
WO2010088142A3
WO2010088142A3 PCT/US2010/021717 US2010021717W WO2010088142A3 WO 2010088142 A3 WO2010088142 A3 WO 2010088142A3 US 2010021717 W US2010021717 W US 2010021717W WO 2010088142 A3 WO2010088142 A3 WO 2010088142A3
Authority
WO
WIPO (PCT)
Prior art keywords
bound
distance
abstraction
lbd
value
Prior art date
Application number
PCT/US2010/021717
Other languages
French (fr)
Other versions
WO2010088142A2 (en
Inventor
In-Ho Moon
Original Assignee
Synopsys, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys, Inc. filed Critical Synopsys, Inc.
Priority to EP10736259.2A priority Critical patent/EP2382571B1/en
Publication of WO2010088142A2 publication Critical patent/WO2010088142A2/en
Publication of WO2010088142A3 publication Critical patent/WO2010088142A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Embodiments of the present invention provide methods and apparatuses for verifying the functionality of a circuit. The system can determine a lower-bound-distance (LBD) value, such that the LBD value is associated with an LBD abstract model of the CUV which does not satisfy a property. The system can use an abstraction-refinement technique to determine whether the CUV satisfies the property. The system can determine an upper-bound-distance value for an abstract model which is being used in the abstraction-refinement technique, and can determine whether the LBD value is greater than or equal to the upper-bound-distance value. If so, the system can conclude that the abstract model does not satisfy the property, and hence, the system can decide not to perform reachability analysis on the abstract model that is currently being used in the abstraction-refinement technique.
PCT/US2010/021717 2009-01-29 2010-01-22 Method and apparatus for performing abstraction-refinement using a lower-bound-distance WO2010088142A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10736259.2A EP2382571B1 (en) 2009-01-29 2010-01-22 Method and apparatus for performing abstraction-refinement using a lower-bound-distance

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/362,084 2009-01-29
US12/362,084 US8032848B2 (en) 2009-01-29 2009-01-29 Performing abstraction-refinement using a lower-bound-distance to verify the functionality of a circuit design

Publications (2)

Publication Number Publication Date
WO2010088142A2 WO2010088142A2 (en) 2010-08-05
WO2010088142A3 true WO2010088142A3 (en) 2010-11-04

Family

ID=42355201

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/021717 WO2010088142A2 (en) 2009-01-29 2010-01-22 Method and apparatus for performing abstraction-refinement using a lower-bound-distance

Country Status (5)

Country Link
US (1) US8032848B2 (en)
EP (1) EP2382571B1 (en)
CN (1) CN101794324B (en)
TW (1) TWI461945B (en)
WO (1) WO2010088142A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102968515B (en) * 2011-08-31 2016-03-30 国际商业机器公司 For calculating the method and apparatus of the checking coverage rate of integrated circuit model
US9395148B1 (en) * 2015-06-12 2016-07-19 George Huang Recoil management system
US9665682B1 (en) * 2015-09-30 2017-05-30 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for enhancing formal verification with counter acceleration for electronic designs
US10394699B1 (en) * 2017-09-11 2019-08-27 Cadence Design Systems, Inc. Method and system for reusing a refinement file in coverage grading

Citations (3)

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US20040123254A1 (en) * 2002-12-20 2004-06-24 International Business Machines Corporation Model checking with layered localization reduction
US20060129959A1 (en) * 2004-12-09 2006-06-15 Mang Yiu C Abstraction refinement using controllability and cooperativeness analysis
US20060212837A1 (en) * 2005-03-17 2006-09-21 Prasad Mukul R System and method for verifying a digital design using dynamic abstraction

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US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
TW564313B (en) * 2000-06-28 2003-12-01 Cadence Design Systems Inc Method and apparatus for testing an integrated circuit, probe card for testing a device under test, apparatus for generating test vectors, computer-readable medium having instructions for testing a device under test and generating test vectors and method
US6665848B2 (en) * 2001-01-12 2003-12-16 International Business Machines Corporation Time-memory tradeoff control in counterexample production
US20020173942A1 (en) * 2001-03-14 2002-11-21 Rochit Rajsuman Method and apparatus for design validation of complex IC without using logic simulation
US6848088B1 (en) * 2002-06-17 2005-01-25 Mentor Graphics Corporation Measure of analysis performed in property checking
TWI240191B (en) * 2002-10-24 2005-09-21 Faraday Tech Corp A method for EDA tools to bypass a plurality of clock branches in the EDA tools
TWI220486B (en) * 2003-02-27 2004-08-21 Faraday Tech Corp Method for functional verification of hardware design
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JP2007536581A (en) * 2004-05-07 2007-12-13 メンター・グラフィクス・コーポレーション Integrated circuit layout design method using process variation band
JP2007164231A (en) * 2005-12-09 2007-06-28 Nec Electronics Corp Semiconductor design support device
US20090007038A1 (en) * 2007-04-05 2009-01-01 Nec Laboratories America, Inc. Hybrid counterexample guided abstraction refinement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040123254A1 (en) * 2002-12-20 2004-06-24 International Business Machines Corporation Model checking with layered localization reduction
US20060129959A1 (en) * 2004-12-09 2006-06-15 Mang Yiu C Abstraction refinement using controllability and cooperativeness analysis
US20060212837A1 (en) * 2005-03-17 2006-09-21 Prasad Mukul R System and method for verifying a digital design using dynamic abstraction

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Design, Automation and Test in Europe Conference and Exhibition, 2004", vol. 1, February 2004, article PER BJESSE ET AL.: "Using Counter Example Guided Abstraction Refinemen t to Find Complex Bugs", pages: 156 - 161 *
GISLI R. HJALTASON ET AL.: "Properties of Embedding Methods for Simi larity Searching in Metric Spaces", vol. 25, no. 4, April 2003 (2003-04-01), pages 1 - 20 *
SATYAKI DAS ET AL.: "Counter-Example Based Predicate Discovery in P redicate Abstraction", FORMAL METHODS IN COMPUTER-AIDED DESIGN, vol. 2517, November 2002 (2002-11-01), pages 19 - 32 *
See also references of EP2382571A4 *

Also Published As

Publication number Publication date
EP2382571B1 (en) 2018-09-26
US20100192114A1 (en) 2010-07-29
EP2382571A4 (en) 2013-11-20
WO2010088142A2 (en) 2010-08-05
US8032848B2 (en) 2011-10-04
CN101794324B (en) 2013-10-23
TW201040768A (en) 2010-11-16
TWI461945B (en) 2014-11-21
EP2382571A2 (en) 2011-11-02
CN101794324A (en) 2010-08-04

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