TW564313B - Method and apparatus for testing an integrated circuit, probe card for testing a device under test, apparatus for generating test vectors, computer-readable medium having instructions for testing a device under test and generating test vectors and method - Google Patents

Abstract

A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.

Description

564313 A7 B7 五、發明説明（2 ) synthesis)來決定，邏輯合成將電路的功能描述轉換成特定 的電路實作。然後將邏輯基本單元佈放到適當的位置（亦 即，給定其在電路配置中特定的座標位置）並加以接線（亦 即’按照設計者的電路定義把線路接起來）。該佈放及接 線軟體通常接受該邏輯合成程序所產生之一扁平網表作爲 其輸入α此一扁平網表從一標準目標單元程式庫（cell library)找出特定的邏輯基本單元複本（logic cell instance)， 並描述特定的單元對單元之連接。此一單元對單元之連接 體配置檔，其中包括每一條金屬線（亦即電線）和每一個通 道（亦即，各晶片層之間的金屬過渡層）的實體位置。 在產生用於傳送到製造設備之遮蔽檔案之前的最後一個 步驟是使用實體驗證及配置確認軟體對配置檔案進行若干 個設計規則查核（DRCs)。近來，爲處理非常龐大且複雜的 設計，在設計中，每一個區段或區塊會建立一個網表。後 續被佈放及接線的區塊，以階層式的觀點視之爲「基本單 元」，然後，在接下來的全設計階段中，它們又再被佈放 及接線而形成整個晶片的配置。在此一階層式的作法中， 該等DRCs亦以階層的方式進行。針對特定晶片設計程序的 進一步解釋在例如5,838,583號的美國專利中有所説明，全 文以提示方式併入本文。 積體電路在半導體鑄造廠的製造期間通常係做在半導體 晶圓上，這是多步骤製程的一部份。通常會在單一的半導 體晶圓上大量地複製一個單一的積體電路設計，重覆的積 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）564313 A7 B7 5. Invention description (2) synthesis) to determine, logical synthesis converts the functional description of the circuit into a specific circuit implementation. The basic logic unit is then placed in the appropriate location (ie, given its specific coordinate position in the circuit configuration) and wired (ie, ‘connect the lines according to the designer ’s circuit definition). The deployment and wiring software usually accepts a flat netlist generated by the logic synthesis program as its input α This flat netlist finds a specific logical basic cell copy from a standard target cell library (logic cell) instance), and describe the specific unit-to-unit connection. This unit-to-unit connector configuration file includes the physical location of each metal wire (ie, wire) and each channel (ie, metal transition layer between wafer layers). The last step before generating a mask file for transmission to manufacturing equipment is to use physical verification and configuration validation software to perform several design rule checks (DRCs) on the configuration file. Recently, to deal with very large and complex designs, a netlist is created for each segment or block in the design. The blocks that are subsequently laid out and wired are regarded as “basic units” from a hierarchical perspective. Then, in the next full design stage, they are laid out and wired to form the entire chip configuration. In this hierarchical approach, the DRCs are also implemented in a hierarchical manner. Further explanations of specific wafer design procedures are described in, for example, U.S. Patent No. 5,838,583, which is incorporated herein by reference in its entirety. Integrated circuits are usually fabricated on semiconductor wafers during the fabrication of semiconductor foundries, which is part of a multi-step process. A single integrated circuit design is usually duplicated in large quantities on a single semiconductor wafer. Repeated product -5- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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564313 A7 B7 五、發明説明（3 ) 體電路行列均等地配置於半導體晶圓上。製造含有積體電 路之半導體晶圓的步骤可能包括蝕刻、沉積、擴散 (diffusion)及清潔等程序，所有這些程序皆在規定的容許條 件下進行。 一般而言，半導體晶圓上有一些積體電路會因爲製程中 的瑕疵而-不適合大量生產。每一晶圓上，有問題之積體電 路的數目有一部份與製程的品質和一致性有關。然而，即 使設計藍圖是正確的，但可能因爲製程中電子元件不滿足 因爲應隔離的電子路徑太過靠近或發生短路，或因爲其它 在蝕刻、沉積、擴散或清潔等製程中的瑕疵等因素，即使 半導體鑄造廠已經盡最大的努力，每一晶圓上經常還是會 有很多不合格的積體電路。積體電路，包括微電路、電線 和構成其一部份的元件，不斷朝尺寸縮小發展，造成製程 中發生瑕疵可能性增加，而使得半導體晶圓上總會有一些 (而且有時候是全部）不合格的積體電路。 在製造程序之後，一半導體晶圓通常要通過封裝程序， 此程序中，晶圓被切成方塊然後加以封裝以供裝運或結合 到電子裝置中。未能在該等裝運或結合的動作之前找出有 問題的積體電路的下場是很嚴重的。若一個有瑕疵的積體 電路未在交貨前未被找出來，它有可能被裝到產品上並賣= 給消費者或使用者，最後它可能在使用中發生故障。這些 故障除了有損晶片設計者及半導體製造商的聲譽之外，還 會造成消費者或最終使用者應用上嚴重的問題。此外，更 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 564313 A7 B7 五、發明説明（4 ) 換整個有瑕疵的產品的成本遠大於在有瑕疵的元件被組裝 到最終的產品之前就先加以移除的成本。 因此，應對積體電路施以測試以保證它們能夠正常地運 作。這些測試可在半導體晶圓製造完成時進行，及/或在 封裝之後進行。已有各種不同的測試被發展出來供這些製 造階段使-用。這些測試大部份是透過一塊連接到一台自動 化機器的「探測卡」。該探測卡爲一測試夾具，它與要被 測試的積體電路（本文中亦稱之爲受測裝置或DUT)直接接 測卡之該自動化機器通常包括一台電腦，其中存有各種由 設計或測試工程師專爲該DUT所開發的測試資訊。測試的 類別可包括用以確保該積體電路的功能是完整的功能測試 ，例如診斷測試和應力測試；還包括用以確保該DUT的邏 輯沒有結構上的錯誤的結構測試，例如内建的自我測試 (BISTs)和基於掃描的測試。 每一項測試所需的時間是選擇積體電路之測試型式的考 慮因素之一。由於積體電路通常是大量生產製程的一部份 ，製程中會生產數萬甚至數百萬個單元，因此，即使是相 當簡短的測試，總加起來也會造成嚴重的延遲。此外，製 造後之測試通常需要昂貴、專門的測試設備，每台測試機 器可能需要花費數萬或數百萬元。由於積體電路所包含的-閘極不斷地增加，達到數百萬或數千萬的數目，因此傳統 上快速的測試技術在積體電路全測的情況下變得太過耗時 或沒有效率。相同的理由，測試成本急速地變成積體電路 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 313 A7 B7 五、發明説明（8 ) ^ " 試，至少部份地測試該積體電路之記憶體及資料路徑；沙） 執行診斷測試，至少部份個別地測試該隨機邏輯元件區塊 ’（c)使用測試向量執行應力測試（stress test)，至少部份集 體地測試該隨機邏輯元件區塊；以及⑷執行該積體電路之 基於掃描（scan-based)測試，至少部份地測試該積體電路中 是否有結-構上的疵病。 本發明在第五方面爲一探測卡，用於測試一受測試裝置 。該探測卡最好包括一個受測裝置介面、一個測試器介面 以及一個用以礙命秦用於該受測裝置之測試； 。該探測卡最好進一步包含一個資料轉譯器，連接在該記 憶體和測試器之間，用於格式化在記憶體和測試器介面之 間通訊的資料。 本發明在第六方面爲一用於測試一受測試裝置的探測卡 ’該探測卡最好包含一個受測裝置介面、一個測試器介面 ，以及一個連接在該測試器介面和該受測裝置介面之間的 類比訊號產生器。該類比訊號產生器最好是設定成接收來 自該測試器介面之代表類比測試的數位訊號，根據該數位 訊號產生一類比訊號，並傳送該類比訊號到該受測裝置介 面。該探測器最好進一步包括一個資料轉譯器，連線於該 受測裝致置介面及該測試器介面之間，用於格式化在該受 測裝置介面和測試器介面之間通訊的資料。 二 本發明在第七方面爲一塊用於測試一受測裝置之探測卡 ，該探測卡最好包含一個受測裝置介面、一個測試器介面 、一個至少與該受測裝置之兩個接點連接的摺回電路（fold- -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 564313564313 A7 B7 V. Description of the Invention (3) The body circuits are arranged evenly on the semiconductor wafer. The steps for manufacturing a semiconductor wafer containing integrated circuits may include processes such as etching, deposition, diffusion, and cleaning, all of which are performed under specified allowable conditions. Generally speaking, there are some integrated circuits on semiconductor wafers that are flawed in the process-not suitable for mass production. The number of problematic integrated circuits on each wafer is partly related to the quality and consistency of the process. However, even if the design blueprint is correct, it may be because the electronic components in the process are not satisfied, the electronic paths that should be isolated are too close or short-circuited, or because of other defects in the process such as etching, deposition, diffusion, or cleaning. Even though semiconductor foundries have done their best, there are often many substandard integrated circuits on each wafer. Integrated circuits, including microcircuits, wires, and components that form part of them, continue to shrink in size, increasing the possibility of defects in the process, and there will always be some (and sometimes all) on semiconductor wafers Unqualified integrated circuit. After the manufacturing process, a semiconductor wafer typically goes through a packaging process, in which the wafer is diced and then packaged for shipment or incorporation into an electronic device. Failure to locate the problematic integrated circuit before such shipments or combined actions is serious. If a defective integrated circuit is not found before delivery, it may be installed on the product and sold = to consumers or users, and it may eventually fail during use. In addition to damaging the reputation of chip designers and semiconductor manufacturers, these failures can cause serious problems for consumer or end-user applications. In addition, more -6-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 A7 B7 V. Description of the invention (4) The cost of replacing the entire defective product is much greater than that of the defective component The cost of removing it before it is assembled into the final product. Therefore, integrated circuits should be tested to ensure that they function properly. These tests can be performed at the completion of semiconductor wafer fabrication and / or after packaging. Various tests have been developed for these manufacturing stages. Most of these tests are through a “probe card” connected to an automated machine. The detection card is a test fixture, which is directly connected to the integrated circuit to be tested (also referred to herein as the device under test or DUT). The automated machine usually includes a computer in which various design Or test information developed by the test engineer specifically for the DUT. The types of tests may include functional tests to ensure that the function of the integrated circuit is complete, such as diagnostic tests and stress tests; and structural tests to ensure that the logic of the DUT is free of structural errors, such as the built-in self Tests (BISTs) and scan-based tests. The time required for each test is one of the considerations in selecting the test pattern of the integrated circuit. Because integrated circuits are usually part of a mass production process, where tens of thousands or even millions of units are produced, even a fairly short test can add up to serious delays. In addition, post-manufacturing tests often require expensive, specialized test equipment, and each test machine can cost tens or millions of dollars. Because the gates included in integrated circuits are constantly increasing, reaching millions or tens of millions, traditionally fast testing techniques have become too time-consuming or inefficient in the case of integrated circuits. . For the same reason, the test cost has rapidly changed to integrated circuits. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 313 A7 B7 V. Description of the invention (8) ^ " try, at least partially Test the memory and data paths of the integrated circuit; sand) perform diagnostic tests, at least partly test the random logic element block '(c) use test vectors to perform stress tests, at least partly collectively Testing the random logic element block; and performing a scan-based test of the integrated circuit to test at least partially whether there is a structural-structural defect in the integrated circuit. The fifth aspect of the present invention is a probe card for testing a device under test. The probe card preferably includes an interface of the device under test, a tester interface, and an interface for preventing Qin from using the device under test; The probe card preferably further includes a data translator connected between the memory and the tester for formatting data communicated between the memory and the tester interface. In a sixth aspect, the present invention is a probe card for testing a device under test. The probe card preferably includes a device tested interface, a tester interface, and a connection between the tester interface and the device tested interface. Analog signal generator in between. The analog signal generator is preferably configured to receive a digital signal representative of an analog test from the tester interface, generate an analog signal based on the digital signal, and send the analog signal to the interface of the device under test. Preferably, the detector further includes a data translator connected between the tested device interface and the tester interface for formatting data communicated between the tested device interface and the tester interface. 2. In the seventh aspect, the present invention is a probe card for testing a device under test. The probe card preferably includes a device tested interface, a tester interface, and at least two contacts connected to the device under test. Fold circuit (fold- -11-This paper size applies to Chinese National Standard (CNS) A4 specification (210X 297 mm) 564313

造：試台測試一積體電路的方法。該方法最好包括步驟： 獲得用於一積體電路設計之虛擬元件區塊的功能層級診斷 測試；將該等診斷測試轉換成準確定時的診斷測試；將該 等準確i時的#斷測試轉換成記憶體載入指以及應用 一用於一受測裝置之介面協定於該等記憶體載入指令。 本發阶在第十五方面爲一電腦可讀的媒體，其上儲存一 連_的指令，用於指出及測試一已製造完成之積體電路。 該一連串指令用於執行一組動作的集合，包括⑷指出虛擬 兀件區塊；（b)指出虛擬元件區塊之間的互連；指出用於 測試已製造完成之虛擬元件區塊的診斷測試的集合；（句指 出用於測試已製造芫成之積體電路的測試向量的集合。 本發明在第十六方面爲一電腦可讀的媒體，其上儲存一 連串用於產生及/或轉譯用於在一製造測試台測試一積體 電路的測試向量。該等一連串的指令用於執行一組動作的 集合’包括（a)指出用於測試該積體電路之一功能規格的功 能階I測試向量；（b)將該等測試向量轉譯成訊息區塊； (c) 應用一介面協定於該等訊息區塊以產生測試向量資料； (d) 應用遠積體電路之一介面協定於該測試向量資料。 本發明在第十七方面爲一製造一電可腦可讀之媒體的方 法’該媒體中儲存一積體電路之設計及一組用於製造及測 試已製造完成之積體電路之功能的測試輸入。該方法最好二 包括步驟：（a)設計要用在積體電路之設計的虛擬元件區塊 ;(b)針對每一虛擬元件區塊設計一個特別的診斷測試； (c)決定包含該虛擬元件區塊之積體電路的設計；（d)獲得 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公袭:） 564313 A7 B7 五、發明説明（13 ) 圖9A爲圖7所提及之摺回機制之一較佳實作例，其中該 擅回機制完全地駐在該受測晶片上。 圖9B爲圖7所提及之摺回機制之另一較佳實作例，其中 測試資料從一 PCI介面寫出，然後再從一 I/O接點寫出。 圖10爲一探測卡以及至一 DUT及測試器之介面卡的實體 配置圖。- 圖11爲一晶片製造測試程序之較佳測試順序的流程圖。 較佳具體實施例詳細説明 以下將參考附圖來説明較佳具體實施例。然而，首先要 先討論與電子設計自動化（EDA)軟體工具相關的一般背景 資訊。 如先前發明背景一節中所討論者，晶片設計者通常使用 由上而下的設計方法，例如，使用Verilog®或VHDL等硬體 描述語言（HDLs)，以階層式的方式，定義電路的功能元件 ，然後把每一個元件分解成愈來愈小的元件，來建立一積 體電路。積體電路中所使用的元件可歸類爲功能或是通訊 的元件或區塊。 就HDL或其它高階描述語言而言，實際的邏輯基本單元 (logic cell)實作一般而言是由邏輯合成來決定，邏輯合成將 電路的功能描述轉換成特定的電路實作。該電路實作通常 爲一網表的形式，其中包括邏輯基本單元或元件區塊，且_ 包括一個或以上的通訊區塊。然後該等實體區塊被佈放以 及接線，得到一個實體配置檔。該實體配置檔通常被用作 製造積體電路的設計藍圖。在設計程序的每一個階段以及 -16- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313 A7 B7 五、發明説明（16 ) 以該配置資料庫195作爲和該大量儲存裝置的介面。配置 資料庫195可以使用任何傳統的資料庫標準加以實作，例 如EDIF、LEF或DEF。電腦110亦可包含或連接到含有一個 或多個組件庫（未畫出）的大量儲存裝置，該組件庫指出可 供電路設計所使用之電子元件的特徵。 請參斧圖2，圖示爲一簡化的1C 200的例子的方塊圖，其 中指出一個基礎區塊202和若干個週邊元件區塊B1，...，B12 及它們在積體電路200上的位置，它們之間的連線已經確 定。實際上，在更眞實的積體電路設計中，積體電路200 可能更爲複雜。然而，圖2係作爲説明的目的。基礎區塊 202最好包括一個處理器204、一個記憶體206、若干個其它 的元件A1, ...，A5和一個包含一匯流排208和12個埠210的通 訊區塊。埠210最好是陰陽同體（androgynous)的，其中每一 個皆可在積體電路200完成配置時被設定成目標（target)或起 始器（initiator)。基礎區塊202，包括其元件（處理器204、記 憶體206和元A1到A5)，及其它週邊元件區塊最好在配置資料 庫195中都有完整的描述。最好是，該等區塊之放置就位 置及連接到基礎區塊202上之埠的長度而言是最佳化的。 圖3爲一以區塊爲基礎之電路設計之一般程序的流程圖 300，圖中畫出前述抽象積體電路設計之各個階層中的一 部份。如圖3所示，一個形式爲HDL檔案或其它高階功能- 描述之註册轉移邏輯（RTL)檔案301經歷一個規定（平面規劃 及部份指派）程序302。在此一程序302中，元件區塊從一個 組件庫306中被找出來以便執RTL檔案301中的特定功能。 -19- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）Manufacturing: The method of testing a integrated circuit on a test bench. The method preferably includes the steps of: obtaining a functional-level diagnostic test of a virtual component block for an integrated circuit design; converting the diagnostic test into an accurately timed diagnostic test; converting the accurate #off test at the time Memory loading means and applying an interface protocol for a device under test to the memory loading instructions. In the fifteenth aspect, this stage is a computer-readable medium, which stores a series of instructions for pointing out and testing a completed integrated circuit. The series of instructions are used to perform a set of actions, including: pointing out virtual component blocks; (b) pointing out interconnections between virtual component blocks; pointing out diagnostic tests for testing completed virtual component blocks (The sentence indicates the set of test vectors used to test the fabricated integrated circuit. The present invention in a sixteenth aspect is a computer-readable medium on which a series of files for generating and / or translating are stored. Test vectors for testing an integrated circuit in a manufacturing test bench. The series of instructions used to perform a set of actions' includes (a) a functional order I test that specifies a functional specification of the integrated circuit Vector; (b) translate the test vectors into message blocks; (c) apply an interface protocol to the message blocks to generate test vector data; (d) apply an interface protocol to a remote integrated circuit for the test Vector data. The present invention in a seventeenth aspect is a method for manufacturing an electrically brain-readable medium. The medium stores a design of an integrated circuit and a set of products for manufacturing and testing the finished product. Test input for the function of the circuit. The method preferably includes two steps: (a) designing virtual component blocks to be used in the design of the integrated circuit; (b) designing a special diagnostic test for each virtual component block; (c) Determine the design of the integrated circuit containing the virtual component block; (d) Obtain -14- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public attack :) 564313 A7 B7 V. Invention Explanation (13) FIG. 9A is a preferred implementation example of the retracement mechanism mentioned in FIG. 7, where the revocation mechanism resides entirely on the chip under test. FIG. 9B is a diagram of the retracement mechanism mentioned in FIG. Another preferred implementation example, in which test data is written from a PCI interface, and then from an I / O contact. Figure 10 is a physical configuration diagram of a probe card and an interface card to a DUT and tester. -Figure 11 is a flowchart of a preferred test sequence for a wafer manufacturing test procedure. Detailed Description of the Preferred Embodiments The preferred embodiments will be described below with reference to the drawings. However, first, the electronic design automation (EDA) General background information about software tools As discussed in the Background of the Invention section above, chip designers often use a top-down design approach, for example, using hardware description languages (HDLs) such as Verilog® or VHDL to define the functional elements of the circuit in a hierarchical manner. , And then decompose each component into smaller and smaller components to build an integrated circuit. The components used in integrated circuits can be classified as functional or communication components or blocks. HDL or other high-level descriptions In terms of language, the actual logic cell implementation is generally determined by logic synthesis, which translates the functional description of a circuit into a specific circuit implementation. The circuit implementation is usually a netlist Form, which includes a logical basic unit or component block, and _ includes one or more communication blocks. These physical blocks are then laid out and wired to get a physical configuration file. This physical profile is often used as a design blueprint for manufacturing integrated circuits. At each stage of the design process and -16- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 A7 B7 V. Description of the invention (16) The configuration database 195 is used as the large number Interface to the storage device. The configuration database 195 can be implemented using any traditional database standard, such as EDIF, LEF, or DEF. The computer 110 may also include or be connected to a large number of storage devices containing one or more component libraries (not shown) that indicate the characteristics of the electronic components available for circuit design. Please refer to FIG. 2, which is a block diagram of an example of a simplified 1C 200, which indicates a basic block 202 and several peripheral component blocks B1, ..., B12 and their components on the integrated circuit 200. Location, the connection between them has been determined. In fact, in a more solid integrated circuit design, the integrated circuit 200 may be more complicated. However, FIG. 2 is for illustrative purposes. The basic block 202 preferably includes a processor 204, a memory 206, several other components A1, ..., A5, and a communication block including a bus 208 and 12 ports 210. Port 210 is preferably androgynous, and each of them can be set as a target or initiator when the integrated circuit 200 is configured. The basic block 202, including its components (processor 204, memory 206, and elements A1 to A5), and other peripheral component blocks are preferably fully described in the configuration database 195. Preferably, the placement of such blocks is optimized in terms of location and the length of the ports connected to the base block 202. FIG. 3 is a flowchart 300 of a general procedure of a block-based circuit design. The figure shows a part of each layer of the aforementioned abstract integrated circuit design. As shown in FIG. 3, a registration transfer logic (RTL) file 301 in the form of an HDL file or other high-level function-description undergoes a prescribed (planning and partial assignment) procedure 302. In this procedure 302, a component block is found from a component library 306 to perform a specific function in the RTL file 301. -19- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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k 564313 A7 B7 五、發明説明（17 ) 該等元件區塊最好是預先定義好的，不過，它們中的一個 或多個可基於並未儲存或最近才儲存到組件庫306中的自 訂的設計。 下一個步驟303中，執行一邏輯合成，在一較佳具體實 施例中，元件間之連接的功能描述被轉換成能夠以一網表 檔案304之形式儲存之一特殊連接實作。此一編譯程序303 的一部份通常會參考組件庫306，組件庫306儲存與通訊介 面相關的資訊以及元件的特徵，這些是在決定其功能上的 連接性時所必須的。如前述，網表檔案304通常會從組件 庫306中找出該等元件區塊，並描述特定的元件對元件的 連接性。 然後，利用圖3所示的實體設計程序309來佈放網表檔案 304並加以接線，而得到一配置檔案3 10。在這個處理階段 過程中會利用組件庫306，以便獲得關於網表檔案304中可 能呈現之組件大小的資訊。以前，此資訊包括介面規格， 例如介面的數量和位置，不論每一個該等介面爲一目標 (target)或起始器（initiator)，以及接點的數量和它們的訊號 分派。如前面發明背景一節所述，接下來是進行放置和接 線的動作，這些動作可以用讓積體電路的最終性能達到最 佳的方式加以自動化，作法是最小化連線長度和積體電路 的總體足跡（footprint)。然而，此一放置及接線的程序需遵_ 守從組件庫306所得到的介面規格。 進一步如圖3所示，利用配置檔310，可執行一驗證程序 312，而得到一個GDSII或GIF格式的遮蔽檔315。遮蔽檔315 -20- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐）k 564313 A7 B7 V. Description of the invention (17) These component blocks are preferably predefined, but one or more of them can be based on customizations that have not been stored or have been recently stored in the component library 306 the design of. In the next step 303, a logic synthesis is performed. In a preferred embodiment, the functional description of the connection between the components is converted into a special connection implementation that can be stored in the form of a netlist file 304. A part of this compiler 303 usually refers to the component library 306. The component library 306 stores information related to the communication interface and the characteristics of the components, which are necessary in determining its functional connectivity. As mentioned above, the netlist file 304 usually finds these component blocks from the component library 306 and describes the specific component-to-component connectivity. Then, the physical design program 309 shown in FIG. 3 is used to lay out and connect the netlist file 304 to obtain a configuration file 310. The component library 306 is utilized during this processing phase in order to obtain information about the size of the components that may be present in the netlist file 304. Previously, this information included interface specifications, such as the number and location of interfaces, whether each such interface was a target or initiator, and the number of contacts and their signal assignments. As mentioned in the Background of the Invention section above, the next steps are placement and wiring. These actions can be automated in a way that maximizes the final performance of the integrated circuit by minimizing the length of the wiring and the overall integrated circuit. Footprint. However, this placement and wiring procedure must comply with the interface specifications obtained from the component library 306. As further shown in FIG. 3, using the configuration file 310, a verification procedure 312 can be performed to obtain a mask file 315 in GDSII or GIF format. Mask 315 -20- This paper size applies to China National Standard (CNS) A4 (210X297 mm)

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線 564313 A7 _19_5!__ 五、發明説明（ ） 同階段測試電路設計。可應用測試向量420來測試功能設 計檔案401的功能。相同的測試向量420若經過適當的轉譯 ，亦可用來測試網表檔案404及/或配置擋案410。 在一較佳具體實施例中，利用一資料庫430，以複數個 虛擬元件區塊440的形式來儲存虛擬元件區塊資料43 1，以 及以診斷測試輸入集合441的形式來儲存診斷資料432。每 一個診斷測試的集合441係針對一特定虛擬元件區塊440的 特殊架構量身訂做。因此，一診斷測試集合441係與一特 定的虛擬元件區塊440相關連。此觀念在圖4中以資料庫430 中的虛擬元件區塊1...N和它旁邊的診斷測試集合1...N來表 不。母次在一特定的虛擬元件區塊440被用在一設計中時 ，最好是使用與該虛擬元件區塊相關的同一個診斷測試集 合441，因爲它已經被特別準備好要用在該虛擬元件區塊 440的架構上。或者，給定·-虛擬元件區塊440，可以提供 多個診斷測試集合441。 虚擬元件區塊440是設計大尺度電路的資源。虛擬元件 區塊440可部份被預先定型（從邏輯和功能的觀點）及被預先 測試和預先驗證。一般而言，儘可能讓更多的虛擬元件區 塊440内部電路預先定型，而外部連接（例如接點的位置）可 以是「軟性」的或在虛擬元件區塊440產生之後是可以作 設定的。可以從資料庫430取出虛擬元件區塊440，並將它^ 結合到功能設計檔案401(或甚至是更低階的檔案）中。由於 虛擬元件區塊440大部份已預先定型，因此它們的内部電 路不需要合成或驗證，亦不需要佈放或接線。相反地，虛 -22- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Line 564313 A7 _19_5! __ 5. Description of the invention () Test circuit design at the same stage. The test vector 420 may be applied to test the function of the function design file 401. The same test vector 420 can also be used to test the netlist file 404 and / or the configuration file 410 if properly translated. In a preferred embodiment, a database 430 is used to store the virtual component block data 43 1 in the form of a plurality of virtual component blocks 440, and the diagnostic data 432 is stored in the form of a diagnostic test input set 441. Each set of diagnostic tests 441 is tailored to the specific architecture of a specific virtual element block 440. Therefore, a diagnostic test set 441 is associated with a specific virtual element block 440. This concept is shown in FIG. 4 by the virtual component blocks 1 ... N in the database 430 and the diagnostic test set 1 ... N next to it. When a specific virtual component block 440 is used in a design, it is best to use the same diagnostic test set 441 associated with the virtual component block, because it is specifically prepared for use in the virtual The architecture of the element block 440. Alternatively, given the virtual component block 440, multiple diagnostic test sets 441 may be provided. The virtual element block 440 is a resource for designing a large-scale circuit. The virtual component block 440 may be partially pre-shaped (from a logical and functional point of view) and pre-tested and pre-validated. Generally speaking, as much as possible, let the internal circuit of more virtual component block 440 be predetermined, and the external connection (such as the position of the contact) can be "soft" or can be set after the virtual component block 440 is generated . The virtual component block 440 can be taken from the database 430 and incorporated into the functional design file 401 (or even a lower-level file). Since most of the virtual component blocks 440 are pre-shaped, their internal circuits do not need to be synthesized or verified, nor need they be laid or wired. In contrast, the virtual -22- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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線 564313Line 564313

如疋元件區塊440係整個被放到整體的電路設計中，並連接 到其它設計元件。 在驗澄階段以及在半導體晶圓460之製造及/或積體電路 之封裝之後，應提供測試設計的辦法，作爲設計程序的一 #份。具體地説，用於測試基於掃描之測試的性能的掃描 邏輯取好疋在網表的階層結合到設計中。因此，在設計之 此一階層’會產生與該縮減遮蔽檔415對應的掃描樣式以 供製造階段使用。同樣地，把邏輯結合到積體電路QC)的 設計中，以便執行内建的自我測試（BISTs)。當提供一特定 的測試訊號給裝置時’該製造好的1C會自動執行這些測試。 於是’用於該1C的遮蔽構案和得自設計和驗證階段的輸 入被包裝起來送到壓鸽廒，開始製造的程序。在一具體實 知例中’该等測試輸入包括適合於製程環境的診斷測試輸 入和測試向量的集合，且最好包括用於起始BISTy々掃描樣 式和知入k號的集合。例如，該等測試輸入（亦即，診斷 測試、應力測試、基於掃描的測試和BIST測試）可適用於 —壓鑄廠在製造及測試操作時所專用的測試台450。這也b 測試輸入最好包括在擁有智慧財產權之電腦可讀的套裝軟 體中，其中包括提供給鑄造廠之該1C遮蔽檔案。 在一具體實施例中，該等診斷測試輸入和測試向量係直 接輸入到製造測試台450，並由測試台450加以轉譯以便靡， 用於受測裝置（DUT)。例如，測試台450中的一個測試轉譯 器（亦即轉譯功能）可包括一個以處理器（例如，多用途處 理器）執行的軟體，其中該軟體最好亦包括在該擁有智攀、 -23- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公爱) 五、發明説明（21 ) 4產權的套裝軟體中，用於在測試資料被輸入到丁之前 加以轉澤。另一可能的作法是，把該等經過轉譯的診斷測 試和測試向量納入到提供給鑄造廠之具有智慧財產權的套 裝軟體中’如此’測試台450便不需要與此功能相當的測 試轉譯器。 圖3所-示爲一用於穩健地測試複雜積體電路之測試台5〇〇 的較佳具體實施例，不論是規劃於晶圓上或加以封裝，從 每一晶圓（或封裝）的測試時間和測試成本而言，都是可行 的。測試台500最好包括一個測試台5〇2和一塊探測卡5〇4， 探測卡上放置要測試的個別IC晶圓。探測卡5〇4最好針對1(： 的没计汀製且包括多個元件，以便不需要和測試器5〇2作 高頻寬通訊即可啓動耶丁的at-speed測試。 測试台500之設計一般而言最好能夠達成傳統製造測試 功能以外的若干個目標。第一，測試台5〇〇使用先前已產 生的測试輸入來完成1C的驗證階段。第二，測試台5〇〇被規 劃成對DUT本身，其次對探測卡504，最後對測試器5〇2進 行密集處理（processing-intensive)的測試操作，而且測試的 方式係使件測試^§» 502和探測卡504之間的I/O達到最少。第 三，測試台500規劃測試的順序使每一 DUT的平均測試時間 達到最短。最好是，該測試順序係針對每一個1C設計訂製。 在·具體實施例中’測試器502最好包括一個測試控制_ 器510、一個測試輸入轉譯器506和一個測試排程器508。測 試控制器510最好控制整體測試操作，且最好包含用於探 測卡504之一般測試指令。測試輸入轉譯器506轉譯得自ic -24- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313Rugao component block 440 is put into the overall circuit design and connected to other design components. During the verification phase and after the fabrication of semiconductor wafer 460 and / or the packaging of integrated circuits, a test design approach should be provided as part of the design process. Specifically, the scan logic used to test the performance of the scan-based test is taken into account and incorporated into the design at the hierarchy of the netlist. Therefore, at this level of design, a scan pattern corresponding to the reduced mask file 415 is generated for use in the manufacturing stage. Similarly, the logic is integrated into the design of the integrated circuit (QC) to perform built-in self-tests (BISTs). When a specific test signal is provided to the device, the manufactured 1C will automatically perform these tests. So 'the masking scheme for this 1C and the inputs from the design and verification stages are packaged and sent to the dovetail to begin the manufacturing process. In a specific practical example, the test inputs include a set of diagnostic test inputs and test vectors suitable for a process environment, and preferably include a set of starting BISTy (R) scan patterns and a known k number. For example, such test inputs (ie, diagnostic tests, stress tests, scan-based tests, and BIST tests) may be applicable to a test bench 450 that is dedicated to the die-casting plant during manufacturing and testing operations. This alsob The test input is preferably included in a computer-readable software package with intellectual property rights, including the 1C masking file provided to the foundry. In a specific embodiment, the diagnostic test inputs and test vectors are directly input to the manufacturing test stand 450 and translated by the test stand 450 for use in a device under test (DUT). For example, a test translator (ie, a translation function) in the test stand 450 may include a software (for example, a multi-purpose processor) executing software, wherein the software is preferably also included in the owning Zhipan, -23 -This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love). 5. Description of the invention (21) 4 The property right software is used to convert the test data before it is input into Ding. Another possible approach is to incorporate such translated diagnostic tests and test vectors into the intellectual property packaged software provided to the foundry, so that the test stand 450 does not require a test translator equivalent to this function. Figure 3 shows a preferred embodiment of a test bench 500 for robustly testing complex integrated circuits, whether it is planned on a wafer or packaged, from each wafer (or package). Both test time and test cost are feasible. The test bench 500 preferably includes a test bench 502 and a probe card 504 on which individual IC wafers to be tested are placed. The detection card 504 is preferably aimed at the 1 (:) system and includes multiple components, so that it does not require high-frequency communication with the tester 502 to start the at-speed test of Yeding. The design is generally best to achieve several goals beyond traditional manufacturing test functions. First, the test bench 500 uses previously generated test inputs to complete the 1C verification phase. Second, the test bench 500 is The DUT itself is planned as a pair, followed by the probe card 504, and finally a processing-intensive test operation is performed on the tester 502, and the test method is based on the test between the 502 and the probe card 504. I / O reaches the minimum. Third, the test sequence of the test bench 500 is planned to make the average test time of each DUT the shortest. Preferably, the test sequence is customized for each 1C design. In the specific embodiment ' The tester 502 preferably includes a test controller 510, a test input translator 506, and a test scheduler 508. The test controller 510 preferably controls the overall test operation and preferably includes general tests for the probe card 504 Instruction. Test input translator 506 translated from ic -24- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313

開發之驗證階段的測試向量和診斷測試，以便應用到製造 測試環境中。或者，可選擇讓轉譯的動作在探測卡5〇4 (請 見圖10的資料轉譯n 1004,在下文中討論）或測試台5〇〇上 的/、b地方進行。如别述，在一積體電路詳細設計的驗證 階段，最好產生一些診斷測試來驗證虛擬積體電路中每一 個虛k元件區塊的效能。此外，最好產生具有不同階層劃 刀（varying leveis of refinement)之測試向量以便測試虛擬冗的 整體效能。 測試排程器508控制一 1C設計之測試的執行順序。最好是 測4排程器508排定測試的順序使得每一 的整體測試 時間達到最短。測試排程器5〇8可實作在一個多用途或特 殊用途處理器的軟體中、完全實作在硬體中，或實作成硬 把和軋體的結合。或者，可選擇將測試排程器5〇8的功能 囊括於要提供給壓鑄廠之擁有智慧財產權的電腦可讀的套 裝叙體中（亦即，遮蔽檔案、探測卡504及測試輸入）。 圖6A所tf爲將針對一 IC設計之驗證階段所設計之測試向 臺和％斷測試轉譯成對每一個已製造的好IC個別作測試之 製造階段的較佳方法6〇〇。或者，可選擇使用如前述及圖5 所不I執行轉譯程序且包含軟體、硬體或此兩者之任何結 合的測試-輸入轉譯器來實作測試輸入轉譯方法600。在轉 澤驗證測試時，就用於測試個別元件區塊的診斷測試而言< 在第一個步驟602中，提供設計用於測試一組虛擬元件 的衫斷測試。最好是，一個群組的診斷測試可分解成若干 個測4的集合，每一個集合對應於在IC上有實體代表的— -25- 本紙張尺度適財s s家標準(CNs) A4規格(21〇 I297公釐） 564313 A7 B7 五、發明説明（23 ) 特定的虛擬元件區塊D毐一徊各赵 思母個％ fe/f測試的集合最好只測試 -個元件區塊，且通常並不測試其它元件區塊的任何部份 。此外ϋ診斷測試的集合最好不使用或幾乎不使用 其^件區塊來完成它所對應之元件區塊的測試。 -旦提供了具有與測試無關之元件的診斷測試，下一個 步驟_是獲得使資料能夠相對於—特定架構作交易的診 斷4 λ其疋’ 4等侍自步碟6Q2的診斷測試可能是針 對一特定功能’而不是針對該功能之一特定架構。在一具 體實施例中，彳能有用於被選擇用來執行該給定功能的架 構的診斷測試可供使用，這種情況下，用於該元件的診斷 測試可以被取回。另一可杆的你 j仃的作法是，針對該新的架構， 在功能層級劃分（reflne)該等診斷測試。例如，一個功能層 級的診斷測試可爲對該功能重覆作叠代之CW常式的形 式。要將該診斷測試劃分成爲特定架構的層級，可將該C- code常式轉換成組合碼描述語言（亦即，⑼記憶性指令轉換 成進U 7 )。在此一層級，可以使用診斷測試來驗證 元件區塊的功能以及在製程測試中所需之實體區塊中的位 元錯誤（bit failure)。 在下個y叛606中’沴斷測試被轉換成用在製造測試 台的記憶載人指令。該等記憶栽人指令的形式與測試是要 從測試器-、探測卡還是要在測試台上的受測裝置（dut)執： 行有關。測試最好是從DUT執行，或者，#不可行或沒有 幫助’則從探測卡執行。一旦決定，診斷測試便被固定到 I·夬取或疋暫存$ $憶體中的_組特定的位址，端視快取 -26 564313 A7 B7 五、發明説明（25 ) 段。然後，在下一個步驟612中，根據1C設計所採用的介面 型式，使用點對點介面協定，例如前面所討論的VCI協定 ，來格式化該等訊息區塊。最後一個步驟616，經過適當 格式化的診斷測試和測試向量被當作分開的區塊載入到 DUT中並作爲標準製造測試方法的一最佳測試程序的一部 份執行。-(請見圖11 )。 圖6B所示爲將測試從虛擬1C設計之驗證階段移植到用於 證明設計之眞實1C測試的製造階段。在一設計驗證階段中 ，可以利用不同的層級來描述測試向量。亦即，一組測試 向量可能適用於一較高或功能層級的設計，而其它的向量 可能適用於更細節或硬體設計之特定的架構層級。然後應 用設計驗證程序中測試輸入劃分之變化層級的觀念，將一 驗證環境中之功能測試向量移植成一製造測試環境中有用 的測試向量。如圖6B所示，利用開發用來劃分功能測試向 量的軟體模組，功能測試向量在測試一晶片所需之準確定 時層級不斷地被劃分成測試輸入。如圖6B所示，可執行類 似於診斷資料設計的測試資料移植，在以區塊爲基礎的設 计程序中測試虛擬元件區塊。這些診斷測試被擴大，用以 在製程環境中測試與晶片中之虛擬元件區塊互補的實體。 圖10爲一探測卡1000和至一 DUT 1002及一測試器…(^之 介面的具體實施例的配置置圖。此一探測卡1〇〇〇實作係特二 別爲DUT 1002所代表的特定Ic設計所訂製。由於是一訂製 的元件，探測卡1000可以和IC設計程序同時或在IC設計程 序之後的任何方便的時間加以設計。在一具體實施例中， -28- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公董） -------Test vectors and diagnostic tests in the verification phase of development for application to manufacturing test environments. Alternatively, you can choose to have the translating action performed on the probe card 504 (see the data translation n 1004 in Figure 10, discussed below) or at /, b on the test bench 500. As mentioned, in the verification stage of the detailed design of the integrated circuit, it is best to generate some diagnostic tests to verify the performance of each virtual k component block in the virtual integrated circuit. In addition, it is best to generate test vectors with varying leveis of refinement in order to test the overall effectiveness of virtual redundancy. The test scheduler 508 controls the execution order of a 1C design test. It is preferable that the test scheduler 508 schedules the test sequence so that the overall test time of each is minimized. The test scheduler 508 can be implemented in the software of a multi-purpose or special-purpose processor, completely in hardware, or a combination of hard and rolled. Alternatively, the function of the test scheduler 508 may be included in a computer-readable package with intellectual property rights to be provided to the die-casting plant (ie, mask files, probe card 504, and test input). The tf in FIG. 6A is a preferred method of translating the test stage and% breaking test designed for the verification stage of an IC design into the manufacturing stage of testing each good IC individually. Alternatively, the test input translation method 600 may be implemented using a test-input translator that executes the translation process as described above and shown in FIG. 5 and includes software, hardware, or any combination of the two. In the translation verification test, in terms of a diagnostic test for testing individual component blocks < In a first step 602, a break test designed to test a set of virtual components is provided. Preferably, a group of diagnostic tests can be decomposed into a number of test sets, each set corresponding to a physical representative on the IC — -25- this paper standard ss home standards (CNs) A4 specifications ( 21〇I297 mm) 564313 A7 B7 V. Description of the invention (23) Specific virtual component blocks D 毐 Zhao Simu% fe / f test set is best to test only one component block, and usually No part of other component blocks is tested. In addition, the set of diagnostic tests is best not to use or hardly use its block to complete the test of its corresponding component block. -Once a diagnostic test is provided with components that are not related to the test, the next step is to obtain a diagnostic that enables the data to be traded with respect to a specific architecture. A specific function 'is not directed to a specific architecture of that function. In a specific embodiment, no diagnostic test is available for the architecture selected to perform the given function, in which case the diagnostic test for that component can be retrieved. Another good way to do this is to reflne these diagnostic tests at the functional level for the new architecture. For example, a functional level diagnostic test may be in the form of a CW routine that iterates over the function. To divide the diagnostic test into a hierarchy of a specific architecture, the C-code routine can be converted into a combination code description language (that is, the memory instruction is converted into U 7). At this level, diagnostic tests can be used to verify the functionality of the component blocks and bit failures in the physical blocks required in the process test. In the next traitor 606 'test is converted to a memory manned command used to make the test bench. The form of these memory planting instructions is related to whether the test should be performed from the tester-, the probe card, or the test device (dut) on the test bench. The test is best performed from the DUT, or #not feasible or not helpful 'from the probe card. Once determined, the diagnostic test is pinned to a specific group of addresses in I · Capture or Temporary Storage $, the end-view cache -26 564313 A7 B7 V. Description of the invention (25) paragraph. Then, in the next step 612, the message blocks are formatted using a point-to-point interface protocol, such as the VCI protocol discussed earlier, according to the interface type used by the 1C design. In the final step 616, the properly formatted diagnostic tests and test vectors are loaded into the DUT as separate blocks and executed as part of an optimal test procedure for standard manufacturing test methods. -(See Figure 11). Figure 6B shows the migration of testing from the verification phase of a virtual 1C design to the manufacturing phase of proof 1C testing. In a design verification phase, test levels can be described at different levels. That is, a set of test vectors may be suitable for a higher or functional level design, while other vectors may be suitable for a more detailed or hardware specific design level. Then, the concept of the change level of the test input division in the design verification program is applied, and the functional test vector in a verification environment is transplanted into a test vector that is useful in a manufacturing test environment. As shown in FIG. 6B, using software modules developed to divide the functional test vectors, the functional test vectors are continuously divided into test inputs when the required accuracy for testing a chip is determined. As shown in Figure 6B, test data migration similar to diagnostic data design can be performed, and virtual component blocks can be tested in a block-based design program. These diagnostic tests are expanded to test entities in the process environment that are complementary to the virtual component blocks in the chip. FIG. 10 is a configuration diagram of a specific embodiment of a probe card 1000 and a DUT 1002 and a tester ... (^). The implementation of this probe card 1000 is specifically represented by the DUT 1002. Customized by specific IC design. Because it is a custom component, the probe card 1000 can be designed at the same time as the IC design process or at any convenient time after the IC design process. In a specific embodiment, -28- this paper Standards apply to China National Standard (CNS) A4 specifications (210 X 297 public directors) -------

裝 訂Binding

564313 A7 _B7__ 五、發明説明（27 ) DUT 1002或記憶體及控制邏輯1006格式化來自測試器1001 的資料。資料轉譯器1004若實作成爲一可程式的裝置，則 可以使探測卡1000適用於各種不同的積體電路設計，尤其 是共同引導的設計，例如那些可以基於一共同基礎區塊的 設計。 時脈產生器1008具有至測試器1001的控制連線以及至 DUT 1002和記憶體及控制邏輯1006的連線。時脈產生器 1008裝在探測卡1000上以使測試器1001發送高速度時脈的 成本和複雜度減到最低。時脈產生器1008最好裝在探測卡 1000上，其部份原因是DUT 1002通常不包括用於驅動時脈 的石英振盪器，雜訊也是要考量的可能因素。 類比訊號產生器1012包括至測試器1001和DUT 1002的連 線。此外，探測卡1000最好提供直接的測試器介面1014以 便從測試器1001直接測試DUT 1002。探測卡1000還提供介 於測試杏1001和DUT 1002之間的掃描測試介面1 〇 1 〇，以允 許測試器在DUT 1002内部的不同邏輯點上直接進行掃描測 試。 圖7描述測試台的一些有助於執行擴大到製程環境之測 試向量和診斷測試的較佳特徵。這些特徵主要是利用DUT 的處理和記憶能力，其次是利用探測卡，來完成測試。對 於不同的Ι-C設計而言，可能不具備其中一些特徵，因爲有-些特徵只對於具有特定屬性的設計是有幫助的。 其中一項較佳的特徵爲，晶片上的記憶體，最好是快取 圮憶體，是可以鎖定的，如此可確保已載入的診斷測試不564313 A7 _B7__ 5. Description of the invention (27) The DUT 1002 or the memory and control logic 1006 formats the data from the tester 1001. If the data translator 1004 is implemented as a programmable device, the probe card 1000 can be applied to various different integrated circuit designs, especially co-directed designs, such as those that can be based on a common basic block. The clock generator 1008 has a control connection to the tester 1001 and a connection to the DUT 1002 and the memory and control logic 1006. The clock generator 1008 is mounted on the detection card 1000 to minimize the cost and complexity of the tester 1001 sending high-speed clocks. The clock generator 1008 is best installed on the detection card 1000. Part of the reason is that the DUT 1002 does not usually include a quartz oscillator for driving the clock. Noise is also a possible factor to consider. The analog signal generator 1012 includes connections to the tester 1001 and the DUT 1002. In addition, the probe card 1000 preferably provides a direct tester interface 1014 to directly test the DUT 1002 from the tester 1001. The probe card 1000 also provides a scanning test interface 1 0 1 0 between the tester 1001 and the DUT 1002 to allow the tester to directly perform the scan test at different logical points inside the DUT 1002. Figure 7 depicts some of the preferred features of the test bench that facilitate the execution of test vectors and diagnostic tests that extend to the process environment. These features mainly utilize the processing and memory capabilities of the DUT, followed by the use of the probe card to complete the test. For different I-C designs, some of these features may not be available, because some features are only helpful for designs with specific attributes. One of the better features is that the memory on the chip, preferably a cache memory, can be locked, so as to ensure that the loaded diagnostic tests are not

564313 A7 __ B7 五、發明説明（3〇 ) 晶片傳送到探測卡1〇〇〇上。在圖9八中，利用一邏輯狀態使 得能夠在其中一個I/C)接點9〇2處同時讀取及寫入測試資料 。在此一邏輯狀態中，一個例如已經載入到DUT之記憶體 中的測試係由該裝置利用DUT上用來處理I/O運作的處理器 來執行。讀出來的測試資料被摺回到要被讀取之其内有加 總查核的-晶片中。該摺回邏輯係整合到1C設計中，且用於 在製造時提升1C測試的效率。該等摺回亦可内建於DUT内 各別的電路區塊中以改善該等區塊之測試效率。當Dut或 個別的區塊同時包括類比輸入及類比輸出時，可將類比訊 號摺回設計到積體電路中。 圖9B爲一摺回邏輯91〇之另一具體實施例，其中，測試 資料係從一晶片920上之一通訊介面912 (例如PCI介面）寫出 ，然後再從一 I/O接點914寫出。一晶片外（0ff_chip)通訊介 面916 (例如PCI介面）剝除協定資訊並傳送原始測資料至一 總計查核918。然後通訊介面916把資料摺回到晶片920中。 在測試結束時，可以將得自DUT 920的一個總計查核（未畫 出）與探測卡1000上的總計查核918作比較，以隔離任何發 生錯誤的位置（亦即，到DUT的輸入或從DUT的輸出）。由 於探測卡1000具上有總計查核916，因此資料可以不需要傳 送到測試器。在一具體實施例中，係經由一個串列輸入/ 輸出（SIO)接點922摺回910到晶片920中。在另一具體實施例= 中，如圖9A所示，摺回到晶片的動作還會驅動探測卡1〇〇〇 上的一個外部總計查核，以隔離任何，發生錯誤的位置。該 晶片外（off-chip)邏輯係内建在探測卡1000的設計中，而且 -33- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 564313564313 A7 __ B7 V. Description of the invention (30) The chip is transferred to the detection card 1000. In Figure 9-8, a logic state is used to enable simultaneous reading and writing of test data at one of the I / C) contacts 902. In this logical state, a test, for example, that has been loaded into the memory of a DUT, is performed by the device using a processor on the DUT that handles I / O operations. The read-out test data is folded back into the wafer to be read with a total check. This foldback logic is integrated into the 1C design and is used to improve the efficiency of 1C testing during manufacturing. These retracements can also be built into individual circuit blocks within the DUT to improve the test efficiency of these blocks. When Dut or individual block includes both analog input and analog output, the analog signal can be designed back into the integrated circuit. FIG. 9B is another specific embodiment of a wrap-around logic 91. The test data is written from a communication interface 912 (such as a PCI interface) on a chip 920, and then written from an I / O contact 914. Out. An off-chip (0ff_chip) communication interface 916 (such as a PCI interface) strips the protocol information and sends the original test data to a total check 918. The communication interface 916 then folds the data back into the chip 920. At the end of the test, a total check (not shown) obtained from the DUT 920 can be compared to the total check 918 on the probe card 1000 to isolate any place where an error occurred (ie, to the DUT input or from the DUT). Output). Since there are a total of 916 checks on 1000 probe cards, the data may not need to be transferred to the tester. In a specific embodiment, it is folded back 910 into the chip 920 via a serial input / output (SIO) contact 922. In another specific embodiment, as shown in FIG. 9A, the action of turning back to the wafer will also drive an external total check on the probe card 1000 to isolate any place where an error occurs. The off-chip logic system is built into the design of the probe card 1000, and -33- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 564313

可實作於例如圖_示的資料轉譯器中。 μ再參考圖7 ’圖π之額外特點可幫助測試，而 不而要成本極问的測試器。這些額外的特點將探測卡和測 4器I間的頻寬取小化而無損於而了在心測試上的要 求。在-具體實施例中，該探測卡包含大量的記憶體，用 以Its小通到測4器的頻寬（例如5〇〇 mbits的RAM)。藉由把 大量的記憶體從測$器移到探測卡上，冑能在^連到測 =器=情況下，於DUT和探測卡之間進行一些特定的高速 資料交易。例如，相對於測試器和探測卡之間的頻寬而言 ,雖然資料在探測卡和DUT之間以高速度傳送，但資料傳 送很少發生突增的情況。因此，藉由在探測卡上安裝一 FIFO ’資料便能㈣規律地從測試器傳送到探測卡，使得 資料以高速爆量傳送離開FIFC^，j DUT時可維持在fif〇中。 雖然探測卡上使用愈多的記憶體，其成本愈高，但儘量使 用做在晶片上的記憶體可使這些成本達到最少。此外，相 對於把記憶體分攤到所有可能要被測試的晶片上，在探測 卡上增加記憶體的成本是很低的。 該測試台之另一較佳特點爲，該DUT之類比介面係有效 率地被轉換成數位介面。此一轉換係藉由在測試卡上安裝 一個類比訊號產器而達成。在一較佳具體實施例中，並不 以測試器傳送類比測試訊號到DUT的類比介面，而是從測、 試器傳送代表特定類比訊號之數位碼到探測卡。然後，根 據來自測試器的數位訊號碼，探測卡產生適當的類比訊號 ，並提供該訊號給DUT作爲輸入。 -34- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313 五、發明説明（ 此外’從驗證階殺 ,^ _ 又知植過來的測試向量和診斷測試及其 ΰ w I的(例如掃描測試）最好是以最少量的形式從 傳送到探測卡以使測試台之兩元件之間的頻寬負擔 \— 例如，沴斷測試最好是以傳送到探測卡的一個 短字串加以參昭。紗、、 、 ’、、、…、後琢罕串最好執行一密集處理的測試 以除去任何因A測試器而造成的頻寬限制。該短字串可爲 ，弋表儲存在抓測卡上之測試向量的代碼的形A。或者， 該字_可代表-個用於執行耗時測試之眞實的診斷測試， 然後選擇性地自動被探測卡修改以產生額外的診斷測試。 在測試向量方面，測試器可規劃成只傳送一組與測試向量 相關的關鍵功把性資訊，以及提供探測卡上的邏輯以產生 l田的U n這些控制訊號會被應用到而了以便執行 K亦可選擇性地根據測試器所提供的一個掃描樣式辨 視器，在探測卡上產生基於掃描的測試。 另較佳特徵爲，讓探測卡和DUT使用分開的電源供應 ，以保護DUT。藉由讓電源供應分開，在打開一個即丁的 電源時，便不需要爲每一個贿循環切換探測卡的開關。 此外，藉由維持分開的電源，可更容易執行與切換dut電 源有關的測試。例如，藉由讓探測卡和DUT使用分開的電 源供應，可以在電力從DUT之分開的電源提供過來時，檢 查該DUT的電流。 一- 該測試台尚有另一較佳特徵爲，在測試器和DUT的接點 之間具備直接的介面。利用這些介面，可以執行DUT的類 比檢查，例如該等接點之驅動器的驅動強度和電壓位準。 -35- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂 線 告本 申請曰期 队π——一」 案 號 090115780 類 別 G\〇( ^ ^/(τν 以上各欄由本局填註） )¾ 3· 19 倏!下 年月日^ /了補无 Α4 C4 中文說明書替換頁(92年3月）564313 中 is名稱 黑J專利説明書 文 測試積體電路之方法及裝置，用於測試一受測試裝置之探測卡，產生測試向 量之方法’具有用於測試受測試裝置及產生測試向量之指令之電腦可讀取媒 體’以及用於產生診斷測試之方法 英 文 "METHOD AND APPARATUS FOR TESTING AN iNTEGRATED CIRCUIT, PROBE CARD FOR TESTING A DEVICE UNDER TEST, APPARATUS FOR GENERATING TEST VECTORS, COMPUTER-READABLE MEDIUM HAVING INSTRUCTIONS FOR TESTING A DEVICE UNDER TEST AND GENERATING TEST VECTORS, AND METHOD FOR GENERATING DIAGNOSTIC TESTS” 姓 名 國 籍It can be implemented in, for example, a data translator as shown in FIG. Refer back to Figure 7 'for additional features of Figure π to help test without the costly tester. These additional features minimize the bandwidth between the probe card and the tester I without compromising the requirements on the heart test. In a specific embodiment, the detection card contains a large amount of memory, and it is used to pass the bandwidth of the tester to the tester (for example, 500 mbits of RAM). By moving a large amount of memory from the tester to the probe card, it is possible to perform some specific high-speed data transactions between the DUT and the probe card in the case where the tester is connected to the tester. For example, compared to the bandwidth between the tester and the probe card, although data is transmitted at a high speed between the probe card and the DUT, there is rarely a sudden increase in data transfer. Therefore, by installing a FIFO 'on the probe card, the data can be regularly transmitted from the tester to the probe card, so that the data is transmitted away from the FIFC at a high-speed burst, and j DUT can be maintained in fif0. Although the more memory used on the probe card, the higher the cost, but using the memory on the chip as much as possible can minimize these costs. In addition, the cost of adding memory to the probe card is very low compared to allocating memory to all the chips that may be tested. Another preferred feature of the test bench is that the analog interface of the DUT is efficiently converted to a digital interface. This conversion is achieved by installing an analog signal generator on the test card. In a preferred embodiment, the tester does not transmit the analog test signal to the analog interface of the DUT, but transmits the digital code representing the specific analog signal from the tester to the probe card. Then, based on the digital signal number from the tester, the probe card generates the appropriate analog signal and provides the signal to the DUT as input. -34- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 V. Description of the invention (In addition, 'from the verification stage, ^ _ also know the test vectors and diagnostic tests that have been planted and their ΰ w I (such as a scanning test) is best transmitted from the test card to the probe card in the smallest amount to make the bandwidth between the two components of the test bench \ — For example, the interrupt test is preferably sent to the probe card. Refer to a short string. Yarn ,,, ',,, ..., post-mortem string is best to perform a dense processing test to remove any bandwidth limitation caused by the A tester. The short string can be , The form A of the code of the test vector stored on the capture card. Or, the word _ can represent a solid diagnostic test used to perform time-consuming tests, and then optionally automatically modified by the probe card to generate Additional diagnostic tests. In terms of test vectors, the tester can be planned to transmit only a set of key functional information related to the test vectors, as well as provide logic on the probe card to generate fields. These control signals will be applied. Arrived for execution K can also selectively generate a scan-based test on the probe card according to a scan pattern viewer provided by the tester. Another preferred feature is to allow the probe card and the DUT to use separate power supplies to protect the DUT. By separating the power supply, it is not necessary to switch the probe card switch for each bribe cycle when turning on an instant power supply. In addition, by maintaining a separate power supply, it is easier to perform tests related to switching the power supply of the dut. For example, by using a separate power supply for the probe card and the DUT, it is possible to check the current of the DUT when power is supplied from a separate power source for the DUT. One-Another preferred feature of the test bench is that in There is a direct interface between the tester and the contacts of the DUT. Using these interfaces, analog checks of the DUT can be performed, such as the drive strength and voltage level of the drivers of these contacts. (CNS) A4 size (210 X 297 mm) Gutters for this application date team π-1 "Case No. 090115780 Category G \ 〇 (^ ^ / (τν The above columns are filled by the Bureau )) ¾ 3 · 19 倏! The next year, month and day ^ / Lebubu A4 C4 Chinese manual replacement page (March 1992) 564313 is the name of the black J patent specification text test method and device for integrated circuits Method for testing a probe card of a device under test, generating a test vector 'Computer-readable medium having instructions for testing the device under test and generating test vectors', and method for generating a diagnostic test English " METHOD AND APPARATUS FOR TESTING AN iNTEGRATED CIRCUIT, PROBE CARD FOR TESTING A DEVICE UNDER TEST, APPARATUS FOR GENERATING TEST VECTORS, COMPUTER-READABLE MEDIUM HAVING INSTRUCTIONS FOR TESTING A DEVICE UNDER TEST AND GENERATING TEST VECTORS, AND METHOD FOR GENERATING DIAGN ”

1. 勞偷斯H.庫基 LAURENCE H. COOKE1. LAURENCE H. COOKE

2. 克理斯多夫κ.里納德 CHRISTOPHER K. LENNARD 1.2.均美國 -、發明 ~創作 人 住、居所 1 ·美國加州洛斯蓋托市西班牙農場路25399號 2.美國加州聖左斯市橡木河路555號丨“束 國 籍 美商卡登斯系統設計公司 CADENCE DESIGN SYSTEMS, INC. 美國 三、申請人 美國加州聖左斯市希理艾溫紐2655號2. CHRISTOPHER K. LENNARD 1.2. All are American-, inventor-creator's residence, residence 1. 25399 Spanish Farm Road, Los Gato, California, USA 2. San Joss, California, USA No. 555 Oak River Road 丨 "Bound nationality American business cardens system design company CADENCE DESIGN SYSTEMS, INC. United States III.

R-L·史密斯麥肯瑟 R L. SMITH MCKEITHENR-L. Smith McKenther R L. SMITH MCKEITHEN

A7 B7 564313 第090115780號專利申請案 中文說明書替換頁(92年3月） 五、發明説明（1 ) 本專利申請範圍同2000年7月3日所申適名稱為「System-Οη-a-Chip-l」的60/216,746號美國臨時專利以及2000年6月28 曰所申請名稱為「用於測試及驗證整合虛擬電路區塊之電 路設計的裝置及方法」的60/214,928號美國臨時專利等申請 案的範圍，以上兩專利申請案以提示方式併入本文。 發明背景 1 .發明範圍 本發明係關於電子設計自動化，更明確地說，本發明係 關於在製造及/或裝配階段的期間測試積體電路的裝置和方 法。 2.背景 電路晶片設計者經常會使用電子設計自動化（EDA)軟體 工具來輔助設計程序，以便能夠在原型製作或生產之前先 對晶片的設計進行模擬。使用EDA軟體工具作晶片設計通 常是反覆循環的程序，藉此使晶片的設計逐步趨向完美。 一般而言，晶片設計者藉由在一台電腦工作站上輸入資訊 來設計電路，該電腦工作站通常具備高品質的繪圖能力， 以便依需要顯示局部的電路設計。設計者一般是使用諸如A7 B7 564313 Patent Application No. 090115780 Chinese Specification Replacement Page (March 1992) V. Description of the Invention (1) The scope of this patent application is the same as that applied for on July 3, 2000 as "System-Οη-a-Chip" -l "U.S. Provisional Patent No. 60 / 216,746 and U.S. Provisional Patent No. 60 / 214,928 entitled" Apparatus and Method for Testing and Validating Circuit Design Integrated with Virtual Circuit Blocks "applied on June 28, 2000 The scope of the applications, the above two patent applications are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Scope of the Invention The present invention relates to electronic design automation, and more specifically, the present invention relates to devices and methods for testing integrated circuits during the manufacturing and / or assembly stages. 2. Background Circuit chip designers often use electronic design automation (EDA) software tools to assist in the design process so that they can simulate the design of the chip before prototyping or production. The use of EDA software tools for chip design is usually a iterative process, which gradually improves the design of the chip. In general, chip designers design circuits by entering information on a computer workstation, which usually has high-quality drawing capabilities to display local circuit designs as needed. Designers generally use

Verilog®或VHDL等硬體描述語言（HDLs)，採由上而下的設 計方法，階層式地定義電路的功能元件，然後將每一個元 件分解成一個比一個還小的元件，以產生一積體電路。 一積體電路之各項元件最初係以其功能操作及相關的輸 入和輸出加以定義。就HDL或它高階描述語言而言，實際 的邏輯基本單元(logic cell)實作一般而言是由邏輯合成（logic -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂Hardware description languages (HDLs), such as Verilog® or VHDL, adopt a top-down design method to define the functional elements of the circuit hierarchically, and then decompose each element into one smaller than one to produce a product. Body circuit. The various components of an integrated circuit are initially defined by their functional operation and associated inputs and outputs. As far as HDL or its high-level description language is concerned, the actual implementation of logical basic cells (logic cells) is generally composed of logic (logic -4- This paper standard applies to China National Standard (CNS) A4 specification (210 X 297 public) (Centimeters)

線 564313Line 564313

餐务修亚丨 萄无I 第090115780號專利申，案 中文說明書替換頁(92^3月）Catering Service Asia 丨 Patent No. 090115780 Patent Application, Chinese Manual Replacement Page (92 ^ March)

五、發明説明（ -8 - 製造上很昂貴的部份。 傳統測試程序的H ， 气婵々，欠W 、、’工吊曰有大I的形式為測 二電二===路的探測卡’在測試器 數ϋ Μ M k 由；早一個積體電路上可能有 d忒樣式了此會相當冗長。使用積 月反私路的一般介面電路來載入測 花費相當長的時間。快速庫 ：〜果可叱要 处 速尤力測攻疋在積體電路的操作效 :極限上測試裝置階層的功能，測試器和要被測試之積體 "路裝置之間的頻寬限制可能使此測試更加難以執行。 有些人嘗試藉由使用t高速的測試器（例如速度達綱 者，而-般為25MHz)來加快測試的速度。然而，高速 測試器可能極為昂貴。而且，在這麼高的速度下，由於阻 、部饧與頻率相關’連接測試器到積體電路(經由探測卡) 之電線的長度可能成為使速度受限的因素。因此，進行測 4時必須使用很短的電線，如此增加了測試設備在設計上 的限制，並可能使測試設備的自動化作業更麻煩且昂貴。 另一個解決的辦法是在受測裝置上增設額外的測試1/〇接 點。這種作法的問題是，頂多只有線性的改善，與積體電 路上所增加之受測閘極的密度相較之下並不顯著。可以利 用該等額外的測試I/O接點把眾多的掃描測試字串輸入到 DUT中，但同樣地，效能的改善很有限，因為能提供給額 外接點的空間很有限。此外，加入額外的測試接點會增加 晶片的封裝成本。 沿相同的線路，使用訊號I/O接點也能更快地傳送測試 本紙張尺度通用中國國家標準(CNS) A4規格(210 X 297公釐） 裝 訂 564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 B7 f %補无 五、發明説明（6 ) 輸入到DUT。為達此目的，必須針對該組訊號I/O接點的某 些部份進行測試及使用I/O的多工處理。然而，這樣作會造 成效能上的負擔。此外，由於能提供給I/O接點的空間很有 P艮，因此此一替選方案只能提供很有限的利益。 電路設計的最新發展之一是所謂的虛擬元件區塊的出 現，一般的看法是，虛擬元件區塊是預先設計好且已預先 定型（pre-hardened)(或半固定）之軟體形式（例如GDSII格式） 的電路設計，它可以很容易的重覆使用或循環利用於不同 的大型電路設計中。虛擬元件（或VC)區塊的一個優點是可 以縮短整體電路的設計時間，因而加快上市的速度。虛擬 元件區塊也可以從邏輯或功能的觀點加以驗證，這樣也會 節省設計程序中驗證部份所花的時間。 從設計的觀點雖然已證明虛擬元件區塊的方便性，但當 將它們整合到矽上面較大型的電路設計和製造時，還是會 有故障的情形，原因可能是製程的瑕疵，也可能是在嘗試 整合到較大型電路設計時所引起的問題。因此，如同任何 其它型式的積體電路，有一部份是以虛擬元件區塊為基礎 的積體電路通常必須在製造階段加以測試及驗證以確保其 功能正常。因此，按照傳統的電子設計自動化程序，必須 針對每一個結合一虛擬元件區塊的新積體電路設計撰寫新 的測試（不論是功能、診斷或應力測試）。設計這些測試可 能和如前述在製程中執行它們一樣耗時及昂貴。 因此，就製造及/或封裝的立場，若能提供改善積體電 路之測試的裝置，包括設計測試、執行測試，以及測試裝 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 564313 第090115780號專利申請案 中文說明書替換頁(92年3月） j 浐？·學: A7 L..................... Ί·Π gry …’‘一....， ·. .. _V. Description of the invention (-8-Very expensive part in manufacturing. The traditional test procedure H, discouraged, owed W, and 'work hanging said that there is a large I in the form of testing two electric two === road detection The card's number in the tester is Μ M k; there may be a d 忒 pattern on an integrated circuit earlier, which will be quite tedious. It takes a long time to load the test using the general interface circuit of the integrated moon anti-private circuit. Fast Library: ~ If you want to speed up, test the operating efficiency of the integrated circuit: test the function of the device hierarchy at the limit, the bandwidth limitation between the tester and the integrated circuit to be tested may be limited Makes this test more difficult to perform. Some people have tried to speed up the test by using a high-speed tester (such as a speed master, and usually 25MHz). However, high-speed testers can be extremely expensive. At high speeds, the length of the wire connecting the tester to the integrated circuit (via the probe card) may be a factor that restricts speed because of resistance and frequency dependence. Therefore, it is necessary to use a short Wires, so added testing The design limitation of the equipment may make the automation of the test equipment more cumbersome and expensive. Another solution is to add additional test 1/0 contacts on the device under test. The problem with this approach is that at most Only the linear improvement is not significant compared to the increased density of the tested gates on the integrated circuit. You can use these additional test I / O contacts to input a large number of scan test strings into the DUT However, the improvement in performance is limited because the space available for additional contacts is limited. In addition, adding additional test contacts will increase the packaging cost of the chip. Use the signal I / O contacts along the same line It can also transmit the test faster. This paper size is the common Chinese National Standard (CNS) A4 specification (210 X 297 mm). Binding 564313 No. 090115780 Patent Application Chinese Specification Replacement Page (March 1992) A7 B7 f% V. Description of the invention (6) Input to the DUT. In order to achieve this, it is necessary to test and use I / O multiplexing for some parts of the group of signal I / O contacts. However, this will cause performance on In addition, because the space that can be provided to I / O contacts is very large, this alternative solution can only provide very limited benefits. One of the latest developments in circuit design is the emergence of so-called virtual component blocks The general view is that the virtual component block is a circuit design that is pre-designed and pre-hardened (or semi-fixed) in the form of software (such as GDSII format), which can be easily reused or recycled. Used in different large circuit designs. One of the advantages of the virtual component (or VC) block is that it can shorten the overall circuit design time and thus speed up the time to market. The virtual component block can also be verified from a logical or functional point of view. This will also save time in the verification part of the design process. Although the convenience of virtual component blocks has been proven from a design point of view, when they are integrated into the larger circuit design and manufacturing of silicon, there will still be failures, which may be due to process defects or in Problems when trying to integrate into larger circuit designs. Therefore, like any other type of integrated circuit, a part of the integrated circuit based on the virtual component block must usually be tested and verified at the manufacturing stage to ensure that it functions properly. Therefore, according to traditional electronic design automation procedures, new tests (whether functional, diagnostic, or stress tests) must be written for each new integrated circuit design that incorporates a block of virtual components. Designing these tests can be as time consuming and expensive as performing them in the process as previously described. Therefore, from the standpoint of manufacturing and / or packaging, if you can provide devices that improve the testing of integrated circuits, including design testing, execution testing, and test equipment. 9- This paper size applies to China National Standard (CNS) A4 specifications (210X297 (Mm) 564313 Replacement page for Chinese specification of Patent Application No. 090115780 (March 1992) j 浐? · Learning: A7 L ........... Ί · Π gry… ’‘ 一 ..., · ... _

五、發明説明（7 ) 置和元件，則會很有幫助。若能提供改善的方法用來測心 從預先定義或已預先定型（pre-hardened)之虛擬元件區塊戶$ 開發出之積體電路，則更有幫助。 & 發明概述 本發明在一方面提供用於測試積體電路的裝置和方去 本發明在第二方面為在一製程環境中測試一包含隨機邏 輯元件區塊之積體電路的方法。該方法包括步驟：執行j 内建的自我測試，至少部份地測試該積體電路之記憶 資料路徑；執行診斷測試，至少部份地個別測試該隨機邏 輯元件區塊；使用測試向量執行應力測試（stresstest)，至^ 部份集體地測試該隨機邏輯元件區塊；以及執行基於掃= (scan-based)之積體電路測試，至少部份地測試該積體電= 中是否有結構上的疵病。 本發明在第三方面為一用於測試一積體電路的方法，該 積體電路包含一個記憶體，用以儲存用於起始内建自我測 試的簽名、用於診斷測試的輸入、用於應力測試的測試向 量及用於基於掃描之測試的測試樣式。該裝置最好進一步 包含一個處理器，用於起始及評估該積體電路在内建自我 測試、診斷測試、應力測試及基於掃描之測試等方面的效 本發明在第四方面為一電腦可讀的媒體，其中儲存一系 歹J用以4已製造％成之積體電路的指令。該積體電路 最好包含一1己憶體、隨機邏輯元件區塊及資料路徑。該一 系列的扎令用於執行一組命令，包括⑷執行内建的自我測 本紙張尺度適财㈣雜準5. Description of the invention (7) The arrangement and components will be very helpful. It would be more helpful if an improved method could be provided to test the integrated circuit developed from a predefined or pre-hardened virtual component block user $. & Summary of the Invention The present invention provides, in one aspect, a device and method for testing an integrated circuit. The second aspect of the present invention is a method for testing an integrated circuit including random logic element blocks in a process environment. The method includes the steps of: performing a built-in self-test to at least partially test the memory data path of the integrated circuit; performing a diagnostic test, and at least partially individually testing the random logic element block; and performing a stress test using a test vector (Stresstest) to ^ collectively test the random logic element block; and perform a scan-based integrated circuit test to at least partially test whether there is a structural Defect. In a third aspect, the present invention is a method for testing an integrated circuit. The integrated circuit includes a memory for storing a signature for starting a built-in self-test, an input for a diagnostic test, and a Test vectors for stress tests and test patterns for scan-based tests. The device preferably further includes a processor for initiating and evaluating the effectiveness of the integrated circuit including built-in self-test, diagnostic test, stress test, and scan-based test. The present invention is a computer Read the media, which stores a series of instructions for 4% of the integrated circuit that has been manufactured. The integrated circuit preferably includes a memory, a block of random logic elements, and a data path. This series of commands is used to execute a set of commands, including performing a built-in self-test.

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564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 _ ___ B7 五、發明説明（9 ) back circuit)以及一個連線於該受測裝置介面及該測試器介 面之間的資料轉譯器。最好是，該資料轉澤器格式化在該 受測裝置介面和該測試器介面之間通訊的測試資料。 本發明在第八方面為一積體電路，該積體電路包含經由 一匯流排連接之電路元件區塊及具有連接至該匯流排之對 應引線的I/O接點。該等I/O接點最好具備讓外界與該積體 電路通訊的能力。該積體電路最好進一步包括一個用於將 在該等引線之一上傳送的訊號重新導向的摺回電路，以及 一個用於啟用及停用該擅回電路的摺回邏輯。 本發明在第九方面為一電腦可讀的媒體，其上儲存一連 串用於指出一積體電路的指令。該等一連串的指令用於執 行一組動作集合，包括指出經由一匯流排互連的電路元件 區塊，以及指出具有連接至該匯流排之引線的I/O接點。該 等I/O接點最好具備讓外界與該積體電路通訊的能力。該等 動作集合最好進一步包括指出用於將在該等引線之一上傳 送的訊號重新導向的摺回電路，以及指出用於啟用及停用 該摺回電路的摺回邏輯。 本發明在第十方面為一用於測試一受測裝置之測試裝置。 孩測試裝置最好包括該受測裝置，其中該受測裝置包含記憶 體以及用於在對一受測裝置進行測試時鎖定該記憶體至少 一部份的測試邏輯。該測試裝置最好進一步包括一測試 器’其中該測試器連線至該受測裝置，且傳送用於鎖定該記 憶體至少一部份之數位訊號。該測試裝置最好進一步包括一 塊連線至該受測裝置及該測試器之探測卡，其中該探測卡包 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(21〇x 297公釐)564313 Replacement page of the Chinese specification for the patent application No. 090115780 (March 1992) A7 _ ___ B7 V. Description of the invention (9) back circuit) and data connected between the interface of the device under test and the interface of the tester Translator. Preferably, the data translator formats test data communicated between the device under test interface and the tester interface. The eighth aspect of the present invention is an integrated circuit including a circuit element block connected via a bus and an I / O contact having a corresponding lead connected to the bus. The I / O contacts preferably have the ability to allow the outside world to communicate with the integrated circuit. The integrated circuit preferably further includes a foldback circuit for redirecting a signal transmitted on one of the leads, and a foldback logic for enabling and disabling the unauthorized circuit. The present invention in a ninth aspect is a computer-readable medium having stored thereon a series of instructions for pointing out an integrated circuit. These series of instructions are used to perform a set of actions, including designating blocks of circuit elements interconnected via a bus, and designating I / O contacts with leads connected to the bus. The I / O contacts preferably have the ability to allow the outside world to communicate with the integrated circuit. The set of actions preferably further includes indicating a foldback circuit for redirecting a signal carried on one of the leads, and foldback logic for enabling and disabling the foldback circuit. The invention in a tenth aspect is a test device for testing a device under test. The test device preferably includes the device under test, wherein the device under test includes memory and test logic for locking at least a portion of the memory when testing a device under test. The test device preferably further includes a tester 'wherein the tester is connected to the device under test and transmits a digital signal for locking at least a part of the memory. The test device preferably further includes a detection card connected to the device under test and the tester, wherein the detection card package is -12- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21 × 297 mm) )

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564313 第090115780號專利申請案 中文說明書替換頁(92年3月） 五、發明説明（10 ) 括一個用於傳送時脈訊號到該受測裝置的時脈產生器和/ 個連線在該晶片介面和該測試器介面之間的資料轉譯器。 最好是，該資料轉譯器格式化在該晶片介面和該測試器介 面之間通訊的測試資料。 本發明在第十一方面為一產生用於在一製造測試台測試 一積體電路之測試向量的方法。該方法最好包括步驟··獲 得功能階層的測試向量；將該等向量轉換成一系列的訊息 區塊；應用一介面協定於該等一系列的訊息區塊，以產生 測試向量資料；以及應用一用於受測裝置之介面協定於該 測試向量資料。 本發明在第十二方面為一用於產生測試向量以便在一製 造測試台測試一積體電路的裝置。該裝置最好包括一個用 於獲彳于功旎階層之測試向量的记憶體，以及一個連接到該 記憶體的處理器，用以將該等測試向量轉譯成訊息區塊、 應用一介面協定於該等訊息區塊以產生測試向量資料，以 及應用一用於一受測裝置之介面協定於該測試向量資料。 本發明在第十三方面為一電腦可讀的媒體，其上儲存一 連率的指令，用以在一製造測試台產生用於測試一積體電 路的測試向量。該一連串的指令用於執行一組動作的集 口，包括⑷指出功能階層的測試向量；（b)將該等測試向量 轉澤成訊息區塊；(c)應用-介面協定於該等訊息區塊以產 生測試向量資料；以及（d)應用一用於該積體電路之介面協 疋於違測試向量資料。 本發月在第十四方面為一用於產生診斷測試以便在一製 -13-564313 No. 090115780 Patent Application Chinese Specification Replacement Page (March 1992) V. Description of the Invention (10) Include a clock generator and / or connections on the chip for transmitting clock signals to the device under test Data translator between the interface and the tester interface. Preferably, the data translator formats the test data communicated between the chip interface and the tester interface. The present invention in an eleventh aspect is a method of generating a test vector for testing an integrated circuit in a manufacturing test bench. The method preferably includes the steps of: obtaining functional level test vectors; converting the vectors into a series of information blocks; applying an interface agreement to the series of information blocks to generate test vector data; and applying a The interface used for the device under test is based on the test vector data. The present invention in a twelfth aspect is a device for generating test vectors for testing an integrated circuit in a manufacturing test stand. The device preferably includes a memory for obtaining test vectors from the functional hierarchy, and a processor connected to the memory for translating the test vectors into message blocks and applying an interface protocol. Generate test vector data on the message blocks, and apply an interface protocol for a device under test to the test vector data. In a thirteenth aspect, the present invention is a computer-readable medium having a serial command stored thereon for generating a test vector for testing an integrated circuit at a manufacturing test bench. The series of instructions are used to execute a set of actions, including the test vectors that indicate the functional hierarchy; (b) translating the test vectors into message blocks; (c) the application-interface agreement in these message areas Block to generate test vector data; and (d) applying an interface for the integrated circuit to assist in violating the test vector data. This month is in the fourteenth aspect for generating diagnostic tests for one system -13-

564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 B7564313 Patent Application No. 090115780 Patent Replacement Sheet of Chinese Manual (March 1992) A7 B7

五、發明説明（12 ) 用於該積體電路之高階測試向量；（e)利用該等測試向量及 診斷測試來驗證該積體電路；⑴擴大該診斷測試及測試向 量使適用於製程環境，及（g)連同該等被擴大的測試向量把 積體電路之設計包封起來。 圖示簡單說明 圖1為與本發明各個具體實施例相關之電腦裝置的圖示。 圖2為使用圖1所示電腦裝置，在元件區塊已佈放到該積 體電路晶片之後，所產生之簡化的積體電路圖示。 圖3為設計一電路之一般程序的流程圖，圖示為該抽象 電路（circuit abstraction)的各個不同階層。 圖4所示為一虛擬元件區塊及診斷測試資訊管理裝置， 圖中說明虛擬元件區塊資訊（包括測試和診斷資訊）在/電 子設計自動化程序之各個階段中的應用。 圖5為圖4所示測試台之一具體實施例的方塊圖。 圖6A為將測試從一設計驗證階段轉譯到一製造階段之禚 序的流程圖，其中係對已製造好之個別的1C做測試。 圖6B為將一虛擬1C設計之驗證測試移植到製造階段之用 以確認該設計的真實1C測試。 圖7為規劃一測試台以幫助執行擴大到製程環境之測試 向量及診斷測試的步驟。 圖8為一晶片的實體配置圖，該晶片具有傳送診斷資料 到電路區塊以便執行特定診斷測試的介面，以及傳送測試 向量資料到適當的記憶體以便啟動一局部仏邛〇^應力測試 執行的介面。 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公董） 装 订V. Description of the invention (12) High-order test vectors for the integrated circuit; (e) Use the test vectors and diagnostic tests to verify the integrated circuit; ⑴ Expand the diagnostic tests and test vectors to apply to the process environment, And (g) enclose the design of the integrated circuit together with the expanded test vectors. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a computer device related to various embodiments of the present invention. FIG. 2 is a simplified integrated circuit diagram generated by using the computer device shown in FIG. 1 after component blocks have been placed on the integrated circuit chip. Fig. 3 is a flow chart of a general procedure for designing a circuit, showing the different levels of the circuit abstraction. Figure 4 shows a virtual component block and diagnostic test information management device, which illustrates the application of virtual component block information (including test and diagnostic information) in each stage of the electronic design automation process. FIG. 5 is a block diagram of a specific embodiment of the test stand shown in FIG. 4. FIG. 6A is a flowchart of a process for translating a test from a design verification stage to a manufacturing stage, in which individual manufactured 1Cs are tested. Figure 6B illustrates the migration of verification testing of a virtual 1C design to the manufacturing stage to confirm the true 1C test of the design. Figure 7 shows the steps for planning a test bench to help perform test vectors and diagnostic tests that are extended to the process environment. FIG. 8 is a physical configuration diagram of a chip having an interface for transmitting diagnostic data to a circuit block to perform a specific diagnostic test, and transmitting test vector data to an appropriate memory for initiating a local stress test. interface. -15- This paper size applies to China National Standard (CNS) A4 (210 X 297 public directors) binding

線 564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 B7 a修正i 補充 五、 發明説明（14 ) 在製造階段，可進行各種測試以確定電路設計正確可行。 圖1為與本發明各個具體實施例相關之電腦裝置100的圖 示。如圖1所示，電腦裝置100包括一部與一顯示器191及各 種輸入-輸出裝置192連接的電腦110。電腦110可包含1個或 多個處理器（未畫出），以及數量足以滿足裝置100之速度和 處理需求之工作記憶體（亦即RAM)。電腦110可包括，例 如，一台SPARC工作站，可以從位在加州聖塔克拉拉之Sun Microsystems，Inc.公司購得。 前文中所用「處理器」一辭最好是規劃用來執行軟體的 多用途處理器（與硬配線處理器相對照），以便具備多種用 途且使處理器程式設計具有彈性，以及在需要時修改或替 換軟體。然而，廣義而言，「處理器」一辭係指能夠執行 本文所述各項電子功能之任何形式的處理器。因此，處理 器一辭係泛指各種電算裝置或方法，包括，例如使用多個 處理器執行不同任務或同一任務分散於不同處理器。該（等） 處理器可為多用途CPU或訊號處理裝置中經常使用的特殊 用途處理器。此外，多顆處理器可規劃成主-從（server-client) 或其它網路架構，例如管道陣列（pipeline array)或處理器串 列（series of processors)等。此外，一些或全部的處理方法可 以用定製或hard-wired的電路實作，例如特殊應用的積體電 路（ASIC)、場可程式閘極陣列（FPGA)或其它邏輯裝置。 全文中，與「處理器」相關連的「記憶體」一辭係指任 何處理器可存取的儲存媒體，其儲存容量滿足裝置或裝置 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂Line 564313 Patent Application No. 090115780 Chinese Specification Replacement Page (March 1992) A7 B7 a Revision i Supplement V. Description of Invention (14) During the manufacturing stage, various tests can be performed to confirm that the circuit design is correct and feasible. FIG. 1 is a diagram of a computer device 100 related to various embodiments of the present invention. As shown in FIG. 1, the computer device 100 includes a computer 110 connected to a display 191 and various input-output devices 192. The computer 110 may include one or more processors (not shown) and a working memory (ie, RAM) sufficient to meet the speed and processing requirements of the device 100. The computer 110 may include, for example, a SPARC workstation, available from Sun Microsystems, Inc. of Santa Clara, California. The term "processor" as used in the previous article is best planned for a multi-purpose processor (as opposed to a hard-wired processor) used to execute software in order to have multiple uses and to allow flexibility in processor programming and modification when needed Or replace the software. In the broadest sense, however, the term "processor" refers to any form of processor capable of performing the various electronic functions described herein. Therefore, the term processor refers to a variety of computing devices or methods, including, for example, the use of multiple processors to perform different tasks or the same task being spread across different processors. The processor (s) may be a multi-purpose CPU or a special-purpose processor often used in signal processing devices. In addition, multiple processors can be planned as a server-client or other network architecture, such as a pipeline array or a series of processors. In addition, some or all of the processing methods can be implemented with custom or hard-wired circuits, such as application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other logic devices. In the full text, the term "memory" in relation to "processor" refers to any processor-accessible storage medium with a storage capacity that meets the requirements of a device or device-17- This paper standard applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) Staple

線 564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 B7Line 564313 Patent Application No. 090115780 Patent Specification Replacement Page (March 1992) A7 B7

五、發明説明（15 ) 元件的需求，以使本文所述之各項電子功能易於執行。最 好是，該記憶體包括讓該處理器直接存取的隨機存取記憶 體（RAM)。或者，該記憶體可為硬式磁碟或其它非揮發記 憶裝置或元件，用來儲存資料、軟體及/或其它形式之電子 式呈現的資訊。 請再參考圖1，電腦110包括儲存於其中的程式碼，在一 具體實施例中，該程式碼包括一個區塊平面配置器（block floorplanner) 120、一 個區塊放置器（block placer) 130、一個邏 輯合成器（logic synthesizer) 135和一個佈線空間估計器 (routing space estimator) 140。區塊平面配置器120定義區塊功 能、區塊區域及它們的限制，以便電路設計者進行交談式 平面配置操作及控制區塊放置器130之放置操作。區塊放置 器130按照電路設計者所定義的限制，決定區塊内基本單元 的放置。按照區塊放置器130對該等區塊之配置，佈線空間 估計器140估計區塊佈線所需的佈線空間。 為支援前述之裝置元件，可使用一個晶片平面配置器 150、整體/細部路由器160、標準基本單元放置器170、邏輯 合成器180和HDL編輯器190。晶片平面配置器150、整體/細 部路由器160、標準基本單元放置器170、邏輯合成器180和 HDL編輯器190是以傳統方式的操作，這些元件的設計是電 子設計自動化中所熟知的。市面可買到的這些裝置元件有 Preview™、Cell3TM、QPlace™、Synergy™ 和 Verilog® 等0 電腦1 1 0最好是連到一台具備一個配置資料庫1 9 5的大量儲 存裝置（例如，磁碟片或卡匣儲存裝置），前述裝置元件 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 564313 修工 第090115780號專利申請案 中文說明書替換頁(92年3月）5. Description of the Invention (15) The need for components to facilitate the implementation of various electronic functions described herein. Preferably, the memory includes random access memory (RAM) for direct access by the processor. Alternatively, the memory may be a hard disk or other non-volatile memory device or element used to store data, software, and / or other forms of electronically presented information. Please refer to FIG. 1 again, the computer 110 includes code stored therein. In a specific embodiment, the code includes a block floor planner 120, a block placer 130, A logic synthesizer 135 and a routing space estimator 140. The block plane configurator 120 defines block functions, block areas, and their restrictions, so that the circuit designer can perform interactive plane configuration operations and control the placement operations of the block placer 130. The block placer 130 determines the placement of the basic cells in the block according to the restrictions defined by the circuit designer. According to the configuration of the blocks by the block placer 130, the wiring space estimator 140 estimates the wiring space required for the block wiring. To support the aforementioned device components, a wafer plane configurator 150, overall / detail router 160, standard base unit placer 170, logic synthesizer 180, and HDL editor 190 can be used. The wafer plane configurator 150, overall / detail router 160, standard basic unit placer 170, logic synthesizer 180, and HDL editor 190 operate in a conventional manner, and the design of these components is well known in electronic design automation. These commercially available device components include Preview ™, Cell3TM, QPlace ™, Synergy ™, and Verilog®. 0 Computer 1 1 0 is best connected to a mass storage device with a configuration database 195 (for example, Magnetic disk or cassette storage device), the aforementioned device components are in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 Repair Manual No. 090115780 Patent Application Chinese Manual Replacement Page (March 1992 )

五、發明説明（18 ) 可提供給一鑄造廠，其中含有讓鑄造廠據以製造出一實際 積體電路的足夠資訊。 本發明之相關的特定具體實施例在一方面提供一些裝置 及方法，用來測試電路之設計，尤其是那些結合虚擬元件 區塊的電路設計，在一部份的半導體製程中，該等虛擬元 件區塊已經縮減成;^7。 在一具體實施例中，一虛擬元件區塊資料庫係與特別為 該等虛擬元件區塊量身訂做之預先開發的診斷測試一併提 供，因此該等虛擬元件區塊及相關的診斷測試可以很容易 地在不同的電路設計中重覆使用及循環利用。 圖4為一設計及驗證管理裝置4〇〇的流程圖，圖示為虛擬 元件區塊資訊（包括測試和診斷資訊）在一電子設計自動化 程序之各個不同階段下的應用。在一方面，圖4所描述的 电子$又计自動化泥程與圖3所示者類似。因此，圖4所示的 功能設計及/或暫存器轉移邏輯（RTL)檔案4〇丨可為硬體描述 浯& (HDL)檔案或其它高階功能描述的形式。與圖3所示的 流程相似，該功能設計檔案4〇1經歷一個編譯程序4〇3，此 程序將該電路的功能描述轉換成一個可以儲存成網表檔案 404形式的特殊電路實作。利用一實體設計程序4〇9佈放及 接線網表檔案404的邏輯基本單元，而得到一配置樓案 410。利用配置檔案41〇，可執行一驗證程序412，而得到一 個可以表示成GDSII或GIF等格式的遮蔽檔案4丨5。遮蔽檔案 415可提供給一鑄造廠，用來產生半導體晶圓46〇。 可按照任何傳統的方法來產生測試向量42〇，以便在不 -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313 第090115780號專利申請案 中文說明書替換頁(92年3月）5. Description of the invention (18) can be provided to a foundry, which contains enough information for the foundry to make an actual integrated circuit. Specific specific embodiments of the present invention provide devices and methods on one hand for testing circuit designs, especially those circuit designs that incorporate virtual component blocks. In a part of the semiconductor manufacturing process, these virtual components The block has been reduced to; ^ 7. In a specific embodiment, a virtual component block database is provided together with pre-developed diagnostic tests specially tailored for the virtual component blocks. Therefore, the virtual component blocks and related diagnostic tests are provided. It can be easily reused and recycled in different circuit designs. Figure 4 is a flowchart of a design and verification management device 400, which illustrates the application of virtual component block information (including test and diagnostic information) at various stages of an electronic design automation process. In one aspect, the electronic meter described in FIG. 4 is similar to that shown in FIG. 3. Therefore, the functional design and / or register transfer logic (RTL) file 40 shown in FIG. 4 may be in the form of a hardware description file (HDL) file or other high-level functional description. Similar to the flow shown in FIG. 3, the functional design file 401 undergoes a compiling program 403, which converts the functional description of the circuit into a special circuit implementation that can be stored in the form of a netlist file 404. A physical design program 409 is used to deploy and connect the logical basic units of the netlist file 404 to obtain a configuration building plan 410. Using the configuration file 41, a verification program 412 can be performed, and a mask file 4 5 that can be expressed in a format such as GDSII or GIF is obtained. The shadow file 415 may be provided to a foundry to produce semiconductor wafers 460. The test vector 42 can be generated in accordance with any conventional method, so that in the case of -21-this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 Replacement page of the Chinese specification of patent application No. 090115780 ( March 1992)

記憶體或暫存器記憶體的大小和型式而定。藉此，每一 + 斷測試被分配記憶體中的一個位址，炊德佘 ^ …俊疋整的分派列表 被提供給一測試排程器。 在下一個步驟614中，診斷測試，較理相，姐 王心根據實體上斷 開DUT的裝置匯流排的區塊的特定介面協定6 叫彻疋成格式化。 最好是，此一格式化動作包括將該等診斷測試連同…裝置 匯流排和虛擬元件介面（VCI)(請見2〇〇1年1月18日所提出 Lyon & Lyon LLP案號260/086之標題為「電路元件介面的 申請案，此案討論VSIA虛擬元件介面標準（〇CB 2 i 〇)，全 文以提示方式併入本文）協定一起包裝起來。針對VC〗協定 所作的格式化簡化了關於元件設計介面的問題。藉由將 VCI協定整合到元件設計中，可將診斷測試載入到快取或 其它記憶體中，不太需要在乎裝置匯流排是使用哪一種匯 流排架構。此外，協定最好允許元件以程式的方式設定成 用於資料通訊的起始器（initiator)或目標（target)狀態。 在測試向量方面，第一個步驟6〇8最好是獲得在驗證階 段期間設計用來測試虛擬I C之設計的測試向量。所得到之 該等測試向量最好是可以被用來在規格的高階層（通常是在 功能階層）對1C執行應力測試，而且包含一個記錄在一電 月自可瀆媒體上的資料檔案。要轉譯該等測試向量以供在製 程環境中使用，在下一個步驟610中，最好將測試向量檔 案轉換或分解成一或多個訊息區塊或封包以幫助傳送測試 資料到一製造測試台的記憶體中。每一個訊息區塊可為， 例如，能夠在一匯排流上傳送之一個字組寬度的資料片 -27- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公董）Depending on the size and type of memory or register memory. With this, each + test is assigned an address in the memory, and the entire assignment list is provided to a test scheduler. In the next step 614, the diagnostic test compares reasonably, the sister Wang Xin calls the formatting according to the specific interface protocol 6 of the block that physically disconnects the device bus of the DUT. Preferably, this formatting action includes combining these diagnostic tests with ... the device bus and the Virtual Component Interface (VCI) (see Lyon & Lyon LLP case number 260 / filed January 18, 2001) The title of 086 is “Application for Circuit Component Interface. This case discusses the VSIA virtual component interface standard (〇CB 2 i 〇), which is incorporated by reference in its entirety). The agreement is packaged together. The formatting simplification for the VC protocol It solves the problem of the component design interface. By integrating the VCI protocol into the component design, diagnostic tests can be loaded into the cache or other memory. The protocol preferably allows the components to be programmed into an initiator or target state for data communication. In terms of test vectors, the first step 608 is best obtained during the verification phase Test vectors designed to test the design of virtual ICs. The resulting test vectors should preferably be used to perform applications to 1C at a high level of the specification (usually at the functional level). Test, and it contains a data file recorded on a media file. To translate these test vectors for use in the process environment, in the next step 610, it is best to convert or decompose the test vector file into one or Multiple message blocks or packets to help transmit test data to the memory of a manufacturing test bench. Each message block can be, for example, a block-wide data piece capable of being transmitted on a bus-27 -This paper size applies to China National Standard (CNS) A4 (210 X 297 directors)

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564313 第090115780號專利申請案 中文說明書替換頁(92年3月） 補充 rj ....—------------------ B7 五 發明説明（26 ) 提供給壓鑄廠之包含IC遮蔽檔案和測試輸入之擁有智慧財 產權的套裝軟體還包括特別設計用於測試根據該遮蔽檔案 中的設計所製造之積體電路及執行指定測試輸入的探測 卡。壓鑄廠訂定該探測卡的配置（亦即，卡的尺寸和形狀、 探頭的位置以及和DUT的介面）和介面，包括用於與測試器 通訊的訊號集合。由於此一得自壓鑄廠的資訊非常有限， 因此最好將探測卡1000納入到提供給壓鑄廠之擁有智慧財 產權的套裝軟體中。 探測卡1000最好視需要包括下列任何一個或多個項目： 一個資料轉譯器1004、一個記憶及控制邏輯1006、一個高 速時脈產生器1008、一個類比訊號產生器1012、一個掃描 測試介面1010和一個直接測試介面1014。探測卡1000和測試 器1001之間的介面通常包括一個測試器介面，且探測卡 1000和DUT 1002之間通常包括一個DUT介面。DUT 1002的位 置最好能夠與探測卡1000上的每一個元件導電相連。探測 卡1000上之元件的位置要特別設計，以提高DUT 1002上面 元件區塊的at-speed診斷測試和使用測試向量的at-speed應力 測試的效能。 資料轉譯器1 004可實作成一個hard-wired元件、一個FPGA、 一個執行軟體的多用途處理器或其它型式的處理器。資料轉譯 器1004最好包括連接到記憶體和控制邏輯1 006及測試器1001 的連線。資料轉譯器1004最好進一步包括一個VCI及晶片介 面以提供對於DUT 1002上之裝置匯流排的直接存取。資料轉 譯器1004可利用協定或前導（preamble)資訊，為 -29- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂564313 Replacement page for Chinese specification of Patent Application No. 090115780 (March 1992) Supplement rj ....--------------------- B7 Five Inventions (26) Provided The intellectual property rights package for the die-casting plant that includes the IC mask file and test inputs also includes a probe card specifically designed to test integrated circuits manufactured according to the design in the mask file and perform specified test inputs. The die-casting plant determines the configuration of the probe card (ie, the size and shape of the card, the location of the probe, and the interface to the DUT) and interface, including the set of signals used to communicate with the tester. Since this information from the die-casting plant is very limited, it is best to incorporate the detection card 1000 into the packaged software with intellectual property rights provided to the die-casting plant. The detection card 1000 preferably includes any one or more of the following items as needed: a data translator 1004, a memory and control logic 1006, a high-speed clock generator 1008, an analog signal generator 1012, a scan test interface 1010, and A direct test interface 1014. The interface between the probe card 1000 and the tester 1001 usually includes a tester interface, and the probe card 1000 and the DUT 1002 usually include a DUT interface. The position of the DUT 1002 is preferably conductively connected to each element on the detection card 1000. The position of the components on the probe card 1000 should be specially designed to improve the performance of the at-speed diagnostic test of the component block on the DUT 1002 and the at-speed stress test using test vectors. The data translator 1 004 can be implemented as a hard-wired component, an FPGA, a multi-purpose processor executing software, or other types of processors. Data translator 1004 preferably includes connections to memory and control logic 1 006 and tester 1001. The data translator 1004 preferably further includes a VCI and chip interface to provide direct access to the device bus on the DUT 1002. The data translator 1004 can use the agreement or preamble information to -29- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) binding

線 564313 A7 B7 第090115780號專利申請案 中文說明書替換頁(92年3月） 五、發明説明（功） 會在操作期間被移除。由於記憶體中及/或晶片上其它部份 的邏輯及/或記憶元件，該記憶體還可以被指定成為在載： 外部測試時所用的通訊目標。利用此一特點，一個並非設 定用於從外部接收資料的記憶體冑能夠被用㈣㈣^ 有效地成為製造測試程序的一部份。最好是，記憶體之此 -參數化功能係藉由使用允許記憶體被指定作為接收外部 貪料t目標的協足來執行。前述之VCI協定提供此項功 能。此外’某些快取或其它記憶體可自動作交換的動作 (swapped out),除非它們特別被設定成鎖定狀態以防止測試 及診斷資料遺失。ϋ由鎖定某些記憶體位址，有可能遺失 的測試資料便能在測試期間被維持住。有關使用記憶則包 括記憶快取）來測試電路之其它細節及另外的可行方式，請 見Mod在6,003，142號美國專利中的發表，全文在此以參二 文件的方式併入本發明。 同樣地’在另-個較佳的特徵方面，晶片内部之其它區 塊具備-個能夠從-測試埠直接對㈣資料源定址的介 面。這些元件還包括-個虛擬元件(vc)介面]吏元件能夠 被指定成診斷測試的目標。該測試槔包括一個通到晶片上 之裝置匯流排的VC介面，並把它自己指定成為一個用於傳 送測試資料的訊息起始器。測試向量(已經轉譯成準確定時 向量）從受測裝置（DUT)上之此—測試埠被寫人到晶片上特 定的元件（包括記憶體)中’晶片上的每—個元件有其自己 的VC介面（或其它介面）可接受測試資料。 圖8為一晶片_之實ft配置_，晶片8〇〇具有針對特定Line 564313 A7 B7 Patent Application No. 090115780 Chinese Specification Replacement Page (March 1992) 5. Invention Description (Work) will be removed during operation. Due to the logic and / or memory elements in the memory and / or other parts of the chip, the memory can also be designated as a communication target for on-board: external testing. With this feature, a memory that is not designed to receive data from the outside can be used as an effective part of the manufacturing test process. Preferably, the memory-parameterization function is performed by using a cooperative that allows the memory to be designated as a destination for receiving external information. The aforementioned VCI agreement provides this functionality. In addition, certain caches or other memories can be automatically swapped out unless they are specifically locked to prevent loss of test and diagnostic data. By locking certain memory addresses, test data that may be lost can be maintained during the test. For other details and other possible ways to test the circuit using memory (including memory cache), please see Mod published in US Patent No. 6,003,142, which is incorporated herein by reference. Similarly, in another preferred feature, other blocks inside the chip are provided with an interface capable of directly addressing a data source from a test port. These components also include a virtual component (vc) interface, which can be specified as targets for diagnostic tests. The test frame includes a VC interface to a device bus on the chip and designates itself as a message initiator for transmitting test data. The test vector (which has been translated into an accurate timing vector) from this on the device under test (DUT) —the test port is written to a specific component (including memory) on the chip. 'Each component on the chip has its own The VC interface (or other interface) can accept test data. Fig. 8 is a real ft configuration of a wafer. The wafer 800 has a specific

564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 B7 五、發明説明（29 ) 診斷資料傳送診斷資料到適當區塊的介面，以及用於適當 地記憶以便能夠局部地執行at-speed應力測試的測試向量。 利用VC介面，裝置匯流排808的每一個元件（包括處理器 802、記憶體804和電路區塊A...N 806)可設定用來接收及執 行測試資料。若有需要直接存取一元件，則該元件上最好 包括一個VC介面。另一可行的作法為，每一元件包括一個 陰陽同體型式的VC標準介面，使每一元件能夠動態地從介 面之目標的一邊切換到介面之起始的一邊，或反向切換。 該陰陽同體介面之實作細節請見前面所參考到之標題為 「電路元件介面」的申請案。晶片800包含一個週邊元件互 連（PCI)及/或串列輸入/輸出（SIO)介面810，使晶片800的晶 片元件和週邊元件之間能夠通訊。針對晶片800上之每一元 件以及在一測試埠812所實作之一標準介面使得測試向量和 診斷與所使用之裝置匯流排808不相關。 請再參考圖7，at-speed測試台之另一較佳特徵為在晶片 之I/O介面的摺回（fold-back)能力。摺回可提升診斷測試和 應用該等測試向量之測試的速度和效率。圖9A和9B為兩種 摺回機制的細節，兩者可用於測試1C的不同部份。一般而 言，製造程序中並非在每次的循環都使用診斷測試和測試 向量來測試晶片。測試結果係以比較測試輸入和測試輸出 之總計核算的形式來表示。摺回的能力使來自晶片的輸出 線路和通到晶片的輸入線路能夠同時被測試，而可提升這 些測試的效率。圖9A所示為一摺回900之較佳具體實施例， 摺回900完全駐在晶片上，以未經排序的方式將訊號從 -32- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)564313 No. 090115780 Patent Application Chinese Specification Replacement Page (March 1992) A7 B7 V. Invention Description (29) Diagnostic Data Interface for transmitting diagnostic data to the appropriate block, and for proper memory to enable local execution of at -speed test vector for stress test. Using the VC interface, each component of the device bus 808 (including the processor 802, memory 804, and circuit blocks A ... N 806) can be configured to receive and execute test data. If there is a need to directly access a component, the component preferably includes a VC interface. Another feasible method is that each component includes a yin-yang homogeneous VC standard interface, so that each component can dynamically switch from the target side of the interface to the initial side of the interface, or vice versa. For details on the implementation of the yin-yang homogeneous interface, please refer to the application titled "Circuit Component Interface" referred to earlier. The chip 800 includes a peripheral component interconnect (PCI) and / or serial input / output (SIO) interface 810 to enable communication between the chip components of the chip 800 and peripheral components. A standard interface implemented for each component on chip 800 and a test port 812 makes test vectors and diagnostics unrelated to the device bus 808 used. Please refer to FIG. 7 again. Another preferred feature of the at-speed test bench is the fold-back capability of the I / O interface of the chip. Fold-back can increase the speed and efficiency of diagnostic tests and tests using those test vectors. Figures 9A and 9B show details of the two foldback mechanisms. Both can be used to test different parts of 1C. In general, not every cycle of the manufacturing process uses diagnostic tests and test vectors to test the wafer. The test result is expressed in the form of a total calculation comparing the test input and test output. The ability to fold back enables the output lines from the chip and the input lines to the chip to be tested at the same time, which improves the efficiency of these tests. Figure 9A shows a preferred embodiment of the folded-back 900. The folded-back 900 resides entirely on the wafer, and the signals are changed from -32 in an unordered manner. X 297 mm)

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564313 第〇9011578〇號專利申請案 中文說明書替換頁(92年3月）五、發明説明（33 ) A7v Β7564313 Patent Application No. 009011578〇 Replacement Page of Chinese Specification (March 1992) V. Description of Invention (33) A7v Β7

本發明提供測試1C的較佳方法，該方法使用從設計驗證 階段移植到製造階段的測試向量和診斷測試。該等測試方 法可達成穩健且不昂貴之製程階段測試的目標。這些方法 中’取好至少執行四種型式的測試，以完成完整且穩健的 DUT’則武，該等測試型式包括診斷測試、應力測試、内建 的自我測試（BISTs)及掃描測試。在測試記憶體和資料路徑 方面，包括它們的定時和卡住錯誤，BIST大致上是有效 的’達到傳統上所要求之錯誤檢查效能的99·9 %。然而， BIST在測試隨機邏輯方面，包括控制功能，就不這麼有效 率。要測試1C的其它這些領域，可應用診斷測試、應力測 試和基於掃描的測試。診斷測試是設計用來測試個別的電 路區塊，最好疋以at-speed的方式執行。應力測試提供整體 裝置的測4快照，它最好是以at_speed的方式執行移植過來 的/,、】4向量。應力測試一般而言是以冗操作性能的極限， 在裝置的層級測試元件的功能 '然而，這兩種測試通常不 能達到傳統上所要求之大約99·9%的結構性錯誤測試。要 達到此層級的測試性能，最好是執行基於掃描的測試來 完成測試程序。 圖11為一晶片製造測試程序1100以較佳順序執行之較佳 程序的流程圖。處理步騾之順序的首要準則為，最快且最 便宜的測試要先執行，m一特定晶片中是否有瑕疵， :且要節省耗用的時間及昂貴的測試，直到測試程序應 終了為止。圖u所示測試程序1100之順序，其重點 出錯誤的位置（而不是只確定是否有錯誤），這對於，例如 -36- 本紙張尺錢财 S ® ^^^(CNS) A4^(2l〇X297'i¥)The present invention provides a preferred method of testing 1C, which uses test vectors and diagnostic tests that are ported from the design verification stage to the manufacturing stage. These test methods achieve the goal of robust and inexpensive process-stage testing. Among these methods, ‘take at least four types of tests to complete a complete and robust DUT’. These test types include diagnostic tests, stress tests, built-in self-tests (BISTs), and scan tests. In terms of testing memory and data paths, including their timing and stuck errors, BIST is generally effective ', reaching 99.9% of the traditionally required error checking performance. However, BIST is not as effective in testing random logic, including control functions. To test these other areas of 1C, diagnostic tests, stress tests, and scan-based tests can be applied. Diagnostic tests are designed to test individual circuit blocks and are best performed at-speed. The stress test provides a snapshot of the overall device. It is best to execute the transplanted / ,, and [4] vectors in at_speed mode. Stress testing is generally the limit of redundant operating performance, testing the function of components at the device level. However, these two tests usually fail to achieve the traditionally required structural error test of about 99.9%. To achieve this level of test performance, it is best to perform a scan-based test to complete the test program. FIG. 11 is a flowchart of a preferred procedure performed by a wafer manufacturing test procedure 1100 in a preferred order. The first criterion for processing the order of steps is to perform the fastest and cheapest test first, whether there is a defect in a particular chip, and to save time and expensive tests until the test procedure is finished. The sequence of the test procedure 1100 shown in Figure u focuses on the location of the error (rather than just determining whether there is an error). This is, for example, -36- this paper rule money S ® ^^^ (CNS) A4 ^ (2l 〇X297'i ¥)

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第090115780號專利申請案 中文說明書替換頁(92年3月）Chinese Patent Application No. 090115780 Patent Application Replacement Page (March 1992)

’製程測試是在-原型除錯階段執行的情況而纟，是最優 先的。因此，一種決定測試順序的協定為，有些測試若其 前提是特定元件需先經過驗證，則在該等特定元件未經其 它測試驗證之前’該等測試不會執行。在一具體實施例 中，以例如前述及圖5所示的測試排程器，根據錯誤㈣ 及/或鑑別的優先度，來控制測試的順序。 測試程序1100的第一個測試1102是執行内建自我測試 (BIST)。然後在第二個步驟11〇4中，執行…，恃斷測試 以驗證晶片上個別元件區塊的效能。下一個步驟"〇6中， 利用測試向量對晶片施以at.speed測試。由於這些測試通常 是測試裝置整體，它們假設個別元件是沒有問題的。因 此，這些測試應在診斷測試和則訂之後執行。然後，在下 一個步驟謂中，從測試器執行順之基於掃描的測試， 其中掃描樣式可利用現有的軟體工具（例如自動測試樣式產 生（ATPG)軟體）來產生。基於掃描的測試在製造測試台的 測試中通常是最耗時且最昂貴的，因此最好在測試的最後 或接近最後才執行。由於診斷測試和應力測試能夠測試出 絕大部份的錯誤，因此，必須執行的掃描樣式比必要的 99.9%驗證少很多。 或者，可視測試的相對成本，把前兩個測試11〇2和1丨〇4 的順序調換。另-可能的方式是調換步驟11〇4和ιι〇6的順 序。在生產製造的情況中，經過測試的…接下來要被結合 到電子產品中及/或供應給客戶（亦即，，出貨到商場上，，），錯 誤偵測通常比錯誤鑑別具有更高的優先度。因此，測試 -37- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公愛)‘Process testing is performed in the prototype debugging phase, and is the best. Therefore, an agreement that determines the test sequence is that some tests, provided that certain components are verified first, will not be performed until those specific components are verified by other tests'. In a specific embodiment, a test scheduler such as that described above and shown in FIG. 5 is used to control the test sequence according to the error rate and / or the priority of discrimination. The first test 1102 of the test program 1100 is to perform a built-in self test (BIST). Then in the second step 1104, perform a ... test to verify the performance of individual component blocks on the chip. In the next step " 〇6, the wafer is subjected to an at.speed test using a test vector. Since these tests are usually a test device as a whole, they assume that individual components are okay. Therefore, these tests should be performed after diagnostic testing and ordering. Then, in the next step, a scan-based test is performed from the tester, where scan patterns can be generated using existing software tools, such as automated test pattern generation (ATPG) software. Scan-based testing is usually the most time consuming and expensive in manufacturing test bench testing, so it is best to perform it at or near the end of the test. Because diagnostic and stress tests can detect most errors, the scan pattern that must be performed is much less than the necessary 99.9% verification. Or, depending on the relative cost of the test, reverse the order of the first two tests, 1102 and 1 丨 04. Another-possible way is to reverse the order of steps 1104 and ιι 06. In the case of manufacturing, tested ... and then incorporated into the electronic product and / or supplied to the customer (ie, shipped to the mall, ...), error detection is usually higher than error identification Priority. Therefore, the test -37- This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)

564313 A7 B7 第090115780號專利申請案 中文說明書替換頁(92年3月） 五、發明説明（35 ) 順序應能快速地找出故障的1C，以便丢棄它們，並繼續測 試可能是良好的1C。應力測試測試整個裝置，它們所測試 的1C區域比診斷測試大，比診斷測試更有可能且更快找到 錯誤。因此，在生產製造的情況中，應力測試應在診斷測 試之前執行，或選擇在BIST之前執行。 在另一具體實施例中，把類比測試結合到在該測試排序 法（test ordering method)中。通常，類比測試比數位測試慢， 因為類比測試受制於類比裝置之自然穩定時間。然而，它 們通常不像基於掃描的測試那樣耗時及昂貴。因此，對於 類比部份可能相對較小的IC而言，類比測試應在功能測試 (亦即診斷測試1104和應力測試1106)之後執行，但在基於 择描的測試1108之前執行。另外，對於類比裝置佔大部份 的1C而言，類比測試最好是第一個執行的步驟，尤其是在 生產製造的情況中，初期錯誤偵測的優先度可能是最高 的’且類比測試會測試1C的大部份區域。 在另一具體實施例中，基於掃描的測試被分割成兩個分 開的步驟。由於區塊層級的掃描樣式在設計驗證階段已經 生因此區塊層級的知描測試最好在區塊層級之診斷測 喊已經執行之後再進行。此一先後次序的考量特別適用於 原型除錯的情況，在這種情況中，優先度最高的可能是錯 為位置鑑別，而非初期錯誤偵測。此情況下，執行區塊間 掃榣樣式最好是包括在測試步驟的最後或接近最後執行基 於掃描的測試1108。在其它具體實施例中，可變更該等測 試的順序，以達成使每一 DUT之測試成本達到最低的整體564313 A7 B7 No. 090115780 Patent Application Chinese Specification Replacement Page (March 1992) V. Description of Invention (35) The sequence should be able to quickly find the faulty 1Cs so that they can be discarded and continued testing may be a good 1C . Stress tests test the entire device. They test a larger 1C area than diagnostic tests, and are more likely and faster to find errors than diagnostic tests. Therefore, in the case of manufacturing, stress testing should be performed before diagnostic testing or, optionally, before BIST. In another embodiment, an analog test is incorporated into the test ordering method. In general, analog tests are slower than digital tests because analog tests are subject to the natural settling time of the analog device. However, they are usually not as time-consuming and expensive as scan-based testing. Therefore, for ICs where the analog portion may be relatively small, the analog test should be performed after the functional test (ie, the diagnostic test 1104 and the stress test 1106), but before the trace-based test 1108. In addition, for 1C, where analog devices account for the majority, the analog test is the first step to be performed. Especially in the case of manufacturing, the initial error detection may have the highest priority. Will test most areas of 1C. In another specific embodiment, the scan-based test is split into two separate steps. Since the block-level scanning pattern has been generated during the design verification phase, it is best to perform the block-level scan test after the block-level diagnostic test has been performed. This sequence consideration is particularly applicable to the case of prototype debugging. In this case, the highest priority may be the location identification, rather than the initial error detection. In this case, the execution of the inter-block sweep pattern is preferably included at or near the end of the test step to perform the scan-based test 1108. In other specific embodiments, the order of the tests can be changed to achieve the lowest overall cost of each DUT.

564313 第090115780號專利申請案 中文說明書替換頁(92年3月） A7 B7564313 Patent Application No. 090115780 Patent Replacement Sheet of Chinese Manual (March 1992) A7 B7

五、發明説明（36 ) 目標。 關於較佳測試和驗證方法及裝置的進一步資訊請參考隨 附的資料。關於虛擬元件區塊之各方面的額外資訊可在 2000年1月18日所提出之60/176,879號美國臨時專利申請案 中找到，全文在此以提示方式併入本發明。 前面雖然已描述本發明之較佳具體實施例，且隨附的資 料有更進一步的解釋，但仍可能有各種不同的變化，而不 超出本發明之觀念及範圍。一般熟知此技藝者在詳閱本文 之規格及附圖之後，應能明瞭該等變化。因此，本發明只 受限於後附申請專利範圍所述之精神及範圍。 本紙張尺度適用中國國家標準(CNS) A4規格（210 X 297公釐） 564313 第090115780號專利申請案 中文說明書替換頁(92年3月）V. Invention Description (36) Objective. For further information on better testing and verification methods and devices, please refer to the accompanying materials. Additional information on various aspects of the virtual element block can be found in US Provisional Patent Application No. 60 / 176,879, filed January 18, 2000, which is hereby incorporated by reference in its entirety into the present invention. Although the preferred embodiments of the present invention have been described above and the accompanying materials have been further explained, various changes may be made without departing from the concept and scope of the present invention. Those skilled in the art should be able to understand these changes after reading the specifications and drawings in this article. Therefore, the present invention is limited only by the spirit and scope described in the appended patent application scope. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 564313 Patent Application No. 090115780 Patent Replacement Page of Chinese Manual (March 1992)

A7 B7 五、發明説明（ 37) 元件符號對照表 1 00 電腦裝置 110 電腦 1 20 區塊平面配置器 13 0 區塊放置器 13 5 邏輯合成器 1 40 佈線空間估計器 15 0 晶片平面配置器 160 整體/細部路由器 1 70 標準基本單元放置器 1 80 邏輯合成器 1 90 H D L編輯器 19 1 顯示器 1 92 輸入-輸出裝置 195 配置資料庫 200 積體電路 202 基礎區塊 204 處理器 206 記憶體 208 匯流排 2 10 埠 3 04 網表檔案 3 06 組件庫 3 15 遮蔽樓 40 1 設計檔案 404 網表檔案 4 10 配置檔案 4 15 遮蔽樓案 420 測試向量 43 0 資料庫 43 1 虛擬元件區塊資料 43 2 診斷資料 440 虛擬元件區塊 -40- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂A7 B7 V. Description of the invention (37) Component symbol comparison table 1 00 Computer device 110 Computer 1 20 Block plane configurator 13 0 Block placer 13 5 Logic synthesizer 1 40 Wiring space estimator 15 0 Wafer plane configurator 160 Overall / Detail router 1 70 Standard basic unit placer 1 80 Logic synthesizer 1 90 HDL editor 19 1 Display 1 92 Input-output device 195 Configuration database 200 Integrated circuit 202 Basic block 204 Processor 206 Memory 208 Bus Row 2 10 Port 3 04 Netlist file 3 06 Component library 3 15 Shelter building 40 1 Design file 404 Netlist file 4 10 Configuration file 4 15 Shelter building case 420 Test vector 43 0 Database 43 1 Virtual component block data 43 2 Diagnostic data 440 Virtual component block -40- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding

線 564313 第090115780號專利申請案 中文說明書替換頁(92年3月）Line 564313 Patent Application No. 090115780 Patent Specification Replacement Page (March 1992)

五、發明説明（ 38 ) 44 1 診斷測試集合 450 測試台 460 半導體晶圓 500 測試台 502 測試台 5 04 探測卡 5 06 測試輸入轉譯器 5 0 8 測試排程器 5 10 測試控制器 800 晶片 802 處理器 804 記憶體 806 電路區塊 808 裝置匯流排 8 10 輸入/輸出介面 8 12 測試埠 9 10 摺回邏輯 9 12 通訊介面 9 14 I / 0接點 9 16 總計查核 9 18 總計查核 920 晶片 1000 探測卡 100 1 測試裔· 1002 DUT 1004 資料轉譯器 1006 控制邏輯 1008 時脈產生器 10 12 類比訊號產生器 10 14 直接測試介面 -41 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝 訂V. Description of the invention (38) 44 1 Diagnostic test set 450 Test stand 460 Semiconductor wafer 500 Test stand 502 Test stand 5 04 Probe card 5 06 Test input translator 5 0 8 Test scheduler 5 10 Test controller 800 Chip 802 Processor 804 Memory 806 Circuit block 808 Device bus 8 10 I / O interface 8 12 Test port 9 10 Foldback logic 9 12 Communication interface 9 14 I / 0 contact 9 16 Total check 9 18 Total check 920 Chip 1000 Probe card 100 1 Test source 1002 DUT 1004 Data translator 1006 Control logic 1008 Clock generator 10 12 Analog signal generator 10 14 Direct test interface -41-This paper standard applies to China National Standard (CNS) A4 specification (210 X 297 mm) Staple

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564313 A8 B8 C8 D8564313 A8 B8 C8 D8 第090115780號專利申請案 中文申請專利範圍替換本(92年3月） 申請專利範圍Patent Application No. 090115780 Chinese Patent Application Replacement (March 1992) Patent Application Scope 一種用於在一製程環境中測試一包 之積體電路的方法，該方法包括步 含隨機邏輯元件區 驟有： 塊 (a)執行内建的自我測試 路之記憶體和資料路徑； 至少部份地測試該積體 電 (b)執行診斷測試 元件區塊； 至少部份個別地測試該隨機邏輯 (c)使用測試向量來執行庫力 丁應力/則試，至少部份集體地 測试该隨機邏輯元件區塊；及 ⑷執行該積體電路之基㈣描的測試，至少部份地 測試该積體電路中的結構錯誤。 2·如申請專利範圍第β之方法，該方法進—步包❹ 驟：執行該積體電路之類比部份的類比測試。 3.如申請專利範圍第Η之方法，其中該積體電路為一原 型積體電路，且該等步驟之執行順序為步驟⑷，炊後 步驟（b)，然後步驟（c),以及然後步驟（句。 4 ·如申請專利範圍第3項之方法，其中該積體電路包括一 類比部份及一數位部份，該數位部份遠大於該類比部 份，且該方法進一步包括一在步驟⑷和⑷之間執行: 步驟：執行該積體電路之類比部份的類比測試。 5 ·如申請專利範圍第3項之方法，其中該積體電路包括一 類比部份及一數位部份，該類比部份遠大於該數位部 份，且該方法進一步包括一在步騾⑷之前執行的步 驟·執行該積體電路之類比部份的類比測試。 本紙張尺度適用中國國家標準(CNS) A4規格(21〇 X 297公爱） 564313 六、申請專利範圍A method for testing a pack of integrated circuits in a process environment. The method includes the steps of including a random logic element block. Block (a) performs a built-in self-test memory and data path; at least part Partially test the integrated circuit (b) Perform diagnostic test component block; At least partly test the random logic individually (c) Use test vectors to perform the Coulomb stress / test, and at least partly test the collective A block of random logic elements; and performing a test of the basic circuit of the integrated circuit, at least in part, testing for structural errors in the integrated circuit. 2. If the method of the scope of patent application is β, the method further includes the step of: performing an analog test of the analog part of the integrated circuit. 3. The method according to the scope of patent application, wherein the integrated circuit is a prototype integrated circuit, and the execution order of these steps is step ⑷, after cooking step (b), then step (c), and then step (Sentence. 4) If the method of claim 3 of the patent application range, wherein the integrated circuit includes an analog portion and a digital portion, the digital portion is much larger than the analog portion, and the method further includes a step Execute between ⑷ and ⑷: Step: Perform the analog test of the analog part of the integrated circuit. 5 · If the method of the scope of patent application item 3, where the integrated circuit includes an analog part and a digital part, The analog portion is much larger than the digital portion, and the method further includes a step performed before the step · perform an analog test of the analog portion of the integrated circuit. This paper size applies to China National Standard (CNS) A4 Specifications (21〇X 297 public love) 564313 6. Scope of patent application 6 .如申請專利範圍第1項之方法，其中該積體電路為在一 用於場用之積體電路生產的積體電路，且該等步驟之執 行順序為步驟（c)，然後步驟（a)，然後步騾（b)，以及然 後步驟（d)。 7 ·如申請專利範圍第6項之方法，其中該積體電路包括一 類比部份及一數位部份，該數位部份遠大於該類比部 份，且該方法進一步包括一在步驟⑻和⑷之間執行的 步驟：執行該積體電路之類比部份的類比測試。 8 ·如申請專利範圍第6項之方法，其中該積體電路包括一 類比部份及一數位部份，該類比部份遠大於該數位部 份，且眾方法進一步包括一在步驟⑷之前執行的步 驟：執行該積體電路之類比部份的類比測試。 9. 一種用於測武積體電路之裝置，該裝置包括： a · —元憶體’用於儲存起始内建自我測試所需之簽 名、診斷測試所需之輸入、應力測試所需之測試向量以 及基於掃描之測試所需之掃描樣式；以及 b . —處理咨，用於起始内建自我測試、診斷測試、應 力測試及基於掃描的測試並評估該積體電路在這些測試 方面的效能。 10· 11.6. The method according to item 1 of the scope of patent application, wherein the integrated circuit is an integrated circuit produced by an integrated circuit for field use, and the execution order of these steps is step (c), and then step ( a), then step (b), and then step (d). 7 · The method of claim 6 in the patent application range, wherein the integrated circuit includes an analog portion and a digital portion, the digital portion is much larger than the analog portion, and the method further includes a step ⑻ and ⑷ Steps performed between: performing an analog test of the analog portion of the integrated circuit. 8 · The method according to item 6 of the patent application range, wherein the integrated circuit includes an analog portion and a digital portion, the analog portion is much larger than the digital portion, and the methods further include a step before step ⑷ Step: Perform the analog test of the analog part of the integrated circuit. 9. A device for testing a voluminous body circuit, the device includes: a-Yuanyuan 'is used to store signatures required for initial built-in self-test, inputs required for diagnostic testing, and stress required for stress testing Test vectors and scan patterns required for scan-based tests; and b. — Processing instructions to initiate built-in self-tests, diagnostic tests, stress tests, and scan-based tests and evaluate the performance of the integrated circuit in these tests efficacy. 10.11. 裝Hold 如申請專利範圍第9項之裝置，該裝置根據初期錯誤 測與初期錯誤鑑別的相對優先度，規劃該處理器使其 定該積體電路的測試順序。 如申請專利範固第1G項之裝置’纟中該初期錯誤鑑別For example, the device in the ninth scope of the patent application, the device plans the processor to determine the test sequence of the integrated circuit according to the relative priority of the initial error detection and the initial error identification. Such as the initial misidentification in the patent application for the device 1G of Fangu ’ A B c DA B c D 564313 六、申請專利範圍 優先度超越初期錯誤偵測的優先度，且該處理器被規劃 按照内建自我測試、診斷測試、應力測試、然後是基於 知描之測試的次序，排定測試順序。 12·如申請專利範圍第1〇項之裝置，其中該初期錯誤偵測的 優先度超越初期錯誤鑑別的優先度，且該處理器被規劃 按照應力測試、内建自我測試、診斷測試、及基於掃描 之測試的次序，排定測試順序。 13.如申請專利範圍第9項之裝置，其中該記憶體進一步儲 存用於測試該積體電路之類比元件的類比測試，且該處 理器被規劃起始該等類比測試並評估該積體電路在該等 類比測試方面的效能。 H· —種電腦可讀取媒體，該媒體儲存一或多個連續的指 令，用以測試一製造完成的積體電路，該積體電路包含 記憶體、隨機邏輯及資料路徑之元件區塊，該一或多個 連續指令造成一或多個處理器執行複數個動作，該等動 作包括： (a) 執行内建自我測試，至少部份地測試該積體電路 之記憶體及資料路徑； (b) 執行診斷測試，至少部份個別地測試該隨機邏輯 元件區塊； (c) 使用測試向量來執行應力測試，至少部份集體地 測試該隨機邏輯元件區塊；以及 (d) 執行該積體電路之基於掃描的測試，至少部份地 -3 -564313 6. Scope of patent application Priority exceeds the priority of initial error detection, and the processor is planned to arrange the test order according to the built-in self-test, diagnostic test, stress test, and then knowledge-based test. 12. If the device of the scope of patent application No. 10, the priority of the initial error detection is higher than the priority of the initial error identification, and the processor is planned to be based on stress test, built-in self test, diagnostic test, and Scan the test order and schedule the test order. 13. The device according to item 9 of the scope of patent application, wherein the memory further stores analog tests for testing the analog components of the integrated circuit, and the processor is planned to initiate the analog tests and evaluate the integrated circuit Effectiveness in such analog tests. H · — a computer-readable medium that stores one or more consecutive instructions to test a manufactured integrated circuit that includes memory, random logic and component blocks of data paths, The one or more consecutive instructions cause one or more processors to perform a plurality of actions, including: (a) performing a built-in self test, at least partially testing the memory and data paths of the integrated circuit; ( b) performing a diagnostic test, at least partially individually testing the random logic element block; (c) using a test vector to perform a stress test, and at least partially collectively testing the random logic element block; and (d) performing the product Scan-based testing of body circuits, at least in part -3- 564313564313 申請專利範圍 _ 3M. •..n.Patent application scope _ 3M. • ..n. 測試該積體電路之結構性錯誤。 15 ·如申凊專利範圍第1 *項之電腦可讀取媒體，該等動作進 一步包括執行該積體電路之一類比部份之一類比測試。 16.如申請專利範圍第14項之電腦可讀取媒體，其中該積體 電路為一原型積體電路，且該等動作係以動作（a)，然 後動作（b)，然後動作（c)，以及然後動作（d)的順序執 行。 17·如申請專利範圍第14項之電腦可讀取媒體，其中該積體 電路為在一用於場用之積體電路生產的積體電路，且該 等步驟之執行順序為步驟，然後步驟，然後步騾 (b)，以及然後步驟（句。 18. —種用於測試一受測裝置之探測卡，該探測卡包含： (a) —受測裝置介面； (b) —測試器介面； (c) 一記憶體，用於儲存該受測裝置所需的測試輸 入；以及 (d) —資料轉譯器，連接在該記憶體及該測試器介面 之間，用於格式化在該記憶體及該測試器介面之間通訊 的測試資料。 19·如申請專利範圍第18項之探測卡，該探測卡進一步包含 一時脈產生器’該時脈產生器連接在該測試器介面及該 受測裝置介面之間，用於從該測試器介面接收控制訊號 並傳送時脈訊號到該受測裝置。 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱) 564313Test the integrated circuit for structural errors. 15 · If the computer-readable media of item 1 * in the scope of the patent application, these actions further include performing an analog test of an analog portion of the integrated circuit. 16. The computer-readable medium according to item 14 of the scope of patent application, wherein the integrated circuit is a prototype integrated circuit, and the actions are performed by action (a), then action (b), and then action (c) , And then the sequence of actions (d) is performed. 17. If the computer-readable medium of item 14 of the scope of patent application, the integrated circuit is an integrated circuit produced by a integrated circuit for field use, and the execution order of these steps is step, and then step , Then step (b), and then step (sentence. 18.-a probe card for testing a device under test, the probe card contains: (a)-the interface of the device under test; (b)-the interface of the tester (C) a memory for storing the test inputs required by the device under test; and (d) a data translator connected between the memory and the tester interface for formatting the memory Test data for communication between the body and the tester interface. 19. If the probe card for item 18 of the patent application scope, the probe card further includes a clock generator 'the clock generator is connected to the tester interface and the receiver The test device interface is used to receive the control signal from the tester interface and send the clock signal to the device under test. -4- This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) 564313 A8 B8 C8 _____Ό8 ☆、申請專利範圍 20. 如申請專利範圍第18項之探測卡，該探測卡進一步包含 連接到該記憶體之控制邏輯，用於提供輸入給該受測装 置。 21. 如申請專利範圍第20項之探測卡，該探測卡進一步包含 一時脈產生器，該時脈產生器連接在該測試器介面及該 控制邏輯之間，用於從該測試器介面接收控制訊號並傳 送時脈訊號到該控制邏輯。 22·如申請專利範圍第21項之探測卡，該探測卡進一步包含 一類比訊號產生器，該類比訊號產生器連接在該測試器 介面及該受測裝置介面之間，該類比訊號產生器被規劃 從該測試器介面接收代表一類比測試之數位訊號、根據 該數位訊號產生一類比訊號以及傳送該類比訊號到該受 測裝置介面。 23. 如申請專利範圍第22項之探測卡，該資料轉譯器進一步 連接在該受測裝置介面及該測試器介面之間，用於格式 化在該受測裝置介面及該測試器介面之間通訊的測試資 料’且該時脈產生器進一步連接到該受測裝置介面，用 於傳送時脈訊號到該受測裝置。 24. 如申請專利範圍第丨8項之探測卡，其中該記憶體包含一 先進先出（FIFO>。 25·如申請專利範圍第18項之探測卡，該探測卡進一步包含 一摺回電路，該摺回電路連接至少該受測裝置的兩個接 點0 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱：） 564313 六、申請專利範圍A8 B8 C8 _____ Ό8 ☆ Scope of patent application 20. For a probe card with the scope of patent application No. 18, the probe card further includes control logic connected to the memory for providing input to the device under test. 21. If the probe card of the scope of application for patent No. 20, the probe card further comprises a clock generator connected between the tester interface and the control logic for receiving control from the tester interface. Signal and send the clock signal to the control logic. 22. If the detection card of the scope of patent application No. 21, the detection card further includes an analog signal generator, the analog signal generator is connected between the tester interface and the device under test interface, the analog signal generator is It is planned to receive a digital signal representing an analog test from the tester interface, generate an analog signal based on the digital signal, and send the analog signal to the interface of the device under test. 23. If the probe card of the scope of patent application is No. 22, the data translator is further connected between the interface of the device under test and the interface of the tester, and is used for formatting between the interface of the device under test and the interface of the tester Communication test data 'and the clock generator is further connected to the interface of the device under test for transmitting a clock signal to the device under test. 24. If the probe card with the scope of patent application No. 丨 8, the memory contains a first-in-first-out (FIFO>). 25. If the probe card with the scope of patent application No. 18, the probe card further includes a foldback circuit The return circuit is connected to at least two contacts of the device under test. 0 -5- This paper size applies to China National Standard (CNS) A4 specifications (210X297 public love :) 564313 6. Scope of patent application 26·如申請專利範圍第25項之探測卡，該探測卡進一步包含 一連接到總計檢核邏輯之元件介面。 27·如申請專利範圍第18項之探測卡，該探測卡進一步包含 一類比訊號產生器，該類比訊號產生器連接在該測試器 介面及該受測裝置介面之間，該類比訊號產生器被規劃 從該測試器介面接收代表一類比測試的數位訊號、根據 該數位訊號產生一類比訊號以及傳送該類比訊號到該受 測裝置介面。 28·如申請專利~範圍第27項之探測卡，該探測卡進一步包含 一時脈產生器，該時脈產生器連接在該測試器介面及該 受測裝置介面之間，用於從該測試器介面接收時脈訊號 及傳送時脈訊號到該受測裝置。 29_如申請專利範圍第丨8項之探測卡，該探測卡進一步包含 一電源供應，該電源供應連接到該記憶體及該資料轉譯 器’而且與該受測裝置之間是電性絕緣的。 30·如申請專利範圍第18項之探測卡，該探測卡進一步包含 一直接測試介面，用於從一測試器直接執行該受測装置 之測試。 31·如申請專利範圍第18項之探測卡，該探測卡進一步包含 一掃描測試介面，用於從一測試器直接執行該受測装置 之測試。 32. —種用於測試一受測裝置之探測卡，該探測卡包含： (a) —受測裝置介面； -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）26. The detection card of claim 25, further comprising a component interface connected to the total check logic. 27. If the probe card of the scope of application for patent No. 18, the probe card further includes an analog signal generator, the analog signal generator is connected between the tester interface and the device under test interface, and the analog signal generator is It is planned to receive a digital signal representing an analog test from the tester interface, generate an analog signal based on the digital signal, and send the analog signal to the interface of the device under test. 28. If a patent card is applied for a probe card with the scope of item 27, the probe card further includes a clock generator, which is connected between the tester interface and the tested device interface, and is used for removing the tester. The interface receives the clock signal and sends the clock signal to the device under test. 29_ If the probe card of the scope of patent application No. 丨 8, the probe card further includes a power supply, the power supply is connected to the memory and the data translator 'and is electrically insulated from the device under test . 30. The probe card of claim 18, the probe card further includes a direct test interface for directly performing a test of the device under test from a tester. 31. The probe card of claim 18, the probe card further includes a scanning test interface for directly performing a test of the device under test from a tester. 32. —A probe card for testing a device under test, the probe card includes: (a) — the interface of the device under test; -6- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 裝 訂Binding 564313 is--cb 8 8 A B c D 月564313 is--cb 8 8 A B c D month 六、申請專利範圍 (b) —測試器介面； (c) 一類比訊號產生器，連接在該測試器介面及該受 測裝置介面之間，該類比訊號產生器被規劃從該測試器 介面接收代表一類比測試之數位訊號、根據該數位訊號 產生一類比訊號，以及傳送該類比訊號到該受測裝置介 面；及 (d) —資料轉譯器，連接在該受測裝置介面及該測試 器介面之間，且格式化在該受測裝置介面及該測試器介 面之間通訊的測試資料。 33·如申請專利範圍第32項之探測卡，該探測卡進一步包含 一時脈產生器，該時脈產生器連接到該測試器介面及該 控制邏輯，用於從該測試器介面接收控制訊號以及傳送 時脈訊號到該控制邏輯。 3 4 ·如申清專利範圍第3 2項之探測卡，該探測卡進一步包含 一摺回電路，該摺回電路連接至少該受測裝置的兩個接 點。 35·如申請專利範圍第34項之探測卡，其中該摺回電路包含 一個連接到總計檢核邏輯的元件介面。 36·如申請專利範圍第32項之探測卡，該探測卡進一步包含 一電源供應，該電源供應連接到該記憶體及資料轉譯 器’而且與該受測裝置之間是電性絕緣的。 37.如申請專利範圍第32項之探測卡，該探測卡進一步包含 一直接測試器介面，用於從一測試器直接執行該受測裝 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 5643136. Scope of patent application (b)-Tester interface; (c) An analog signal generator connected between the tester interface and the device under test interface. The analog signal generator is planned to receive from the tester interface Digital signal representing an analog test, generating an analog signal based on the digital signal, and transmitting the analog signal to the interface of the device under test; and (d) — data translator, connected to the interface of the device under test and the interface of the tester And format test data communicated between the interface of the device under test and the interface of the tester. 33. If the detection card of the scope of patent application No. 32, the detection card further includes a clock generator connected to the tester interface and the control logic for receiving a control signal from the tester interface and Send a clock signal to the control logic. 3 4 · If the probe card of item 32 of the patent scope is applied, the probe card further includes a return circuit, which is connected to at least two contacts of the device under test. 35. The detection card of claim 34, wherein the return circuit includes a component interface connected to the total check logic. 36. The detection card according to item 32 of the application for a patent, the detection card further comprises a power supply which is connected to the memory and the data translator 'and is electrically insulated from the device under test. 37. If the probe card of the scope of application for patent No. 32, the probe card further includes a direct tester interface for directly executing the tested device from a tester. The paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 564313 置之測試。 38·如申請專利範圍第32項之探測卡，該探測卡進一步包含 掃描測試器介面，用於從一測試器直接執行該受測裝 置之掃描測試。 39· 一種用於測試一受測裝置之探測卡，該探測卡包含： 0) —受測裝置介面； (b) —測試器介面； (c) 一連接該受測裝置至少兩個接點之摺回電路；以 及 (d) —資料轉譯器，連接在該受測裝置介面及該測試 器介面之間，且格式化在該受測裝置介面及該測試器介 面之間通訊的測試資料。 40·如申請專利範圍第39項之探測卡，該探測卡進一步包含 一時脈產生器，該時脈產生器連接到該測試器介面及該 控制邏輯，用於從該測試器介面接收控制訊號以及傳迗 時脈訊號到該控制邏輯。 41. 如申請專利範圍第39項之探測卡，該探測卡進一步包含 一電源供應，該電源供應連接到該記憶體及資料轉譯 器’而且與該受測裝置之間是電性絕緣的。 42. 如申請專利範圍第39項之探測卡，該探測卡進一步包含 一直接測試器介面，用於從一測試器直接執行該受》則装 置之測試。 43·如申請專利範圍第39項之探測卡，該探測卡進一步包含Test. 38. The detection card of claim 32, which further includes a scan tester interface for directly performing a scan test of the device under test from a tester. 39 · A probe card for testing a device under test, the probe card includes: 0)-the interface of the device under test; (b)-the interface of the tester; (c) a connection to at least two contacts of the device under test Foldback circuit; and (d) a data translator connected between the device under test interface and the tester interface and formatting test data communicated between the device under test interface and the tester interface. 40. The probe card according to item 39 of the patent application scope, the probe card further comprising a clock generator connected to the tester interface and the control logic for receiving a control signal from the tester interface and Pass the clock signal to the control logic. 41. If the detection card of the scope of patent application No. 39, the detection card further comprises a power supply, the power supply is connected to the memory and the data translator 'and is electrically insulated from the device under test. 42. If the probe card of the scope of patent application No. 39, the probe card further includes a direct tester interface for directly performing the test of the device from a tester. 43. If the detection card of the scope of patent application No. 39, the detection card further includes -8 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) 564313 as ^ 3. 19-8-This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 564313 as ^ 3. 19 六、申請專利範圍 一掃描測試器介面，用於從一測試器直接執行該受測裝 置之掃描測試。 44· 一種積體電路，該積體電路包含： (a) 複數個經由一匯流排連接之電路元件區塊； (b) 複數個具有複數條對應之連接至該匯流排之引線 I / 0接點，該等I / 〇接點提供與該積體電路之外界通訊 的能力； (c) 一擅回電路，用於將在該等複數條引線之一上面 傳送之一訊號重新導向到該等複數個接點之一；及 (d) 用於啟用及停用該擅回電路之擅回邏輯。 45·如申請專利範圍第44項之積體電路，該積體電路進一步 包含一連接至該匯流排之測試埠，且每一個該等電路元 件區塊各包含一個與該裝置匯流排的介面。 46.如申請專利範圍第45項之積體電路，其中該測試埠包含 一個通訊起始包裝器且每一區塊介面包含一目標包裝 器。 47·如申請專利範圍第46項之積體電路，其中該積體電路進 一步包含一經由一區塊介面連接到該匯流排的可鎖定記 憶體。 48·-種電腦可讀取媒體，其中儲存_或多個連續的用於指 出一積體電路的指令，該等一或多個連續的指令促使一 或多個處理器執行複數個動作，該等動作包括： (a)指出複數個經由一匯流排互連之電路元件區塊； -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 裝 訂6. Scope of patent application A scan tester interface is used to directly perform a scan test of the device under test from a tester. 44. An integrated circuit comprising: (a) a plurality of circuit element blocks connected through a bus; (b) a plurality of corresponding I / 0 leads connected to the bus Points, the I / 〇 contacts provide the ability to communicate with the outside boundary of the integrated circuit; (c) a fraudulent circuit for redirecting a signal transmitted on one of the plurality of leads to the One of a plurality of contacts; and (d) the tamper logic for enabling and disabling the tamper circuit. 45. If the integrated circuit of item 44 of the patent application scope, the integrated circuit further includes a test port connected to the bus, and each of these circuit element blocks includes an interface with the device bus. 46. The integrated circuit of item 45 in the scope of patent application, wherein the test port includes a communication start wrapper and each block interface includes a target wrapper. 47. The integrated circuit of claim 46, wherein the integrated circuit further includes a lockable memory connected to the bus via a block interface. 48 · -A computer-readable medium, which stores _ or a plurality of consecutive instructions for indicating an integrated circuit, and the one or more consecutive instructions cause one or more processors to perform a plurality of actions, the Such actions include: (a) Point out a plurality of circuit element blocks interconnected by a bus; -9- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) binding 564313 Λ BCD 年％3·日修正 一__ MJL 申請專利範圍 (b) 指出複數個具有複數條對應之連接至該匯流排之 引線的I / 0接點，該等I / 0接點提供與該積體電路之外 界通訊的能力； (c) 指出一摺回電路，該摺回電路用於將在該等複數 條引線之一上面傳送之一訊號重新導向到該等複數個接 點之一；以及 (d) 指出用於啟用及停用該摺回電路之摺回邏輯。 49.如申請專利範圍第48項之電腦可讀取媒體，該等動作進 一步包括指出一連接至該匯流排之測試埠，且每一個該 等元件區塊各包含一個與裝置匯流排的區塊介面。 50·如申請專利範圍第49項之電腦可讀取媒體，其中該測試 埠包含一通訊起始包裝器且每一區塊介面包含一目標包 裝器。 51.如申請專利範圍第50項之電腦可讀取媒體，該等動作進 一步包括指出一經由一區塊介面連接到該匯流排之可鎖 定的記憶體。 52· —用於測試一受測裝置之測試裝置，該測試裝置包括： (a) 受測裝置，該受測裝置包含一記憶體及一測試邏 輯’用於在測試該受測裝置的期間鎖定至少一部份該記 憶體； (b) —測試器，該測試器連線至該受測裝置，且傳送 數位訊號以鎖定至少一部份該記憶體；及 (c) 一連線至該受測裝置及該測試器之探測卡，該探 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313 A BCD 六、申請專利範圍 測卡包含一用於傳送時脈訊號到該受測裝置之時脈產生 器及一連線於該受測裝置介面及該測試器介面之間的資 料轉譯器’該資料轉譯器格式化在該受測裝置介面及該 測試器介面之間通訊的測試資料。 53·如申請專利範圍第52項之測試裝置，其中該受測裝置進 一步包含一連接到該受測裝置上之一裝置匯流排之測試 崞’且该受測裝置之每一個元件區塊各包含一個與該裝 置匯流排的區塊介面。 54.如申請專利範圍第53項之測試裝置，其中該測試部包含 一通訊起始包裝器，且每一區塊介面包含一目標包裝 器。 55·如申清專利範圍第52項之測試裝置，其中該受測装置包 含一用以將來自該受測裝置之輸出訊號輸入到該受測装 置的摺回電路及一用以啟動該摺回電路的邏輯。 56. —種用於產生測試向量以便在一製造測試台測試一積體 電路之方法，該方法括步驟： (a) 獲得功能層級的測試向量； (b) 將該等測試向量轉換成一系列的訊息區塊； (c) 應用一介面協定到該等一系列之訊息區塊以產生 測試向量資料；及 (d) 應用一用於一受測裝置之介面協定於該測試向量 資料。 57· —種用於產生測試向量以便在一製造測試台測試—積體 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐） 564313564313 Λ BCD year% 3 · day amendment 1 __ MJL patent application scope (b) indicates a plurality of I / 0 contacts with a plurality of corresponding leads connected to the bus, and these I / 0 contacts are provided with The ability of the integrated circuit to communicate outside the boundary; (c) indicate a foldback circuit for redirecting a signal transmitted over one of the plurality of leads to one of the plurality of contacts ; And (d) indicate the foldback logic used to enable and disable the foldback circuit. 49. If the computer-readable media of item 48 of the scope of patent application, the actions further include indicating a test port connected to the bus, and each of these component blocks each includes a block with the device bus interface. 50. The computer-readable medium of item 49 in the scope of the patent application, wherein the test port includes a communication start wrapper and each block interface includes a target wrapper. 51. In the case of a computer-readable medium of claim 50, the actions further include pointing to a lockable memory connected to the bus via a block interface. 52 · —Test device for testing a device under test, the test device including: (a) the device under test, the device under test includes a memory and a test logic 'for locking during the test of the device under test At least a portion of the memory; (b) a tester connected to the device under test and transmitting a digital signal to lock at least a portion of the memory; and (c) a connection to the receiver The testing device and the probe card of the tester, the probe -10- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 A BCD VI. Patent application scope A clock generator to the device under test and a data translator connected between the device under test interface and the tester interface. The data translator is formatted on the device under test interface and the tester. Test data for communication between interfaces. 53. The test device according to item 52 of the application for a patent, wherein the device under test further includes a test of a device bus connected to the device under test, and each component block of the device under test includes A block interface to the device's bus. 54. The testing device according to item 53 of the patent application scope, wherein the testing section includes a communication starter wrapper, and each block interface includes a target wrapper. 55. The test device according to item 52 of the claim, wherein the device under test includes a return circuit for inputting an output signal from the device under test to the device under test and a circuit for activating the return The logic of the circuit. 56. A method for generating test vectors for testing an integrated circuit in a manufacturing test bench, the method comprising the steps of: (a) obtaining functional level test vectors; (b) converting the test vectors into a series of Message blocks; (c) applying an interface agreement to the series of message blocks to generate test vector data; and (d) applying an interface agreement for a device under test to the test vector data. 57 · —A kind of test vector for generating test vectors for testing on a manufacturing test bench—Integration -11-This paper size is in accordance with China National Standard (CNS) A4 (210 x 297 mm) 564313 電路之裝置，該裝置包含： ⑷-用於儲存功能層級之測試向量的記憶體；及 (b) 一連接到該記憶體的處理器，用於將該等測試洽 讀譯成訊息區埃、應用—介面協定到該訊息區塊以j 生測試向量資料，以及應用—用於-受測裝置之介面惊 定於該測試向量資料。 58. -種用於產生測試向量以便在—製造測試台測試—積體 電路之裝置，該裝置包含： 、 (a) 一用於儲存功能層級之測試向量的裝置；及 ⑻-處理裝置，連接到該料儲存功能層級之測試 向量的裝置，該處理裝置用於將該等測試向量轉譯成訊 :區鬼應用一介面協定到該訊息區塊以產生測試向量 資料’以及應用-用於-受測裝置之介面協定於該測試 向量資料。 59.-種電腦可讀取媒體’該電腦可讀取媒體儲存一或多個 連續的指令’用於產生測試向量以便在一製造測試台測 武-積禮電路’該等-或多個連續的指令促使_或多個 處理器執行複數個動作，該等動作包括： (a) 指出功能層級的測試向量； (b) 將該等測試向量轉換成一系列的訊息區塊； ⑷應用-介面協定到該等一系列之訊息區塊以產生 測試向量資料；及 ⑷應用一用於一 k 訂The device of the circuit includes: (i) a memory for storing test vectors at a functional level; and (b) a processor connected to the memory for translating the tests into a message area, Application—Interface protocol to the message block to generate test vector data, and Application—for—The interface of the device under test is determined by the test vector data. 58.-A device for generating test vectors for testing the integrated circuit at a manufacturing test bench, the device comprising: (a) a device for storing test vectors at a functional level; and-a processing device, connected A device for storing test vectors at the functional level of the material, the processing device is used to translate the test vectors into information: the area ghost applies an interface protocol to the message block to generate test vector data 'and application-for-receiving The interface of the test device is based on the test vector data. 59.- A computer-readable medium 'The computer-readable medium stores one or more consecutive instructions' for generating test vectors for testing a military test bench in a manufacturing test-Jili circuit' etc.-or more consecutive The instructions cause the processor or processors to perform a number of actions, including: (a) test vectors indicating functional levels; (b) converting these test vectors into a series of message blocks; ⑷ application-interface protocol To the series of information blocks to generate test vector data; and ⑷ apply one for a k order 丈測裝置之介面協定於該測試向量 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313 A B c DThe interface agreement of the measuring device is based on the test vector. -12- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 A B c D A、申請專利範圍 資料。 6〇· —種用於產生診斷測試以便在一製造測試台測試一積體 電路之方法，該方法包括步驟： (a) 獲得用於一積體電路設計之虛擬元件區塊的功能 層級測試向量； (b) 將該等診斷測試轉譯成準確定時診斷測試； (c) 將該準確定時診斷測試轉換成記憶載入指令；及 (d) 應用一用於一受測裝置之介面協定於該記憶載入 指令。 61·—種電腦可讀取媒體，該電腦可讀取媒體儲存一或多個 連續的指令，用於產生測試向量以便在一製造測試台測 試一積體電路，該等一或多個連續的指令促使一或多個 處理器執行複數個動作，該等動作包括： (a) 指出一複數個虛擬元件區塊； (b) 指出該等複數個虛擬元件區塊之間的互連； (c) 指出一複數個用於測試已製造完成之該等複數個 虛擬元件區塊之診斷測試的集合，每一個該等診斷測試 的集合測試该等複數個虛擬元件區塊中對應的一個；及 (d) 指定一個用於測試該已製造完成之積體電路之測 試向量的集合。 62·—種電腦可讀取媒體，該電腦可讀取媒體儲存一或多個 連續的指令，用於產生測試向量以便在一製造測試台測 試一積體電路，該等一或多個連續的指令促使一或多個 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 564313 A8 ； B8 ; C8 ! ____ D8 六、申請專利範園 處理器執行複數個動作，該等動作包括： (a) 指出用於測試該積體電路之功能規格之一功能層 級的測試向量； (b) 將該等測試向量轉譯成訊息區塊； (c) 應用一介面協定到該等一系列之訊息區塊以產生 測試向量資料；及 (d) 應用該積體電路之一介面協定於該測試向量資料。 63·—種用於製造一電腦可讀取媒體之方法，該電腦可讀取 媒體包含一積體電路之一設計及用於製造和測試該已製 造完成之積體電路的功能的測試輸入的集合，該方法包 括步驟： ⑷設計要用在該積體電路之設計中的虛擬元件區塊； (b) 針對每一虛擬元件區塊設計一診斷測試； (c) 決定包含蔹等虛擬元件區塊之該積體電路的設計； (d) 獲得用於該積體電路之高階測試向量； ⑷利用該等測試向量及診斷測試來驗證該積體電路； (f) 擴大該等診斷測試及測試向量到一製程環境；及 (g) 連同該等擴大的測試向量包裝該積體電：:設計。 •14-A. Information on the scope of patent application. 60. A method for generating a diagnostic test to test an integrated circuit at a manufacturing test bench, the method comprising the steps of: (a) obtaining a functional level test vector of a virtual component block for an integrated circuit design (B) translate these diagnostic tests into accurate timed diagnostic tests; (c) convert the accurate timed diagnostic tests into memory load instructions; and (d) apply an interface protocol for a device under test to the memory Load instruction. 61 · —A computer-readable medium that stores one or more consecutive instructions for generating test vectors for testing an integrated circuit in a manufacturing test bench. The one or more consecutive The instructions cause one or more processors to perform a plurality of actions including: (a) specifying a plurality of virtual element blocks; (b) specifying an interconnection between the plurality of virtual element blocks; (c) ) Indicate a set of diagnostic tests for testing the plurality of virtual component blocks that have been manufactured, each set of such diagnostic tests testing a corresponding one of the plurality of virtual component blocks; and ( d) Specify a set of test vectors for testing the completed integrated circuit. 62 · —A computer-readable medium that stores one or more consecutive instructions for generating test vectors for testing an integrated circuit in a manufacturing test bench, such one or more consecutive The instruction prompts one or more -13- This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 564313 A8; B8; C8! ____ D8 6. The patent applicant Fanyuan processor performs a number of actions, These actions include: (a) specifying a test vector at the functional level for testing the functional specifications of the integrated circuit; (b) translating the test vectors into message blocks; (c) applying an interface protocol to the Waiting for a series of message blocks to generate test vector data; and (d) applying an interface agreement of the integrated circuit to the test vector data. 63 · —A method for manufacturing a computer-readable medium containing a design of an integrated circuit and test inputs for manufacturing and testing the function of the completed integrated circuit The method includes the steps of: ⑷ designing virtual component blocks to be used in the design of the integrated circuit; (b) designing a diagnostic test for each virtual component block; (c) determining to include virtual component areas such as 蔹Block the design of the integrated circuit; (d) obtain high-order test vectors for the integrated circuit; ⑷ use the test vectors and diagnostic tests to verify the integrated circuit; (f) expand the diagnostic tests and tests Vector to a process environment; and (g) package the integrated circuit with the expanded test vector :: design. • 14-