WO2010035450A1 - 試験モジュール、試験装置および試験方法 - Google Patents
試験モジュール、試験装置および試験方法 Download PDFInfo
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- WO2010035450A1 WO2010035450A1 PCT/JP2009/004734 JP2009004734W WO2010035450A1 WO 2010035450 A1 WO2010035450 A1 WO 2010035450A1 JP 2009004734 W JP2009004734 W JP 2009004734W WO 2010035450 A1 WO2010035450 A1 WO 2010035450A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
- G01R31/31919—Storing and outputting test patterns
- G01R31/31921—Storing and outputting test patterns using compression techniques, e.g. patterns sequencer
Definitions
- the present invention relates to a test module, a test apparatus, and a test method.
- the present invention particularly relates to a test module, a test apparatus, and a test method for compressing and storing a test program used for testing a device under test.
- This application is related to the following Japanese application and claims priority from the following Japanese application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application. 1. Japanese Patent Application No. 2008-247690 Filing Date September 26, 2008
- the test apparatus performs a test of a device under test (DUT: Device Under Test) to be tested based on a test program.
- the test program is to compare the instruction to be executed by the test equipment with the test pattern output to each terminal of the device under test or the output pattern output from each terminal of the device under test. Including.
- a test apparatus that compresses a test program using a repetitive instruction is used for the purpose of reducing the data amount of the test program.
- an IDXI instruction is executed as a repeat instruction, and the same test pattern can be repeatedly output to each terminal of the DUT for the number of times designated as an operand. That is, in the conventional test apparatus, when the same pattern is continuously used for a plurality of instruction cycles for all terminals, the size of the test program is reduced by using repetitive instructions.
- Patent Document 1 discloses a test apparatus that stores a test mode sequence in a test mode or a test pattern sequence in a normal mode independently for each instruction in a test pattern memory.
- a pattern sequence in a format suitable for the operation mode of the DUT is stored in the test pattern memory so that the test program can be effectively compressed.
- an object of one aspect of the present invention is to provide a test module, a test apparatus, and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous specific examples of the present invention.
- a compression information storage unit that stores compressed information that associates a pattern string and pattern string identification information that identifies the pattern string with respect to a plurality of compressed information, and a pattern
- a basic pattern storage unit that stores pattern sequence data including a sequence or pattern sequence identification information in association with an instruction as a group of basic patterns for a plurality of pattern sequence data, and instruction information for instructing the processing order of the basic patterns are stored.
- the selection compression information used for the basic pattern to be processed indicated by the instruction information from the plurality of compression information stored in the compression information storage unit, and the basic pattern to be processed The basic pattern reading unit that reads the pattern string data to be read from the basic pattern storage unit and the basic pattern reading unit
- the extracted pattern string data includes pattern string identification information
- a pattern string reading unit that reads the pattern string corresponding to the pattern string identification information with reference to the selection compression information selected by the selection unit and a basic pattern reading unit
- a test module including a pattern string included in the read pattern string data or a pattern output unit that outputs a pattern string corresponding to the pattern string identification information read by the pattern string reading unit.
- the information processing apparatus may further include a basic pattern information storage unit that stores compressed information identification information for identifying compressed information used for processing of the basic pattern in association with the basic pattern. Selection compression information can be selected by referring to the information.
- the compressed information storage unit can store compressed information further including frequency information specifying the number of repetitions of the pattern string as the compressed information, and the pattern output unit can output the pattern string repeatedly by the number of repetitions specified by the frequency information.
- the compression information storage unit can store compression information including a predetermined pattern string defined in advance or an arbitrary pattern string defined for each compression information as a pattern string.
- the compression information storage unit includes a plurality of arbitrary pattern strings as a pattern string, and single pattern string identification information for identifying the whole of the plurality of arbitrary pattern strings as frequency information indicating the number of the plurality of arbitrary pattern strings.
- the pattern output unit can output a plurality of arbitrary pattern strings as many as specified by the number-of-times information.
- the compression information storage unit can store a pattern string and pattern string identification information for each input or output channel as compression information, and the pattern output unit can output a pattern string for each channel.
- the compression information storage unit stores the high-speed mode pattern string or the low-speed mode pattern string as the pattern string, and identifies whether the pattern string is the high-speed mode pattern string or the low-speed mode pattern string as the pattern string identification information.
- Pattern identification information can be stored.
- the compression information storage unit stores the high-speed mode pattern sequence as a pattern sequence included in the compression information, and also uses short bit pattern sequence identification information that can designate one address space as the pattern sequence identification information or an address larger than one address space.
- a long bit pattern string identification information that can specify a space can be stored, and a predefined high frequency default pattern string that is frequently used can be assigned as a pattern string identified by the short bit pattern string identification information.
- a low-frequency default pattern sequence that is less frequently used than a predefined high-frequency default pattern sequence can be assigned.
- the compressed information storage unit can store an arbitrary pattern sequence defined for each piece of compressed information as well as a high-speed mode pattern sequence as all pattern sequences included in the compressed information, and can store null data as pattern sequence identification information.
- a compression information storage unit that stores a plurality of pieces of compression information that associates a pattern string and pattern string identification information that identifies the pattern string, and a pattern string or pattern string identification information are commanded
- a basic pattern storage unit that stores the pattern sequence data included in association with a plurality of pattern sequence data as a group of basic patterns, an instruction information storage unit that stores instruction information that indicates the processing order of the basic patterns, and instruction information
- the selection unit that selects the selection compression information to be used for the basic pattern to be processed instructed from the plurality of pieces of compression information stored in the compression information storage unit, and the pattern string data included in the basic pattern to be processed is the basic pattern.
- the basic pattern reading unit read from the storage unit and the pattern string data read by the basic pattern reading unit
- the pattern string reading unit that reads the pattern string corresponding to the pattern string identification information with reference to the selected compression information selected by the selection unit, and the pattern string data read by the basic pattern reading unit
- a test apparatus including a pattern sequence included in a pattern sequence or a pattern sequence corresponding to pattern sequence identification information read out by a pattern sequence reading unit.
- a compression information storing step for storing compressed information for associating a pattern string and a pattern string identification information for identifying the pattern string for a plurality of compressed information, and a pattern string or pattern string identification information are instructed
- a basic pattern storage stage for storing the pattern string data included in association with each other as a group of basic patterns for a plurality of pattern string data, an instruction information storage stage for storing instruction information for instructing the processing order of the basic patterns, and instruction information
- a selection stage for selecting the selection compression information to be used for the basic pattern to be processed indicated by, from a plurality of pieces of compression information stored in the compression information storage stage, and a basic pattern for reading pattern string data included in the basic pattern to be processed
- a pattern string is added to the pattern string data read in the readout stage and the basic pattern readout stage.
- a test method including a pattern output step of outputting a pattern sequence corresponding to the pattern sequence or the pattern sequence identification information read in the pattern sequence reading stage.
- FIG. 1 shows a configuration of a test module 10 according to the present embodiment.
- the structure of the sequential pattern generation part 142 and the sequential pattern generation part 146 which concern on this embodiment is shown.
- An example of the compression information which concerns on this embodiment is shown.
- An example of the test program which concerns on this embodiment is shown.
- the compression format of the test program which concerns on this embodiment is shown.
- An example of the pattern compression information which concerns on the modification of this embodiment is shown.
- An example of the pattern compression information which concerns on the further modification of this embodiment is shown.
- An example of the pattern compression information which concerns on the further modification of this embodiment is shown.
- An example of the pattern compression information which concerns on the further modification of this embodiment is shown.
- An example of the pattern compression information which concerns on the further modification of this embodiment is shown.
- FIG. 1 shows a configuration of a test module 10 according to the present embodiment.
- the test module 10 may be used in a test apparatus that tests the DUT 100 including one or a plurality of terminals, and includes a main memory 102, a central pattern control unit 112, and a plurality of channel blocks 130.
- the main memory 102 stores the test program of the DUT 100 and records an output pattern output from the DUT 100 as a result of executing the test program.
- the main memory 102 includes an instruction memory 104, a plurality of test pattern memories 106, a plurality of expected value pattern memories 108, and a digital capture memory 110.
- the instruction memory 104 stores each instruction included in the test program.
- the test pattern memory 106 may be an example of a basic pattern storage unit.
- the test pattern memory 106 stores pattern string data including a pattern string or pattern string identification information in association with an instruction as a group of basic patterns for a plurality of pattern string data.
- Each of the plurality of test pattern memories 106 is provided corresponding to each terminal of the DUT 100, and stores a test pattern string used for each terminal in association with each instruction, during an instruction cycle period for executing the instruction.
- the test pattern sequence may be an example of a pattern sequence. For example, when the test module 10 generates a 32-bit signal per instruction cycle and outputs it to the DUT 100, the test pattern memory 106 associates with each instruction and outputs 32 bits during one instruction cycle. A test pattern sequence of 32 test patterns corresponding to the signals of is stored.
- the expected value pattern memory 108 may be an example of a basic pattern storage unit.
- the expected value pattern memory 108 stores pattern string data including pattern strings or pattern string identification information in association with instructions as a group of basic patterns for a plurality of pattern string data.
- Each of the plurality of expected value pattern memories 108 is provided corresponding to each terminal of the DUT 100, and stores an expected value pattern string used for each terminal in association with each instruction for an instruction cycle period for executing the instruction.
- the expected value pattern sequence may be an example of a pattern sequence, and includes a plurality of expected value patterns to be sequentially compared with a plurality of output patterns sequentially output from the terminals of the DUT 100 during the instruction cycle period.
- the digital capture memory 110 records an output pattern output from the DUT 100 as a result of executing the test program.
- the instruction memory 104, the plurality of test pattern memories 106, the plurality of expected value pattern memories 108, and / or the digital capture memory 110 may be provided by being divided into separate memory modules that constitute the main memory 102. These may be provided as different storage areas in the same memory module.
- the central pattern control unit 112 is connected to the main memory 102 and the plurality of channel blocks 130, and performs a process common to each terminal of the DUT 100.
- the central pattern control unit 112 includes a pattern list memory 114, a vector generation control unit 116, a central capture control unit 120, and a pattern result memory 122.
- the pattern list memory 114 may be an example of an instruction information storage unit.
- the pattern list memory 114 stores instruction information that instructs the processing order of basic patterns.
- the pattern list memory 114 stores the start / end address of the routine in the instruction memory 104, the start address of the test pattern in the test pattern memory 106, and the expected value pattern in the expected value pattern memory 108 for each of the main routine or each subroutine of the test program. Stores the start address, etc.
- the vector generation control unit 116 may be an example of an instruction execution unit, and sequentially executes instructions included in the test program of the DUT 100 for each instruction cycle. More specifically, the vector generation control unit 116 sequentially reads out each instruction from the start address to the end address from the pattern list memory 114 and executes them sequentially for each routine.
- the central capture control unit 120 receives the pass / fail judgment results for each terminal of the DUT 100 from each channel block 130 and totals the pass / fail judgment results of the DUT 100 for each routine.
- the pattern result memory 122 stores the quality determination result of the DUT 100 for each routine.
- Each of the plurality of channel blocks 130 is provided corresponding to each terminal of the DUT 100.
- Each channel block 130 includes a channel pattern generation unit 140, a timing generation unit 160, a driver 170, and a comparator 180.
- the channel pattern generation unit 140 generates a test pattern sequence or an expected value pattern sequence used for testing the terminal, and compares the output pattern sequence and the expected value pattern sequence of the DUT 100.
- the channel pattern generation unit 140 includes a default pattern memory 118, a sequential pattern generation unit 142, a format control unit 144, a sequential pattern generation unit 146, a hunt / compare unit 148, a fail capture control unit 150, and a fail capture memory. 152.
- the default pattern memory 118 may be an example of a compressed information storage unit.
- the predetermined pattern memory 118 stores, for a plurality of pieces of compressed information, compressed information that associates a pattern string and pattern string identification information that identifies the pattern string.
- the default pattern memory 118 stores a test pattern string and / or an expected value pattern string, that is, a preset default pattern string among the pattern strings in association with default pattern identification information for identifying the default pattern string.
- the predetermined pattern identification information may be an example of pattern string identification information.
- the test pattern memory 106 and / or the expected value pattern memory 108 stores the default pattern identification information of the default pattern string instead of the pattern string itself for the same pattern string as the default pattern string.
- the sequential pattern generation unit 142 receives from the vector generation control unit 116 the start address of the test pattern sequence to be output corresponding to the routine to be executed. Then, the sequential pattern generation unit 142 reads the test pattern sequence from the test pattern memory 106 in order from the start address corresponding to each instruction cycle, and sequentially outputs it to the format control unit 144.
- the format control unit 144 functions as a test pattern output unit according to the present embodiment together with the driver 170, and converts the test pattern sequence into a format for controlling the driver 170.
- the sequential pattern generation unit 146 receives the start address of the expected value pattern sequence from the vector generation control unit 116 corresponding to the routine to be executed. Then, the sequential pattern generation unit 146 reads the expected value pattern from the expected value pattern memory 108 in order from the start address corresponding to each instruction cycle, and sequentially outputs the expected value pattern to the hunt / compare unit 148 and the fail capture control unit 150.
- the hunt compare unit 148 is an example of an expected value comparison unit according to the present embodiment, and receives the output pattern sequence output from the DUT 100 via the comparator 180 and compares it with the expected value pattern sequence.
- the hunt compare unit 148 starts the comparison with the expected value pattern sequence on the condition that a specific header pattern is output from the DUT 100 for an output pattern sequence output from the DUT 100 with indefinite timing. May be included.
- the fail capture control unit 150 receives information on match / mismatch between the output pattern sequence of the DUT 100 and the expected value pattern sequence from the hunt compare unit 148, and generates a pass / fail judgment result of the DUT 100 for the terminal.
- the fail capture memory 152 stores fail information including the result of the hunt processing by the hunt / compare unit 148 or the value of the output pattern that does not match the expected value.
- the timing generation unit 160 generates a timing at which the driver 170 outputs each test pattern in the test pattern sequence, and a timing at which the comparator 180 takes in the output pattern of the DUT 100.
- the driver 170 functions as a test pattern output unit according to the present embodiment together with the format control unit 144, and each test output by the format control unit 144 in the channel pattern generation unit 140 at the timing specified by the timing generation unit 160.
- the pattern is output to the DUT 100.
- the comparator 180 acquires the output pattern output from the terminal of the DUT 100 at the timing specified by the timing generation unit 160 and supplies the output pattern to the hunt / compare unit 148 and the digital capture memory 110 in the channel block 130.
- FIG. 2 shows a configuration of the sequential pattern generation unit 142 and the sequential pattern generation unit 146 according to the present embodiment, together with the default pattern memory 118.
- Sequential pattern generation unit 142 includes a pattern memory reading unit 200, a default pattern reading unit 210, a pattern selection unit 220, and a selection unit 230.
- the pattern memory reading unit 200 may be an example of a basic pattern reading unit.
- the pattern memory reading unit 200 reads pattern string data included in the basic pattern to be processed from the test pattern memory 106 or the expected value pattern memory 108.
- the pattern memory reading unit 200 receives the pattern string data stored in the test pattern memory 106 in association with the one instruction, that is, the test pattern string or the predetermined pattern identification information. read out.
- the selection unit 230 stores a plurality of selection compression information used for the basic pattern to be processed instructed by the pattern list that may be an example of the instruction information in the default pattern memory 118 that may be an example of the compression information storage unit. Select from compression information.
- the predetermined pattern memory 118 has a plurality of pieces of compressed information 1 to compressed information n.
- the selection unit 230 can select one of a plurality of pieces of compressed information for each pattern.
- the compression information can be switched for each basic pattern by including the selection unit 230.
- a basic pattern information storage unit that stores compressed information identification information for identifying compressed information used for processing of the basic pattern in association with the basic pattern can be provided, and the selection unit 230 refers to the compressed information identification information. Select compression information.
- the default pattern reading unit 210 may be an example of a pattern string reading unit.
- the default pattern reading unit 210 refers to the selection compression information selected by the selection unit 230 when the pattern sequence data read by the pattern memory reading unit 200 includes default pattern identification information that may be an example of pattern sequence identification information.
- the default pattern sequence corresponding to the default pattern sequence identification information is read out.
- the default pattern reading unit 210 converts the default pattern identification information into a corresponding default pattern string.
- the pattern selection unit 220 may be an example of a pattern output unit.
- the pattern selection unit 220 outputs a pattern string included in the pattern string data read by the pattern memory reading unit 200 or a pattern string corresponding to the pattern string identification information read by the pattern string reading unit.
- the pattern selection unit 220 is a test pattern sequence read by the pattern memory reading unit 200 from the test pattern memory 106 or a predetermined pattern reading unit corresponding to the one instruction during the instruction cycle period for executing the one instruction. 210 selects a default pattern string read from the default pattern memory 118 and outputs it to the format control unit 144.
- the pattern selection unit 220 determines which of the test pattern string or the predetermined pattern identification information is read from the test pattern memory 106 in association with the one command, and the test pattern string is read. In the case where it is done, the test pattern sequence output from the pattern memory reading unit 200 is output to the format control unit 144. On the other hand, when the default pattern identification information is read, the default pattern string output from the default pattern reading unit 210 is output to the format control unit 144. In response to this, the format control unit 144 and the driver 170, which are examples of the test pattern output unit according to the present embodiment, are connected to the driver 170 with the test pattern sequence or the default pattern sequence selected by the pattern selection unit 220. Output to the terminal of DUT100.
- the sequential pattern generation unit 146 has the same configuration as the sequential pattern generation unit 142, description thereof is omitted. Note that the channel pattern generation unit 140 has a function of the sequential pattern generation unit 142 and the sequential pattern generation unit 146 instead of the configuration in which the sequential pattern generation unit 142 and the sequential pattern generation unit 146 described above are separately provided. A configuration including a sequential pattern generation unit may be employed.
- FIG. 3 shows an example of compressed information according to the present embodiment.
- the test pattern memory 106 and / or the expected value pattern memory 108 is used for the purpose of making it possible to determine whether a pattern string or predetermined pattern identification information is stored, and / or test pattern compression information and / or Expected value pattern compression information (hereinafter collectively referred to as “pattern compression information”) is stored in association with each instruction.
- pattern compression information / or test pattern compression information and / or Expected value pattern compression information
- the 0th bit of the pattern compression information according to the present embodiment is used as vector length information for designating the vector length of the pattern string used during one instruction cycle.
- the test module 10 includes a plurality of operation modes having different vector lengths of pattern strings used during one instruction cycle.
- the test module 10 includes a first operation mode (high speed mode) in which a test is performed using, for example, 32 test pattern strings or an expected value pattern string, and a small number of tests, for example, one pattern compared to the high speed mode.
- a second operation mode (low speed mode) in which a test is performed using the pattern sequence or the expected value pattern sequence.
- the vector length information specifies whether the pattern sequence corresponding to the pattern compression information is handled as the pattern sequence in the first operation mode or the second operation mode.
- the pattern compression information identifies that the pattern string is stored in the case of a predetermined specific value (the 1st to 3rd bits are “000”). To do.
- the test pattern memory 106 and / or the expected value pattern memory 108 store a pattern sequence of the first operation mode, that is, a pattern sequence of 32 patterns, together with the pattern compression information, in association with the command.
- the pattern compression information is used as the default pattern identification information when the specified value is not a specific value (the first to third bits are “001” to “111”).
- the test pattern memory 106 and / or the expected value pattern memory 108 stores the pattern compression information in association with the command, and no pattern string is added.
- the test module 10 performs the following operation. First, when executing one instruction, the pattern memory reading unit 200 reads pattern compression information from the test pattern memory 106 or the expected value pattern memory 108, and the pattern compression information is a specific value (the 0-3rd bit is “0000”). If ")", the pattern string is further read. Next, when the pattern compression information is not a specific value, the default pattern reading unit 210 reads a default pattern sequence stored in the default pattern memory 118 in association with the pattern compression information. Then, the pattern selection unit 220 selects the pattern sequence output from the pattern memory reading unit 200 when the pattern compression information is a specific value, and the default pattern output from the default pattern reading unit 210 when the pattern compression information is not a specific value. Select the pattern column.
- the pattern compression information includes a pattern string when a predetermined specific value (the first to third bits are “000” and “111”). Is stored.
- the test pattern memory 106 and / or the expected value pattern memory 108 are associated with the 16 instructions executed during the continuous 16 instruction cycle period, together with the pattern compression information, A pattern sequence of the second operation mode, that is, one pattern sequence per instruction is stored.
- the test pattern memory 106 and / or the expected value pattern memory 108 are executed during the instruction cycle period corresponding to the number of patterns specified by the fourth to seventh bits.
- the pattern sequence of the second operation mode having the length for the number of patterns is stored together with the pattern compression information.
- the test pattern memory 106 and / or the expected value pattern memory 108 can store a variable length pattern corresponding to one pattern compression information by changing the fourth to seventh bits.
- the pattern compression information is used as the default pattern identification information when the specified value is not a specific value (the first to third bits are “001” to “110”).
- the test pattern memory 106 and / or the expected value pattern memory 108 stores the pattern compression information in association with the command, and no pattern string is added.
- the test module 10 performs the following operation. First, when executing one instruction, the pattern memory reading unit 200 reads pattern compression information from the test pattern memory 106 or the expected value pattern memory 108, and the pattern compression information is a specific value (the 0-3rd bit is “1000”). If it is “or“ 1111 ”), the pattern string is further read. Next, when the pattern compression information is not a specific value, the default pattern reading unit 210 reads a default pattern sequence stored in the default pattern memory 118 in association with the pattern compression information.
- the pattern selection unit 220 selects the pattern sequence output from the pattern memory reading unit 200 when the pattern compression information is a specific value, and the default pattern output from the default pattern reading unit 210 when the pattern compression information is not a specific value. Select the pattern column. In the second operation mode, each pattern of the selected pattern sequence is sequentially used from the one instruction to a plurality of instruction cycle periods.
- FIG. 4 shows an example of a test program according to this embodiment.
- the test program illustrated in FIG. 4 includes a plurality of instructions to be executed sequentially, and a test pattern output to the DUT 100 during an instruction cycle in which the instructions are executed in association with each instruction and each terminal (CH1 to CH4). Including columns.
- the instruction memory 104 stores each instruction shown in FIG.
- Each of the plurality of test pattern memories 106 identifies a test pattern sequence output during an instruction cycle period for executing the instruction or a predetermined pattern sequence output during the instruction cycle period in association with each instruction. Pattern compression information used as default pattern identification information to be stored is stored.
- the test pattern memory 106 of the terminal CH1 stores the test pattern sequence ⁇ 011... 110 ⁇
- the test pattern memory 106 of the terminal CH2 stores the test pattern sequence ⁇ 000 ... 110 ⁇
- the test pattern memory 106 of the terminal CH3 stores the test pattern sequence ⁇ 011 ... 000 ⁇
- the test pattern memory 106 of the terminal CH4 stores the test pattern sequence ⁇ 001 ... 110 ⁇ . Is stored. More specifically, the test pattern memory 106 combines these test pattern strings with pattern compression information of a specific value (0-3 bits are “0000”) and a pattern string added to the pattern compression information. Store as.
- the test pattern memory 106 of the terminal CH1 and the terminal CH2 stores pattern compression information CODEH1 (the 0-3rd bit is “0001”) other than a specific value
- the test pattern memory 106 at the terminal CH3 stores pattern compression information CODEH2 other than the specific value (the 0-3rd bit is “0010”)
- the test pattern memory 106 at the terminal CH4 stores pattern compression information CODEH3 (0-3rd other than the specific value).
- Each bit stores “0011”).
- the plurality of test pattern memories 106 can store different default pattern identification information for each terminal in association with the same command.
- the test pattern memory 106 of the terminal CH1 stores pattern compression information CODEH1 other than the specific value, and the terminals CH2 to 4 display pattern compression information and test pattern string of the specific value. Is stored.
- test program storage format shown above for each terminal, whether the test pattern sequence with a large amount of data is stored or replaced with the default pattern identification information is stored for each terminal corresponding to the same instruction. It can be determined independently, and the data amount of the test program can be reduced more efficiently.
- the first test pattern memory 106 corresponding to the first terminal of the DUT 100 stores one test pattern string in association with one instruction, and the second test corresponding to the second terminal of the DUT 100.
- the pattern memory 106 may store pattern compression information including one predetermined pattern identification information in association with the one command.
- the first pattern memory reading unit 200 corresponding to the first terminal of the DUT 100 associates the pattern compression information of the specific value stored in the first test pattern memory 106 in association with the one instruction and one Read the test pattern string.
- the second pattern memory reading unit 200 corresponding to the second terminal reads one pattern compression information that is not a specific value and is stored in the second test pattern memory 106 in association with the one instruction.
- the second default pattern reading unit 210 corresponding to the second terminal reads one default pattern string stored in the default pattern memory 118 in association with one pattern compression information that is not a specific value. Then, the first channel pattern generation unit 140 and the driver 170 corresponding to the first terminal receive the one read out from the first test pattern memory 106 during one instruction cycle period for executing the one instruction. A test pattern string is output to the first terminal. On the other hand, the second format control unit 144 and the driver 170 corresponding to the second terminal receive the second predetermined pattern sequence read by the second predetermined pattern reading unit 210 during the one instruction cycle period. Output to the terminal.
- pattern compression information for specifying a test pattern string or predetermined pattern identification information is stored for each terminal independently for each test pattern memory 106. Can increase the possibility of compressing the test program.
- test pattern string is stored in the test pattern memory 106
- expected value pattern string is stored in the expected value pattern memory 108.
- FIG. 5 shows a compression format of the test program according to the present embodiment.
- FIG. 5A shows a test program before compression. This test program operates the test module 10 in the first operation mode (high speed mode) on lines 1-2 and 28-30, and outputs a test pattern sequence of 32 patterns per instruction cycle. Let In the third to 27th lines, the test module 10 is operated in the second operation mode (low speed mode), and one pattern is output per instruction cycle.
- test pattern sequence (B) in FIG. 5 is a test program after compression.
- the test pattern sequence ⁇ VA1 ... VA32 ⁇ before compression is stored in the default pattern memory 118 as a default pattern sequence corresponding to the default pattern identification information “H1”.
- the test pattern sequence ⁇ VA1... VA32 ⁇ before compression is stored in the test pattern memory 106 after being replaced with the pattern compression information CODEH1 that designates the default pattern identification information “H1”.
- the test pattern sequences ⁇ VB1 ... VB32 ⁇ , ⁇ VD1 ... VD32 ⁇ , and ⁇ VE1 ... VE32 ⁇ before compression are pre-set pattern identification information “H2”, “H4”, and “H5”.
- the pattern compression information CODEH 2, CODEH 4, and CODEH 5 specifying “is stored in the test pattern memory 106.
- the test pattern sequence ⁇ SA1 ... SA16 ⁇ sequentially output corresponding to 16 consecutive commands in the second operation mode is a default pattern sequence in the second operation mode corresponding to the default pattern identification information "L1". Stored in the default pattern memory 118. Further, the test pattern sequence ⁇ VX1... VX32 ⁇ before compression is stored in the test pattern memory 106 as a set of the pattern compression information CODEH0 having a specific value (the first to fourth bits are “0000”) and the test pattern sequence. Stored. Similarly, the test pattern sequence ⁇ SA17... SA25 ⁇ before compression includes pattern compression information CODEL7 having a specific value (1-4th bit is "1111" and 5th-8th bit is "9"). It is stored in the test pattern memory 106 as a set of test pattern strings ⁇ SA17... SA25 ⁇ having 9 patterns.
- the test module 10 stores many test pattern sequences included in the test program by storing frequently occurring test pattern sequences in the default pattern memory 118 as default pattern sequences. Can be replaced with pattern compression information designating the predetermined pattern sequence, and the size of the test program can be efficiently reduced.
- test pattern string is stored in the test pattern memory 106
- expected value pattern string is stored in the expected value pattern memory 108, and the description thereof is omitted.
- FIG. 6 shows an example of pattern compression information according to a modification of the present embodiment.
- the high speed mode is designated by the code of all the compression information. According to such pattern compression information, the number of predetermined patterns that can be used in the high speed mode can be increased.
- FIG. 7 shows an example of pattern compression information according to a further modification of the present embodiment.
- an arbitrary pattern string is designated by all the compression information codes.
- null data as a 4-bit compression code, that is, to reduce the 4-bit compression code, thereby increasing the compression rate.
- Information indicating that all codes are specified in the high speed mode or specified in an arbitrary pattern sequence can be stored in the pattern information memory.
- FIG. 8 shows an example of pattern compression information according to a further modification of the present embodiment.
- 8 bits are assigned as the code of the compression information, and it is specified that a plurality of arbitrary pattern strings are included as a pattern string by the upper 4 bits “0111”. Also, the number of a plurality of arbitrary pattern strings designated by “1001” of the lower 4 bits is designated. That is, the compression information can include number-of-times information that specifies the number of repetitions of the pattern string. The lower 4 bits “1001” indicate that the arbitrary pattern sequence is repeated 10 times. According to such pattern compression information, the code of the compression information in the pattern string data related to the second and subsequent repetitions can be eliminated, and the compression rate of the pattern string data can be increased.
- FIG. 9 shows an example of pattern compression information according to a further modification of the present embodiment.
- 8 bits are assigned as the code of the compression information, and the upper 4 bits “0110” are designated to repeat the same pattern sequence a plurality of times. Further, the number of repetitions is specified by “0011” of the lower 4 bits. That is, the compression information can include number-of-times information that specifies the number of repetitions of the pattern string. The lower 4 bits “0011” indicate that the arbitrary pattern sequence is repeated five times. According to such pattern compression information, the code of the compression information in the pattern string data related to the second and subsequent repetitions can be eliminated, and the compression rate of the pattern string data can be increased.
- the compression information in FIG. 9 can be specified for each input or output channel. Therefore, even when the number of repetitions is different between the input channel and the output channel, which cannot be specified by IDXI, which is a repetition command, the number of repetitions can be specified for each channel, so that the compression rate can be increased.
- IDXI which is a repetition command
- FIG. 9 an arbitrary pattern sequence is illustrated as a repeated pattern sequence, but the present invention can also be applied to a default pattern sequence.
- FIG. 10 shows an example of pattern compression information according to a further modification of the present embodiment.
- 8 bits are assigned as a compression information code designating the high-speed mode, and a pattern string designated by 8 bits together with a pattern string designated by only the upper 4 bits and the lower 4 bits. And divide. That is, the high-speed mode pattern sequence is stored as the pattern sequence included in the compression information, and the short bit pattern sequence identification information that can designate one address space or an address space larger than the one address space can be designated as the pattern sequence identification information. Stores long bit pattern string identification information.
- a predefined high-frequency default pattern sequence is assigned, and as the pattern sequence identified by the long bit pattern sequence identification information, the predefined high-frequency default pattern Assign a low-frequency default pattern column that is less frequently used than the column.
- the high-frequency default pattern string is specified by a 4-bit compression information code
- the low-frequency default pattern is specified by an 8-bit compression information code. Therefore, the overall compression rate can be increased. Since the compression code in the low speed mode is the same as described above, the description thereof is omitted.
- the pattern sequence stored in the plurality of test pattern memories 106 and / or the plurality of expected value pattern memories 108 for the same instruction is provided for each terminal of the DUT 100.
- the compression can be performed independently, and the compression efficiency of the test program can be increased. Further, as a result of efficiently compressing the test program, the average amount of data read from the test pattern memory 106 and / or the expected value pattern memory 108 per instruction can be reduced, and the required throughput of the main memory 102 can be kept relatively low. Can do.
- test modules 100 DUT 102 Main memory 104 Instruction memory 106 Test pattern memory 108 Expected value pattern memory 110 Digital capture memory 112 Central pattern control unit 114 Pattern list memory 116 Vector generation control unit 118 Default pattern memory 120 Central capture control unit 122 Pattern result memory 130 Channel block 140 Channel pattern generation unit 142 Sequential pattern generation unit 144 Format control unit 146 Sequential pattern generation unit 148 Hunt / compare unit 150 Fail capture control unit 152 Fail capture memory 160 Timing generation unit 170 Driver 180 Comparator 200 Pattern memory read unit 210 Default pattern read unit 220 Pattern selection unit 230 Selecting section
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Abstract
Description
1.特願2008-247690 出願日 2008年9月26日
図5の(a)は圧縮前の試験プログラムである。本試験プログラムは、第1-2行目、及び第28-30行目において、試験モジュール10を、第1動作モード(ハイスピードモード)で動作させ、命令サイクル当たり32パターンの試験パターン列を出力させる。また、第3―27行目において、試験モジュール10を、第2動作モード(ロースピードモード)で動作させ、命令サイクル当たり1パターンを出力させる。
また、圧縮前の試験パターン列{VX1...VX32}は、特定値(第1-4ビットが"0000")のパターン圧縮情報CODEH0と、当該試験パターン列との組として試験パターンメモリ106に格納される。同様に、圧縮前の試験パターン列{SA17...SA25}は、特定値(第1-4ビットが"1111"、かつ、第5-8ビットが"9")のパターン圧縮情報CODEL7と、パターン数が9の試験パターン列{SA17...SA25}の組として試験パターンメモリ106に格納される。
100 DUT
102 メインメモリ
104 命令メモリ
106 試験パターンメモリ
108 期待値パターンメモリ
110 デジタルキャプチャメモリ
112 セントラルパターン制御部
114 パターンリストメモリ
116 ベクタ生成制御部
118 既定パターンメモリ
120 セントラルキャプチャ制御部
122 パターンリザルトメモリ
130 チャネルブロック
140 チャネルパターン生成部
142 シーケンシャルパターン生成部
144 フォーマット制御部
146 シーケンシャルパターン生成部
148 ハント・コンペア部
150 フェイルキャプチャ制御部
152 フェイルキャプチャメモリ
160 タイミング生成部
170 ドライバ
180 コンパレータ
200 パターンメモリ読出部
210 既定パターン読出部
220 パターン選択部
230 選択部
Claims (11)
- パターン列および前記パターン列を識別するパターン列識別情報を対応付ける圧縮情報を、複数の前記圧縮情報について格納する圧縮情報格納部と、
前記パターン列または前記パターン列識別情報を命令に対応付けて含むパターン列データを、複数の前記パターン列データについて一群の基本パターンとして格納する基本パターン格納部と、
前記基本パターンの処理順序を指示する指示情報を格納する指示情報格納部と、
前記指示情報が指示する処理対象の基本パターンに使用する選択圧縮情報を、前記圧縮情報格納部に格納された複数の前記圧縮情報から選択する選択部と、
処理対象の前記基本パターンに含まれる前記パターン列データを、前記基本パターン格納部から読み出す基本パターン読出部と、
前記基本パターン読出部が読み出した前記パターン列データに前記パターン列識別情報を含む場合に、前記選択部が選択した前記選択圧縮情報を参照して、前記パターン列識別情報に対応するパターン列を読み出すパターン列読出部と、
前記基本パターン読出部が読み出した前記パターン列データに含まれる前記パターン列または前記パターン列読出部が読み出した前記パターン列識別情報に対応する前記パターン列を出力するパターン出力部と、
を備えた試験モジュール。 - 前記基本パターンの処理に使用する圧縮情報を識別する圧縮情報識別情報を前記基本パターンと対応付けて格納する基本パターン情報格納部、をさらに備え、
前記選択部は、前記圧縮情報識別情報を参照して前記選択圧縮情報を選択する、
請求項1に記載の試験モジュール。 - 前記圧縮情報格納部は、前記圧縮情報として、前記パターン列の繰り返し回数を指定する回数情報をさらに含む前記圧縮情報を格納し、
前記パターン出力部は、前記回数情報で指定される繰り返し回数だけ前記パターン列を繰り返して出力する、
請求項2に記載の試験モジュール。 - 前記圧縮情報格納部は、前記パターン列として、予め定義された既定パターン列または前記圧縮情報ごとに定義される任意パターン列を含む前記圧縮情報を格納する、
請求項3に記載の試験モジュール。 - 前記圧縮情報格納部は、前記パターン列として複数の前記任意パターン列を含むと共に、複数の前記任意パターン列の全体を識別する単一のパターン列識別情報を、複数の前記任意パターン列の数を指標する回数情報として格納し、
前記パターン出力部は、前記回数情報で指定される数だけ複数の前記任意パターン列を出力する、
請求項4に記載の試験モジュール。 - 前記圧縮情報格納部は、前記圧縮情報として、入力または出力のチャネルごとの前記パターン列および前記パターン列識別情報を格納し、
前記パターン出力部は、前記チャネルごとに前記パターン列を出力する、
請求項1に記載の試験モジュール。 - 前記圧縮情報格納部は、前記パターン列として、高速モードパターン列または低速モードパターン列を格納するとともに、前記パターン列識別情報として、前記パターン列が前記高速モードパターン列であるか前記低速モードパターン列であるかを識別するパターン識別情報を格納する、
請求項1に記載の試験モジュール。 - 前記圧縮情報格納部は、前記圧縮情報に含まれる前記パターン列として前記高速モードパターン列を格納するとともに、前記パターン列識別情報として、一のアドレス空間が指定できる短ビットパターン列識別情報または前記一のアドレス空間より大きなアドレス空間が指定できる長ビットパターン列識別情報を格納し、
前記短ビットパターン列識別情報が識別するパターン列として、予め定義された使用頻度の高い高頻度既定パターン列を割り当て、
前記長ビットパターン列識別情報が識別するパターン列として、予め定義された前記高頻度既定パターン列より使用頻度の低い低頻度既定パターン列を割り当てる、
請求項7に記載の試験モジュール。 - 前記圧縮情報格納部は、前記圧縮情報に含まれる全ての前記パターン列として、前記高速モードパターン列であると共に前記圧縮情報ごとに定義される任意パターン列を格納し、前記パターン列識別情報としてヌルデータを格納する、
請求項7に記載の試験モジュール。 - パターン列および前記パターン列を識別するパターン列識別情報を対応付ける圧縮情報を、複数の前記圧縮情報について格納する圧縮情報格納部と、
前記パターン列または前記パターン列識別情報を命令に対応付けて含むパターン列データを、複数の前記パターン列データについて一群の基本パターンとして格納する基本パターン格納部と、
前記基本パターンの処理順序を指示する指示情報を格納する指示情報格納部と、
前記指示情報が指示する処理対象の基本パターンに使用する選択圧縮情報を、前記圧縮情報格納部に格納された複数の前記圧縮情報から選択する選択部と、
処理対象の前記基本パターンに含まれる前記パターン列データを、前記基本パターン格納部から読み出す基本パターン読出部と、
前記基本パターン読出部が読み出した前記パターン列データに前記パターン列識別情報を含む場合に、前記選択部が選択した前記選択圧縮情報を参照して、前記パターン列識別情報に対応するパターン列を読み出すパターン列読出部と、
前記基本パターン読出部が読み出した前記パターン列データに含まれる前記パターン列または前記パターン列読出部が読み出した前記パターン列識別情報に対応する前記パターン列を出力するパターン出力部と、
を備えた試験装置。 - パターン列および前記パターン列を識別するパターン列識別情報を対応付ける圧縮情報を、複数の前記圧縮情報について格納する圧縮情報格納段階と、
前記パターン列または前記パターン列識別情報を命令に対応付けて含むパターン列データを、複数の前記パターン列データについて一群の基本パターンとして格納する基本パターン格納段階と、
前記基本パターンの処理順序を指示する指示情報を格納する指示情報格納段階と、
前記指示情報が指示する処理対象の基本パターンに使用する選択圧縮情報を、前記圧縮情報格納段階で格納された複数の前記圧縮情報から選択する選択段階と、
処理対象の前記基本パターンに含まれる前記パターン列データを読み出す基本パターン読出段階と、
前記基本パターン読出段階で読み出した前記パターン列データに前記パターン列識別情報を含む場合に、前記選択段階で選択した前記選択圧縮情報を参照して、前記パターン列識別情報に対応するパターン列を読み出すパターン列読出段階と、
前記基本パターン読出段階で読み出した前記パターン列データに含まれる前記パターン列または前記パターン列読出段階で読み出した前記パターン列識別情報に対応する前記パターン列を出力するパターン出力段階と、
を備えた試験方法。
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