WO2010016212A1 - Field effect transistor manufacturing method - Google Patents
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- WO2010016212A1 WO2010016212A1 PCT/JP2009/003650 JP2009003650W WO2010016212A1 WO 2010016212 A1 WO2010016212 A1 WO 2010016212A1 JP 2009003650 W JP2009003650 W JP 2009003650W WO 2010016212 A1 WO2010016212 A1 WO 2010016212A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Definitions
- the present invention relates to a method for manufacturing a field effect transistor.
- Group III nitride compound semiconductors such as GaN have a large band gap, high breakdown field strength, and high electron mobility.
- a field effect transistor capable of high withstand voltage and high speed operation using the group III nitride compound semiconductor as a constituent material has been advanced.
- a field effect transistor having a vertical structure in which carriers can move in a direction perpendicular to the substrate surface has attracted attention as a device that can realize low on-resistance and high breakdown voltage.
- This type of vertical structure is disclosed in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2007-142243) and Non-patent Document 1 (Masakazu Kanechika et al. Jpn. J. Appl. Phys., Vol. 46, No. 21, pp. L 503-L505, 2007).
- FIG. 1 is a schematic view of a cross-sectional structure of an AlGaN / GaN heterojunction field effect transistor having a vertical structure disclosed in Non-Patent Document 1.
- this field effect transistor has an n-type GaN layer 1002, a p-type GaN layer 1003, an n-type GaN layer 1006, and an i-type AlGaN layer 1007 on an n-type GaN substrate 1001. .
- a gate electrode 1010 is formed on the AlGa layer 1007 with an SiO 2 layer 1009 interposed therebetween, and source electrodes 1008 are formed on both sides of the gate electrode 1010.
- a p-type impurity diffusion layer is formed immediately below the source electrode 1008.
- a drain electrode 1008 is formed on the back surface of the n-type GaN substrate 1001. When this field effect transistor is in an on state, carriers injected from the source electrode 1008 flow through a channel region (two-dimensional electron gas) formed in the vicinity of the surfaces of the GaN layer 1006 and the AlGaN layer 1007, and the p-type GaN layer It flows to the drain electrode 1008 in the vertical direction through the opening 1003.
- a channel region two-dimensional electron gas
- the manufacturing method of this field effect transistor is as follows.
- An n-type GaN layer 1002 to which Si is added, a p-type GaN layer to which Mg is added, an AlN layer, and an i-type GaN layer are epitaxially grown on the n-type GaN substrate 1001 in this order.
- An SiO 2 mask pattern is formed on the resulting laminated structure, and dry etching is performed using the SiO 2 mask pattern. Thereafter, the SiO 2 mask pattern is removed.
- a p-type GaN layer 1003 having an opening as shown in FIG. 1 is formed.
- an n-type GaN layer 1006 is embedded and grown in the opening, and an i-type AlGaN layer 1007 is epitaxially grown on the n-type GaN layer 1006.
- Si ions are implanted into the AlGaN layer 1007 and activated to form a p-type impurity diffusion layer.
- a source electrode (ohmic electrode) 1008 made of a Ti / Al multilayer film is formed on these p-type impurity diffusion layers.
- a gate electrode 1010 made of n + type polysilicon is formed, and activation annealing is performed.
- the GaN layer 1006 is regrown in this opening, but the GaN layer 1006 thus regrown There is a problem of low crystallinity.
- the crystallinity of the GaN layer 1006 is low, current collapse occurs and electron mobility in the channel region decreases.
- silicon which is an n-type impurity, is added to the GaN layer 1006, there is a problem that electron mobility is lowered. Furthermore, it is difficult to reduce the on-resistance due to the low electron mobility.
- the present invention provides a method of manufacturing a field effect transistor that has a structure in which carriers flow in the vertical direction, and can achieve reduction in electron mobility and reduction in on-resistance in a channel region. Is.
- the steps of continuously growing each layer constituting the laminated structure including the electron barrier layer and the electron transit layer in this order Forming an electron conduction region in the stacked structure from one side of the region where the gate electrode is formed to a region closer to the substrate than the electron barrier layer from the electron transit layer; Forming the gate electrode on the electron transit layer; Forming a source electrode on the electron transit layer on the other side of the region where the gate electrode is formed; Forming a drain electrode electrically connected to one end of the electron conducting region on the substrate side;
- a method for manufacturing a field effect transistor is provided.
- FIG. 1 is a diagram schematically showing a cross-sectional structure of a field effect transistor according to a first embodiment of the present invention. It is a figure which shows roughly the cross-section of the field effect transistor which is a modification of 1st Embodiment. It is a figure which shows roughly the cross-section of the field effect transistor of 2nd Embodiment which concerns on this invention. It is a figure which shows roughly the cross-section of the field effect transistor which is a modification of 2nd Embodiment. It is a figure which shows roughly the cross-section of the field effect transistor concerning a modification.
- FIG. 2 is a diagram schematically showing a cross-sectional structure of the field effect transistor 10 according to the first embodiment of the present invention.
- a buffer layer 102, a high concentration n-type semiconductor layer 103, a drift layer 104, a p-type electron barrier layer 105, an electron transit layer 106 and an electron supply layer 107 are laminated on a substrate 101 in this order. It has a laminated structure.
- This laminated structure is covered with an insulating film 111.
- a gate electrode 112 is formed in the opening formed in the insulating film 111 on the electron supply layer 107.
- an electron conduction region 108 is formed on the etched surface formed in the stacked structure. ing.
- the electron conduction region 108 is provided so as to extend from one end of the electron transit layer 106 to a region closer to the substrate 101 than the p-type electron barrier layer 105.
- a source electrode 109 is formed on the electron supply layer 107 on the other side of the left and right sides of the gate electrode 112 (the other side in the gate length direction).
- a drain electrode 110 is formed on the substrate 101 with a buffer layer 102 and a high-concentration n-type semiconductor layer 103 interposed therebetween. The drain electrode 110 is formed on the surface side of the substrate 101, and is electrically connected to one end of the electron conduction region 108 through the high concentration n-type semiconductor layer 103.
- the upper surface of the electron transit layer 106 is heterojunction to the electron supply layer 107, and when the field effect transistor 10 is operated, a channel region of a two-dimensional electron gas is formed at and near the heterojunction interface. At this time, electrons injected from the source electrode 109 can move to the drain electrode 110 through the channel region and the electron conduction region 108.
- the manufacturing method of the field effect transistor 10 includes the following basic steps (a) to (h).
- A) A plurality of compound semiconductor layers constituting the buffer layer 102, the high-concentration n-type semiconductor layer 103, the drift layer 104, the electron barrier layer 105, the electron transit layer 106, and the electron supply layer 107 on the substrate 101 in this order.
- B) The stacked structure is etched on one of the left and right sides of the region where the gate electrode 112 is formed (the side of the region where the gate electrode 112 is formed), and electrons are transmitted from one end of the electron transit layer 106.
- (G) A step of forming the gate electrode 112 in the opening of the insulating film 111 on the electron transit layer 106.
- (H) A step of forming a protective film 113 that covers the entire element except a part of the electrode surface.
- a group III nitride compound semiconductor substrate such as GaN or AlN is used as the substrate 101, but the substrate 101 is not limited to this.
- a silicon substrate, a sapphire substrate, or a silicon carbide substrate may be used for the substrate 101.
- a buffer layer 102, a high-concentration n-type semiconductor layer 103, a drift layer 104, an electron barrier layer 105, an electron transit layer are formed by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxial growth (MBE).
- MOVPE metal organic vapor phase epitaxy
- MBE molecular beam epitaxial growth
- continuously growing a plurality of compound semiconductor layers means a growth process of the buffer layer 102, a growth process of the high-concentration n-type semiconductor layer 103, a growth process of the drift layer 104, a growth process of the electron barrier layer 105, A series of growth processes including the growth process of the electron transit layer 106 and the growth process of the electron supply layer 107 is performed continuously. That is, each layer is continuously epitaxially grown in the stacking order, and in the middle of the layer growth process, the growth is stopped, an opening is formed by etching or the like, and the layer is regrowth from the opening as in the past. Not implemented. In particular, it is preferable that each layer is continuously grown in the same apparatus, that is, each layer is continuously grown without being removed from the apparatus for growing each layer.
- the buffer layer 102 may be made of, for example, a group III nitride compound semiconductor such as AlN, GaN, or AlGaN.
- the buffer layer 102 may include a superlattice structure (for example, an AlGaN / GaN superlattice structure) that is lattice-matched to the upper surface of the substrate 101 or a composition modulation structure.
- the high-concentration n-type semiconductor layer 103 is a group III nitride compound semiconductor into which an n-type impurity such as silicon (Si), sulfur (S), selenium (Se), or oxygen (O) is introduced at a high concentration. What is necessary is just to comprise. Examples of the group III nitride compound semiconductor include GaN, InN, and AlN.
- the drift layer 104 may be made of a group III nitride compound semiconductor such as GaN, InN, or AlN.
- Examples of the n-type impurity introduced into the drift layer 104 include Si, S, Se, and O.
- the impurity concentration can be set to a desired value, but is preferably 1 ⁇ 10 18 cm ⁇ 3 or less in order to reduce electric field concentration. In particular, when the pressure resistance is increased, the concentration is preferably 1 ⁇ 10 17 cm ⁇ 3 or less.
- the electron barrier layer 105 is a group III nitride compound semiconductor layer into which a p-type impurity such as beryllium (Be), carbon (C), or magnesium (Mg) is introduced at a high concentration.
- a p-type impurity such as beryllium (Be), carbon (C), or magnesium (Mg)
- the group III nitride compound semiconductor include GaN, InN, and AlN.
- the concentration of the p-type impurity introduced into the electron barrier layer 105 can be set to a desired value. However, in order to maintain the formation of a potential barrier against electrons in the high voltage region, the concentration is 1 ⁇ 10 18 cm ⁇ 3 or more. It is desirable to be.
- the electron transit layer 106 may be made of, for example, a group III nitride compound semiconductor such as GaN, InN, or AlN.
- the electron transit layer 106 is made of, for example, In a Al b Ga 1-ab N (0 ⁇ a ⁇ 1, 0 ⁇ b ⁇ 1, a + b ⁇ 1).
- the electron transit layer 106 may be added with n-type impurities such as Si, S, Se, and O, or p-type impurities such as Be, C, and Mg.
- the impurity concentration in the electron transit layer 106 becomes too high, the influence of Coulomb scattering increases and the electron mobility decreases, so the impurity concentration is desirably 1 ⁇ 10 17 cm ⁇ 3 or less.
- the electron transit layer 106 is formed continuously in one growth process without passing through process processes such as photolithography and dry etching.
- the electron supply layer 107 is a layer that is heterojunction with the upper surface of the electron transit layer 106 and is made of a group III nitride compound semiconductor such as GaN, InN, or AlN.
- the electron supply layer 107 is made of, for example, In c Al d Ga 1-cd N (0 ⁇ c ⁇ 1, 0 ⁇ d ⁇ 1, c + d ⁇ 1).
- the electron supply layer 107 is made of a material or composition having a smaller electron affinity than the electron transit layer 106. In this embodiment, no impurity is introduced into the electron supply layer 107, but an n-type impurity such as Si, S, Se, or O may be introduced instead.
- the electron conduction region 108 is located on the opposite side of the source electrode 109 with the gate electrode 112 interposed therebetween in plan view from the substrate surface side.
- the electron conduction region 108 extends from the electron supply layer 107 side to the drift layer 104 side, one end is in contact with the electron supply layer 107 and the electron transit layer 106, and the other end is an electron. It is in contact with a region (in this embodiment, the drift layer 104) located on the substrate side with respect to the barrier layer.
- the electron conduction region 108 is provided in contact with the electron supply layer 107, the electron transit layer 106, the electron barrier layer 105, and the drift layer 104, and is located in the middle of the thickness of the drift layer 104 from the electron supply layer 107 side. It extends to.
- the electron conductive region 108 can be formed by introducing an n-type impurity into the laminated structure from the etched surface of the laminated structure and activating the introduced n-type impurity by heat treatment.
- the etched surface can be obtained by dry etching the laminated structure on the substrate 101.
- the electron conduction region 108 can be formed by ion-implanting an n-type impurity such as silicon into the laminated structure from the etched surface and activating the implanted ions by heat treatment.
- the electron conductive region 108 can be formed by depositing amorphous or polycrystalline silicon on the etched surface by, for example, CVD, and then diffusing the deposited silicon into a laminated structure by heat treatment. Note that not only the impurity diffusion region in which silicon is diffused by the heat treatment but also silicon that is not diffused in the stacked structure forms the electron conductive region 108 as a conductive film. Silicon may be solid-phase diffused on the etched surface.
- the electron conductive region 108 may be formed by forming a metal conductive film on the etched surface of the laminated structure, for example, by sputtering. Furthermore, it is desirable to cause the semiconductor layer constituting the stacked structure and the metal conductive film to react with each other by heat treatment.
- the metal conductive film includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), gold (Au), tantalum (Ta), What is necessary is just to comprise by 1 type, or 2 or more types of metal materials selected from the group which consists of zirconium (Zr) and yttrium (Y). It is preferable to form a metal conductive film in ohmic contact on the etched surface.
- the electron conductive region 108 may be formed by re-growing a compound semiconductor layer such as an n-type GaN layer on the etched surface of the stacked structure by the MOVPE method or the MBE method. Even when the electron conduction region 108 is formed by re-growing the compound semiconductor layer, even if the crystallinity of the electron conduction region is deteriorated, impurities are doped at a very high concentration to reduce the resistance. do it. In the case of an electron transit layer, it is difficult to reduce the resistance by doping impurities at a very high concentration, so that a layer with good crystallinity is required.
- the source electrode 109 and the drain electrode 110 are formed by a lift-off process (steps (d) and (e)).
- the source electrode 109 and the drain electrode 110 are in ohmic contact with the electron supply layer 107 and the high-concentration n-type semiconductor layer 103, respectively. More specifically, a part of the upper surface of the high-concentration n-type semiconductor layer 103 is exposed by dry etching to form a region where the drain electrode 110 is to be formed.
- a resist pattern is formed on the stacked structure using photolithography, and then a metal layer is formed on the resist pattern and the stacked structure by sputtering. Thereafter, the electrode pattern of the source electrode 109 and the drain electrode 110 can be formed by removing the resist pattern and the metal material on the resist pattern at the same time.
- Each of the source electrode 109 and the drain electrode 110 includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), or gold (Au). As long as it is made of a metal material, it may have a structure in which a plurality of metal layers are laminated.
- an insulating film is formed so as to cover the entire surface of the laminated structure, and this insulating film is patterned to form an insulating film 111 having an opening as shown in FIG. Further, a groove is formed in the electron supply layer 107 by dry etching the electron supply layer 107 using the insulating film 111 as a mask. Then, the gate electrode 112 is embedded in the groove of the electron supply layer 107 and the opening of the insulating film 111 (step (g)).
- a gate electrode 112 having a T-shaped cross section as shown in FIG. 2 is formed. That is, the gate electrode 112 has a portion inserted into the groove of the electron supply layer 107 through the opening of the insulating film 111 and a flange portion extending in the lateral direction from the opening of the insulating film 111. Yes. As shown in FIG. 2, a flange portion of the gate electrode 112 extending from the opening of the insulating film 111 toward the electron conduction region 108 extends from the opening of the gate electrode 112 toward the source electrode 109. It is longer than the existing heel part. Thereby, the electric field concentration in the vicinity of the gate electrode 112 can be relaxed, and the breakdown voltage can be improved.
- a configuration is adopted in which the length of the flange portion of the gate electrode 112 on the electron conduction region 108 side is longer than the flange portion of the gate electrode 112 on the source electrode 109 side. Is not to be done.
- the heel portion of the gate electrode 112 on the electron conducting region 108 side is equal to the heel portion of the gate electrode 112 on the source electrode 109 side, or the heel portion of the gate electrode 112 on the electron conducting region 108 side is the source electrode 109 of the gate electrode 112.
- the gate capacitance increases for the effect of improving the breakdown voltage and reducing the current collapse.
- the gain reduction due to is increased.
- the gate electrode 112 may be made of a metal material such as W, Mo, Si, Ti, Pt, Nb, Al, or Au, and may have a structure in which a plurality of metal layers are stacked.
- the gate electrode 112 may be formed using a semiconductor material that is in Schottky contact with the base electron supply layer 107 instead of a metal material.
- this semiconductor material is preferably a material that does not react with the insulating film 111 and the protective film 113.
- a protective film 113 that covers the gate electrode 112 is formed on the stacked structure by a CVD method (step (h)).
- the insulating film 111 and the protective film 113 are, for example, one selected from the group consisting of silicon (Si), magnesium (Mg), hafnium (Hf), aluminum (Al), titanium (Ti), and tantalum (Ta). Or what is necessary is just to comprise by 2 or more types of oxides or nitrides.
- the protective film 113 may be formed of an organic insulator.
- the effects produced by the method of manufacturing the field effect transistor 10 of the first embodiment are as follows.
- the electron barrier layer 105 and the electron transit layer 106 are continuously epitaxially grown on the substrate 101, and then, at a position on the side of the gate electrode 112 and away from the source electrode 109.
- An etched surface is formed, and an electron conduction region 108 is formed on the etched surface.
- a part of the electron barrier layer 105 and the electron transit layer 106 is etched, and the electron transit layer is regrown on the processed surface.
- the electron transit layer 106 is continuously epitaxially grown together with other layers, and since there is no regrowth after stopping the growth and undergoing a process step such as photolithography or dry etching, the crystalline layer is crystalline.
- a good electron transit layer 106 can be obtained, and an electric field effect in which the electron mobility at and near the heterojunction interface between the electron transit layer 106 and the electron supply layer 107 is high and the resistance (channel resistance) of the channel region is low.
- the transistor 10 can be manufactured.
- the ridge portion of the gate electrode 112 on the electron conduction region 108 side is longer than the ridge portion of the gate electrode 112 on the source electrode 109 side, electric field concentration in the vicinity of the gate electrode 112 can be reduced.
- the breakdown voltage can be improved.
- local electric field concentration in the channel region is suppressed and potential fluctuation is suppressed, current collapse can be further suppressed.
- FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 10A, which is a modification of the first embodiment.
- a potential control electrode 115 is formed on the opposite side of the electron conduction region 108 from the drift layer 104 via a potential control insulating film (insulating film) 114.
- the potential control insulating film 114 preferably contains at least one of aluminum, silicon, hafnium, zirconium, tantalum, and titanium and at least one of oxygen and nitrogen.
- the potential control insulating film 116 preferably has a dielectric constant of 6 or more from the viewpoint of securing a large capacitance C1 described later.
- the potential control insulating film 116 it is preferable to use aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, or the like.
- the thickness of the potential control insulating film 116 is preferably 10 nm or more from the viewpoint of preventing dielectric breakdown of the insulating film.
- the potential of the electron conduction region 108 is different from that of the potential control electrode 115. It is determined by the ratio of the capacitance C1 between the electron conduction regions 108, the electron conduction region 108, and the capacitance C2 of the high-concentration n-type semiconductor layer 103.
- the potential Vc of the electron conduction region 108 is lower than the drain voltage Vd, it is considered that a voltage drop occurs in the drift layer 104 (note that the potential of the high concentration n-type semiconductor layer 103 is approximately the same as the drain voltage Vd. is there). Accordingly, the electric field can be concentrated in the drift layer 104, and the concentration of the electric field on the drain end of the gate electrode can be suppressed, so that the off breakdown voltage can be improved. Even when the electron conduction region is formed of a semiconductor material, the potential on the potential control insulating film 114 side of the electron conduction region 108 can be regarded as Vc, and the same effect can be expected. Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved.
- the potential control insulating film 114 and the potential control electrode 115 may be formed after the electron conduction region 108 is formed. That is, the potential control insulating film 114 is formed after the electron conduction region 108 is formed, and then the potential control electrode 115 is formed on the potential control insulating film 114. Thereafter, the potential control electrode 115 may be grounded or connected to the gate electrode.
- FIG. 4 is a diagram schematically showing a cross-sectional structure of the field effect transistor 20 of the second embodiment.
- the field effect transistor 20 has a stacked structure in which a high-concentration n-type semiconductor layer 203, a drift layer 204, an electron barrier layer 205, an electron transit layer 206, and an electron supply layer 207 are stacked in this order on a substrate 201. Yes.
- An insulating film 211 is formed on the laminated structure.
- a gate electrode 212 is formed in the opening formed in the insulating film 211 on the electron supply layer 207.
- an electron conduction region 208 in which electrons as carriers flow in the vertical direction is formed in a stacked structure.
- the electron conduction region 208 is provided so as to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the p-type electron barrier layer 205.
- a source electrode 209 is formed on the electron supply layer 207 on the other of the left and right sides of the gate electrode 212.
- a drain electrode 210 is formed on the back surface of the substrate 201, and the drain electrode 210 is electrically connected to one end of the electron conduction region 208 through the substrate 201, the high concentration n-type semiconductor layer 203 and the drift layer 204.
- the upper surface of the electron transit layer 206 is heterojunction to the electron supply layer 207, and when the field effect transistor 20 is operated, a channel region of two-dimensional electron gas is formed at and near the heterojunction interface. At this time, electrons injected from the source electrode 209 can move to the drain electrode 210 through the channel region and the electron conduction region 208.
- the manufacturing method of the field effect transistor 20 includes the following basic steps (a) to (h).
- (G) A step of forming the gate electrode 212 in the opening of the insulating film 211 on the electron transit layer 206.
- (H) A step of forming a protective film 213 that covers the entire element except the source electrode 209.
- a conductive group III nitride compound semiconductor substrate made of GaN, AlN, or the like is used as the substrate 201.
- the substrate 201 is not limited to this.
- a silicon carbide substrate or a silicon substrate may be used for the substrate 201.
- a high-concentration n-type semiconductor layer 203, a drift layer 204, an electron barrier layer 205, an electron transit layer 206, and an electron supply are formed by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).
- MOVPE metal organic vapor phase epitaxy
- MBE molecular beam epitaxy
- a plurality of compound semiconductor layers constituting each of the layers 207 are continuously grown.
- Growing a plurality of compound semiconductor layers continuously means a growth process of the buffer layer 202, a growth process of the high-concentration n-type semiconductor layer 203, a growth process of the drift layer 204, a growth process of the electron barrier layer 205, an electron transit layer
- a series of growth steps of the growth step 206 and the growth step of the electron supply layer 207 are continuously performed. That is, each layer is continuously epitaxially grown in the stacking order, and the growth is stopped in the middle of the growth process of each layer, and after the process steps such as photolithography and dry etching, the regrowth is not performed. Among these, it is preferable that each layer is continuously grown in the same apparatus.
- the high-concentration n-type semiconductor layer 203, the drift layer 204, the electron barrier layer 205, the electron transit layer 206, and the electron supply layer 207 are respectively the high-concentration n-type semiconductor layer 103, the drift layer 104, and the electron barrier in the first embodiment. What is necessary is just to comprise with the same material and composition as the layer 105, the electron transit layer 106, and the electron supply layer 107. If the impurity concentration in the electron transit layer 206 becomes too high, the influence of Coulomb scattering increases and the electron mobility decreases. Therefore, the impurity concentration is preferably 1 ⁇ 10 17 cm ⁇ 3 or less. In addition, since electrons are supplied from the electron supply layer 207 to the electron transit layer 206, the electron supply layer 207 is made of a material or composition having a smaller electron affinity than the electron transit layer 206.
- the electron conduction region 208 is located on the opposite side of the source electrode 209 across the gate electrode 212 in plan view from the substrate surface side.
- the configuration is the same as that of the electron conduction region 208, but extends from the electron supply layer 207 side to the drift layer 204 side, and one end thereof is in contact with the electron supply layer 207 and the electron transit layer 206, The other end is in contact with a region (in this embodiment, the drift layer 203) located closer to the substrate than the electron barrier layer. More specifically, the electron conduction region 208 is provided in contact with the electron supply layer 207, the electron transit layer 206, the electron barrier layer 205, and the drift layer 204. The electron conduction region 208 is formed up to the middle of the thickness of the drift layer 204.
- the electron conduction region 208 can be formed using substantially the same manufacturing process as the electron conduction region 108 of the first embodiment. That is, the electron conduction region 208 is formed by diffusing n-type impurities into the laminated structure from the etched surface formed in the laminated structure. Alternatively, the electron conduction region 208 may be formed by ion-implanting n-type impurities into the stacked structure and performing a heat treatment from the surface of the stacked structure to a depth reaching the drift layer 204 region. The acceleration voltage at the time of ion implantation is controlled so that the implantation depth of n-type impurity ions reaches the drift layer 204. Also in the first embodiment, the electron conduction region 108 may be formed by ion-implanting n-type impurities into the laminated structure and performing heat treatment.
- the gate electrode 212, the source electrode 209, the insulating film 211, and the protective film 213 are formed using substantially the same manufacturing process as the gate electrode 112, the source electrode 109, the insulating film 111, and the protective film 113 of the first embodiment, respectively. can do.
- the drain electrode 210 is formed by forming a single-layer or multilayer metal film by, for example, a vacuum deposition method.
- the effects produced by the method of manufacturing the field effect transistor 20 of the second embodiment are as follows. Similar to the first embodiment, in the manufacturing method of the second embodiment, the electron barrier layer 205 and the electron transit layer 206 are continuously epitaxially grown on the substrate 201, and then on the side of the gate electrode 212. Then, an etched surface is formed at a position away from the source electrode 209, and an electron conduction region 208 is formed on the etched surface. In other words, after the electron barrier layer 205 and the electron transit layer 206 are epitaxially grown, a part of the electron barrier layer 205 and the electron transit layer 206 is etched, and the electron transit layer is regrown on the processed surface.
- the field effect transistor 20 is operated by applying a high voltage between the gate electrode 212 and the drain electrode 210, the field effect transistor 20 has a structure in which carriers flow in the vertical direction through the electron conduction region 208.
- FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 20A, which is a modification of the second embodiment.
- a potential control electrode 115 for controlling the potential of the electron conduction region 208 via the potential control insulating film 114 is disposed on the opposite side of the drift layer 203 of the electron conduction region 208.
- Such a field effect transistor 20A can provide the same effects as those of the modification of the first embodiment. Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved.
- the potential control insulating film 114 and the potential control electrode 115 may be formed after the electron conduction region 208 is formed, as in the modification of the first embodiment.
- the field effect transistor of the first example has the same structure as that of the field effect transistor 10 of the first embodiment, and was produced by the same method as that of the first embodiment.
- As the substrate 101 a silicon substrate having a (111) plane as a main surface was used.
- each layer is continuously grown in the same apparatus by the MOVPE method.
- the field effect transistor of the second example has the same structure as the field effect transistor 10A of the modification of the first embodiment.
- the substrate 101 a silicon carbide substrate having a Si surface as a main surface was used.
- An n-type GaN layer doped with Si impurity concentration: 5 ⁇ 10 16 cm ⁇ 3, film thickness: 4000 nm
- Mg impurity concentration 1 ⁇ 10 19 cm ⁇ as the electron barrier layer 105.
- each layer is continuously grown in the same apparatus by the MOVPE method.
- the electron conduction region 108 is formed by removing a part of the laminated structure by dry etching to form an etched surface, and a Ti / Al laminated structure (Ti layer thickness: 30 nm, Al layer thickness on the etched surface). : 180 nm), and heat treatment was performed at 650 ° C. for 30 seconds. Thereafter, an Al 2 O 3 film (film thickness: 100 nm) is formed as the potential control insulating film 114 by sputtering, and a Ti / Pt / Au laminated structure (Ti film thickness: 10 nm, Pt layer is formed as the potential control electrode 415. Film thickness: 80 nm, Au layer film thickness: 300 nm).
- the field effect transistor of the third example has the same structure as that of the field effect transistor 20 of the second embodiment, and was produced by the same method as that of the second embodiment.
- As the substrate 201 an n-type GaN substrate having a (0001) plane as a main surface was used.
- the buffer layer 202, the high-concentration n-type semiconductor layer 203, the drift layer 204, the electron barrier layer 205, and the electron supply layer 207 were successively grown to obtain a stacked structure.
- each layer is continuously grown in the same apparatus by the MOVPE method.
- the electron conduction region 208 was formed by ion-implanting Si into the etched surface (implantation energy: 200 KeV, implantation amount: 5 ⁇ 10 14 cm ⁇ 2 ) and performing activation annealing by heat treatment at 1200 ° C. for 1 hour. . Thereafter, the gate electrode 112, the source electrode 109, and the drain electrode 110 were formed.
- the field effect transistor of the fourth example has the same structure as the field effect transistor 20A of the modification of the second embodiment, and was created by the same method as that of the modification of the second embodiment.
- As the substrate 201 an n-type GaN substrate having a (0001) plane as a main surface was used.
- the buffer layer 202, the high-concentration n-type semiconductor layer 203, the drift layer 204, the electron barrier layer 205, and the electron supply layer 207 were successively grown to obtain a stacked structure.
- each layer is continuously grown in the same apparatus by the MOVPE method.
- the electron conduction region 208 was formed by ion-implanting Si into the etched surface (implantation energy: 200 KeV, implantation amount: 5 ⁇ 10 14 cm ⁇ 2 ) and performing activation annealing by heat treatment at 1200 ° C. for 1 hour. .
- a ZrO 2 film (film thickness: 300 nm) is formed by sputtering as the potential control insulating film 214, and a Ti / Pt / Au laminated structure (Ti layer film thickness: 10 nm, Pt layer film) is formed as the potential control electrode 415. (Thickness: 80 nm, Au layer thickness: 300 nm) was formed by sputtering. Thereafter, the gate electrode 112, the source electrode 109, and the drain electrode 110 were formed.
- the two-dimensional electron gas can be generated at and near the heterojunction interface between the electron transit layer 106 and the electron supply layer 107 using the piezo effect and the spontaneous polarization effect. It is not limited to this. Even if the concentration of the two-dimensional electron gas at and around the heterointerface is adjusted by introducing n-type impurities such as Si, S, Se, and O into the electron supply layer 107 having a larger band gap than the electron transit layer 106. Good (modulation doping). The same applies to the electron transit layer 206 and the electron supply layer 207 of the second embodiment.
- the thickness of each of the compound semiconductor layers 102 to 107 formed on the substrate 101 can be set to a desired thickness. If the lattice constant is significantly different from the above, it is desirable to make it less than the critical film thickness (thickness at which dislocation occurs in the crystal and the lattice distortion is relaxed). The same applies to the compound semiconductor layers 203 to 207 formed on the substrate 201 of the second embodiment.
- the field effect transistor 10 of the first embodiment has a heterojunction interface between the electron transit layer 106 and the electron supply layer 107, and a channel of a two-dimensional electron gas is formed at and near the heterojunction interface.
- the present invention is not limited to this.
- the field effect transistor 10 may have a single electron transit layer instead of the combination of the electron supply layer 107 and the electron transit layer 106. The same applies to the combination of the electron transit layer 206 and the electron supply layer 207 of the second embodiment.
- a Schottky junction is formed between the electron supply layer 107, which is a compound semiconductor layer, and the gate electrode 112.
- the invention is not limited to this.
- a MIS (Metal-Insulator-Semiconductor) structure in which a gate insulating film is formed between the electron supply layer 107 and the gate electrode 112.
- a MIS structure in which a gate insulating film is formed between the electron supply layer 207 and the gate electrode 212 of the second embodiment.
- the electron supply layers 107 and 207 are made of p such as Be, C, or Mg in order to suppress the gate leakage current.
- Type impurities may be introduced.
- the electron conductive regions 108 and 208 are provided on the end side of the electron transit layers 106 and 206, but the present invention is not limited to this.
- an electron conduction region 108 may be disposed at the center of the drift layer 104, the p-type electron barrier layer 105, the electron transit layer 106, and the electron supply layer 107.
- This transistor includes a plurality of source electrodes 109 and a gate electrode 112. Specifically, when viewed from the substrate surface side, a gate electrode 112 is disposed adjacent to the source electrode 109, an electron conduction region 108 is disposed next to the gate electrode 112, and further, next to the electron conduction region 108.
- the gate electrode 112A is disposed, and the source electrode 109A is disposed adjacent to the gate electrode 112A.
- the electron conductive region 108 is disposed so as to be sandwiched between the pair of source electrodes 109 and 109A.
- each layer constituting a stacked structure including the electron barrier layer and the electron transit layer in this order is continuously epitaxially grown on the substrate, and then the electron conduction region 108 is formed. do it.
Abstract
Disclosed is a manufacturing method having a step wherein a laminate structure that includes an electron barrier layer (105) and an electron transit layer (106) in that order is grown continuously on a substrate (101); a step wherein, on one side of a region where a gate electrode (112) is formed, an electron conduction region (108) is formed in a laminate structure extending from one edge of the electron transit layer (106) to a region that is more toward the substrate (101) than the electron barrier layer (105); a step wherein a gate electrode (112) is formed on the electron transit layer (106); a step wherein a source electrode (109) is formed on the electron transit layer (106) on the other side of the gate electrode (112); and a step wherein a drain electrode (110) is formed.
Description
本発明は、電界効果トランジスタの製造方法に関する。
The present invention relates to a method for manufacturing a field effect transistor.
ＧａＮなどのIII族窒化物系化合物半導体は、大きなバンドギャップを有し、高い絶縁破壊電界強度と高い電子移動度を有している。近年、このIII族窒化物系化合物半導体を構成材料とする高耐圧・高速動作が可能な電界効果トランジスタの研究開発が進められている。中でも、キャリアが基板面に垂直な方向に移動できる縦型構造を有する電界効果トランジスタは、低オン抵抗化と高耐圧化とを実現し得るデバイスとして注目されている。この種の縦型構造は、たとえば、特許文献１（特開２００７－１４２２４３号公報）や非特許文献１（Masakazu Kanechika et al., "A Vertical Insulated Gate AlGaN/GaN Hete rojunction Field-Effect Transistor", Jpn. J. Appl. Phys., Vol. 46, No. 21, pp. L 503-L505, 2007）に開示されている。
Group III nitride compound semiconductors such as GaN have a large band gap, high breakdown field strength, and high electron mobility. In recent years, research and development of a field effect transistor capable of high withstand voltage and high speed operation using the group III nitride compound semiconductor as a constituent material has been advanced. In particular, a field effect transistor having a vertical structure in which carriers can move in a direction perpendicular to the substrate surface has attracted attention as a device that can realize low on-resistance and high breakdown voltage. This type of vertical structure is disclosed in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2007-142243) and Non-patent Document 1 (Masakazu Kanechika et al. Jpn. J. Appl. Phys., Vol. 46, No. 21, pp. L 503-L505, 2007).
図１は、非特許文献１に開示された縦型構造を有するＡｌＧａＮ／ＧａＮヘテロ接合型電界効果トランジスタの断面構造の概略図である。図１に示されるように、この電界効果トランジスタは、ｎ型ＧａＮ基板１００１上に、ｎ型ＧａＮ層１００２、ｐ型ＧａＮ層１００３、ｎ型ＧａＮ層１００６およびｉ型ＡｌＧａＮ層１００７を有している。ＡｌＧａ層１００７上には、ＳｉＯ２層１００９を介してゲート電極１０１０とが形成されておりこのゲート電極１０１０の両側にソース電極１００８が形成されている。ソース電極１００８の直下には、それぞれ、ｐ型不純物拡散層が形成されている。そして、ｎ型ＧａＮ基板１００１の裏面にはドレイン電極１００８が形成されている。この電界効果トランジスタがオン状態のとき、ソース電極１００８から注入されたキャリアは、ＧａＮ層１００６とＡｌＧａＮ層１００７との面付近に形成されたチャネル領域（２次元電子ガス）を流れ、ｐ型ＧａＮ層１００３の開口部を介して縦方向にドレイン電極１００８へ流れる。
FIG. 1 is a schematic view of a cross-sectional structure of an AlGaN / GaN heterojunction field effect transistor having a vertical structure disclosed in Non-Patent Document 1. As shown in FIG. 1, this field effect transistor has an n-type GaN layer 1002, a p-type GaN layer 1003, an n-type GaN layer 1006, and an i-type AlGaN layer 1007 on an n-type GaN substrate 1001. . A gate electrode 1010 is formed on the AlGa layer 1007 with an SiO 2 layer 1009 interposed therebetween, and source electrodes 1008 are formed on both sides of the gate electrode 1010. A p-type impurity diffusion layer is formed immediately below the source electrode 1008. A drain electrode 1008 is formed on the back surface of the n-type GaN substrate 1001. When this field effect transistor is in an on state, carriers injected from the source electrode 1008 flow through a channel region (two-dimensional electron gas) formed in the vicinity of the surfaces of the GaN layer 1006 and the AlGaN layer 1007, and the p-type GaN layer It flows to the drain electrode 1008 in the vertical direction through the opening 1003.
この電界効果トランジスタの製法は以下の通りである。ｎ型ＧａＮ基板１００１上に、Ｓｉが添加されたｎ型ＧａＮ層１００２と、Ｍｇが添加されたｐ型ＧａＮ層と、ＡｌＮ層と、ｉ型ＧａＮ層とをこの順にエピタキシャル成長させる。この結果得られた積層構造上にＳｉＯ２マスクパターンを形成し、これを用いたドライエッチングを実行する。その後、ＳｉＯ２マスクパターンを除去する。この結果、図１に示されるような開口部を持つｐ型ＧａＮ層１００３が形成される。
The manufacturing method of this field effect transistor is as follows. An n-type GaN layer 1002 to which Si is added, a p-type GaN layer to which Mg is added, an AlN layer, and an i-type GaN layer are epitaxially grown on the n-type GaN substrate 1001 in this order. An SiO 2 mask pattern is formed on the resulting laminated structure, and dry etching is performed using the SiO 2 mask pattern. Thereafter, the SiO 2 mask pattern is removed. As a result, a p-type GaN layer 1003 having an opening as shown in FIG. 1 is formed.
その後、この開口部にｎ型ＧａＮ層１００６を埋め込み成長させ、このｎ型ＧａＮ層１００６上にｉ型ＡｌＧａＮ層１００７をエピタキシャル成長させる。次に、ＡｌＧａＮ層１００７にＳｉイオンを注入し活性化してｐ型不純物拡散層を形成する。そして、これらｐ型不純物拡散層上に、Ｔｉ／Ａｌ多層膜からなるソース電極（オーミック電極）１００８を形成する。次いで、ＳｉＯ２層１００９を成膜した後、ｎ＋型ポリシリコンからなるゲート電極１０１０を形成し、活性化アニールを実行する。
Thereafter, an n-type GaN layer 1006 is embedded and grown in the opening, and an i-type AlGaN layer 1007 is epitaxially grown on the n-type GaN layer 1006. Next, Si ions are implanted into the AlGaN layer 1007 and activated to form a p-type impurity diffusion layer. Then, a source electrode (ohmic electrode) 1008 made of a Ti / Al multilayer film is formed on these p-type impurity diffusion layers. Next, after forming a SiO 2 layer 1009, a gate electrode 1010 made of n + type polysilicon is formed, and activation annealing is performed.
図１の電界効果トランジスタは、ｐ型ＧａＮ層１００３の開口部を介してｎ型ＧａＮ基板１００１の裏面に向けて縦方向にキャリアが流れる構造を有し、当該電界効果トランジスタの半導体層表面の固定電荷や半導体層と絶縁膜との界面の固定電荷の影響を受けることなく、キャリアの移動経路における局所的な電界集中を抑制できるため、ＧａＮの絶縁破壊耐圧の物性値（＝約３．３×１０６Ｖ／ｃｍ）に近い最大電界強度を期待できる。
The field effect transistor of FIG. 1 has a structure in which carriers flow in the vertical direction toward the back surface of the n-type GaN substrate 1001 through the opening of the p-type GaN layer 1003, and the surface of the semiconductor layer of the field effect transistor is fixed. Since the local electric field concentration in the carrier movement path can be suppressed without being affected by the electric charge or the fixed electric charge at the interface between the semiconductor layer and the insulating film, the physical property value of the breakdown voltage of GaN (= about 3.3 × A maximum electric field strength close to 10 6 V / cm can be expected.
図１の縦型構造を得るために、エッチングによりｐ型ＧａＮ層１００３の開口部を形成した後、この開口部でＧａＮ層１００６を再成長させているが、この再成長されたＧａＮ層１００６の結晶性が低いという問題がある。ＧａＮ層１００６の結晶性が低いと、電流コラプスの発生やチャネル領域での電子移動度の低下が起こる。また、ＧａＮ層１００６には、ｎ型不純物であるシリコンが添加されるため、電子移動度が低くなるという問題もある。さらに、電子移動度が低いことに起因してオン抵抗の低減が困難となる。
In order to obtain the vertical structure of FIG. 1, after the opening of the p-type GaN layer 1003 is formed by etching, the GaN layer 1006 is regrown in this opening, but the GaN layer 1006 thus regrown There is a problem of low crystallinity. When the crystallinity of the GaN layer 1006 is low, current collapse occurs and electron mobility in the channel region decreases. In addition, since silicon, which is an n-type impurity, is added to the GaN layer 1006, there is a problem that electron mobility is lowered. Furthermore, it is difficult to reduce the on-resistance due to the low electron mobility.
上記に鑑みて本発明は、縦方向にキャリアが流れる構造を有しながら、チャネル領域での電子移動度の低下の防止とオン抵抗の低減とを実現し得る電界効果トランジスタの製造方法を提供するものである。
In view of the above, the present invention provides a method of manufacturing a field effect transistor that has a structure in which carriers flow in the vertical direction, and can achieve reduction in electron mobility and reduction in on-resistance in a channel region. Is.
本発明によれば、基板上に、電子障壁層と電子走行層とをこの順に含む積層構造を構成する各層を連続的に成長させる工程と、
ゲート電極が形成される領域の一方の側で、前記電子走行層から前記電子障壁層よりも前記基板側の領域に亘って前記積層構造に電子伝導領域を形成する工程と、
前記電子走行層上に前記ゲート電極を形成する工程と、
前記ゲート電極が形成される領域の他方の側における前記電子走行層上にソース電極を形成する工程と、
前記電子伝導領域の前記基板側の一端と電気的に接続されるドレイン電極を形成する工程と、
を備える電界効果トランジスタの製造方法が提供される。 According to the present invention, on the substrate, the steps of continuously growing each layer constituting the laminated structure including the electron barrier layer and the electron transit layer in this order;
Forming an electron conduction region in the stacked structure from one side of the region where the gate electrode is formed to a region closer to the substrate than the electron barrier layer from the electron transit layer;
Forming the gate electrode on the electron transit layer;
Forming a source electrode on the electron transit layer on the other side of the region where the gate electrode is formed;
Forming a drain electrode electrically connected to one end of the electron conducting region on the substrate side;
A method for manufacturing a field effect transistor is provided.
ゲート電極が形成される領域の一方の側で、前記電子走行層から前記電子障壁層よりも前記基板側の領域に亘って前記積層構造に電子伝導領域を形成する工程と、
前記電子走行層上に前記ゲート電極を形成する工程と、
前記ゲート電極が形成される領域の他方の側における前記電子走行層上にソース電極を形成する工程と、
前記電子伝導領域の前記基板側の一端と電気的に接続されるドレイン電極を形成する工程と、
を備える電界効果トランジスタの製造方法が提供される。 According to the present invention, on the substrate, the steps of continuously growing each layer constituting the laminated structure including the electron barrier layer and the electron transit layer in this order;
Forming an electron conduction region in the stacked structure from one side of the region where the gate electrode is formed to a region closer to the substrate than the electron barrier layer from the electron transit layer;
Forming the gate electrode on the electron transit layer;
Forming a source electrode on the electron transit layer on the other side of the region where the gate electrode is formed;
Forming a drain electrode electrically connected to one end of the electron conducting region on the substrate side;
A method for manufacturing a field effect transistor is provided.
縦方向にキャリアが流れる構造を有しながら、電子走行層に形成されるチャネル領域での電子移動度の低下の防止とチャネル抵抗の低減とを実現し得る電界効果トランジスタの製造方法を提供することができる。
To provide a method of manufacturing a field effect transistor that has a structure in which carriers flow in the vertical direction and can realize prevention of reduction of electron mobility and reduction of channel resistance in a channel region formed in an electron transit layer. Can do.
上述した目的、およびその他の目的、特徴および利点は、以下に述べる好適な実施の形態、およびそれに付随する以下の図面によってさらに明らかになる。
縦型構造を有するＡｌＧａＮ／ＧａＮヘテロ接合型電界効果トランジスタの断面構造の概略図である。
本発明に係る第１の実施形態の電界効果トランジスタの断面構造を概略的に示す図である。
第１の実施形態の変形例である電界効果トランジスタの断面構造を概略的に示す図である。
本発明に係る第２の実施形態の電界効果トランジスタの断面構造を概略的に示す図である。
第２の実施形態の変形例である電界効果トランジスタの断面構造を概略的に示す図である。
変形例にかかる電界効果トランジスタの断面構造を概略的に示す図である。
The above-described object and other objects, features, and advantages will become more apparent from the preferred embodiments described below and the accompanying drawings.
It is the schematic of the cross-section of the AlGaN / GaN heterojunction field effect transistor which has a vertical structure. 1 is a diagram schematically showing a cross-sectional structure of a field effect transistor according to a first embodiment of the present invention. It is a figure which shows roughly the cross-section of the field effect transistor which is a modification of 1st Embodiment. It is a figure which shows roughly the cross-section of the field effect transistor of 2nd Embodiment which concerns on this invention. It is a figure which shows roughly the cross-section of the field effect transistor which is a modification of 2nd Embodiment. It is a figure which shows roughly the cross-section of the field effect transistor concerning a modification.
以下、本発明に係る実施の形態について図面を参照しつつ説明する。なお、すべての図面において、同様な構成要素には同一符号を付し、その詳細な説明は重複しないように適宜省略される。
また、この出願は、２００８年８月６日に出願された日本出願特願２００８－２０３４８７を基礎とする優先権を主張し、その開示のすべてをここに取り込む。 Embodiments according to the present invention will be described below with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and detailed description thereof is appropriately omitted so as not to overlap.
This application claims priority based on Japanese Patent Application No. 2008-203487 filed on Aug. 6, 2008, the entire disclosure of which is incorporated herein.
また、この出願は、２００８年８月６日に出願された日本出願特願２００８－２０３４８７を基礎とする優先権を主張し、その開示のすべてをここに取り込む。 Embodiments according to the present invention will be described below with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and detailed description thereof is appropriately omitted so as not to overlap.
This application claims priority based on Japanese Patent Application No. 2008-203487 filed on Aug. 6, 2008, the entire disclosure of which is incorporated herein.
（第１の実施形態）
図２は、本発明に係る第１の実施形態の電界効果トランジスタ１０の断面構造を概略的に示す図である。この電界効果トランジスタ１０は、基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、ｐ型電子障壁層１０５、電子走行層１０６および電子供給層１０７がこの順に積層された積層構造を有している。この積層構造は絶縁膜１１１で被覆されている。電子供給層１０７上において絶縁膜１１１に形成された開口部にゲート電極１１２が形成されている。 (First embodiment)
FIG. 2 is a diagram schematically showing a cross-sectional structure of thefield effect transistor 10 according to the first embodiment of the present invention. In this field effect transistor 10, a buffer layer 102, a high concentration n-type semiconductor layer 103, a drift layer 104, a p-type electron barrier layer 105, an electron transit layer 106 and an electron supply layer 107 are laminated on a substrate 101 in this order. It has a laminated structure. This laminated structure is covered with an insulating film 111. A gate electrode 112 is formed in the opening formed in the insulating film 111 on the electron supply layer 107.
図２は、本発明に係る第１の実施形態の電界効果トランジスタ１０の断面構造を概略的に示す図である。この電界効果トランジスタ１０は、基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、ｐ型電子障壁層１０５、電子走行層１０６および電子供給層１０７がこの順に積層された積層構造を有している。この積層構造は絶縁膜１１１で被覆されている。電子供給層１０７上において絶縁膜１１１に形成された開口部にゲート電極１１２が形成されている。 (First embodiment)
FIG. 2 is a diagram schematically showing a cross-sectional structure of the
ゲート電極１１２の左右両側（基板面に平行な方向における両側）のうちの一方の側（ゲート長方向の一方の側）では、積層構造に形成されたエッチング加工面に電子伝導領域１０８が形成されている。この電子伝導領域１０８は、電子走行層１０６の一端から、ｐ型電子障壁層１０５よりも基板１０１側の領域に延在するように設けられている。ゲート電極１１２の左右両側のうちの他方の側（ゲート長方向の他方の側）では、電子供給層１０７上にソース電極１０９が形成されている。また、基板１０１上には、バッファ層１０２および高濃度ｎ型半導体層１０３を介してドレイン電極１１０が形成されている。このドレイン電極１１０は、基板１０１の表面側に形成されており、高濃度ｎ型半導体層１０３を介して電子伝導領域１０８の一端と電気的に接続されている。
On one side (one side in the gate length direction) of the left and right sides of the gate electrode 112 (both sides in the direction parallel to the substrate surface), an electron conduction region 108 is formed on the etched surface formed in the stacked structure. ing. The electron conduction region 108 is provided so as to extend from one end of the electron transit layer 106 to a region closer to the substrate 101 than the p-type electron barrier layer 105. A source electrode 109 is formed on the electron supply layer 107 on the other side of the left and right sides of the gate electrode 112 (the other side in the gate length direction). A drain electrode 110 is formed on the substrate 101 with a buffer layer 102 and a high-concentration n-type semiconductor layer 103 interposed therebetween. The drain electrode 110 is formed on the surface side of the substrate 101, and is electrically connected to one end of the electron conduction region 108 through the high concentration n-type semiconductor layer 103.
電子走行層１０６の上面は、電子供給層１０７にヘテロ接合されており、電界効果トランジスタ１０の動作時には、そのヘテロ接合界面およびその近傍に２次元電子ガスのチャネル領域が形成される。このとき、ソース電極１０９から注入された電子は、チャネル領域と電子伝導領域１０８とを介してドレイン電極１１０へ移動することができる。
The upper surface of the electron transit layer 106 is heterojunction to the electron supply layer 107, and when the field effect transistor 10 is operated, a channel region of a two-dimensional electron gas is formed at and near the heterojunction interface. At this time, electrons injected from the source electrode 109 can move to the drain electrode 110 through the channel region and the electron conduction region 108.
上記電界効果トランジスタ１０の製造方法は、下記（ａ）～（ｈ）の基本工程を有するものである。
（ａ）基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子走行層１０６および電子供給層１０７をそれぞれ構成する複数の化合物半導体層をこの順に含む積層構造を連続的にエピタキシャル成長させる工程。
（ｂ）ゲート電極１１２が形成される領域の左右両側のうちの一方の側（ゲート電極１１２が形成される領域の側方）で、積層構造をエッチングして、電子走行層１０６の一端から電子障壁層１０５よりも基板１０１側の領域に亘ってエッチング加工面を形成する工程。
（ｃ）当該エッチング加工面に電子伝導領域１０８を形成する工程。
（ｄ）ゲート電極１１２が形成される領域の当該左右両側のうちの他方の側（ゲート電極１１２が形成される領域の側方であって、電子伝導領域１０８が形成される側と反対側）における電子走行層１０６上に電子供給層１０７を介してソース電極１０９を形成する工程。
（ｅ）電子伝導領域１０８の基板１０１側の一端と電気的に接続されるドレイン電極１１０を形成する工程。
（ｆ）パターニングされた絶縁膜１１１を形成する工程。
（ｇ）電子走行層１０６上における絶縁膜１１１の開口部にゲート電極１１２を形成する工程。
（ｈ）電極表面の一部を除く素子全体を被覆する保護膜１１３を形成する工程。
なお、工程（ｄ）は、工程（ｂ）の前段で実施してもよい。
基板１０１としては、本実施形態では、ＧａＮやＡｌＮなどのIII族窒化物系化合物半導体基板を使用するが、これに限定されるものではない。たとえば、シリコン基板、サファイア基板あるいは炭化シリコン基板を基板１０１に使用してもよい。この基板１０１上には、有機金属気相成長（ＭＯＶＰＥ）法や分子線エピタキシャル成長（ＭＢＥ）法により、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子走行層１０６および電子供給層１０７を構成する複数の化合物半導体層を連続的にエピタキシャル成長させる。
ここで、複数の化合物半導体層を連続的に成長させるとは、バッファ層１０２の成長工程、高濃度ｎ型半導体層１０３の成長工程、ドリフト層１０４の成長工程、電子障壁層１０５の成長工程、電子走行層１０６の成長工程および電子供給層１０７の成長工程の一連の成長工程を連続して実施することである。すなわち、積層順に各層を連続してエピタキシャル成長させることであり、従来のように、層の成長工程の途中で、成長を止め、エッチング等で開口を形成し、その開口から層を再成長することは実施しない。なかでも、各層を同一装置内で連続成長させる、すなわち、各層を成長させるための装置から出さずに、各層を連続成長させることが好ましい。 The manufacturing method of thefield effect transistor 10 includes the following basic steps (a) to (h).
(A) A plurality of compound semiconductor layers constituting thebuffer layer 102, the high-concentration n-type semiconductor layer 103, the drift layer 104, the electron barrier layer 105, the electron transit layer 106, and the electron supply layer 107 on the substrate 101 in this order. A step of continuously epitaxially growing the laminated structure.
(B) The stacked structure is etched on one of the left and right sides of the region where thegate electrode 112 is formed (the side of the region where the gate electrode 112 is formed), and electrons are transmitted from one end of the electron transit layer 106. Forming an etched surface over a region closer to the substrate 101 than the barrier layer 105;
(C) A step of forming the electronconductive region 108 on the etched surface.
(D) The other side of the left and right sides of the region where thegate electrode 112 is formed (on the side of the region where the gate electrode 112 is formed and opposite to the side where the electron conduction region 108 is formed) Forming a source electrode 109 on the electron transit layer 106 in FIG.
(E) A step of forming adrain electrode 110 electrically connected to one end of the electron conduction region 108 on the substrate 101 side.
(F) A step of forming a patternedinsulating film 111.
(G) A step of forming thegate electrode 112 in the opening of the insulating film 111 on the electron transit layer 106.
(H) A step of forming aprotective film 113 that covers the entire element except a part of the electrode surface.
In addition, you may implement a process (d) in the front | former stage of a process (b).
In the present embodiment, a group III nitride compound semiconductor substrate such as GaN or AlN is used as thesubstrate 101, but the substrate 101 is not limited to this. For example, a silicon substrate, a sapphire substrate, or a silicon carbide substrate may be used for the substrate 101. On this substrate 101, a buffer layer 102, a high-concentration n-type semiconductor layer 103, a drift layer 104, an electron barrier layer 105, an electron transit layer are formed by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxial growth (MBE). 106 and the plurality of compound semiconductor layers constituting the electron supply layer 107 are continuously epitaxially grown.
Here, continuously growing a plurality of compound semiconductor layers means a growth process of thebuffer layer 102, a growth process of the high-concentration n-type semiconductor layer 103, a growth process of the drift layer 104, a growth process of the electron barrier layer 105, A series of growth processes including the growth process of the electron transit layer 106 and the growth process of the electron supply layer 107 is performed continuously. That is, each layer is continuously epitaxially grown in the stacking order, and in the middle of the layer growth process, the growth is stopped, an opening is formed by etching or the like, and the layer is regrowth from the opening as in the past. Not implemented. In particular, it is preferable that each layer is continuously grown in the same apparatus, that is, each layer is continuously grown without being removed from the apparatus for growing each layer.
（ａ）基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子走行層１０６および電子供給層１０７をそれぞれ構成する複数の化合物半導体層をこの順に含む積層構造を連続的にエピタキシャル成長させる工程。
（ｂ）ゲート電極１１２が形成される領域の左右両側のうちの一方の側（ゲート電極１１２が形成される領域の側方）で、積層構造をエッチングして、電子走行層１０６の一端から電子障壁層１０５よりも基板１０１側の領域に亘ってエッチング加工面を形成する工程。
（ｃ）当該エッチング加工面に電子伝導領域１０８を形成する工程。
（ｄ）ゲート電極１１２が形成される領域の当該左右両側のうちの他方の側（ゲート電極１１２が形成される領域の側方であって、電子伝導領域１０８が形成される側と反対側）における電子走行層１０６上に電子供給層１０７を介してソース電極１０９を形成する工程。
（ｅ）電子伝導領域１０８の基板１０１側の一端と電気的に接続されるドレイン電極１１０を形成する工程。
（ｆ）パターニングされた絶縁膜１１１を形成する工程。
（ｇ）電子走行層１０６上における絶縁膜１１１の開口部にゲート電極１１２を形成する工程。
（ｈ）電極表面の一部を除く素子全体を被覆する保護膜１１３を形成する工程。
なお、工程（ｄ）は、工程（ｂ）の前段で実施してもよい。
基板１０１としては、本実施形態では、ＧａＮやＡｌＮなどのIII族窒化物系化合物半導体基板を使用するが、これに限定されるものではない。たとえば、シリコン基板、サファイア基板あるいは炭化シリコン基板を基板１０１に使用してもよい。この基板１０１上には、有機金属気相成長（ＭＯＶＰＥ）法や分子線エピタキシャル成長（ＭＢＥ）法により、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子走行層１０６および電子供給層１０７を構成する複数の化合物半導体層を連続的にエピタキシャル成長させる。
ここで、複数の化合物半導体層を連続的に成長させるとは、バッファ層１０２の成長工程、高濃度ｎ型半導体層１０３の成長工程、ドリフト層１０４の成長工程、電子障壁層１０５の成長工程、電子走行層１０６の成長工程および電子供給層１０７の成長工程の一連の成長工程を連続して実施することである。すなわち、積層順に各層を連続してエピタキシャル成長させることであり、従来のように、層の成長工程の途中で、成長を止め、エッチング等で開口を形成し、その開口から層を再成長することは実施しない。なかでも、各層を同一装置内で連続成長させる、すなわち、各層を成長させるための装置から出さずに、各層を連続成長させることが好ましい。 The manufacturing method of the
(A) A plurality of compound semiconductor layers constituting the
(B) The stacked structure is etched on one of the left and right sides of the region where the
(C) A step of forming the electron
(D) The other side of the left and right sides of the region where the
(E) A step of forming a
(F) A step of forming a patterned
(G) A step of forming the
(H) A step of forming a
In addition, you may implement a process (d) in the front | former stage of a process (b).
In the present embodiment, a group III nitride compound semiconductor substrate such as GaN or AlN is used as the
Here, continuously growing a plurality of compound semiconductor layers means a growth process of the
バッファ層１０２は、たとえば、ＡｌＮやＧａＮ、ＡｌＧａＮなどのIII族窒化物系化合物半導体で構成すればよい。バッファ層１０２は、基板１０１の上面と格子整合する超格子構造（たとえば、ＡｌＧａＮ／ＧａＮ超格子構造）や組成変調構造を含んでもよい。高濃度ｎ型半導体層１０３は、たとえば、シリコン（Ｓｉ）、イオウ（Ｓ）、セレン（Ｓｅ）または酸素（Ｏ）などのｎ型不純物が高濃度に導入されたIII族窒化物系化合物半導体で構成すればよい。III族窒化物系化合物半導体としては、たとえば、ＧａＮ、ＩｎＮ、ＡｌＮが挙げられる。
The buffer layer 102 may be made of, for example, a group III nitride compound semiconductor such as AlN, GaN, or AlGaN. The buffer layer 102 may include a superlattice structure (for example, an AlGaN / GaN superlattice structure) that is lattice-matched to the upper surface of the substrate 101 or a composition modulation structure. The high-concentration n-type semiconductor layer 103 is a group III nitride compound semiconductor into which an n-type impurity such as silicon (Si), sulfur (S), selenium (Se), or oxygen (O) is introduced at a high concentration. What is necessary is just to comprise. Examples of the group III nitride compound semiconductor include GaN, InN, and AlN.
ドリフト層１０４は、たとえば、ＧａＮやＩｎＮ、ＡｌＮなどのIII族窒化物系化合物半導体で構成すればよい。ドリフト層１０４に導入するｎ型不純物としては、たとえば、Ｓｉ、Ｓ、Ｓｅ、Ｏが挙げられる。不純物濃度は、所望の値とすることができるが、電界集中を緩和するために、１×１０１８ｃｍ－３以下の濃度であることが好ましい。特に、耐圧性を高めるときには１×１０１７ｃｍ－３以下の濃度であることが好ましい。
The drift layer 104 may be made of a group III nitride compound semiconductor such as GaN, InN, or AlN. Examples of the n-type impurity introduced into the drift layer 104 include Si, S, Se, and O. The impurity concentration can be set to a desired value, but is preferably 1 × 10 18 cm −3 or less in order to reduce electric field concentration. In particular, when the pressure resistance is increased, the concentration is preferably 1 × 10 17 cm −3 or less.
電子障壁層１０５は、たとえば、ベリリウム（Ｂｅ）、炭素（Ｃ）またはマグネシウム（Ｍｇ）などのｐ型不純物が高濃度に導入されたIII族窒化物系化合物半導体層である。このIII族窒化物系化合物半導体としては、たとえば、ＧａＮ、ＩｎＮ、ＡｌＮが挙げられる。電子障壁層１０５に導入されるｐ型不純物濃度は、所望の値とすることができるが、高電圧領域で電子に対する電位障壁の形成を維持するためには、１×１０１８ｃｍ－３以上であることが望ましい。
The electron barrier layer 105 is a group III nitride compound semiconductor layer into which a p-type impurity such as beryllium (Be), carbon (C), or magnesium (Mg) is introduced at a high concentration. Examples of the group III nitride compound semiconductor include GaN, InN, and AlN. The concentration of the p-type impurity introduced into the electron barrier layer 105 can be set to a desired value. However, in order to maintain the formation of a potential barrier against electrons in the high voltage region, the concentration is 1 × 10 18 cm −3 or more. It is desirable to be.
電子走行層１０６は、たとえば、ＧａＮ、ＩｎＮ、ＡｌＮなどのIII族窒化物系化合物半導体で構成すればよい。電子走行層１０６は、たとえば、ＩｎaＡｌｂＧａ１－ a－ｂＮ（０≦a≦１、０≦ｂ≦１、a＋ｂ≦１）で構成される。この電子走行層１０６には、Ｓｉ、Ｓ、Ｓｅ、Ｏなどのｎ型不純物、あるいは、Ｂｅ、Ｃ、Ｍｇなどのｐ型不純物を添加してもよい。ただし、電子走行層１０６内の不純物濃度が高くなり過ぎると、クーロン散乱の影響が大きくなり、電子の移動度が低下するため、不純物濃度は１×１０１７ｃｍ－３以下であることが望ましい。
電子走行層１０６は、フォトリソグラフィやドライエッチングなどのプロセス工程を経ずに、一つの成長工程で、連続的に形成されたものである。 Theelectron transit layer 106 may be made of, for example, a group III nitride compound semiconductor such as GaN, InN, or AlN. The electron transit layer 106 is made of, for example, In a Al b Ga 1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1). The electron transit layer 106 may be added with n-type impurities such as Si, S, Se, and O, or p-type impurities such as Be, C, and Mg. However, if the impurity concentration in the electron transit layer 106 becomes too high, the influence of Coulomb scattering increases and the electron mobility decreases, so the impurity concentration is desirably 1 × 10 17 cm −3 or less.
Theelectron transit layer 106 is formed continuously in one growth process without passing through process processes such as photolithography and dry etching.
電子走行層１０６は、フォトリソグラフィやドライエッチングなどのプロセス工程を経ずに、一つの成長工程で、連続的に形成されたものである。 The
The
電子供給層１０７は、電子走行層１０６の上面にヘテロ接合し、ＧａＮやＩｎＮ、ＡｌＮなどのIII族窒化物系化合物半導体からなる層である。電子供給層１０７は、たとえば、たとえば、ＩｎｃＡｌｄＧａ１－ ｃ－ｄＮ（０≦ｃ≦１、０≦ｄ≦１、ｃ＋ｄ≦１）で構成される。電子供給層１０７から電子走行層１０６へ電子が供給されるために、電子供給層１０７は、電子走行層１０６よりも小さな電子親和力を持つ材料または組成からなる。なお、本実施形態では、電子供給層１０７に不純物は導入されていないが、この代わりに、Ｓｉ、Ｓ、Ｓｅ、Ｏなどのｎ型不純物を導入してもよい。
The electron supply layer 107 is a layer that is heterojunction with the upper surface of the electron transit layer 106 and is made of a group III nitride compound semiconductor such as GaN, InN, or AlN. The electron supply layer 107 is made of, for example, In c Al d Ga 1-cd N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1, c + d ≦ 1). In order to supply electrons from the electron supply layer 107 to the electron transit layer 106, the electron supply layer 107 is made of a material or composition having a smaller electron affinity than the electron transit layer 106. In this embodiment, no impurity is introduced into the electron supply layer 107, but an n-type impurity such as Si, S, Se, or O may be introduced instead.
電子伝導領域１０８は、基板面側からの平面視において、ゲート電極１１２を挟んでソース電極１０９と反対側に位置する。
本実施形態では、電子伝導領域１０８は、電子供給層１０７側からドリフト層１０４側に延在し、一方の端部が、電子供給層１０７および電子走行層１０６に接し、他方の端部が電子障壁層よりも基板側に位置する領域（本実施形態では、ドリフト層１０４）に接している。より詳細に説明すると、電子伝導領域１０８は、電子供給層１０７、電子走行層１０６、電子障壁層１０５、ドリフト層１０４に接して設けられ、電子供給層１０７側からドリフト層１０４の厚みの途中位置まで延在している。
電子伝導領域１０８は、積層構造のエッチング加工面から当該積層構造にｎ型不純物を導入し、当該導入されたｎ型不純物を熱処理により活性化することで形成することができる。エッチング加工面は、基板１０１上の積層構造をドライエッチングすることで得られる。たとえば、このエッチング加工面から積層構造にシリコンなどのｎ型不純物をイオン注入し、当該注入されたイオンを熱処理で活性化することで電子伝導領域１０８を形成することができる。あるいは、たとえばＣＶＤ法により、エッチング加工面にアモルファスまたは多結晶のシリコンを堆積した後、当該堆積されたシリコンを熱処理で積層構造に拡散させることで電子伝導領域１０８を形成することもできる。なお、熱処理によりシリコンが拡散した不純物拡散領域だけでなく、積層構造内に拡散されないシリコンも、導電膜として電子伝導領域１０８を構成する。エッチング加工面にシリコンを固相拡散させてもよい。 Theelectron conduction region 108 is located on the opposite side of the source electrode 109 with the gate electrode 112 interposed therebetween in plan view from the substrate surface side.
In the present embodiment, theelectron conduction region 108 extends from the electron supply layer 107 side to the drift layer 104 side, one end is in contact with the electron supply layer 107 and the electron transit layer 106, and the other end is an electron. It is in contact with a region (in this embodiment, the drift layer 104) located on the substrate side with respect to the barrier layer. More specifically, the electron conduction region 108 is provided in contact with the electron supply layer 107, the electron transit layer 106, the electron barrier layer 105, and the drift layer 104, and is located in the middle of the thickness of the drift layer 104 from the electron supply layer 107 side. It extends to.
The electronconductive region 108 can be formed by introducing an n-type impurity into the laminated structure from the etched surface of the laminated structure and activating the introduced n-type impurity by heat treatment. The etched surface can be obtained by dry etching the laminated structure on the substrate 101. For example, the electron conduction region 108 can be formed by ion-implanting an n-type impurity such as silicon into the laminated structure from the etched surface and activating the implanted ions by heat treatment. Alternatively, the electron conductive region 108 can be formed by depositing amorphous or polycrystalline silicon on the etched surface by, for example, CVD, and then diffusing the deposited silicon into a laminated structure by heat treatment. Note that not only the impurity diffusion region in which silicon is diffused by the heat treatment but also silicon that is not diffused in the stacked structure forms the electron conductive region 108 as a conductive film. Silicon may be solid-phase diffused on the etched surface.
本実施形態では、電子伝導領域１０８は、電子供給層１０７側からドリフト層１０４側に延在し、一方の端部が、電子供給層１０７および電子走行層１０６に接し、他方の端部が電子障壁層よりも基板側に位置する領域（本実施形態では、ドリフト層１０４）に接している。より詳細に説明すると、電子伝導領域１０８は、電子供給層１０７、電子走行層１０６、電子障壁層１０５、ドリフト層１０４に接して設けられ、電子供給層１０７側からドリフト層１０４の厚みの途中位置まで延在している。
電子伝導領域１０８は、積層構造のエッチング加工面から当該積層構造にｎ型不純物を導入し、当該導入されたｎ型不純物を熱処理により活性化することで形成することができる。エッチング加工面は、基板１０１上の積層構造をドライエッチングすることで得られる。たとえば、このエッチング加工面から積層構造にシリコンなどのｎ型不純物をイオン注入し、当該注入されたイオンを熱処理で活性化することで電子伝導領域１０８を形成することができる。あるいは、たとえばＣＶＤ法により、エッチング加工面にアモルファスまたは多結晶のシリコンを堆積した後、当該堆積されたシリコンを熱処理で積層構造に拡散させることで電子伝導領域１０８を形成することもできる。なお、熱処理によりシリコンが拡散した不純物拡散領域だけでなく、積層構造内に拡散されないシリコンも、導電膜として電子伝導領域１０８を構成する。エッチング加工面にシリコンを固相拡散させてもよい。 The
In the present embodiment, the
The electron
あるいは、たとえばスパッタ法により、積層構造のエッチング加工面に金属導電膜を形成することで電子伝導領域１０８を形成してもよい。さらには、積層構造を構成する半導体層と当該金属導電膜とを熱処理により相互反応させることが望ましい。金属導電膜は、タングステン（Ｗ）、モリブデン（Ｍｏ）、シリコン（Ｓｉ）、チタン（Ｔｉ）、白金（Ｐｔ）、ニオブ（Ｎｂ）、アルミニウム（Ａｌ）、金（Ａｕ）、タンタル（Ｔａ）、ジルコニウム（Ｚｒ）、イットリウム（Ｙ）からなる群から選択された１種または２種以上の金属材料で構成すればよい。当該エッチング加工面には、オーミック接触する金属導電膜を形成するのが好ましい。
Alternatively, the electron conductive region 108 may be formed by forming a metal conductive film on the etched surface of the laminated structure, for example, by sputtering. Furthermore, it is desirable to cause the semiconductor layer constituting the stacked structure and the metal conductive film to react with each other by heat treatment. The metal conductive film includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), gold (Au), tantalum (Ta), What is necessary is just to comprise by 1 type, or 2 or more types of metal materials selected from the group which consists of zirconium (Zr) and yttrium (Y). It is preferable to form a metal conductive film in ohmic contact on the etched surface.
あるいは、ＭＯＶＰＥ法やＭＢＥ法により、積層構造のエッチング加工面にｎ型ＧａＮ層などの化合物半導体層を再成長させて電子伝導領域１０８を形成してもよい。
電子伝導領域１０８を、化合物半導体層を再成長させて形成する際、電子伝導領域の結晶性が悪くなってしまうような場合であっても、非常に高濃度に不純物をドープし、低抵抗化すればよい。
なお、電子走行層の場合には、非常に高濃度に不純物をドープして低抵抗化することは難しいため、結晶性が良好なものが必要とされるのである。
電子伝導領域１０８の形成後、リフトオフ工程によりソース電極１０９とドレイン電極１１０とを形成する（工程（ｄ），（ｅ））。これらソース電極１０９とドレイン電極１１０は、それぞれ、電子供給層１０７と高濃度ｎ型半導体層１０３とにオーミック接触する。より具体的には、ドライエッチングにより高濃度ｎ型半導体層１０３の上面の一部を露出させて、ドレイン電極１１０が形成されるべき領域を形成する。次いで、フォトリソグラフィを用いて積層構造上にレジストパターンを形成し、その後、スパッタ法によりレジストパターンと積層構造の上に金属層を成膜する。その後、レジストパターンと当該レジストパターン上の金属材料とを同時に除去することで、ソース電極１０９とドレイン電極１１０の各電極パターンを形成することができる。 Alternatively, the electronconductive region 108 may be formed by re-growing a compound semiconductor layer such as an n-type GaN layer on the etched surface of the stacked structure by the MOVPE method or the MBE method.
Even when theelectron conduction region 108 is formed by re-growing the compound semiconductor layer, even if the crystallinity of the electron conduction region is deteriorated, impurities are doped at a very high concentration to reduce the resistance. do it.
In the case of an electron transit layer, it is difficult to reduce the resistance by doping impurities at a very high concentration, so that a layer with good crystallinity is required.
After the formation of theelectron conduction region 108, the source electrode 109 and the drain electrode 110 are formed by a lift-off process (steps (d) and (e)). The source electrode 109 and the drain electrode 110 are in ohmic contact with the electron supply layer 107 and the high-concentration n-type semiconductor layer 103, respectively. More specifically, a part of the upper surface of the high-concentration n-type semiconductor layer 103 is exposed by dry etching to form a region where the drain electrode 110 is to be formed. Next, a resist pattern is formed on the stacked structure using photolithography, and then a metal layer is formed on the resist pattern and the stacked structure by sputtering. Thereafter, the electrode pattern of the source electrode 109 and the drain electrode 110 can be formed by removing the resist pattern and the metal material on the resist pattern at the same time.
電子伝導領域１０８を、化合物半導体層を再成長させて形成する際、電子伝導領域の結晶性が悪くなってしまうような場合であっても、非常に高濃度に不純物をドープし、低抵抗化すればよい。
なお、電子走行層の場合には、非常に高濃度に不純物をドープして低抵抗化することは難しいため、結晶性が良好なものが必要とされるのである。
電子伝導領域１０８の形成後、リフトオフ工程によりソース電極１０９とドレイン電極１１０とを形成する（工程（ｄ），（ｅ））。これらソース電極１０９とドレイン電極１１０は、それぞれ、電子供給層１０７と高濃度ｎ型半導体層１０３とにオーミック接触する。より具体的には、ドライエッチングにより高濃度ｎ型半導体層１０３の上面の一部を露出させて、ドレイン電極１１０が形成されるべき領域を形成する。次いで、フォトリソグラフィを用いて積層構造上にレジストパターンを形成し、その後、スパッタ法によりレジストパターンと積層構造の上に金属層を成膜する。その後、レジストパターンと当該レジストパターン上の金属材料とを同時に除去することで、ソース電極１０９とドレイン電極１１０の各電極パターンを形成することができる。 Alternatively, the electron
Even when the
In the case of an electron transit layer, it is difficult to reduce the resistance by doping impurities at a very high concentration, so that a layer with good crystallinity is required.
After the formation of the
ソース電極１０９とドレイン電極１１０の各々は、タングステン（Ｗ）、モリブデン（Ｍｏ）、シリコン（Ｓｉ）、チタン（Ｔｉ）、白金（Ｐｔ）、ニオブ（Ｎｂ）、アルミニウム（Ａｌ）または金（Ａｕ）などの金属材料からなるものであればよく、複数の金属層を積層した構造を有していてもよい。
Each of the source electrode 109 and the drain electrode 110 includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), or gold (Au). As long as it is made of a metal material, it may have a structure in which a plurality of metal layers are laminated.
その後、積層構造全面を被覆するように絶縁膜を形成し、この絶縁膜をパターニングして図２に示すような開口部を持つ絶縁膜１１１を形成する。さらに、この絶縁膜１１１をマスクとして電子供給層１０７にドライエッチングを施すことにより電子供給層１０７に溝を形成する。そして、電子供給層１０７の溝と絶縁膜１１１の開口部とにゲート電極１１２を埋め込む（工程（ｇ））。
Thereafter, an insulating film is formed so as to cover the entire surface of the laminated structure, and this insulating film is patterned to form an insulating film 111 having an opening as shown in FIG. Further, a groove is formed in the electron supply layer 107 by dry etching the electron supply layer 107 using the insulating film 111 as a mask. Then, the gate electrode 112 is embedded in the groove of the electron supply layer 107 and the opening of the insulating film 111 (step (g)).
この結果、図２に示すようにＴ字状の断面形状を有するゲート電極１１２が形成される。すなわち、このゲート電極１１２は、絶縁膜１１１の開口部を介して電子供給層１０７の溝に挿入された部分と、絶縁膜１１１の開口部から横方向へ延在する庇部分とを有している。図２に示されるように、ゲート電極１１２のうち絶縁膜１１１の開口部から電子伝導領域１０８の方向へ延在する庇部分は、ゲート電極１１２のうち当該開口部からソース電極１０９の方向へ延在する庇部分よりも長い。これにより、ゲート電極１１２の近傍の電界集中を緩和することができ、耐圧の向上が可能である。
As a result, a gate electrode 112 having a T-shaped cross section as shown in FIG. 2 is formed. That is, the gate electrode 112 has a portion inserted into the groove of the electron supply layer 107 through the opening of the insulating film 111 and a flange portion extending in the lateral direction from the opening of the insulating film 111. Yes. As shown in FIG. 2, a flange portion of the gate electrode 112 extending from the opening of the insulating film 111 toward the electron conduction region 108 extends from the opening of the gate electrode 112 toward the source electrode 109. It is longer than the existing heel part. Thereby, the electric field concentration in the vicinity of the gate electrode 112 can be relaxed, and the breakdown voltage can be improved.
本実施形態では、好適な構成として、ゲート電極１１２の電子伝導領域１０８側の庇部分の長さが、ゲート電極１１２のソース電極１０９側の庇部分よりも長い構成を採用したが、これに限定されるものではない。ゲート電極１１２の電子伝導領域１０８側の庇部分とゲート電極１１２のソース電極１０９側の庇部分とが等しい、あるいは、ゲート電極１１２の電子伝導領域１０８側の庇部分がゲート電極１１２のソース電極１０９側の庇部分よりも短い形態もあり得る。ただし、ゲート電極１１２の電子伝導領域１０８側の庇部分と比べて、ゲート電極１１２のソース電極１０９側の庇部分が長すぎると、耐圧の向上や電流コラプス低減の効果に対し、ゲート容量の増大による利得低下が大きくなる。
In the present embodiment, as a preferred configuration, a configuration is adopted in which the length of the flange portion of the gate electrode 112 on the electron conduction region 108 side is longer than the flange portion of the gate electrode 112 on the source electrode 109 side. Is not to be done. The heel portion of the gate electrode 112 on the electron conducting region 108 side is equal to the heel portion of the gate electrode 112 on the source electrode 109 side, or the heel portion of the gate electrode 112 on the electron conducting region 108 side is the source electrode 109 of the gate electrode 112. There may also be a form that is shorter than the side collar. However, if the ridge portion on the source electrode 109 side of the gate electrode 112 is too long compared to the ridge portion on the electron conduction region 108 side of the gate electrode 112, the gate capacitance increases for the effect of improving the breakdown voltage and reducing the current collapse. The gain reduction due to is increased.
ゲート電極１１２は、Ｗ、Ｍｏ、Ｓｉ、Ｔｉ、Ｐｔ、Ｎｂ、ＡｌまたはＡｕなどの金属材料からなるものであればよく、複数の金属層を積層した構造を有していてもよい。ゲート電極１１２は、金属材料の代わりに、下地の電子供給層１０７にショットキ接触する半導体材料を用いて形成されてもよい。ただし、この半導体材料は、絶縁膜１１１や保護膜１１３と反応しない材料であることが望ましい。
The gate electrode 112 may be made of a metal material such as W, Mo, Si, Ti, Pt, Nb, Al, or Au, and may have a structure in which a plurality of metal layers are stacked. The gate electrode 112 may be formed using a semiconductor material that is in Schottky contact with the base electron supply layer 107 instead of a metal material. However, this semiconductor material is preferably a material that does not react with the insulating film 111 and the protective film 113.
上記ゲート電極１１２の形成後、ＣＶＤ法により、積層構造上にゲート電極１１２を被覆する保護膜１１３を形成する（工程（ｈ））。上記絶縁膜１１１と保護膜１１３は、たとえば、シリコン（Ｓｉ）、マグネシウム（Ｍｇ）、ハフニウム（Ｈｆ）、アルミニウム（Ａｌ）、チタン（Ｔｉ）およびタンタル（Ｔａ）よりなる群から選択された１種または２種以上の酸化物または窒化物で構成すればよい。酸化物または窒化物などの無機化合物の代わりに、保護膜１１３が有機絶縁物で構成されてもよい。
After the formation of the gate electrode 112, a protective film 113 that covers the gate electrode 112 is formed on the stacked structure by a CVD method (step (h)). The insulating film 111 and the protective film 113 are, for example, one selected from the group consisting of silicon (Si), magnesium (Mg), hafnium (Hf), aluminum (Al), titanium (Ti), and tantalum (Ta). Or what is necessary is just to comprise by 2 or more types of oxides or nitrides. Instead of an inorganic compound such as oxide or nitride, the protective film 113 may be formed of an organic insulator.
上記第１の実施形態の電界効果トランジスタ１０の製造方法が奏する効果は以下の通りである。
第１の実施形態の製造方法は、基板１０１上で電子障壁層１０５と電子走行層１０６を連続的にエピタキシャル成長させ、その後に、ゲート電極１１２の側方であってソース電極１０９から離れた位置にエッチング加工面を形成し、このエッチング加工面に電子伝導領域１０８を形成する。言い換えれば、電子障壁層１０５と電子走行層１０６とをエピタキシャル成長させた後に、これら電子障壁層１０５と電子走行層１０６の一部をエッチングし、その加工面上に電子走行層を再成長させるという製造工程を行わずに、ソース電極１０９からの注入電子が縦方向へ移動できる経路（電子伝導領域）１０８を形成することが可能である。よって、電子走行層１０６は、他の層とともに連続してエピタキシャル成長したものであり、成長を止めてフォトリソグラフィやドライエッチングなどのプロセス工程を経た後、再成長させたものはないので、結晶性の良好な電子走行層１０６とすることができ、この電子走行層１０６と電子供給層１０７とのヘテロ接合界面およびその近傍での電子移動度が高く、チャネル領域の抵抗（チャネル抵抗）が低い電界効果トランジスタ１０を作製することができる。 The effects produced by the method of manufacturing thefield effect transistor 10 of the first embodiment are as follows.
In the manufacturing method of the first embodiment, theelectron barrier layer 105 and the electron transit layer 106 are continuously epitaxially grown on the substrate 101, and then, at a position on the side of the gate electrode 112 and away from the source electrode 109. An etched surface is formed, and an electron conduction region 108 is formed on the etched surface. In other words, after the electron barrier layer 105 and the electron transit layer 106 are epitaxially grown, a part of the electron barrier layer 105 and the electron transit layer 106 is etched, and the electron transit layer is regrown on the processed surface. Without performing the process, it is possible to form a path (electron conduction region) 108 through which electrons injected from the source electrode 109 can move in the vertical direction. Therefore, the electron transit layer 106 is continuously epitaxially grown together with other layers, and since there is no regrowth after stopping the growth and undergoing a process step such as photolithography or dry etching, the crystalline layer is crystalline. A good electron transit layer 106 can be obtained, and an electric field effect in which the electron mobility at and near the heterojunction interface between the electron transit layer 106 and the electron supply layer 107 is high and the resistance (channel resistance) of the channel region is low. The transistor 10 can be manufactured.
第１の実施形態の製造方法は、基板１０１上で電子障壁層１０５と電子走行層１０６を連続的にエピタキシャル成長させ、その後に、ゲート電極１１２の側方であってソース電極１０９から離れた位置にエッチング加工面を形成し、このエッチング加工面に電子伝導領域１０８を形成する。言い換えれば、電子障壁層１０５と電子走行層１０６とをエピタキシャル成長させた後に、これら電子障壁層１０５と電子走行層１０６の一部をエッチングし、その加工面上に電子走行層を再成長させるという製造工程を行わずに、ソース電極１０９からの注入電子が縦方向へ移動できる経路（電子伝導領域）１０８を形成することが可能である。よって、電子走行層１０６は、他の層とともに連続してエピタキシャル成長したものであり、成長を止めてフォトリソグラフィやドライエッチングなどのプロセス工程を経た後、再成長させたものはないので、結晶性の良好な電子走行層１０６とすることができ、この電子走行層１０６と電子供給層１０７とのヘテロ接合界面およびその近傍での電子移動度が高く、チャネル領域の抵抗（チャネル抵抗）が低い電界効果トランジスタ１０を作製することができる。 The effects produced by the method of manufacturing the
In the manufacturing method of the first embodiment, the
また、ゲート電極１１２とドレイン電極１１０間に高電圧を印加して電界効果トランジスタ１０を動作させたとき、電界効果トランジスタ１０は電子伝導領域１０８を介して縦方向にキャリアが流れる構造を有するため、電子供給層１０７と絶縁膜１１１との界面に生じた固定電荷の影響を受けることなく、キャリアの移動経路における局所的な電界集中を抑制することができる。これにより、耐圧の向上が可能となる。また、ＧａＮの絶縁破壊耐圧の物性値（＝約３．３×１０６Ｖ／ｃｍ）に近い最大電界強度を期待することが可能である。
Further, when the field effect transistor 10 is operated by applying a high voltage between the gate electrode 112 and the drain electrode 110, the field effect transistor 10 has a structure in which carriers flow in the vertical direction through the electron conduction region 108. Local electric field concentration in the carrier movement path can be suppressed without being affected by the fixed charges generated at the interface between the electron supply layer 107 and the insulating film 111. Thereby, the breakdown voltage can be improved. In addition, it is possible to expect a maximum electric field strength close to a physical property value of dielectric breakdown voltage of GaN (= about 3.3 × 10 6 V / cm).
さらに、上述の通り、ゲート電極１１２の電子伝導領域１０８側の庇部分は、ゲート電極１１２のソース電極１０９側の庇部分よりも長いので、ゲート電極１１２の近傍の電界集中を緩和することができ、耐圧の向上が可能となる。また、チャネル領域における局所的な電界集中が抑制され、電位変動が抑制されるので、電流コラプスのさらなる抑制が可能である。
Furthermore, as described above, since the ridge portion of the gate electrode 112 on the electron conduction region 108 side is longer than the ridge portion of the gate electrode 112 on the source electrode 109 side, electric field concentration in the vicinity of the gate electrode 112 can be reduced. The breakdown voltage can be improved. In addition, since local electric field concentration in the channel region is suppressed and potential fluctuation is suppressed, current collapse can be further suppressed.
（第１の実施形態の変形例）
図３は、上記第１の実施形態の変形例である電界効果トランジスタ１０Ａの断面構造を概略的に示す断面図である。この電界効果トランジスタ１０Ａは、電子伝導領域１０８のドリフト層１０４と反対側に電位制御絶縁膜（絶縁膜）１１４を介して電位制御電極１１５が形成されている。
電位制御絶縁膜１１４としては、アルミ、珪素、ハフニウム、ジルコニウム、タンタル、チタンのうち少なくとも１種と、酸素と窒素のうち少なくとも１種を含むことが好ましい。
なかでも、後述する容量Ｃ１を大きく確保する観点から、電位制御絶縁膜１１６は誘電率が６以上であることが好ましい。
たとえば、電位制御絶縁膜１１６としては、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、酸化タンタル、酸化チタン等を使用することが好ましい。
また、電位制御絶縁膜１１６の厚みは、絶縁膜の絶縁破壊防止の観点から、１０ｎｍ以上であることが好ましい。また、容量Ｃ１が小さくなることを抑制するために、４００ｎｍ以下であることが好ましい。 (Modification of the first embodiment)
FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure of afield effect transistor 10A, which is a modification of the first embodiment. In this field effect transistor 10A, a potential control electrode 115 is formed on the opposite side of the electron conduction region 108 from the drift layer 104 via a potential control insulating film (insulating film) 114.
The potentialcontrol insulating film 114 preferably contains at least one of aluminum, silicon, hafnium, zirconium, tantalum, and titanium and at least one of oxygen and nitrogen.
In particular, the potential control insulating film 116 preferably has a dielectric constant of 6 or more from the viewpoint of securing a large capacitance C1 described later.
For example, as the potential control insulating film 116, it is preferable to use aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, or the like.
The thickness of the potential control insulating film 116 is preferably 10 nm or more from the viewpoint of preventing dielectric breakdown of the insulating film. Moreover, in order to suppress that the capacity | capacitance C1 becomes small, it is preferable that it is 400 nm or less.
図３は、上記第１の実施形態の変形例である電界効果トランジスタ１０Ａの断面構造を概略的に示す断面図である。この電界効果トランジスタ１０Ａは、電子伝導領域１０８のドリフト層１０４と反対側に電位制御絶縁膜（絶縁膜）１１４を介して電位制御電極１１５が形成されている。
電位制御絶縁膜１１４としては、アルミ、珪素、ハフニウム、ジルコニウム、タンタル、チタンのうち少なくとも１種と、酸素と窒素のうち少なくとも１種を含むことが好ましい。
なかでも、後述する容量Ｃ１を大きく確保する観点から、電位制御絶縁膜１１６は誘電率が６以上であることが好ましい。
たとえば、電位制御絶縁膜１１６としては、酸化アルミニウム、酸化ハフニウム、酸化ジルコニウム、酸化タンタル、酸化チタン等を使用することが好ましい。
また、電位制御絶縁膜１１６の厚みは、絶縁膜の絶縁破壊防止の観点から、１０ｎｍ以上であることが好ましい。また、容量Ｃ１が小さくなることを抑制するために、４００ｎｍ以下であることが好ましい。 (Modification of the first embodiment)
FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure of a
The potential
In particular, the potential control insulating film 116 preferably has a dielectric constant of 6 or more from the viewpoint of securing a large capacitance C1 described later.
For example, as the potential control insulating film 116, it is preferable to use aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, or the like.
The thickness of the potential control insulating film 116 is preferably 10 nm or more from the viewpoint of preventing dielectric breakdown of the insulating film. Moreover, in order to suppress that the capacity | capacitance C1 becomes small, it is preferable that it is 400 nm or less.
この変形例のように、電位制御電極１１５を有する電解トランジスタでは、電子伝導領域１０８が金属的な材料である場合、ピンチオフ時には電流が流れないため、電子伝導領域１０８の電位は電位制御電極１１５と電子伝導領域間１０８の容量Ｃ１と電子伝導領域１０８と高濃度ｎ型半導体層１０３の容量Ｃ２との比で決まる。例えば、電位制御電極１１５を接地すなわち0Vととし、ドレイン電圧と等しい電位となる高濃度ｎ型半導体層１０２の電位をVdとした場合、電子伝導領域１０８の電位Vcは、Vc=C2Vd/(C1-C2)であらわされる。すなわち電位制御電極１１５と電子伝導領域１０８と間の容量C1を、電子伝導領域１０８と高濃度ｎ型半導体層１０３間の容量C2に対し大きな値とすることで、電子伝導領域１０８の電位Vcはドレイン電圧Vdと比較して格段に低い電位にすることができる。
電子伝導領域１０８の電位Ｖｃをドレイン電圧Ｖｄよりも低くした場合、ドリフト層１０４で電圧降下が起きると考えられる（なお、高濃度ｎ型半導体層１０３の電位は、ドレイン電圧Ｖｄと略同じ程度である）。
従って、ドリフト層１０４にて電界を集中させることができ、ゲート電極のドレイン端への電界集中を抑制することができることからオフ耐圧を向上することができる。電子伝導領域が半導体材料で形成されている場合にも、電子伝導領域１０８の電位制御絶縁膜１１４側の電位をVcとみなすことができ、同様の効果が期待できる。
なお、電位制御電極をゲート電極と接続させた場合も同様にオフ耐圧を向上することができる。更にオン抵抗を低減する効果もあるが、一方でゲート容量の増大により利得が低下する可能性もある。
なお、電位制御絶縁膜１１４、電位制御電極１１５は、電子伝導領域１０８を形成した後に形成すればよい。すなわち、電子伝導領域１０８を形成した後に、電位制御絶縁膜１１４を形成し、その後、電位制御絶縁膜１１４上に電位制御電極１１５を形成すればよい。その後、電位制御電極１１５を接地し、または、ゲート電極と接続すればよい。 In the electrolytic transistor having thepotential control electrode 115 as in this modification, when the electron conduction region 108 is a metallic material, no current flows at the time of pinch-off, so the potential of the electron conduction region 108 is different from that of the potential control electrode 115. It is determined by the ratio of the capacitance C1 between the electron conduction regions 108, the electron conduction region 108, and the capacitance C2 of the high-concentration n-type semiconductor layer 103. For example, when the potential control electrode 115 is grounded, that is, 0 V, and the potential of the high-concentration n-type semiconductor layer 102 that is equal to the drain voltage is Vd, the potential Vc of the electron conduction region 108 is Vc = C2Vd / (C1 -C2). That is, by setting the capacitance C1 between the potential control electrode 115 and the electron conduction region 108 to a value larger than the capacitance C2 between the electron conduction region 108 and the high-concentration n-type semiconductor layer 103, the potential Vc of the electron conduction region 108 is The potential can be made much lower than the drain voltage Vd.
When the potential Vc of theelectron conduction region 108 is lower than the drain voltage Vd, it is considered that a voltage drop occurs in the drift layer 104 (note that the potential of the high concentration n-type semiconductor layer 103 is approximately the same as the drain voltage Vd. is there).
Accordingly, the electric field can be concentrated in thedrift layer 104, and the concentration of the electric field on the drain end of the gate electrode can be suppressed, so that the off breakdown voltage can be improved. Even when the electron conduction region is formed of a semiconductor material, the potential on the potential control insulating film 114 side of the electron conduction region 108 can be regarded as Vc, and the same effect can be expected.
Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved. Furthermore, there is an effect of reducing the on-resistance, but on the other hand, there is a possibility that the gain is lowered due to an increase in the gate capacitance.
Note that the potentialcontrol insulating film 114 and the potential control electrode 115 may be formed after the electron conduction region 108 is formed. That is, the potential control insulating film 114 is formed after the electron conduction region 108 is formed, and then the potential control electrode 115 is formed on the potential control insulating film 114. Thereafter, the potential control electrode 115 may be grounded or connected to the gate electrode.
電子伝導領域１０８の電位Ｖｃをドレイン電圧Ｖｄよりも低くした場合、ドリフト層１０４で電圧降下が起きると考えられる（なお、高濃度ｎ型半導体層１０３の電位は、ドレイン電圧Ｖｄと略同じ程度である）。
従って、ドリフト層１０４にて電界を集中させることができ、ゲート電極のドレイン端への電界集中を抑制することができることからオフ耐圧を向上することができる。電子伝導領域が半導体材料で形成されている場合にも、電子伝導領域１０８の電位制御絶縁膜１１４側の電位をVcとみなすことができ、同様の効果が期待できる。
なお、電位制御電極をゲート電極と接続させた場合も同様にオフ耐圧を向上することができる。更にオン抵抗を低減する効果もあるが、一方でゲート容量の増大により利得が低下する可能性もある。
なお、電位制御絶縁膜１１４、電位制御電極１１５は、電子伝導領域１０８を形成した後に形成すればよい。すなわち、電子伝導領域１０８を形成した後に、電位制御絶縁膜１１４を形成し、その後、電位制御絶縁膜１１４上に電位制御電極１１５を形成すればよい。その後、電位制御電極１１５を接地し、または、ゲート電極と接続すればよい。 In the electrolytic transistor having the
When the potential Vc of the
Accordingly, the electric field can be concentrated in the
Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved. Furthermore, there is an effect of reducing the on-resistance, but on the other hand, there is a possibility that the gain is lowered due to an increase in the gate capacitance.
Note that the potential
（第２の実施形態）
次に、本発明に係る第２の実施形態について説明する。図４は、第２の実施形態の電界効果トランジスタ２０の断面構造を概略的に示す図である。この電界効果トランジスタ２０は、基板２０１上に、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７がこの順に積層された積層構造を有している。この積層構造上には絶縁膜２１１が形成されている。電子供給層２０７上において絶縁膜２１１に形成された開口部にゲート電極２１２が形成されている。 (Second Embodiment)
Next, a second embodiment according to the present invention will be described. FIG. 4 is a diagram schematically showing a cross-sectional structure of thefield effect transistor 20 of the second embodiment. The field effect transistor 20 has a stacked structure in which a high-concentration n-type semiconductor layer 203, a drift layer 204, an electron barrier layer 205, an electron transit layer 206, and an electron supply layer 207 are stacked in this order on a substrate 201. Yes. An insulating film 211 is formed on the laminated structure. A gate electrode 212 is formed in the opening formed in the insulating film 211 on the electron supply layer 207.
次に、本発明に係る第２の実施形態について説明する。図４は、第２の実施形態の電界効果トランジスタ２０の断面構造を概略的に示す図である。この電界効果トランジスタ２０は、基板２０１上に、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７がこの順に積層された積層構造を有している。この積層構造上には絶縁膜２１１が形成されている。電子供給層２０７上において絶縁膜２１１に形成された開口部にゲート電極２１２が形成されている。 (Second Embodiment)
Next, a second embodiment according to the present invention will be described. FIG. 4 is a diagram schematically showing a cross-sectional structure of the
ゲート電極２１２の左右両側（基板面に平行な方向における両側）のうちの一方の側では、キャリアである電子が縦方向に流れる電子伝導領域２０８が積層構造に形成されている。この電子伝導領域２０８は、電子走行層２０６の一端から、ｐ型電子障壁層２０５よりも基板２０１側の領域に延在するように設けられている。ゲート電極２１２の左右両側のうちの他方の側では、電子供給層２０７上にソース電極２０９が形成されている。また、基板２０１の裏面にはドレイン電極２１０が形成されており、このドレイン電極２１０は、基板２０１、高濃度ｎ型半導体層２０３およびドリフト層２０４を介して電子伝導領域２０８の一端と電気的に接続される。
電子走行層２０６の上面は、電子供給層２０７にヘテロ接合されており、電界効果トランジスタ２０の動作時には、そのヘテロ接合界面およびその近傍に２次元電子ガスのチャネル領域が形成される。このとき、ソース電極２０９から注入された電子は、チャネル領域と電子伝導領域２０８とを介してドレイン電極２１０へ移動することができる。 On one side of the left and right sides of the gate electrode 212 (both sides in the direction parallel to the substrate surface), anelectron conduction region 208 in which electrons as carriers flow in the vertical direction is formed in a stacked structure. The electron conduction region 208 is provided so as to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the p-type electron barrier layer 205. A source electrode 209 is formed on the electron supply layer 207 on the other of the left and right sides of the gate electrode 212. A drain electrode 210 is formed on the back surface of the substrate 201, and the drain electrode 210 is electrically connected to one end of the electron conduction region 208 through the substrate 201, the high concentration n-type semiconductor layer 203 and the drift layer 204. Connected.
The upper surface of theelectron transit layer 206 is heterojunction to the electron supply layer 207, and when the field effect transistor 20 is operated, a channel region of two-dimensional electron gas is formed at and near the heterojunction interface. At this time, electrons injected from the source electrode 209 can move to the drain electrode 210 through the channel region and the electron conduction region 208.
電子走行層２０６の上面は、電子供給層２０７にヘテロ接合されており、電界効果トランジスタ２０の動作時には、そのヘテロ接合界面およびその近傍に２次元電子ガスのチャネル領域が形成される。このとき、ソース電極２０９から注入された電子は、チャネル領域と電子伝導領域２０８とを介してドレイン電極２１０へ移動することができる。 On one side of the left and right sides of the gate electrode 212 (both sides in the direction parallel to the substrate surface), an
The upper surface of the
上記電界効果トランジスタ２０の製造方法は、下記（ａ）～（ｈ）の基本工程を有するものである。
（ａ）基板２０１上に、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７をそれぞれ構成する複数の化合物半導体層をこの順に含む積層構造を連続的にエピタキシャル成長させる工程。
（ｂ）ゲート電極２１２が形成される領域の左右両側のうちの一方の側（ゲート電極２１２が形成される領域の側方）で、積層構造をエッチングして、電子走行層２０６の一端から電子障壁層２０５よりも基板２０１側の領域に亘ってエッチング加工面を形成する工程。
（ｃ）当該エッチング加工面に電子伝導領域２０８を形成する工程。
（ｄ）ゲート電極２１２が形成される領域の当該左右両側のうちの他方の側（ゲート電極２１２が形成される領域の側方であって、電子伝導領域２０８が形成される側と反対側）における電子走行層２０６上に電子供給層２０７を介してソース電極２０９を形成する工程。
（ｅ）基板２０１の裏面にドレイン電極２１０を形成する工程。
（ｆ）パターニングされた絶縁膜２１１を形成する工程。
（ｇ）電子走行層２０６上における絶縁膜２１１の開口部にゲート電極２１２を形成する工程。
（ｈ）ソース電極２０９を除く素子全体を被覆する保護膜２１３を形成する工程。
なお、工程（ｄ）は、工程（ｂ）の前段で実施してもよい。 The manufacturing method of thefield effect transistor 20 includes the following basic steps (a) to (h).
(A) A laminated structure including a plurality of compound semiconductor layers in this order on thesubstrate 201, each of which constitutes a high-concentration n-type semiconductor layer 203, a drift layer 204, an electron barrier layer 205, an electron transit layer 206, and an electron supply layer 207. Continuous epitaxial growth process.
(B) The stacked structure is etched on one side of the left and right sides of the region where thegate electrode 212 is formed (side of the region where the gate electrode 212 is formed), and electrons are transmitted from one end of the electron transit layer 206. Forming an etched surface over a region closer to the substrate 201 than the barrier layer 205;
(C) A step of forming an electronconductive region 208 on the etched surface.
(D) The other side of the left and right sides of the region where thegate electrode 212 is formed (on the side of the region where the gate electrode 212 is formed and opposite to the side where the electron conduction region 208 is formed) Forming a source electrode 209 via an electron supply layer 207 on the electron transit layer 206 in FIG.
(E) A step of forming thedrain electrode 210 on the back surface of the substrate 201.
(F) A step of forming a patternedinsulating film 211.
(G) A step of forming thegate electrode 212 in the opening of the insulating film 211 on the electron transit layer 206.
(H) A step of forming aprotective film 213 that covers the entire element except the source electrode 209.
In addition, you may implement a process (d) in the front | former stage of a process (b).
（ａ）基板２０１上に、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７をそれぞれ構成する複数の化合物半導体層をこの順に含む積層構造を連続的にエピタキシャル成長させる工程。
（ｂ）ゲート電極２１２が形成される領域の左右両側のうちの一方の側（ゲート電極２１２が形成される領域の側方）で、積層構造をエッチングして、電子走行層２０６の一端から電子障壁層２０５よりも基板２０１側の領域に亘ってエッチング加工面を形成する工程。
（ｃ）当該エッチング加工面に電子伝導領域２０８を形成する工程。
（ｄ）ゲート電極２１２が形成される領域の当該左右両側のうちの他方の側（ゲート電極２１２が形成される領域の側方であって、電子伝導領域２０８が形成される側と反対側）における電子走行層２０６上に電子供給層２０７を介してソース電極２０９を形成する工程。
（ｅ）基板２０１の裏面にドレイン電極２１０を形成する工程。
（ｆ）パターニングされた絶縁膜２１１を形成する工程。
（ｇ）電子走行層２０６上における絶縁膜２１１の開口部にゲート電極２１２を形成する工程。
（ｈ）ソース電極２０９を除く素子全体を被覆する保護膜２１３を形成する工程。
なお、工程（ｄ）は、工程（ｂ）の前段で実施してもよい。 The manufacturing method of the
(A) A laminated structure including a plurality of compound semiconductor layers in this order on the
(B) The stacked structure is etched on one side of the left and right sides of the region where the
(C) A step of forming an electron
(D) The other side of the left and right sides of the region where the
(E) A step of forming the
(F) A step of forming a patterned
(G) A step of forming the
(H) A step of forming a
In addition, you may implement a process (d) in the front | former stage of a process (b).
基板２０１として、本実施形態では、ＧａＮやＡｌＮなどからなる導電性のIII族窒化物系化合物半導体基板を使用するが、これに限定されるものではない。たとえば、炭化シリコン基板またはシリコン基板を基板２０１に使用してもよい。この基板２０１上には、有機金属気相成長（ＭＯＶＰＥ）法や分子線エピタキシャル成長（ＭＢＥ）法により、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７をそれぞれ構成する複数の化合物半導体層を連続的に成長させる。
複数の化合物半導体層を連続的に成長させるとは、バッファ層２０２の成長工程、高濃度ｎ型半導体層２０３の成長工程、ドリフト層２０４の成長工程、電子障壁層２０５の成長工程、電子走行層２０６の成長工程および電子供給層２０７の成長工程の一連の成長工程を連続して実施することである。すなわち、積層順に各層を連続してエピタキシャル成長させることであり、各層の成長工程の途中で、成長を止め、フォトリソグラフィやドライエッチングなどのプロセス工程を経た後、再成長することは実施しない。なかでも、各層を同一装置内で連続成長させることが好ましい。
高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７は、それぞれ、第１の実施形態の高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子走行層１０６および電子供給層１０７と同じ料および組成で構成すればよい。電子走行層２０６内の不純物濃度が高くなり過ぎると、クーロン散乱の影響が大きくなり、電子移動度が低下するため、不純物濃度は１×１０１７ｃｍ－３以下であることが望ましい。また、電子供給層２０７から電子走行層２０６へ電子が供給されるために、電子供給層２０７は、電子走行層２０６よりも小さな電子親和力を持つ材料または組成からなる。 In this embodiment, a conductive group III nitride compound semiconductor substrate made of GaN, AlN, or the like is used as thesubstrate 201. However, the substrate 201 is not limited to this. For example, a silicon carbide substrate or a silicon substrate may be used for the substrate 201. On this substrate 201, a high-concentration n-type semiconductor layer 203, a drift layer 204, an electron barrier layer 205, an electron transit layer 206, and an electron supply are formed by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). A plurality of compound semiconductor layers constituting each of the layers 207 are continuously grown.
Growing a plurality of compound semiconductor layers continuously means a growth process of the buffer layer 202, a growth process of the high-concentration n-type semiconductor layer 203, a growth process of the drift layer 204, a growth process of the electron barrier layer 205, an electron transit layer A series of growth steps of the growth step 206 and the growth step of the electron supply layer 207 are continuously performed. That is, each layer is continuously epitaxially grown in the stacking order, and the growth is stopped in the middle of the growth process of each layer, and after the process steps such as photolithography and dry etching, the regrowth is not performed. Among these, it is preferable that each layer is continuously grown in the same apparatus.
The high-concentration n-type semiconductor layer 203, the drift layer 204, the electron barrier layer 205, the electron transit layer 206, and the electron supply layer 207 are respectively the high-concentration n-type semiconductor layer 103, the drift layer 104, and the electron barrier in the first embodiment. What is necessary is just to comprise with the same material and composition as the layer 105, the electron transit layer 106, and the electron supply layer 107. If the impurity concentration in the electron transit layer 206 becomes too high, the influence of Coulomb scattering increases and the electron mobility decreases. Therefore, the impurity concentration is preferably 1 × 10 17 cm −3 or less. In addition, since electrons are supplied from the electron supply layer 207 to the electron transit layer 206, the electron supply layer 207 is made of a material or composition having a smaller electron affinity than the electron transit layer 206.
複数の化合物半導体層を連続的に成長させるとは、バッファ層２０２の成長工程、高濃度ｎ型半導体層２０３の成長工程、ドリフト層２０４の成長工程、電子障壁層２０５の成長工程、電子走行層２０６の成長工程および電子供給層２０７の成長工程の一連の成長工程を連続して実施することである。すなわち、積層順に各層を連続してエピタキシャル成長させることであり、各層の成長工程の途中で、成長を止め、フォトリソグラフィやドライエッチングなどのプロセス工程を経た後、再成長することは実施しない。なかでも、各層を同一装置内で連続成長させることが好ましい。
高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子走行層２０６および電子供給層２０７は、それぞれ、第１の実施形態の高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子走行層１０６および電子供給層１０７と同じ料および組成で構成すればよい。電子走行層２０６内の不純物濃度が高くなり過ぎると、クーロン散乱の影響が大きくなり、電子移動度が低下するため、不純物濃度は１×１０１７ｃｍ－３以下であることが望ましい。また、電子供給層２０７から電子走行層２０６へ電子が供給されるために、電子供給層２０７は、電子走行層２０６よりも小さな電子親和力を持つ材料または組成からなる。 In this embodiment, a conductive group III nitride compound semiconductor substrate made of GaN, AlN, or the like is used as the
Growing a plurality of compound semiconductor layers continuously means a growth process of the buffer layer 202, a growth process of the high-concentration n-
The high-concentration n-
電子伝導領域２０８は、基板面側からの平面視において、ゲート電極２１２を挟んでソース電極２０９と反対側に位置する。
本実施形態では、電子伝導領域２０８と同様の構成であるが、電子供給層２０７側からドリフト層２０４側に延在し、一方の端部が、電子供給層２０７および電子走行層２０６に接し、他方の端部が電子障壁層よりも基板側に位置する領域（本実施形態では、ドリフト層２０３）に接している。より詳細に説明すると、電子伝導領域２０８は、電子供給層２０７、電子走行層２０６、電子障壁層２０５、ドリフト層２０４に接して設けられている。電子伝導領域２０８は、ドリフト層２０４の厚みの途中位置まで形成されている。
電子伝導領域２０８は、上記第１の実施形態の電子伝導領域１０８とほぼ同じ製造工程を用いて形成することができる。すなわち、電子伝導領域２０８は、積層構造に形成されたエッチング加工面から積層構造内にｎ型不純物を拡散させることで形成される。この代わりに、積層構造表面からドリフト層２０４の領域に達する深さまで、積層構造内にｎ型不純物をイオン注入し熱処理を施すことにより電子伝導領域２０８を形成してもよい。イオン注入の際の加速電圧は、ｎ型不純物イオンの打ち込み深さがドリフト層２０４に達するように制御される。なお、第１の実施形態においても、積層構造内にｎ型不純物をイオン注入し熱処理を施すことにより電子伝導領域１０８を形成してもよい。 Theelectron conduction region 208 is located on the opposite side of the source electrode 209 across the gate electrode 212 in plan view from the substrate surface side.
In this embodiment, the configuration is the same as that of theelectron conduction region 208, but extends from the electron supply layer 207 side to the drift layer 204 side, and one end thereof is in contact with the electron supply layer 207 and the electron transit layer 206, The other end is in contact with a region (in this embodiment, the drift layer 203) located closer to the substrate than the electron barrier layer. More specifically, the electron conduction region 208 is provided in contact with the electron supply layer 207, the electron transit layer 206, the electron barrier layer 205, and the drift layer 204. The electron conduction region 208 is formed up to the middle of the thickness of the drift layer 204.
Theelectron conduction region 208 can be formed using substantially the same manufacturing process as the electron conduction region 108 of the first embodiment. That is, the electron conduction region 208 is formed by diffusing n-type impurities into the laminated structure from the etched surface formed in the laminated structure. Alternatively, the electron conduction region 208 may be formed by ion-implanting n-type impurities into the stacked structure and performing a heat treatment from the surface of the stacked structure to a depth reaching the drift layer 204 region. The acceleration voltage at the time of ion implantation is controlled so that the implantation depth of n-type impurity ions reaches the drift layer 204. Also in the first embodiment, the electron conduction region 108 may be formed by ion-implanting n-type impurities into the laminated structure and performing heat treatment.
本実施形態では、電子伝導領域２０８と同様の構成であるが、電子供給層２０７側からドリフト層２０４側に延在し、一方の端部が、電子供給層２０７および電子走行層２０６に接し、他方の端部が電子障壁層よりも基板側に位置する領域（本実施形態では、ドリフト層２０３）に接している。より詳細に説明すると、電子伝導領域２０８は、電子供給層２０７、電子走行層２０６、電子障壁層２０５、ドリフト層２０４に接して設けられている。電子伝導領域２０８は、ドリフト層２０４の厚みの途中位置まで形成されている。
電子伝導領域２０８は、上記第１の実施形態の電子伝導領域１０８とほぼ同じ製造工程を用いて形成することができる。すなわち、電子伝導領域２０８は、積層構造に形成されたエッチング加工面から積層構造内にｎ型不純物を拡散させることで形成される。この代わりに、積層構造表面からドリフト層２０４の領域に達する深さまで、積層構造内にｎ型不純物をイオン注入し熱処理を施すことにより電子伝導領域２０８を形成してもよい。イオン注入の際の加速電圧は、ｎ型不純物イオンの打ち込み深さがドリフト層２０４に達するように制御される。なお、第１の実施形態においても、積層構造内にｎ型不純物をイオン注入し熱処理を施すことにより電子伝導領域１０８を形成してもよい。 The
In this embodiment, the configuration is the same as that of the
The
ゲート電極２１２、ソース電極２０９、絶縁膜２１１および保護膜２１３は、それぞれ、上記第１の実施形態のゲート電極１１２、ソース電極１０９、絶縁膜１１１および保護膜１１３とほぼ同じ製造工程を用いて形成することができる。ドレイン電極２１０は、たとえば真空蒸着法により単層または多層の金属膜を成膜することで形成される。
The gate electrode 212, the source electrode 209, the insulating film 211, and the protective film 213 are formed using substantially the same manufacturing process as the gate electrode 112, the source electrode 109, the insulating film 111, and the protective film 113 of the first embodiment, respectively. can do. The drain electrode 210 is formed by forming a single-layer or multilayer metal film by, for example, a vacuum deposition method.
上記第２の実施形態の電界効果トランジスタ２０の製造方法が奏する効果は以下の通りである。
上記第１の実施形態と同様に、第２の実施形態の製造方法は、基板２０１上で電子障壁層２０５と電子走行層２０６を連続的にエピタキシャル成長させ、その後に、ゲート電極２１２の側方であってソース電極２０９から離れた位置にエッチング加工面を形成し、このエッチング加工面に電子伝導領域２０８を形成する。言い換えれば、電子障壁層２０５と電子走行層２０６とをエピタキシャル成長させた後に、これら電子障壁層２０５と電子走行層２０６の一部をエッチングし、その加工面上に電子走行層を再成長させるという製造工程を行わずに、ソース電極２０９からの注入電子が縦方向へ移動できる経路（電子伝導領域）２０８を形成することが可能である。よって、結晶性の良好な電子走行層２０６を形成できるので、この電子走行層２０６と電子供給層２０７とのヘテロ接合界面およびその近傍での電子移動度が高く、チャネル領域の抵抗が低い電界効果トランジスタ２０を作製することができる。
また、ゲート電極２１２とドレイン電極２１０間に高電圧を印加して電界効果トランジスタ２０を動作させたとき、電界効果トランジスタ２０は電子伝導領域２０８を介して縦方向にキャリアが流れる構造を有するため、電界効果トランジスタ２０の電子供給層２０７と絶縁膜２１１との界面に生じた固定電荷の影響を受けることなく、キャリアの移動経路における局所的な電界集中を抑制することができる。これにより、耐圧の向上が可能となる。また、ＧａＮの絶縁破壊耐圧の物性値（＝約３．３×１０６Ｖ／ｃｍ）に近い最大電界強度を期待することが可能である。
さらに、ゲート電極２１２の電子伝導領域２０８側の庇部分は、ゲート電極２１２のソース電極２０９側の庇部分よりも長いので、ゲート電極２１２の近傍の電界集中を緩和することができる。よって、さらなる耐圧の向上が可能である。 The effects produced by the method of manufacturing thefield effect transistor 20 of the second embodiment are as follows.
Similar to the first embodiment, in the manufacturing method of the second embodiment, theelectron barrier layer 205 and the electron transit layer 206 are continuously epitaxially grown on the substrate 201, and then on the side of the gate electrode 212. Then, an etched surface is formed at a position away from the source electrode 209, and an electron conduction region 208 is formed on the etched surface. In other words, after the electron barrier layer 205 and the electron transit layer 206 are epitaxially grown, a part of the electron barrier layer 205 and the electron transit layer 206 is etched, and the electron transit layer is regrown on the processed surface. Without performing the process, it is possible to form a path (electron conduction region) 208 through which injected electrons from the source electrode 209 can move in the vertical direction. Therefore, since the electron transit layer 206 with good crystallinity can be formed, the field effect of high electron mobility at and near the heterojunction interface between the electron transit layer 206 and the electron supply layer 207 and low resistance of the channel region. The transistor 20 can be manufactured.
In addition, when thefield effect transistor 20 is operated by applying a high voltage between the gate electrode 212 and the drain electrode 210, the field effect transistor 20 has a structure in which carriers flow in the vertical direction through the electron conduction region 208. The local electric field concentration in the carrier movement path can be suppressed without being affected by the fixed charge generated at the interface between the electron supply layer 207 and the insulating film 211 of the field effect transistor 20. Thereby, the breakdown voltage can be improved. In addition, it is possible to expect a maximum electric field strength close to a physical property value of dielectric breakdown voltage of GaN (= about 3.3 × 10 6 V / cm).
Furthermore, since the ridge portion of thegate electrode 212 on the electron conduction region 208 side is longer than the ridge portion of the gate electrode 212 on the source electrode 209 side, electric field concentration in the vicinity of the gate electrode 212 can be reduced. Therefore, the breakdown voltage can be further improved.
上記第１の実施形態と同様に、第２の実施形態の製造方法は、基板２０１上で電子障壁層２０５と電子走行層２０６を連続的にエピタキシャル成長させ、その後に、ゲート電極２１２の側方であってソース電極２０９から離れた位置にエッチング加工面を形成し、このエッチング加工面に電子伝導領域２０８を形成する。言い換えれば、電子障壁層２０５と電子走行層２０６とをエピタキシャル成長させた後に、これら電子障壁層２０５と電子走行層２０６の一部をエッチングし、その加工面上に電子走行層を再成長させるという製造工程を行わずに、ソース電極２０９からの注入電子が縦方向へ移動できる経路（電子伝導領域）２０８を形成することが可能である。よって、結晶性の良好な電子走行層２０６を形成できるので、この電子走行層２０６と電子供給層２０７とのヘテロ接合界面およびその近傍での電子移動度が高く、チャネル領域の抵抗が低い電界効果トランジスタ２０を作製することができる。
また、ゲート電極２１２とドレイン電極２１０間に高電圧を印加して電界効果トランジスタ２０を動作させたとき、電界効果トランジスタ２０は電子伝導領域２０８を介して縦方向にキャリアが流れる構造を有するため、電界効果トランジスタ２０の電子供給層２０７と絶縁膜２１１との界面に生じた固定電荷の影響を受けることなく、キャリアの移動経路における局所的な電界集中を抑制することができる。これにより、耐圧の向上が可能となる。また、ＧａＮの絶縁破壊耐圧の物性値（＝約３．３×１０６Ｖ／ｃｍ）に近い最大電界強度を期待することが可能である。
さらに、ゲート電極２１２の電子伝導領域２０８側の庇部分は、ゲート電極２１２のソース電極２０９側の庇部分よりも長いので、ゲート電極２１２の近傍の電界集中を緩和することができる。よって、さらなる耐圧の向上が可能である。 The effects produced by the method of manufacturing the
Similar to the first embodiment, in the manufacturing method of the second embodiment, the
In addition, when the
Furthermore, since the ridge portion of the
（第２の実施形態の変形例）
図５は、上記第２の実施形態の変形例である電界効果トランジスタ２０Ａの断面構造を概略的に示す断面図である。この電界効果トランジスタ２０Aの構造は、電子伝導領域２０８のドリフト層２０３と反対側に電位制御絶縁膜１１４を介して電子伝導領域２０８の電位を制御するための、電位制御電極１１５が配されている。
このような電界効果トランジスタ２０Aでは、第一の実施形態の変形例と同様の効果を奏することができる。
なお、電位制御電極をゲート電極と接続させた場合も同様にオフ耐圧を向上することができる。更にオン抵抗を低減する効果もあるが、一方でゲート容量の増大により利得が低下する可能性もある。
なお、電位制御絶縁膜１１４、電位制御電極１１５は、第１の実施形態の変形例と同様、電子伝導領域２０８を形成した後に形成すればよい。 (Modification of the second embodiment)
FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 20A, which is a modification of the second embodiment. In the structure of this field effect transistor 20A, apotential control electrode 115 for controlling the potential of the electron conduction region 208 via the potential control insulating film 114 is disposed on the opposite side of the drift layer 203 of the electron conduction region 208. .
Such a field effect transistor 20A can provide the same effects as those of the modification of the first embodiment.
Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved. Furthermore, there is an effect of reducing the on-resistance, but on the other hand, there is a possibility that the gain is lowered due to an increase in the gate capacitance.
Note that the potentialcontrol insulating film 114 and the potential control electrode 115 may be formed after the electron conduction region 208 is formed, as in the modification of the first embodiment.
図５は、上記第２の実施形態の変形例である電界効果トランジスタ２０Ａの断面構造を概略的に示す断面図である。この電界効果トランジスタ２０Aの構造は、電子伝導領域２０８のドリフト層２０３と反対側に電位制御絶縁膜１１４を介して電子伝導領域２０８の電位を制御するための、電位制御電極１１５が配されている。
このような電界効果トランジスタ２０Aでは、第一の実施形態の変形例と同様の効果を奏することができる。
なお、電位制御電極をゲート電極と接続させた場合も同様にオフ耐圧を向上することができる。更にオン抵抗を低減する効果もあるが、一方でゲート容量の増大により利得が低下する可能性もある。
なお、電位制御絶縁膜１１４、電位制御電極１１５は、第１の実施形態の変形例と同様、電子伝導領域２０８を形成した後に形成すればよい。 (Modification of the second embodiment)
FIG. 5 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 20A, which is a modification of the second embodiment. In the structure of this field effect transistor 20A, a
Such a field effect transistor 20A can provide the same effects as those of the modification of the first embodiment.
Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved. Furthermore, there is an effect of reducing the on-resistance, but on the other hand, there is a possibility that the gain is lowered due to an increase in the gate capacitance.
Note that the potential
次に、上記実施形態の実施例について説明する。
Next, examples of the above embodiment will be described.
（第１実施例）
第１実施例の電界効果トランジスタは、第１の実施形態の電界効果トランジスタ１０と同じ構造を有し、第１の実施形態と同様の方法で作成した。基板１０１として、（１１１）面を主面とするシリコン基板を使用した。バッファ層１０２としてＡｌＮ層（膜厚：１００ｎｍ）を、高濃度ｎ型半導体層１０３としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：１×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層１０４としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：３×１０１７ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層１０５としてＭｇを添加したＧａＮ層（不純物濃度１×１０１９ｃｍ－３、膜厚：３００ｎｍ）を、電子走行層１０６としてＧａＮ層（膜厚：１００ｎｍ）を、電子供給層１０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２、膜厚：４０ｎｍ）を、ソース電極１０９およびドレイン電極１１０としてＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ａｌ層の膜厚：２００ｎｍ）を、絶縁膜１１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極１１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜１１３としてＳｉＯＮ膜（膜厚８０ｎｍ）を、それぞれ使用した。
基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子供給層１０７の順に各層を連続的に成長させて積層構造を得た。
なお、ここでは、ＭＯＶＰＥ法により同一装置内にて各層を連続成長している。 (First embodiment)
The field effect transistor of the first example has the same structure as that of thefield effect transistor 10 of the first embodiment, and was produced by the same method as that of the first embodiment. As the substrate 101, a silicon substrate having a (111) plane as a main surface was used. Drift of an AlN layer (film thickness: 100 nm) as the buffer layer 102 and an n-type GaN layer (impurity concentration: 1 × 10 19 cm −3 , film thickness: 500 nm) doped with Si as the high-concentration n-type semiconductor layer 103 An n-type GaN layer doped with Si (impurity concentration: 3 × 10 17 cm −3 , film thickness: 4000 nm) as the layer 104, and a GaN layer doped with Mg (impurity concentration 1 × 10 19 cm − as the electron barrier layer 105). 3 , film thickness: 300 nm), GaN layer (film thickness: 100 nm) as the electron transit layer 106, and Al x Ga 1-x N layer (Al composition ratio: x = 0.2, film thickness) as the electron supply layer 107. : 40 nm) as a source electrode 109 and a drain electrode 110 and a Ti / Al stacked structure (Ti layer thickness: 10 nm, Al layer thickness: 200 nm) and S as an insulating film 111 An iN film (film thickness: 120 nm), a Ni / Au laminated structure (Ni film thickness: 15 nm, Au layer film thickness: 400 nm) as the gate electrode 112, and a SiON film (film thickness 80 nm) as the protective film 113 , Each used.
On thesubstrate 101, the buffer layer 102, the high-concentration n-type semiconductor layer 103, the drift layer 104, the electron barrier layer 105, and the electron supply layer 107 were successively grown in this order to obtain a stacked structure.
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
第１実施例の電界効果トランジスタは、第１の実施形態の電界効果トランジスタ１０と同じ構造を有し、第１の実施形態と同様の方法で作成した。基板１０１として、（１１１）面を主面とするシリコン基板を使用した。バッファ層１０２としてＡｌＮ層（膜厚：１００ｎｍ）を、高濃度ｎ型半導体層１０３としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：１×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層１０４としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：３×１０１７ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層１０５としてＭｇを添加したＧａＮ層（不純物濃度１×１０１９ｃｍ－３、膜厚：３００ｎｍ）を、電子走行層１０６としてＧａＮ層（膜厚：１００ｎｍ）を、電子供給層１０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２、膜厚：４０ｎｍ）を、ソース電極１０９およびドレイン電極１１０としてＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ａｌ層の膜厚：２００ｎｍ）を、絶縁膜１１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極１１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜１１３としてＳｉＯＮ膜（膜厚８０ｎｍ）を、それぞれ使用した。
基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子供給層１０７の順に各層を連続的に成長させて積層構造を得た。
なお、ここでは、ＭＯＶＰＥ法により同一装置内にて各層を連続成長している。 (First embodiment)
The field effect transistor of the first example has the same structure as that of the
On the
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
電子伝導領域１０８は、積層構造の一部をドライエッチングにて除去してエッチング加工面を形成し、このエッチング加工面に多結晶のシリコンを積層後、１２００℃で１時間の熱処理を施してシリコンを積層構造中に拡散させることにより形成された。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第１実施例の電界効果トランジスタ１０は、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層１０６と電子供給層１０７の結晶性が良好であることが確認された。 In theelectron conduction region 108, a part of the laminated structure is removed by dry etching to form an etched surface, and polycrystalline silicon is laminated on the etched surface, followed by heat treatment at 1200 ° C. for 1 hour. Was diffused into the laminated structure.
Thereafter, thegate electrode 112, the source electrode 109, and the drain electrode 110 were formed.
Thefield effect transistor 10 of the first embodiment manufactured in this way has a high electron mobility (= about 2 × 10 3 cm 2 / V / sec), and the crystal of the electron transit layer 106 and the electron supply layer 107. It was confirmed that the property was good.
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第１実施例の電界効果トランジスタ１０は、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層１０６と電子供給層１０７の結晶性が良好であることが確認された。 In the
Thereafter, the
The
（第２実施例）
第２実施例の電界効果トランジスタは、第１の実施形態の変形例の電界効果トランジスタ１０Ａと同じ構造を有する。基板１０１として、Ｓｉ面を主面とする炭化珪素基板を使用した。バッファ層１０２としてＡｌＮ層（膜厚：５０ｎｍ）を、高濃度ｎ型半導体層１０３としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：２×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層１０４としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：５×１０１６ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層１０５としてＭｇを添加したＧａＮ層（不純物濃度１×１０１９ｃｍ－３、膜厚：３００ｎｍ）を、電子走行層１０６としてＧａＮ層（膜厚：２００ｎｍ）を、電子供給層１０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２、膜厚：４０ｎｍ）を、ソース電極１０９およびドレイン電極１１０としてＴｉ／Ａｌ／Ｎｂ／Ａｕ積層構造（Ｔｉ層の膜厚：１５ｎｍ、Ａｌ層の膜厚：６０ｎｍ、Ｎｂ層の厚さ：３５ｎｍ、Ａｕ層の厚さ：５０ｎｍ）を、絶縁膜１１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極１１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜１１３としてＳｉＯＮ膜（膜厚８０ｎｍ）を、それぞれ使用した。
基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子供給層１０７の順に各層を連続的に成長させて積層構造を得た。
ここでは、ＭＯＶＰＥ法により同一装置内にて、各層を連続成長している。 (Second embodiment)
The field effect transistor of the second example has the same structure as thefield effect transistor 10A of the modification of the first embodiment. As the substrate 101, a silicon carbide substrate having a Si surface as a main surface was used. Drift of an AlN layer (film thickness: 50 nm) as the buffer layer 102 and an n-type GaN layer (impurity concentration: 2 × 10 19 cm −3 , film thickness: 500 nm) doped with Si as the high-concentration n-type semiconductor layer 103 An n-type GaN layer doped with Si (impurity concentration: 5 × 10 16 cm −3, film thickness: 4000 nm) as the layer 104, and a GaN layer doped with Mg (impurity concentration 1 × 10 19 cm − as the electron barrier layer 105). 3 , film thickness: 300 nm), GaN layer (film thickness: 200 nm) as the electron transit layer 106, and Al x Ga 1-x N layer (Al composition ratio: x = 0.2, film thickness) as the electron supply layer 107. : 40 nm) as a source electrode 109 and a drain electrode 110, a Ti / Al / Nb / Au stacked structure (Ti layer thickness: 15 nm, Al layer thickness: 60 nm, Nb layer thickness: 3) nm, the thickness of the Au layer: 50 nm), a SiN film (film thickness: 120 nm) as the insulating film 111, and a Ni / Au laminated structure as the gate electrode 112 (film thickness of Ni layer: 15 nm, film thickness of the Au layer: 400 nm) and a SiON film (film thickness 80 nm) were used as the protective film 113, respectively.
On thesubstrate 101, the buffer layer 102, the high-concentration n-type semiconductor layer 103, the drift layer 104, the electron barrier layer 105, and the electron supply layer 107 were successively grown in this order to obtain a stacked structure.
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
第２実施例の電界効果トランジスタは、第１の実施形態の変形例の電界効果トランジスタ１０Ａと同じ構造を有する。基板１０１として、Ｓｉ面を主面とする炭化珪素基板を使用した。バッファ層１０２としてＡｌＮ層（膜厚：５０ｎｍ）を、高濃度ｎ型半導体層１０３としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：２×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層１０４としてＳｉを添加したｎ型ＧａＮ層（不純物濃度：５×１０１６ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層１０５としてＭｇを添加したＧａＮ層（不純物濃度１×１０１９ｃｍ－３、膜厚：３００ｎｍ）を、電子走行層１０６としてＧａＮ層（膜厚：２００ｎｍ）を、電子供給層１０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２、膜厚：４０ｎｍ）を、ソース電極１０９およびドレイン電極１１０としてＴｉ／Ａｌ／Ｎｂ／Ａｕ積層構造（Ｔｉ層の膜厚：１５ｎｍ、Ａｌ層の膜厚：６０ｎｍ、Ｎｂ層の厚さ：３５ｎｍ、Ａｕ層の厚さ：５０ｎｍ）を、絶縁膜１１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極１１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜１１３としてＳｉＯＮ膜（膜厚８０ｎｍ）を、それぞれ使用した。
基板１０１上に、バッファ層１０２、高濃度ｎ型半導体層１０３、ドリフト層１０４、電子障壁層１０５、電子供給層１０７の順に各層を連続的に成長させて積層構造を得た。
ここでは、ＭＯＶＰＥ法により同一装置内にて、各層を連続成長している。 (Second embodiment)
The field effect transistor of the second example has the same structure as the
On the
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
電子伝導領域１０８は、積層構造の一部をドライエッチングにて除去してエッチング加工面を形成し、このエッチング加工面にＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：３０ｎｍ、Ａｌ層の膜厚：１８０ｎｍ）を積層後、６５０℃で３０秒の熱処理を施して形成された。
その後、電位制御絶縁膜１１４としてＡｌ２Ｏ３膜（膜厚：１００ｎｍ）をスパッタ法にて形成し、電位制御電極４１５としてＴｉ／Ｐｔ／Ａｕ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ｐｔ層の膜厚：８０ｎｍ、Ａｕ層の膜厚：３００ｎｍ）をスパッタ法にて形成した。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第２実施例の電界効果トランジスタ１０Ａは、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層１０６と電子供給層１０７の結晶性が良好であることが確認された。また、第１実施例と比較してさらに高い耐圧特性とを有することが確認された。 Theelectron conduction region 108 is formed by removing a part of the laminated structure by dry etching to form an etched surface, and a Ti / Al laminated structure (Ti layer thickness: 30 nm, Al layer thickness on the etched surface). : 180 nm), and heat treatment was performed at 650 ° C. for 30 seconds.
Thereafter, an Al 2 O 3 film (film thickness: 100 nm) is formed as the potentialcontrol insulating film 114 by sputtering, and a Ti / Pt / Au laminated structure (Ti film thickness: 10 nm, Pt layer is formed as the potential control electrode 415. Film thickness: 80 nm, Au layer film thickness: 300 nm).
Thereafter, thegate electrode 112, the source electrode 109, and the drain electrode 110 were formed.
Thefield effect transistor 10A according to the second embodiment manufactured in this way has high electron mobility (= about 2 × 10 3 cm 2 / V / sec), and the crystal of the electron transit layer 106 and the electron supply layer 107 is obtained. It was confirmed that the property was good. Moreover, it was confirmed that it has a further higher pressure | voltage resistant characteristic compared with 1st Example.
その後、電位制御絶縁膜１１４としてＡｌ２Ｏ３膜（膜厚：１００ｎｍ）をスパッタ法にて形成し、電位制御電極４１５としてＴｉ／Ｐｔ／Ａｕ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ｐｔ層の膜厚：８０ｎｍ、Ａｕ層の膜厚：３００ｎｍ）をスパッタ法にて形成した。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第２実施例の電界効果トランジスタ１０Ａは、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層１０６と電子供給層１０７の結晶性が良好であることが確認された。また、第１実施例と比較してさらに高い耐圧特性とを有することが確認された。 The
Thereafter, an Al 2 O 3 film (film thickness: 100 nm) is formed as the potential
Thereafter, the
The
（第３実施例）
第３実施例の電界効果トランジスタは、第２の実施形態の電界効果トランジスタ２０と同じ構造を有し、第２の実施形態と同様の方法で作成した。基板２０１として、（０００１）面を主面とするｎ型ＧａＮ基板を使用した。高濃度ｎ型半導体層２０３としてＳｉを添加したＧａＮ層（不純物濃度：１×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層２０４としてＳｉを添加したＧａＮ層（不純物濃度：：３×１０１６ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層２０５としてＭｇを添加したＧａＮ層（不純物濃度：２×１０１９ｃｍ－３、膜厚：２００ｎｍ）を、電子走行層２０６としてＧａＮ層（膜厚：１００ｎｍ）を、電子供給層２０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２５、膜厚：２５ｎｍ）を、ソース電極２０９ドレイン電極２１０としてＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ａｌ層の膜厚：２００ｎｍ）を、絶縁膜２１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極２１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜２１３としてＳｉＯＮ膜（膜厚：８０ｎｍ）を、それぞれ使用した。
基板２０１上に、バッファ層２０２、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子供給層２０７の順に各層を連続的に成長させて積層構造を得た。
ここでは、ＭＯＶＰＥ法により同一装置内にて、各層を連続成長している。
電子伝導領域２０８は、エッチング加工面にＳｉをイオン注入（注入エネルギー：２００ＫｅＶ、注入量：５×１０１４ｃｍ－２）し、１２００℃１時間の熱処理により活性化アニールを行うことにより形成された。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第３実施例の電界効果トランジスタ２０は、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層２０６と電子供給層２０７の結晶性が良好であることが確認された。 (Third embodiment)
The field effect transistor of the third example has the same structure as that of thefield effect transistor 20 of the second embodiment, and was produced by the same method as that of the second embodiment. As the substrate 201, an n-type GaN substrate having a (0001) plane as a main surface was used. A GaN layer doped with Si (impurity concentration: 1 × 10 19 cm −3 , film thickness: 500 nm) as the high-concentration n-type semiconductor layer 203 and a GaN layer doped with Si as the drift layer 204 (impurity concentration :: 3 × 10 16 cm -3, thickness: 4000 nm) and, GaN layer doped with Mg as an electron barrier layer 205 (dopant concentration: 2 × 10 19 cm -3, film thickness: 200 nm) to, GaN layer as the electron transit layer 206 (Film thickness: 100 nm), an Al x Ga 1-x N layer (Al composition ratio: x = 0.25, film thickness: 25 nm) as the electron supply layer 207, and a Ti / Al stacked layer as the source electrode 209 and the drain electrode 210 Structure (Ti layer thickness: 10 nm, Al layer thickness: 200 nm), SiN film (thickness: 120 nm) as insulating film 211, and Ni / Au as gate electrode 212 A stacked structure (Ni layer thickness: 15 nm, Au layer thickness: 400 nm) was used, and a SiON film (film thickness: 80 nm) was used as the protective film 213.
On thesubstrate 201, the buffer layer 202, the high-concentration n-type semiconductor layer 203, the drift layer 204, the electron barrier layer 205, and the electron supply layer 207 were successively grown to obtain a stacked structure.
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
Theelectron conduction region 208 was formed by ion-implanting Si into the etched surface (implantation energy: 200 KeV, implantation amount: 5 × 10 14 cm −2 ) and performing activation annealing by heat treatment at 1200 ° C. for 1 hour. .
Thereafter, thegate electrode 112, the source electrode 109, and the drain electrode 110 were formed.
Thefield effect transistor 20 of the third embodiment manufactured in this way has high electron mobility (= about 2 × 10 3 cm 2 / V / sec), and the crystal of the electron transit layer 206 and the electron supply layer 207 is obtained. It was confirmed that the property was good.
第３実施例の電界効果トランジスタは、第２の実施形態の電界効果トランジスタ２０と同じ構造を有し、第２の実施形態と同様の方法で作成した。基板２０１として、（０００１）面を主面とするｎ型ＧａＮ基板を使用した。高濃度ｎ型半導体層２０３としてＳｉを添加したＧａＮ層（不純物濃度：１×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層２０４としてＳｉを添加したＧａＮ層（不純物濃度：：３×１０１６ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層２０５としてＭｇを添加したＧａＮ層（不純物濃度：２×１０１９ｃｍ－３、膜厚：２００ｎｍ）を、電子走行層２０６としてＧａＮ層（膜厚：１００ｎｍ）を、電子供給層２０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２５、膜厚：２５ｎｍ）を、ソース電極２０９ドレイン電極２１０としてＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ａｌ層の膜厚：２００ｎｍ）を、絶縁膜２１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極２１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜２１３としてＳｉＯＮ膜（膜厚：８０ｎｍ）を、それぞれ使用した。
基板２０１上に、バッファ層２０２、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子供給層２０７の順に各層を連続的に成長させて積層構造を得た。
ここでは、ＭＯＶＰＥ法により同一装置内にて、各層を連続成長している。
電子伝導領域２０８は、エッチング加工面にＳｉをイオン注入（注入エネルギー：２００ＫｅＶ、注入量：５×１０１４ｃｍ－２）し、１２００℃１時間の熱処理により活性化アニールを行うことにより形成された。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第３実施例の電界効果トランジスタ２０は、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層２０６と電子供給層２０７の結晶性が良好であることが確認された。 (Third embodiment)
The field effect transistor of the third example has the same structure as that of the
On the
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
The
Thereafter, the
The
（第４実施例）
第４実施例の電界効果トランジスタは、第２の実施形態の変形例の電界効果トランジスタ２０Ａと同じ構造を有し、第２の実施形態の変形例と同様の方法で作成した。基板２０１として、（０００１）面を主面とするｎ型ＧａＮ基板を使用した。高濃度ｎ型半導体層２０３としてＳｉを添加したＧａＮ層（不純物濃度：１×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層２０４としてＳｉを添加したＧａＮ層（不純物濃度：：３×１０１６ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層２０５としてＭｇを添加したＧａＮ層（不純物濃度：２×１０１９ｃｍ－３、膜厚：２００ｎｍ）を、電子走行層２０６としてＧａＮ層（膜厚：１００ｎｍ）を、電子供給層２０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２５、膜厚：２５ｎｍ）を、ソース電極２０９ドレイン電極２１０としてＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ａｌ層の膜厚：２００ｎｍ）を、絶縁膜２１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極２１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜２１３としてＳｉＯＮ膜（膜厚：８０ｎｍ）を、それぞれ使用した。 (Fourth embodiment)
The field effect transistor of the fourth example has the same structure as the field effect transistor 20A of the modification of the second embodiment, and was created by the same method as that of the modification of the second embodiment. As thesubstrate 201, an n-type GaN substrate having a (0001) plane as a main surface was used. A GaN layer doped with Si (impurity concentration: 1 × 10 19 cm −3 , film thickness: 500 nm) as the high-concentration n-type semiconductor layer 203 and a GaN layer doped with Si as the drift layer 204 (impurity concentration :: 3 × 10 16 cm -3, thickness: 4000 nm) and, GaN layer doped with Mg as an electron barrier layer 205 (dopant concentration: 2 × 10 19 cm -3, film thickness: 200 nm) to, GaN layer as the electron transit layer 206 (Film thickness: 100 nm), an Al x Ga 1-x N layer (Al composition ratio: x = 0.25, film thickness: 25 nm) as the electron supply layer 207, and a Ti / Al stacked layer as the source electrode 209 and the drain electrode 210 Structure (Ti layer thickness: 10 nm, Al layer thickness: 200 nm), SiN film (thickness: 120 nm) as insulating film 211, and Ni / Au as gate electrode 212 A stacked structure (Ni layer thickness: 15 nm, Au layer thickness: 400 nm) was used, and a SiON film (film thickness: 80 nm) was used as the protective film 213.
第４実施例の電界効果トランジスタは、第２の実施形態の変形例の電界効果トランジスタ２０Ａと同じ構造を有し、第２の実施形態の変形例と同様の方法で作成した。基板２０１として、（０００１）面を主面とするｎ型ＧａＮ基板を使用した。高濃度ｎ型半導体層２０３としてＳｉを添加したＧａＮ層（不純物濃度：１×１０１９ｃｍ－３、膜厚：５００ｎｍ）を、ドリフト層２０４としてＳｉを添加したＧａＮ層（不純物濃度：：３×１０１６ｃｍ－３、膜厚：４０００ｎｍ）を、電子障壁層２０５としてＭｇを添加したＧａＮ層（不純物濃度：２×１０１９ｃｍ－３、膜厚：２００ｎｍ）を、電子走行層２０６としてＧａＮ層（膜厚：１００ｎｍ）を、電子供給層２０７としてＡｌｘＧａ１－ｘＮ層（Ａｌ組成比：ｘ＝０．２５、膜厚：２５ｎｍ）を、ソース電極２０９ドレイン電極２１０としてＴｉ／Ａｌ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ａｌ層の膜厚：２００ｎｍ）を、絶縁膜２１１としてＳｉＮ膜（膜厚：１２０ｎｍ）を、ゲート電極２１２としてＮｉ／Ａｕ積層構造（Ｎｉ層の膜厚：１５ｎｍ、Ａｕ層の膜厚：４００ｎｍ）を、保護膜２１３としてＳｉＯＮ膜（膜厚：８０ｎｍ）を、それぞれ使用した。 (Fourth embodiment)
The field effect transistor of the fourth example has the same structure as the field effect transistor 20A of the modification of the second embodiment, and was created by the same method as that of the modification of the second embodiment. As the
基板２０１上に、バッファ層２０２、高濃度ｎ型半導体層２０３、ドリフト層２０４、電子障壁層２０５、電子供給層２０７の順に各層を連続的に成長させて積層構造を得た。
ここでは、ＭＯＶＰＥ法により同一装置内にて、各層を連続成長している。
電子伝導領域２０８は、エッチング加工面にＳｉをイオン注入（注入エネルギー：２００ＫｅＶ、注入量：５×１０１４ｃｍ－２）し、１２００℃１時間の熱処理により活性化アニールを行うことにより形成された。
その後、電位制御絶縁膜２１４としてＺｒＯ２膜（膜厚：３００ｎｍ）をスパッタ法にて形成し、電位制御電極４１５としてＴｉ／Ｐｔ／Ａｕ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ｐｔ層の膜厚：８０ｎｍ、Ａｕ層の膜厚：３００ｎｍ）をスパッタ法にて形成した。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第４実施例の電界効果トランジスタ２０Ａは、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層２０６と電子供給層２０７の結晶性が良好であることが確認された。また、第３実施例と比較してさらに高い耐圧特性とを有することが確認された。 On thesubstrate 201, the buffer layer 202, the high-concentration n-type semiconductor layer 203, the drift layer 204, the electron barrier layer 205, and the electron supply layer 207 were successively grown to obtain a stacked structure.
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
Theelectron conduction region 208 was formed by ion-implanting Si into the etched surface (implantation energy: 200 KeV, implantation amount: 5 × 10 14 cm −2 ) and performing activation annealing by heat treatment at 1200 ° C. for 1 hour. .
Thereafter, a ZrO 2 film (film thickness: 300 nm) is formed by sputtering as the potential control insulating film 214, and a Ti / Pt / Au laminated structure (Ti layer film thickness: 10 nm, Pt layer film) is formed as the potential control electrode 415. (Thickness: 80 nm, Au layer thickness: 300 nm) was formed by sputtering.
Thereafter, thegate electrode 112, the source electrode 109, and the drain electrode 110 were formed.
The field effect transistor 20A of the fourth embodiment manufactured in this way has a high electron mobility (= about 2 × 10 3 cm 2 / V / sec), and the crystal of theelectron transit layer 206 and the electron supply layer 207 It was confirmed that the property was good. Moreover, it was confirmed that it has a higher breakdown voltage characteristic compared with the third embodiment.
ここでは、ＭＯＶＰＥ法により同一装置内にて、各層を連続成長している。
電子伝導領域２０８は、エッチング加工面にＳｉをイオン注入（注入エネルギー：２００ＫｅＶ、注入量：５×１０１４ｃｍ－２）し、１２００℃１時間の熱処理により活性化アニールを行うことにより形成された。
その後、電位制御絶縁膜２１４としてＺｒＯ２膜（膜厚：３００ｎｍ）をスパッタ法にて形成し、電位制御電極４１５としてＴｉ／Ｐｔ／Ａｕ積層構造（Ｔｉ層の膜厚：１０ｎｍ、Ｐｔ層の膜厚：８０ｎｍ、Ａｕ層の膜厚：３００ｎｍ）をスパッタ法にて形成した。
その後、ゲート電極１１２，ソース電極１０９およびドレイン電極１１０を形成した。
このように作製された第４実施例の電界効果トランジスタ２０Ａは、高い電子移動度（＝約２×１０３ｃｍ２／Ｖ／ｓｅｃ）を有し、電子走行層２０６と電子供給層２０７の結晶性が良好であることが確認された。また、第３実施例と比較してさらに高い耐圧特性とを有することが確認された。 On the
Here, each layer is continuously grown in the same apparatus by the MOVPE method.
The
Thereafter, a ZrO 2 film (film thickness: 300 nm) is formed by sputtering as the potential control insulating film 214, and a Ti / Pt / Au laminated structure (Ti layer film thickness: 10 nm, Pt layer film) is formed as the potential control electrode 415. (Thickness: 80 nm, Au layer thickness: 300 nm) was formed by sputtering.
Thereafter, the
The field effect transistor 20A of the fourth embodiment manufactured in this way has a high electron mobility (= about 2 × 10 3 cm 2 / V / sec), and the crystal of the
以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。たとえば、上記第１の実施形態では、ピエゾ効果や自発分極効果を用いて、電子走行層１０６と電子供給層１０７とのヘテロ接合界面およびその近傍で２次元電子ガスの発生を可能としているが、これに限定されるものではない。電子走行層１０６よりも大きなバンドギャップを持つ電子供給層１０７にＳｉ、Ｓ、Ｓｅ、Ｏなどのｎ型不純物を導入することでヘテロ界面およびその近傍の２次元電子ガスの濃度を調整してもよい（変調ドーピング）。第２の実施形態の電子走行層２０６と電子供給層２０７についても同様である。
As described above, the embodiments of the present invention have been described with reference to the drawings. However, these are exemplifications of the present invention, and various configurations other than the above can be adopted. For example, in the first embodiment, the two-dimensional electron gas can be generated at and near the heterojunction interface between the electron transit layer 106 and the electron supply layer 107 using the piezo effect and the spontaneous polarization effect. It is not limited to this. Even if the concentration of the two-dimensional electron gas at and around the heterointerface is adjusted by introducing n-type impurities such as Si, S, Se, and O into the electron supply layer 107 having a larger band gap than the electron transit layer 106. Good (modulation doping). The same applies to the electron transit layer 206 and the electron supply layer 207 of the second embodiment.
上記第１の実施形態では、基板１０１上に形成される化合物半導体層１０２～１０７の各々の厚みは、所望の厚みとすることができるが、これら化合物半導体層１０２～１０７の格子定数が基板１０１の格子定数と大きく異なる場合には、臨界膜厚（結晶内で転位が発生して格子歪みが緩和する膜厚）未満にすることが望ましい。第２の実施形態の基板２０１上に形成される化合物半導体層２０３～２０７についても、同様である。
上記第１の実施形態の電界効果トランジスタ１０は、電子走行層１０６と電子供給層１０７とのヘテロ接合界面を有し、このヘテロ接合界面およびその近傍に２次元電子ガスのチャネルが形成されるが、これに限定されるものではない。たとえば、電界効果トランジスタ１０において、電子供給層１０７と電子走行層１０６の組み合わせの代わりに単一の電子走行層を有する形態もあり得る。第２の実施形態の電子走行層２０６と電子供給層２０７の組み合わせについても、同様である。 In the first embodiment, the thickness of each of the compound semiconductor layers 102 to 107 formed on thesubstrate 101 can be set to a desired thickness. If the lattice constant is significantly different from the above, it is desirable to make it less than the critical film thickness (thickness at which dislocation occurs in the crystal and the lattice distortion is relaxed). The same applies to the compound semiconductor layers 203 to 207 formed on the substrate 201 of the second embodiment.
Thefield effect transistor 10 of the first embodiment has a heterojunction interface between the electron transit layer 106 and the electron supply layer 107, and a channel of a two-dimensional electron gas is formed at and near the heterojunction interface. However, the present invention is not limited to this. For example, the field effect transistor 10 may have a single electron transit layer instead of the combination of the electron supply layer 107 and the electron transit layer 106. The same applies to the combination of the electron transit layer 206 and the electron supply layer 207 of the second embodiment.
上記第１の実施形態の電界効果トランジスタ１０は、電子走行層１０６と電子供給層１０７とのヘテロ接合界面を有し、このヘテロ接合界面およびその近傍に２次元電子ガスのチャネルが形成されるが、これに限定されるものではない。たとえば、電界効果トランジスタ１０において、電子供給層１０７と電子走行層１０６の組み合わせの代わりに単一の電子走行層を有する形態もあり得る。第２の実施形態の電子走行層２０６と電子供給層２０７の組み合わせについても、同様である。 In the first embodiment, the thickness of each of the compound semiconductor layers 102 to 107 formed on the
The
また、上記第１の実施形態の電界効果トランジスタ１０は、化合物半導体層である電子供給層１０７とゲート電極１１２との間にショットキ接合が形成されているが、これに限定されるものではない。たとえば、電子供給層１０７とゲート電極１１２との間にゲート絶縁膜が形成されたＭＩＳ（Metal-Insulator-Semiconductor）構造もあり得る。同様に、第２の実施形態の電子供給層２０７とゲート電極２１２との間にゲート絶縁膜が形成されたＭＩＳ構造もあり得る。
上記第１および第２の実施形態において、ゲート電極１１２，２１２としてショットキー電極を用いる場合には、ゲートリーク電流を抑制するために、電子供給層１０７，２０７にＢｅ，Ｃ，Ｍｇなどのｐ型不純物を導入してもよい。 In thefield effect transistor 10 of the first embodiment, a Schottky junction is formed between the electron supply layer 107, which is a compound semiconductor layer, and the gate electrode 112. However, the invention is not limited to this. For example, there may be a MIS (Metal-Insulator-Semiconductor) structure in which a gate insulating film is formed between the electron supply layer 107 and the gate electrode 112. Similarly, there may be a MIS structure in which a gate insulating film is formed between the electron supply layer 207 and the gate electrode 212 of the second embodiment.
In the first and second embodiments, when a Schottky electrode is used as the gate electrodes 112 and 212, the electron supply layers 107 and 207 are made of p such as Be, C, or Mg in order to suppress the gate leakage current. Type impurities may be introduced.
上記第１および第２の実施形態において、ゲート電極１１２，２１２としてショットキー電極を用いる場合には、ゲートリーク電流を抑制するために、電子供給層１０７，２０７にＢｅ，Ｃ，Ｍｇなどのｐ型不純物を導入してもよい。 In the
In the first and second embodiments, when a Schottky electrode is used as the
また、前記各実施形態では、電子伝導領域１０８、２０８は、電子走行層１０６、２０６の端部側に設けられていたが、これに限られるものではない。たとえば、図６に示すように、ドリフト層１０４、ｐ型電子障壁層１０５、電子走行層１０６および電子供給層１０７の中央部分に電子伝導領域１０８を配置してもよい。
このトランジスタは、複数のソース電極１０９，ゲート電極１１２を備えている。具体的には、基板面側からみて、ソース電極１０９に隣接して、ゲート電極１１２が配置され、このゲート電極１１２の隣に電子伝導領域１０８が配置され、さらに、電子伝導領域１０８の隣に、ゲート電極１１２Aが配置され、このゲート電極１１２Aの隣にソース電極１０９Aが配置されている。電子伝導領域１０８は、一対のソース電極１０９,１０９Aに挟まれるように配置されている。
このようなトランジスタは、前記各実施形態と同様、基板上に、電子障壁層と電子走行層とをこの順に含む積層構造を構成する各層を連続的にエピタキシャル成長させた後、電子伝導領域１０８を形成すればよい。 In each of the above embodiments, the electron conductive regions 108 and 208 are provided on the end side of the electron transit layers 106 and 206, but the present invention is not limited to this. For example, as shown in FIG. 6, an electron conduction region 108 may be disposed at the center of the drift layer 104, the p-type electron barrier layer 105, the electron transit layer 106, and the electron supply layer 107.
This transistor includes a plurality ofsource electrodes 109 and a gate electrode 112. Specifically, when viewed from the substrate surface side, a gate electrode 112 is disposed adjacent to the source electrode 109, an electron conduction region 108 is disposed next to the gate electrode 112, and further, next to the electron conduction region 108. The gate electrode 112A is disposed, and the source electrode 109A is disposed adjacent to the gate electrode 112A. The electron conductive region 108 is disposed so as to be sandwiched between the pair of source electrodes 109 and 109A.
In such a transistor, as in each of the above embodiments, each layer constituting a stacked structure including the electron barrier layer and the electron transit layer in this order is continuously epitaxially grown on the substrate, and then theelectron conduction region 108 is formed. do it.
このトランジスタは、複数のソース電極１０９，ゲート電極１１２を備えている。具体的には、基板面側からみて、ソース電極１０９に隣接して、ゲート電極１１２が配置され、このゲート電極１１２の隣に電子伝導領域１０８が配置され、さらに、電子伝導領域１０８の隣に、ゲート電極１１２Aが配置され、このゲート電極１１２Aの隣にソース電極１０９Aが配置されている。電子伝導領域１０８は、一対のソース電極１０９,１０９Aに挟まれるように配置されている。
このようなトランジスタは、前記各実施形態と同様、基板上に、電子障壁層と電子走行層とをこの順に含む積層構造を構成する各層を連続的にエピタキシャル成長させた後、電子伝導領域１０８を形成すればよい。 In each of the above embodiments, the electron
This transistor includes a plurality of
In such a transistor, as in each of the above embodiments, each layer constituting a stacked structure including the electron barrier layer and the electron transit layer in this order is continuously epitaxially grown on the substrate, and then the
Claims (21)
- 基板上に、電子障壁層と電子走行層とをこの順に含む積層構造を構成する各層を連続的に成長させる工程と、
ゲート電極が形成される領域の一方の側で、前記電子走行層から前記電子障壁層よりも前記基板側の領域に亘って前記積層構造に電子伝導領域を形成する工程と、
前記電子走行層上に前記ゲート電極を形成する工程と、
前記ゲート電極が形成される領域の他方の側における前記電子走行層上にソース電極を形成する工程と、
前記電子伝導領域の前記基板側の一端と電気的に接続されるドレイン電極を形成する工程と、
を備える電界効果トランジスタの製造方法。 A step of continuously growing each layer constituting a stacked structure including an electron barrier layer and an electron transit layer in this order on the substrate;
Forming an electron conduction region in the stacked structure from one side of the region where the gate electrode is formed to a region closer to the substrate than the electron barrier layer from the electron transit layer;
Forming the gate electrode on the electron transit layer;
Forming a source electrode on the electron transit layer on the other side of the region where the gate electrode is formed;
Forming a drain electrode electrically connected to one end of the electron conducting region on the substrate side;
A method for manufacturing a field effect transistor. - 請求項１に記載の電界効果トランジスタの製造方法であって、
前記積層構造を構成する各層を連続的に成長させる工程は、
前記電子障壁層と、前記電子走行層と、前記電子走行層にヘテロ接合する電子供給層とを連続的に成長させる工程を含む、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to claim 1,
The step of continuously growing each layer constituting the laminated structure includes:
A method of manufacturing a field effect transistor, comprising: continuously growing the electron barrier layer, the electron transit layer, and an electron supply layer heterojunction with the electron transit layer. - 請求項１または２に記載の電界効果トランジスタの製造方法であって、
前記ドレイン電極を形成する前記工程では、
前記ドレイン電極を、前記基板の表面側に形成する、電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to claim 1 or 2,
In the step of forming the drain electrode,
A method of manufacturing a field effect transistor, wherein the drain electrode is formed on a surface side of the substrate. - 請求項１または２に記載の電界効果トランジスタの製造方法であって、
前記ドレイン電極を形成する前記工程では、
前記ドレイン電極を、前記基板の裏面に形成し、前記基板を介して前記電子伝導領域と電気的に接続する、電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to claim 1 or 2,
In the step of forming the drain electrode,
A method of manufacturing a field effect transistor, wherein the drain electrode is formed on a back surface of the substrate and electrically connected to the electron conduction region through the substrate. - 請求項１から４のうちのいずれか１項に記載の電界効果トランジスタの製造方法であって、
前記ゲート電極が形成される領域の一方の側で前記積層構造をエッチングして、前記電子走行層から前記電子障壁層よりも前記基板側の領域に亘ってエッチング加工面を形成する工程をさらに備え、
前記電子伝導領域は前記エッチング加工面に形成される、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to any one of claims 1 to 4,
Etching the stacked structure on one side of the region where the gate electrode is to be formed to further form an etching surface from the electron transit layer to the region closer to the substrate than the electron barrier layer; ,
The method of manufacturing a field effect transistor, wherein the electron conductive region is formed on the etched surface. - 請求項５に記載の電界効果トランジスタの製造方法であって、
前記電子伝導領域は、前記エッチング加工面から前記積層構造にｎ型不純物を導入し、当該導入されたｎ型不純物を熱処理により活性化することで形成される、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to claim 5,
The electron conduction region is formed by introducing an n-type impurity into the stacked structure from the etched surface and activating the introduced n-type impurity by heat treatment. - 請求項６に記載の電界効果トランジスタの製造方法であって、
前記電子伝導領域は、前記エッチング加工面にｎ型不純物をイオン注入し、当該注入されたｎ型不純物を熱処理で活性化させることで形成される、電界効果トランジスタ。 It is a manufacturing method of the field effect transistor according to claim 6,
The electron conducting region is formed by ion-implanting n-type impurities into the etched surface and activating the implanted n-type impurities by heat treatment. - 請求項６に記載の電界効果トランジスタの製造方法であって、
前記電子伝導領域は、前記エッチング加工面にアモルファスまたは多結晶のシリコンを堆積し、当該堆積されたシリコンを前記ｎ型不純物として前記積層構造に導入することで形成される、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to claim 6,
The electron conduction region is formed by depositing amorphous or polycrystalline silicon on the etched surface, and introducing the deposited silicon into the stacked structure as the n-type impurity. . - 請求項８に記載の電界効果トランジスタの製造方法であって、
当該堆積されたシリコンは熱処理により前記積層構造に導入される、電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to claim 8,
A method of manufacturing a field effect transistor, wherein the deposited silicon is introduced into the stacked structure by heat treatment. - 請求項５に記載の電界効果トランジスタの製造方法であって、
前記電子伝導領域は、前記エッチング加工面に導電膜を形成することで形成される、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to claim 5,
The method of manufacturing a field effect transistor, wherein the electron conduction region is formed by forming a conductive film on the etched surface. - 請求項１０に記載の電界効果トランジスタの製造方法であって、
前記導電膜は、金属膜であり、
前記電子伝導領域は、前記金属膜と前記積層構造とを熱処理により相互反応させることで形成される、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to claim 10,
The conductive film is a metal film,
The method of manufacturing a field effect transistor, wherein the electron conduction region is formed by causing the metal film and the stacked structure to react with each other by heat treatment. - 請求項１１に記載の電界効果トランジスタの製造方法であって、
前記金属膜は、タングステン（Ｗ）、モリブデン（Ｍｏ）、シリコン（Ｓｉ）、チタン（Ｔｉ）、白金（Ｐｔ）、ニオブ（Ｎｂ）、アルミニウム（Ａｌ）、金（Ａｕ）、タンタル（Ｔａ）、ジルコニウム（Ｚｒ）、イットリウム（Ｙ）からなる群から選択された１種または２種以上の金属材料からなる、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to claim 11,
The metal film includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), gold (Au), tantalum (Ta), A method for producing a field effect transistor, comprising one or more metal materials selected from the group consisting of zirconium (Zr) and yttrium (Y). - 請求項１から４のうちのいずれか１項に記載の電界効果トランジスタの製造方法であって、
前記電子伝導領域は、前記電子障壁層よりも前記基板側の領域に達する深さまで前記積層構造にｎ型不純物をイオン注入することにより形成される、電界効果トランジスタの製造方法。 It is a manufacturing method of the field effect transistor according to any one of claims 1 to 4,
The method of manufacturing a field effect transistor, wherein the electron conduction region is formed by ion-implanting n-type impurities into the stacked structure to a depth reaching a region closer to the substrate than the electron barrier layer. - 請求項１から１３のうちのいずれか１項に記載の電界効果トランジスタの製造方法であって、
前記積層構造は、複数のIII族窒化物系化合物半導体層からなる、電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to any one of claims 1 to 13,
The method for manufacturing a field effect transistor, wherein the stacked structure includes a plurality of group III nitride compound semiconductor layers. - 請求項１から１４に記載の電界効果トランジスタの製造方法であって、
電子伝導領域を形成する前記工程の後段で、
前記電子伝導領域の基板側の一端と反対側の他端上に絶縁膜を形成する工程と、
該絶縁膜上に電位制御電極を形成する工程を実施する電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to claim 1,
After the step of forming the electron conducting region,
Forming an insulating film on the other end on the opposite side of the substrate side of the electron conducting region;
A method for manufacturing a field effect transistor, comprising performing a step of forming a potential control electrode on the insulating film. - 請求項１５に記載の電界効果トランジスタの製造方法であって、
前記電位制御電極を、前記ゲート電極と接続する電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to claim 15,
A method of manufacturing a field effect transistor, wherein the potential control electrode is connected to the gate electrode. - 請求項１５に記載の電界効果トランジスタの製造方法であって、
前記電位制御電極を接地する電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to claim 15,
A method of manufacturing a field effect transistor in which the potential control electrode is grounded. - 請求項１５から１７のいずれかに記載の電界効果トランジスタの製造方法であって、
前記絶縁膜の誘電率が6以上である電界効果トランジスタの製造方法。 A method for producing a field effect transistor according to any one of claims 15 to 17,
A method for manufacturing a field effect transistor, wherein the dielectric constant of the insulating film is 6 or more. - 請求項１５から１８のいずれかに記載の電界効果トランジスタの製造方法であって、
前記絶縁膜が、アルミ、珪素、ハフニウム、ジルコニウム、タンタル、チタンのうち少なくとも１種と、酸素と窒素のうち少なくとも１種を含む電界効果トランジスタの製造方法。 A method for producing a field effect transistor according to any one of claims 15 to 18, comprising:
A method of manufacturing a field effect transistor, wherein the insulating film includes at least one of aluminum, silicon, hafnium, zirconium, tantalum, and titanium and at least one of oxygen and nitrogen. - 請求項１５から１９のいずれかに記載の電界効果トランジスタの製造方法であって、
前記絶縁膜の膜厚が10nm以上であることを特徴とする電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to any one of claims 15 to 19,
A method of manufacturing a field effect transistor, wherein the thickness of the insulating film is 10 nm or more. - 請求項１５から２０のいずれかに記載の電界効果トランジスタの製造方法であって、
前記電位制御絶縁膜の膜厚が400nm以下であることを特徴とする電界効果トランジスタの製造方法。 A method of manufacturing a field effect transistor according to any one of claims 15 to 20,
A method of manufacturing a field effect transistor, wherein the thickness of the potential control insulating film is 400 nm or less.
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| JP2012124325A (en) * | 2010-12-08 | 2012-06-28 | Advantest Corp | Semiconductor device, test device, and manufacturing method |
| US9595594B2 (en) | 2012-06-18 | 2017-03-14 | Fujitsu Limited | Compound semiconductor device and method for manufacturing the same |
| US10784341B2 (en) | 2019-01-21 | 2020-09-22 | Northrop Grumnian Systems Corporation | Castellated superjunction transistors |
| US10804387B1 (en) * | 2019-03-21 | 2020-10-13 | Northrop Grumman Systems Corporation | Vertical superlattice transistors |
| US11342440B2 (en) | 2019-07-22 | 2022-05-24 | Northrop Grumman Systems Corporation | Passivated transistors |
| JP7438918B2 (en) | 2020-11-12 | 2024-02-27 | 株式会社東芝 | semiconductor equipment |
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| JP2002329871A (en) * | 2001-04-27 | 2002-11-15 | Telecommunication Advancement Organization Of Japan | Vertical short-channel insulated gate electrostatic induction transistor, and its manufacturing method thereof |
| JP2006140368A (en) * | 2004-11-15 | 2006-06-01 | Toyota Central Res & Dev Lab Inc | Semiconductor device and its manufacturing method |
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| JP2012124325A (en) * | 2010-12-08 | 2012-06-28 | Advantest Corp | Semiconductor device, test device, and manufacturing method |
| US9595594B2 (en) | 2012-06-18 | 2017-03-14 | Fujitsu Limited | Compound semiconductor device and method for manufacturing the same |
| US10784341B2 (en) | 2019-01-21 | 2020-09-22 | Northrop Grumnian Systems Corporation | Castellated superjunction transistors |
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| US10804387B1 (en) * | 2019-03-21 | 2020-10-13 | Northrop Grumman Systems Corporation | Vertical superlattice transistors |
| US11342440B2 (en) | 2019-07-22 | 2022-05-24 | Northrop Grumman Systems Corporation | Passivated transistors |
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