WO2009101904A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2009101904A1 WO2009101904A1 PCT/JP2009/052067 JP2009052067W WO2009101904A1 WO 2009101904 A1 WO2009101904 A1 WO 2009101904A1 JP 2009052067 W JP2009052067 W JP 2009052067W WO 2009101904 A1 WO2009101904 A1 WO 2009101904A1
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Definitions
- the present invention is based on the priority claim of Japanese patent application: Japanese Patent Application No. 2008-033305 (filed on Feb. 14, 2008), the entire contents of which are incorporated herein by reference. Shall.
- the present invention relates to a semiconductor device in which a semiconductor chip is embedded in a wiring board and a manufacturing method thereof, and more particularly to a semiconductor device suitable for connection at a narrow pitch and a manufacturing method thereof.
- a semiconductor device called a “chip-embedded substrate” in which a semiconductor chip such as a separated LSI chip is embedded in a wiring board, or an insulating resin layer and a wiring layer directly (without a bump) are provided on the semiconductor chip.
- the formed semiconductor device has attracted attention. For example, after the semiconductor chip is embedded in an insulating layer, a via is formed in the insulating layer, and a wiring electrically connected to an external terminal of the semiconductor chip through the via is formed on the insulating layer by plating or the like. To do.
- a land 106a larger than the diameter of the upper portion of the via is formed at the tip of the wiring 106 so as to cover the entire via 105a. Is generally formed (see FIG. 12).
- the performance of semiconductor chips has been increasing, the number of external terminals of the semiconductor chip has been increasing, and the pitch of external terminals has been narrowing.
- the chip-embedded substrate it is required to incorporate and mount such a narrow-pitch semiconductor chip.
- the interval between the vias 105a needs to be larger than the diameter of the lands 106a plus the distance between lands that can ensure sufficient insulation, when the land size is large, the pitch of the external terminals 104 is narrow. There is a problem that it is difficult to incorporate a chip (see FIG. 13).
- connection structure in which the land terminal wiring 206 is connected to the external terminal 204 at the bottom of the via as shown in FIG.
- connection with a narrow pitch limited only to the diameter of the via 205a is possible.
- Patent Document 1 As another structure that does not require a land, in Patent Document 1, a via-hole conductor 304 filled with metal powder and a conductor wiring layer 303 made of a metal foil connected to the via-hole conductor 304 are formed.
- Patent Document 1 Note that the entire disclosure of Patent Document 1 is incorporated herein by reference. The following analysis is given by the present invention. However, the above prior art has the following problems.
- connection area between the wiring 206 and the external terminal 204 of the semiconductor chip 201 is reduced, so that the probability of connection failure is increased and the yield is reduced. There is a problem.
- the connection area is small, there is also a problem that tolerance for misalignment between the wiring 206 and the external terminal 204 of the semiconductor chip 201 is small. Further, even when the wiring 206 and the external terminal 204 of the semiconductor chip 201 are connected at the initial stage, the wiring is caused by temperature fluctuations caused by the subsequent driving of the semiconductor chip 201, stress generated by a thermal cycle test, or the like.
- the LSI layer 203 is not sufficiently protected. Since the LSI layer 203 in the semiconductor chip 201 has low resistance to metal impurities such as copper atoms and ionic impurities such as sodium ions, when the external terminal 204 of the semiconductor chip 201 is exposed, these foreign substances are generated in the LSI layer. It becomes easy to enter the inside of the 203 and the LSI layer 203 is damaged. This is because impurities are touched not only when the external terminals 204 of the semiconductor chip 201 are exposed in the final product, but also when they are not exposed in the final product but are exposed in the middle of the process. The reliability of the final product becomes a problem.
- the chip-embedded substrate is often manufactured using an inexpensive printed wiring board that does not have a high degree of cleanliness, in this case, the probability of intrusion of impurities is further increased, and the semiconductor chip 201 as shown in FIG.
- the problem of impurities entering the LSI layer 203 is further increased.
- impurities that may affect the LSI layer 203 include an etching solution for etching the wiring seed layer and a chemical solution such as a desmear solution that roughens the surface of the insulating resin layer.
- the via-hole conductor 304 since metal powder is used in the via-hole conductor 304, it is difficult to reduce the resistance of the via-hole conductor 304 itself and the interface between the via-hole conductor 304 and the conductor wiring layer 303. There is a problem that a drive failure occurs when a semiconductor chip driven at a high frequency is embedded for high resistance. Further, since the insulating layer 302 is formed by pressing the via-hole conductor 304 containing the metal powder from above with a strong force such as a press, the semiconductor chip uses a fragile material such as a low-k material. There is a problem that the probability of occurrence of a defect is increased due to stress generated in an embedding process or a subsequent reliability test.
- the main problem of the present invention is to provide a semiconductor device that can be connected at a narrow pitch, has a high yield, and is highly reliable, and a method for manufacturing the same.
- an insulating layer is formed on a semiconductor chip having a plurality of external terminals, a plurality of wirings are formed on the insulating layer, and a plurality of vias formed in the insulating layer
- the corresponding external terminal and the wiring are electrically connected to each other through the via, and are formed so as to cover the entire bottom surface of the via and the via sidewall in the via, and are formed integrally with the wiring.
- the wiring is configured to be smaller than the via upper diameter on the via.
- a step of forming an insulating layer on a semiconductor chip having a plurality of external terminals, and a plurality of vias communicating with the external terminals are formed in the insulating layer.
- a step of forming a resist layer on the insulating layer having a wiring opening and a width of the wiring opening on the via being smaller than a via upper diameter.
- the present invention it is possible to reduce a connection pitch with a semiconductor chip, use a semiconductor chip having an external terminal with a narrow pitch, and obtain a semiconductor device with high yield and excellent reliability. There is. Further, by adopting such a structure, a stress applied to a via or the like is further relaxed, and a semiconductor device having excellent reliability can be obtained.
- FIG. 1A is a cross-sectional view schematically showing a configuration of a semiconductor device according to Example 1 of the present invention
- FIG. It is the top view which showed typically an example of the wiring pattern of the semiconductor device which concerns on Example 1 of this invention. It is the top view which showed typically the modification of the wiring pattern of the semiconductor device which concerns on Example 1 of this invention.
- FIG. 6 is a cross-sectional view schematically showing a configuration of a modification of the semiconductor device according to the first embodiment of the present invention and a top view of wiring. It is sectional drawing which showed typically the structure of the modification of the semiconductor device which concerns on Example 1 of this invention. It is the 1st process sectional view showing the manufacturing method of the semiconductor device concerning Example 1 of the present invention.
- FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Conventional Example 1, and a top view of wiring.
- FIG. 10 is a top view schematically showing the arrangement of wirings, lands, and vias in a semiconductor device according to Conventional Example 1.
- FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Conventional Example 2, and a top view of wiring. It is sectional drawing which showed typically the structure of the multilayer wiring board semiconductor device which concerns on the prior art example 3.
- FIG. 6 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Conventional Example 2, and a top view of wiring. It is sectional drawing which showed typically the structure of the multilayer wiring board semiconductor device which concerns on the prior art example 3.
- an insulating layer (5 in FIG. 1) is formed on a semiconductor chip (1 in FIG. 1) having a plurality of external terminals (4 in FIG. 1).
- a plurality of wirings (6 in FIG. 1) are formed on (5 in FIG. 1), and the corresponding external terminals (5a in FIG. 1) are formed through a plurality of vias (5a in FIG. 1) formed in the insulating layer (5 in FIG. 1).
- 4 is a semiconductor device in which the wiring (6 in FIG. 1) is electrically connected, and is formed so as to cover the bottom surface of the via and the entire via sidewall in the via (5a in FIG. 1).
- a via conductive portion (6a in FIG. 1) formed integrally with the wiring (6 in FIG.
- the wiring (6 in FIG. 1) is smaller than the via upper diameter on the via. Composed. Furthermore, the following forms are also possible. It is preferable that the peripheral edge of the via on the insulating layer does not have a land. Preferably, the via conductive portion is completely embedded in the via. It is preferable that the wiring has a circular or elliptical shape on the via, and a diameter or a long diameter thereof is smaller than a via upper diameter. The circular diameter or the major axis of the ellipse is preferably 1/3 or more and 2/3 or less of the via upper diameter. It is preferable that the tip of the wiring on the via does not extend to the center of the via.
- the via conductive portion has one or a plurality of convex portions separated from a tip portion of the wiring on the via and integrated with the via conductive portion.
- the planar shape of the via is preferably an ellipse, an ellipse, or a shape in which a plurality of circles are connected.
- an insulating layer (FIG. 6B) is formed on a semiconductor chip (1 in FIG. 6B) having a plurality of external terminals (4 in FIG. 6B). 5) and a plurality of vias (5a in FIG. 6C) communicating with the external terminals (4 in FIG. 6C) are formed in the insulating layer (5 in FIG. 6C). And forming a wiring opening on the insulating layer (6 in FIG. 7A) and the width of the wiring opening on the via (5a in FIG. 7A). Forming a resist layer (9 in FIG. 7A) configured to be smaller than the via upper diameter, and using the resist layer (9 in FIG.
- the insulating layer (FIG. 7 (B) 5), via conductive portion (6a in FIG. 7B) covering the via bottom and via side wall and wiring (6 in FIG. 7B) are integrated with each other.
- a step of forming the. Furthermore, the following forms are also possible.
- the step of forming the resist layer it is preferable to form the resist layer using a film-like resist. It is preferable that the wiring opening on the via of the resist layer is circular or elliptical and has a diameter or major axis smaller than the via upper diameter.
- the opening for the wiring on the via of the resist layer has a circular diameter or an elliptical major axis that is 1/3 or more and 2/3 or less of the via upper diameter. It is preferable to be formed so that In the step of forming the resist layer, the wiring opening on the via of the resist layer is preferably formed so as not to extend to the center of the via. In the step of forming the resist layer, the wiring opening on the via of the resist layer is formed so as to be separated from an opening connected to the wiring opening on the insulating layer of the resist layer. It is preferred that In the step of forming the resist layer, the wiring openings on the vias of the resist layer are preferably formed to be a plurality of regions. In the step of forming the via, the planar shape of the via is preferably formed in an elliptical shape, an oval shape, or a shape in which a plurality of circles are connected.
- FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to Example 1 of the present invention, and a top view of wiring.
- FIG. 2 is a plan view schematically showing an example of a wiring pattern of the semiconductor device according to the first embodiment of the present invention. Although there are a considerable number of vias 5a on the semiconductor chip 1, only one is shown in FIG.
- the insulating layer 5 is formed on the semiconductor chip 1 having the external terminals 4, and the wiring 6 is formed on the insulating layer 5.
- a plurality of vias 5a are formed in an insulating layer 5, and a via conductive portion 6a made of a conductive material that electrically connects the external terminal 4 and the wiring 6 of the semiconductor chip 1 is filled in the via 5a.
- the via conductive portion 6a is formed so as to cover the entire bottom surface of the via and almost the entire sidewall of the via.
- the width of the wiring 6 is smaller than the via upper diameter, and is formed integrally with the via conductive portion 6a.
- the via upper diameter means the diameter of the upper part of the via 5a, and is generally larger than the bottom of the via when formed by laser or exposure / development, but is not limited thereto.
- the integral formation means that there is no interface between the wiring 6 and the via conductive portion 6a by being formed in one step by plating or the like.
- a semiconductor element such as an LSI (LSI layer 3) is formed on the semiconductor layer 2, and an external terminal 4 is formed at a predetermined position on the LSI layer 3.
- the semiconductor chip 1 is a semiconductor wafer in which LSI layers 3 are collectively formed and separated into individual pieces by dicing or the like.
- the external terminals 4 are generally formed before dicing or the like, but can also be formed after dicing.
- the external terminal 4 is a terminal for electrically connecting the LSI layer 3 formed near the chip surface and the outside, and is also called a semiconductor pad or the like.
- the external terminal 4 is connected to any one of a power source, a ground, a signal, and the like.
- the external terminal 4 may be made of a material mainly containing Al, a material mainly containing Cu, or the like, but is not limited thereto.
- the insulating layer 5 for example, either a non-photosensitive resin or a photosensitive resin can be used, and a ceramic material can also be used.
- Most of the sheet-like resin materials used for the insulating layer 5 are non-photosensitive resins, and the non-photosensitive resin is widely used as a sheet-like insulating material used for printed wiring boards and the like, so the production amount is also large. Many costs can be reduced.
- the non-photosensitive resin and the photosensitive resin may contain an inorganic filler such as a silica filler or an organic filler.
- the via 5a can be formed by laser light irradiation when the insulating layer 5 is a non-photosensitive resin.
- the via 5a can be formed by a drill.
- a laser is generally used for forming the via 5a.
- an excimer laser or the like can be used in addition to the Nd-YAG laser and the CO 2 laser. Since the via 5a formed on the semiconductor chip 1 is smaller than the via used in the printed wiring board, an Nd-YAG laser (third harmonic) or excimer laser capable of forming a via of several tens of microns or less is particularly desirable.
- the via 5a can be formed by an exposure / development process. Even in the case of the exposure / development process, the fine via 5a can be formed.
- Examples of the wiring 6 include a plating material such as copper plating.
- the wiring 6 may be a single layer or a plurality of layers. Further, a resin layer may be formed on the uppermost layer so as to cover at least a part of the wiring.
- the conductive material in the via 5a is formed so as to cover the entire bottom surface of the via and the side wall of the via, so that the thin wiring as in the conventional example 2 (see FIG. 14).
- the external terminals 4 etc. of the semiconductor chip 1 are not exposed at the bottom of the vias, so that the chemical liquid etc. do not touch the external terminals 4 etc. of the semiconductor chip 1 in the subsequent process.
- a semiconductor device excellent in the above can be obtained.
- the wiring 6 on the via is smaller than the diameter of the upper portion of the via 5a, and there is no land structure as in the conventional example 1 (see FIG. 13).
- the diameter of the via Therefore, the via pitch can be reduced to the limit of the via diameter and the minimum via interval, and vias with a narrow pitch can be connected (see FIG. 2).
- the semiconductor chip 1 having a small pitch of the external terminals 4 can be incorporated in the semiconductor device. That is, since a pitch interval is generally small in a semiconductor chip having a large number of terminals, this means that even a multi-pin type semiconductor chip that has been difficult to incorporate in the past can be incorporated without any problem.
- the wiring 6 is narrower than the via 5a and the via conductive portion 6a is filled or close to the structure, the wiring 6 is positioned at the position of the via 5a as shown in FIG. Even when formed with a deviation from the above, there is an advantage that the external terminal 4 of the semiconductor chip 1 is electrically connected without any problem and a short circuit does not occur between the adjacent vias 5a.
- the wiring 6 and the via conductive portion 6a are integrally formed, there is no interface between the wiring 6 and the via conductive portion 6a, and the connection strength is high. The connection strength in this part does not become a problem.
- the via conductive portion 6a is formed first and then the wiring 6 is formed (comparative example), an interface is formed between the via conductive portion 6a and the wiring 6, so that peeling or the like occurs. Becomes lower.
- the stress on the wiring 6 is difficult to reach the bottom of the via. There is an effect that peeling at the interface of the external terminal 4 hardly occurs.
- the via 5a may be completely filled with the via conductive portion 6a as shown in FIG. 1 as long as the entire bottom surface of the via and the entire side wall of the via are covered. As shown in FIG. 4, the via conductive portion 6a may not be completely filled in the via 5a.
- FIG. 1 shows only a single-layer wiring structure, but there may be a plurality of wirings 6 and insulating layers 5 on the wiring 6 as shown in FIG. May be.
- a stacked via with stacked vias can be formed, so that a semiconductor device having a stacked via with a narrow pitch and high reliability can be obtained.
- FIGS. 6 and 7 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
- the semiconductor chip 1 having the external terminals 4 (there are actually many, but only one is shown in the figure) is mounted on, for example, the support plate 8 (step A1; see FIG. 6A).
- the semiconductor chip 1 is embedded in the insulating layer 5 by forming the insulating layer 5 such as resin on the support plate 8 including the semiconductor chip 1 (step A2; see FIG. 6B).
- the insulating layer 5 made of a non-photosensitive resin is formed on the semiconductor chip 1, the insulating layer 5 is not necessarily formed on the active surface (LSI layer 3) of the semiconductor chip 1. Also included is a method of mounting the semiconductor chip 1 with the active surface facing downward on the insulating layer 5 prepared in advance. In this case, the support plate 8 is not required.
- vias 5a communicating with the external terminals 4 of the semiconductor chip 1 are formed in the insulating layer 5 by a laser or the like (step A3; see FIG. 6C).
- a resist layer 9 is formed on the insulating layer 5 for forming a wiring and forming a conductive material in the via (step A4; see FIG. 6D).
- the resist layer 9 is a plating resist.
- a seed layer (not shown) is required in the plating step of FIG. 7B, the seed layer is formed before the resist layer 9 is formed.
- the seed layer may be formed by sputtering or the like, or may be formed by electroless plating or the like.
- the resist layer 9 can also be a film resist.
- the resist includes a varnish resist and a film resist.
- the film-like resist is a resist that has been processed into a film shape in advance, and is stuck on the insulating layer 5 with a laminator or the like.
- An example of a film-like resist is a so-called dry film resist.
- the via 5a can be prevented from being filled with the resist, and the via 5a can be left in the plating process while being hollow. Thus, the cavity is filled with plating in the plating step.
- the varnish-like resist when the varnish is formed on the insulating layer, the varnish droops and fills the inside of the via, so that it cannot be used in the semiconductor device manufacturing method according to the first embodiment in principle.
- the semiconductor device according to the first embodiment it can be used in the manufacturing method.
- the resist layer 9 is patterned (step A5; see FIG. 7A).
- the opening of the resist layer 9 is formed in accordance with the shape of the wiring (6 in FIG. 7B) and the position of the via 5a, but the wiring on the via 5a (6 in FIG. 7B) is formed.
- the width of the opening is set to be smaller than the via upper diameter.
- the opening refers to a vacant portion of the resist layer 9 and can be formed by exposing and developing the resist layer 9.
- the opening may be circular or elliptical at the tip of the wiring.
- the wiring 6 and the via conductive portion 6a are integrally formed by a plating process or the like (step A6; see FIG. 7B).
- the integral formation means that the conductive layer of the wiring 6 and the via conductive portion 6a is formed in one process by plating or the like, thereby reducing the number of processes.
- the interface is not formed between the wiring 6 and the via conductive portion 6a by being formed integrally, a semiconductor device having excellent reliability can be obtained without causing peeling at the interface.
- the via bottom surface and the via sidewall are covered with the via conductive portion 6a.
- the resist layer (9 in FIG. 7B) is removed (step A7; see FIG. 7C).
- the seed layer is removed after the resist layer (9 in FIG. 7B) is peeled off. Perform removal. Thereafter, by removing the support plate 8, a semiconductor device similar to that shown in FIG. 1 can be obtained.
- a semiconductor chip (Specific example 1) using an FR4 substrate as a support plate (8 in FIG. 6A) and having external terminals (4 in FIG. 6A) on the support plate (8 in FIG. 6A). 1) was mounted and fixed. The number of external terminals 4 of the semiconductor chip 1 was about 800.
- Vias (5a in FIG. 6C) were opened at a pitch of 60 ⁇ m using a UV-YAG laser. After the desmear process, when the size of the via (5a in FIG. 6C) was measured, the upper part was 50 ⁇ m and the lower part was 30 ⁇ m.
- a resist layer (9 in FIG. 6D) made of a dry film was attached with a laminator. Exposure is performed using a mask (not shown) formed in advance with a wiring pattern having a width of 20 ⁇ m (the tip portion remains 20 ⁇ m) at a pitch of 60 ⁇ m, followed by development, and wiring made of copper plating (FIG.
- the semiconductor chip (1 in FIG. 6A) is mounted on the support plate (8 in FIG. 6A), the insulating layer (5 in FIG. 6B) is formed, and the vias are formed. (5a in FIG. 6C) was formed, and a resist layer (9 in FIG. 6D) made of a dry film was attached.
- this time intentionally shifting the mask by about 15 ⁇ m, developing, developing, wiring (6 in FIG. 7B) and via conductive layer (FIG. 7 ( B) 6a) was formed, and then the resist layer (9 in FIG. 7B) was removed to form a wiring 6 shifted as shown in FIG.
- the wiring 6 was considerably displaced from the center of the via 5a, but there was no short circuit between the adjacent wirings 6. Further, when a cross-sectional sample was prepared and observed, it was confirmed that the entire via 5a was filled with the via conductive portion 6a.
- Example 1 Similar to Example 1, the semiconductor chip was mounted on a support plate, an insulating layer was formed, a via was formed, and a resist layer made of a dry film was attached. As an exposure mask, exposure is performed using a mask (not shown) in which a 50 ⁇ m land (106a in FIG. 12) is formed at the tip of the wiring (106 in FIG. 12) as shown in FIG. 12) and lands (106a in FIG. 12) were formed, and then the resist layer was removed to form wiring (106 in FIG. 12) having lands (106a in FIG. 12) as shown in FIG. . When the fabricated semiconductor device was observed, it was observed that the land (106a in FIG. 12) and the adjacent wiring (106a in FIG. 12) were short-circuited depending on the location.
- Example 2 A semiconductor device was fabricated in the same manner as in Example 1 except that a varnish resist was used as the plating resist. When the manufactured semiconductor device was observed, the wiring passed almost through the center of the via, but it was confirmed that the external terminals of the semiconductor chip were exposed.
- the connection can be made with the minimum pitch limited by the via size, As shown in FIG. 2, the wiring 6 can be connected to the narrow pitch vias 5a.
- the opening is formed in the plating resist layer so as to be wider than the region of the via 105a as shown in FIG. 13, this opening limits the pitch of the via. It is difficult to connect wiring to vias with a narrow pitch.
- the via conductive portion 6a is filled in the entire via 5a, even when the position of the opening of the resist layer 9 is displaced, as shown in FIG. There is an advantage that the connection between the wiring 6 and the via conductive portion 6a is secured.
- the wiring 6 and the via conductive portion 6a are integrally formed by a plating process or the like, and therefore, compared with the method of forming the wiring and the via conductive portion separately, In addition to simplification, there is no interface between the wiring and the via conductive part, no peeling occurs between the wiring and the via conductive part, the connection strength between the wiring and the via conductive part is strong, and connection reliability It is possible to manufacture an excellent semiconductor device.
- the semiconductor chip 1 at the bottom of the via is not exposed and the semiconductor chip 1 is exposed.
- the surface is not touched by a chemical solution and the reliability is excellent.
- the via conductive portion 6a is completely filled in the via.
- a highly reliable stacked via can be formed at a pitch.
- the entire surface of the via bottom and the side wall surface is covered, so that the external terminal 4 of the semiconductor chip 1 is not exposed and the interface is not exposed. The penetration of the liquid through is also suppressed.
- FIG. 8 is a plan view schematically showing the positional relationship between wirings and vias of the semiconductor device according to the second embodiment of the present invention.
- the tip shape of the wiring 6 on the via conductive portion 6a is circular (see FIG. 8A) or elliptical (see FIG. 8B), and the diameter or long diameter thereof is a via. It is configured to be smaller than the upper diameter. Further, the circular diameter or elliptical major axis of the tip shape of the wiring 6 is not less than 1/3 and not more than 2/3 of the via upper diameter. Other configurations are the same as those of the first embodiment (see FIG. 1).
- step A5 of the first embodiment vias (FIG. 7A) corresponding to openings in the resist layer (corresponding to 9 in FIG. 7A) are formed.
- the upper shape is circular or elliptical, and the diameter or major axis is smaller than the via upper diameter. Further, the circular diameter or the elliptical major axis of the opening of the resist layer (corresponding to 9 in FIG. 7A) is set to 1/3 or more and 2/3 or less of the via upper part diameter.
- Other steps are the same as those in the first embodiment (see FIGS. 6 and 7).
- the shape of the tip of the wiring 6 being circular or elliptical means that the shape of the tip of the wiring 6 on the via conductive portion 6a is circular or elliptical.
- the same effects as those of the first embodiment can be obtained, and since the wiring 6 is smaller than the via upper diameter, the connection at a narrow pitch is possible, and the connection area is increased with a high yield. Since it is large, a highly reliable semiconductor device can be obtained. Further, the symmetry is better than the wiring having a rectangular tip, and the stress is evenly distributed and the reliability is improved.
- the same effects as those of the first embodiment are obtained, and the circular or elliptical diameter or long diameter of the opening of the resist layer (corresponding to 9 in FIG. 7A) is obtained.
- the diameter By making the diameter smaller than the via upper diameter, it becomes possible to connect at a narrow pitch as far as the via size is limited as shown in FIG. 2, and even if an exposure deviation occurs as shown in FIG. And short circuit with vias are suppressed. Further, there is an advantage that the inside of the via is not filled by reducing the opening.
- the shape of the opening of the resist layer (corresponding to 9 in FIG.
- the distance from the opening to the via sidewall is shortened, and plating on the via sidewall is performed. Will be better. Furthermore, when the opening is elliptical, the connection with the adjacent wiring can be reduced while increasing the area of the opening.
- FIG. 9 is a plan view schematically showing the positional relationship between wirings and vias in the semiconductor device according to Example 3 of the present invention.
- the semiconductor device according to Example 3 is configured such that the wiring 6 does not extend to the center of the via 5a.
- Other configurations are the same as those of the first embodiment (see FIG. 1).
- step A5 in the method of manufacturing a semiconductor device according to the third embodiment, a via (see FIG. 7A) in the opening of the resist layer (corresponding to 9 in FIG. 7A). 7 (A) corresponding to 5a) is not extended to the center of the via 5a. Other steps are the same as those in the first embodiment (see FIGS. 6 and 7).
- the same effects as those of the first embodiment can be obtained, and connection at a narrow pitch is possible. Further, according to the method of manufacturing a semiconductor device according to the third embodiment, the same effects as those of the first embodiment can be obtained, and the via 5a can be suppressed from being filled with the resist layer (corresponding to 9 in FIG. 7A).
- FIG. 10 is a plan view schematically showing the positional relationship between wirings and vias in a semiconductor device according to Example 4 of the present invention.
- one or a plurality of convex portions 6b that are separated from the tip end portion of the wiring 6 and integrated with the via conductive portion 6a are formed on the via conductive portion 6a.
- the wiring 6 may be connected to some of the convex portions 6b (see FIG. 10B).
- Other configurations are the same as those of the first embodiment (see FIG. 1).
- vias (see FIG. 7A) of the resist layer (corresponding to 9 in FIG. 7A) are obtained in step A5 of the first embodiment (see FIG. 7A).
- 7 (A) is equivalent to 5a) in which the pattern for the convex portion 6b is separated from the pattern for the wiring 6.
- Other steps are the same as those in the first embodiment (see FIGS. 6 and 7).
- the stress applied to the vias is alleviated and a semiconductor device having excellent reliability can be obtained.
- the shape of the opening in the resist layer (corresponding to 9 in FIG. 7A) on the via (corresponding to 5a in FIG. 7A) is By making the pattern for the convex portion 6b separated from the pattern for the wiring 6, the resist layer (corresponding to 9 in FIG. 7A) works to support each other, and the resist enters the via 5a. Is suppressed.
- FIG. 11 is a plan view schematically showing the positional relationship between wirings and vias in a semiconductor device according to Example 5 of the present invention.
- the planar shape of the via 5a is an ellipse (see FIG. 11A), an ellipse, or a shape in which a plurality of circles are connected (see FIG. 11B). It is composed.
- the tip shape of the wiring 6 on the via conductive portion 6a is made circular or elliptical, and is equal to or less than the circular diameter or elliptical major axis. As long as a part of the tip shape of the wiring 6 is within the range of the width (width in the short direction) of the via conductive portion 6a, the region of the via conductive portion 6a may protrude.
- a plurality of convex portions (6b in FIG. 4) may be formed on the via conductive portion 6a so as to be separated from the tip portion of the wiring 6.
- Other configurations are the same as those of the first embodiment (see FIG. 1).
- the planar shape of the via 5a is elliptical (see FIG. 11A) in Step A3 of the first embodiment (see FIG. 6C), or a plurality of vias are formed.
- the circles are connected to each other (see FIG. 11B).
- step A5 of Example 1 see FIG. 7A
- Other steps are the same as those in the first embodiment (see FIGS. 6 and 7).
- a semiconductor device having a high tolerance with respect to a positional shift in the wiring direction and an excellent yield can be obtained. Further, by forming a plurality of convex portions (6b in FIG. 10) separately from the tip portion of the wiring 6, a semiconductor device having a moderately distributed stress and excellent reliability can be obtained.
- the tip end portion of the wiring 6 refers to a portion existing on the via 5a of the wiring. Since this portion is small, connection at a narrow pitch is possible up to the point where the via size is limited.
- the via 5a is formed of an ellipse, an ellipse, or a plurality of circles, there is an advantage that the tolerance for the deviation in the wiring direction is increased.
- a semiconductor device in which a multi-pin semiconductor chip used for a mobile phone, an electric device or the like is built in a substrate.
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Abstract
Description
本発明は、日本国特許出願:特願2008-033305号(2008年2月14日出願)の優先権主張に基づくものであり、同出願の全記載内容は引用をもって本書に組み込み記載されているものとする。
本発明は、半導体チップを配線基板に埋め込んだ半導体装置及びその製造方法に関し、特に、狭ピッチでの接続に適した半導体装置及びその製造方法に関する。
しかしながら、上記従来技術においては、以下のような課題がある。
2、102、202 半導体層
3、103、203 LSI層
4、104、204 外部端子
5、105、205 絶縁層
5a、105a、205a ビア
6、106、206 配線
6a ビア導電部
6b 凸部
8 支持板
9 レジスト層
106a ランド
301 多層配線基板
302 絶縁層
303 導体配線層
304 バイアホール導体
さらに、以下の形態も可能である。
前記絶縁層上の前記ビアの周縁部にランドを有さないことが好ましい。
前記ビア導電部は、前記ビア内に完全に埋め込まれていることが好ましい。
前記配線は、前記ビア上の形状が円形または楕円形であり、その直径または長径がビア上部径よりも小さいことが好ましい。
前記円形の直径または前記楕円形の長径が、前記ビア上部径の1/3以上2/3以下であることが好ましい。
前記配線の前記ビア上の先端部は、前記ビアの中央まで延在していないことが好ましい。
前記ビア導電部上において前記配線の前記ビア上の先端部と分離して前記ビア導電部と一体となった1又は複数の凸部を有することが好ましい。
前記ビアの平面形状は、楕円状又は長円状もしくは複数の円が繋がった形状になっていることが好ましい。
さらに、以下の形態も可能である。
前記レジスト層を形成する工程において、フィルム状のレジストを用いて前記レジスト層を形成することが好ましい。
前記レジスト層の前記ビア上の前記配線用の開口部は、円形または楕円形であり、かつ、その直径または長径がビア上部径よりも小さくなるように形成されることが好ましい。
前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、前記円形の直径または前記楕円形の長径が、前記ビア上部径の1/3以上2/3以下となるように形成されることが好ましい。
前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、前記ビアの中央まで延在しないように形成されることが好ましい。
前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、前記レジスト層の前記絶縁層上の前記配線用の開口部と繋がる開口部と分離するように形成されることが好ましい。
前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、複数の領域となるように形成されることが好ましい。
前記ビアを形成する工程において、前記ビアの平面形状が楕円状、又は長円状、若しくは複数の円が繋がった形状に形成されることが好ましい。
支持板(図6(A)の8)としてFR4基板を用い、支持板(図6(A)の8)上に外部端子(図6(A)の4)を有する半導体チップ(図6(A)の1)を搭載して固定した。半導体チップ1の外部端子4の数は約800であった。半導体チップ(図6(B)の1)を搭載した支持板(図6(B)の8)上にBステージの非感光性樹脂フィルムよりなる絶縁層(図6(B)の5)を貼り合わせ、熱硬化させた。絶縁層(図6(A)の5)に埋もれた半導体チップ(図6(C)の1)の外部端子(図6(C)の4)の位置にビア(図6(C)の5a)が形成されるようUV-YAGレーザを用いて60μmピッチでビア(図6(C)の5a)を開口した。デスミア処理後、ビア(図6(C)の5a)のサイズを計測すると上部50μm、下部30μmであった。スパッタでCuシード層(図示せず)を形成した後、ドライフィルムよりなるレジスト層(図6(D)の9)をラミネータで貼り付けた。予め作製しておいた60μmピッチで幅20μmの配線パターン(先端部も20μmのまま)が形成されたマスク(図示せず)を用いて露光し、その後、現像し、銅めっきよりなる配線(図7(B)の6)及びビア導電層(図7(B)の6a)を形成し、その後、レジスト層(図7(B)の9)の除去を行った。作製した半導体装置を観察すると配線6の先端部がビア5aのほぼ中央まで伸びており、半導体チップ1の外部端子4はビア導電部6aの下に隠れて見えなかった。断面サンプルを作製して観察すると、ビア5a全体がビア導電部6aで充填されているのが確認できた。また、電気試験より隣り合う配線間では短絡が起きていないことを確認した。
具体例1と同様に、半導体チップ(図6(A)の1)を支持板(図6(A)の8)に搭載し、絶縁層(図6(B)の5)を形成し、ビア(図6(C)の5a)を形成し、ドライフィルムよりなるレジスト層(図6(D)の9)を貼り付けた。具体例1と同じマスク(図示せず)を用いて、今回は意図的に約15μmマスクをずらして露光し、現像し、配線(図7(B)の6)及びビア導電層(図7(B)の6a)を形成し、その後、レジスト層(図7(B)の9)の除去を行い、図3のようにずれた配線6を形成した。作製した半導体装置1を観察すると配線6がビア5aの中央からかなりずれていたが、隣り合う配線6間での短絡はなかった。また断面サンプルを作製して観察するとビア5a全体がビア導電部6aで充填されているのが確認できた。
具体例1と同様に半導体チップを支持板に搭載し、絶縁層を形成し、ビアを形成し、ドライフィルムよりなるレジスト層を貼り付けた。露光マスクとして図12のように配線(図12の106)の先端に50μmのランド(図12の106a)を形成するようにしたマスク(図示せず)を用いて露光し、現像し、配線(図12の106)及びランド(図12の106a)を形成し、その後、レジスト層の除去を行い、図12のようにランド(図12の106a)を有する配線(図12の106)を形成した。作製した半導体装置を観察すると場所によりランド(図12の106a)と隣の配線(図12の106a)が短絡しているのが観察できた。
めっきレジストとしてワニスのレジストを使用する以外は、具体例1と同様に半導体装置を作製した。作製した半導体装置を観察すると配線はビアのほぼ中央を通っていたが、半導体チップの外部端子が露出しているのが確認できた。
Claims (16)
- 複数の外部端子を有する半導体チップ上に絶縁層が形成されるとともに、前記絶縁層上に複数の配線が形成され、前記絶縁層に形成された複数のビアを通じて対応する前記外部端子と前記配線が電気的に接続された半導体装置であって、
前記ビア内においてビア底面およびビア側壁の全面を覆うように形成されるとともに、前記配線と一体的に形成されるビア導電部を備え、
前記配線は、前記ビア上においてビア上部径よりも小さく構成されていることを特徴とする半導体装置。 - 前記絶縁層上の前記ビアの周縁部にランドを有さないことを特徴とする請求項1記載の半導体装置。
- 前記ビア導電部は、前記ビア内に完全に埋め込まれていることを特徴とする請求項1又は2記載の半導体装置。
- 前記配線は、前記ビア上の形状が円形または楕円形であり、その直径または長径がビア上部径よりも小さいことを特徴とする請求項1乃至3のいずれか一に記載の半導体装置。
- 前記円形の直径または前記楕円形の長径が、前記ビア上部径の1/3以上2/3以下であることを特徴とする請求項4記載の半導体装置。
- 前記配線の前記ビア上の先端部は、前記ビアの中央まで延在していないことを特徴とする請求項1乃至5のいずれか一に記載の半導体装置。
- 前記ビア導電部上において前記配線の前記ビア上の先端部と分離して前記ビア導電部と一体となった1又は複数の凸部を有することを特徴とする請求項1乃至6のいずれか一に記載の半導体装置。
- 前記ビアの平面形状は、楕円状又は長円状もしくは複数の円が繋がった形状になっていることを特徴とする請求項1乃至7のいずれか一に記載の半導体装置。
- 複数の外部端子を有する半導体チップ上に絶縁層を形成する工程と、
前記絶縁層に、前記外部端子に通ずる複数のビアを形成する工程と、
前記絶縁層上に、配線用の開口部を有するとともに、前記ビア上の前記配線用の開口部の幅がビア上部径より小さくなるように構成されたレジスト層を形成する工程と、
前記レジスト層をマスクとして、前記絶縁層上にビア底面およびビア側壁を覆うビア導電部と、配線とを一体的に形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 前記レジスト層を形成する工程において、フィルム状のレジストを用いて前記レジスト層を形成することを特徴とする請求項9記載の半導体装置の製造方法。
- 前記レジスト層の前記ビア上の前記配線用の開口部は、円形または楕円形であり、かつ、その直径または長径がビア上部径よりも小さくなるように形成されることを特徴とする請求項9又は10記載の半導体装置の製造方法。
- 前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、前記円形の直径または前記楕円形の長径が、前記ビア上部径の1/3以上2/3以下となるように形成されることを特徴とする請求項11記載の半導体装置の製造方法。
- 前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、前記ビアの中央まで延在しないように形成されることを特徴とする請求項9乃至12のいずれか一に記載の半導体装置の製造方法。
- 前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、前記レジスト層の前記絶縁層上の前記配線用の開口部と繋がる開口部と分離するように形成されることを特徴とする請求項9乃至13のいずれか一に記載の半導体装置の製造方法。
- 前記レジスト層を形成する工程において、前記レジスト層の前記ビア上の前記配線用の開口部は、複数の領域となるように形成されることを特徴とする請求項9乃至14のいずれか一に記載の半導体装置の製造方法。
- 前記ビアを形成する工程において、前記ビアの平面形状が楕円状、又は長円状、若しくは複数の円が繋がった形状に形成されることを特徴とする請求項9乃至15のいずれか一に記載の半導体装置の製造方法。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110074041A1 (en) * | 2009-09-30 | 2011-03-31 | Leung Andrew Kw | Circuit Board with Oval Micro Via |
JP2011176209A (ja) * | 2010-02-25 | 2011-09-08 | Renesas Electronics Corp | 半導体装置の製造方法 |
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JP2010103435A (ja) * | 2008-10-27 | 2010-05-06 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
JP2010199318A (ja) * | 2009-02-25 | 2010-09-09 | Kyocera Corp | 配線基板及びそれを備えた実装構造体 |
JPWO2011024939A1 (ja) * | 2009-08-28 | 2013-01-31 | 日本電気株式会社 | 半導体装置およびその製造方法 |
JP5923326B2 (ja) * | 2012-02-08 | 2016-05-24 | 株式会社ジャパンディスプレイ | 回路基板およびその製造方法、ならびに電気光学装置 |
EP3935923A1 (en) * | 2019-03-06 | 2022-01-12 | TTM Technologies, Inc. | Methods for fabricating printed circuit board assemblies with high density via array |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003198085A (ja) * | 2001-12-25 | 2003-07-11 | Shinko Electric Ind Co Ltd | 回路基板およびその製造方法 |
JP2003218278A (ja) * | 2002-01-28 | 2003-07-31 | Nec Corp | ウェーハレベル・チップスケール・パッケージの製造方法 |
JP2007165497A (ja) * | 2005-12-13 | 2007-06-28 | Dainippon Printing Co Ltd | 多層配線基板 |
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US5578526A (en) * | 1992-03-06 | 1996-11-26 | Micron Technology, Inc. | Method for forming a multi chip module (MCM) |
US6976238B1 (en) * | 2001-06-03 | 2005-12-13 | Cadence Design Systems, Inc. | Circular vias and interconnect-line ends |
-
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JP2003198085A (ja) * | 2001-12-25 | 2003-07-11 | Shinko Electric Ind Co Ltd | 回路基板およびその製造方法 |
JP2003218278A (ja) * | 2002-01-28 | 2003-07-31 | Nec Corp | ウェーハレベル・チップスケール・パッケージの製造方法 |
JP2007165497A (ja) * | 2005-12-13 | 2007-06-28 | Dainippon Printing Co Ltd | 多層配線基板 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110074041A1 (en) * | 2009-09-30 | 2011-03-31 | Leung Andrew Kw | Circuit Board with Oval Micro Via |
US8445329B2 (en) * | 2009-09-30 | 2013-05-21 | Ati Technologies Ulc | Circuit board with oval micro via |
JP2011176209A (ja) * | 2010-02-25 | 2011-09-08 | Renesas Electronics Corp | 半導体装置の製造方法 |
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