WO2009069791A1 - 配線基板、実装構造体及び配線基板の製造方法 - Google Patents

配線基板、実装構造体及び配線基板の製造方法 Download PDF

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Publication number
WO2009069791A1
WO2009069791A1 PCT/JP2008/071741 JP2008071741W WO2009069791A1 WO 2009069791 A1 WO2009069791 A1 WO 2009069791A1 JP 2008071741 W JP2008071741 W JP 2008071741W WO 2009069791 A1 WO2009069791 A1 WO 2009069791A1
Authority
WO
WIPO (PCT)
Prior art keywords
wiring substrate
conductor
manufacturing
mounting structure
conductor portion
Prior art date
Application number
PCT/JP2008/071741
Other languages
English (en)
French (fr)
Inventor
Tadashi Nagasawa
Katsura Hayashi
Original Assignee
Kyocera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corporation filed Critical Kyocera Corporation
Priority to US12/745,223 priority Critical patent/US8431832B2/en
Priority to JP2009543892A priority patent/JP5066192B2/ja
Publication of WO2009069791A1 publication Critical patent/WO2009069791A1/ja

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0209—Inorganic, non-metallic particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09863—Concave hole or via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

　本発明の一実施形態に係る配線基板２は、ビア導体１０が埋設されている絶縁層７を有している。ビア導体１０は、上部よりも下部が幅狭な第１導体部１０ａと、第１導体部１０ａの直下に形成され、第１導体部１０ａと接続されるとともに、第１導体部１０ａの上端幅よりも最大幅が幅広な第２導体部１０ｂと、を含んでいる。絶縁層７は、ビア導体１０と接する表面に複数の凹部Ｔ１ａ，Ｔ１ｂを有し、凹部Ｔ１ａ，Ｔ１ｂにビア導体の凸部Ｔ２ａ，Ｔ２ｂが配されている。  
PCT/JP2008/071741 2007-11-28 2008-11-28 配線基板、実装構造体及び配線基板の製造方法 WO2009069791A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/745,223 US8431832B2 (en) 2007-11-28 2008-11-28 Circuit board, mounting structure, and method for manufacturing circuit board
JP2009543892A JP5066192B2 (ja) 2007-11-28 2008-11-28 配線基板及び実装構造体

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007307097 2007-11-28
JP2007-307097 2007-11-28
JP2007-331877 2007-12-25
JP2007331877 2007-12-25

Publications (1)

Publication Number Publication Date
WO2009069791A1 true WO2009069791A1 (ja) 2009-06-04

Family

ID=40678680

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/071741 WO2009069791A1 (ja) 2007-11-28 2008-11-28 配線基板、実装構造体及び配線基板の製造方法

Country Status (3)

Country Link
US (1) US8431832B2 (ja)
JP (1) JP5066192B2 (ja)
WO (1) WO2009069791A1 (ja)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011100797A (ja) * 2009-11-04 2011-05-19 Panasonic Electric Works Co Ltd 回路基板
CN102484950A (zh) * 2009-08-24 2012-05-30 株式会社村田制作所 树脂多层基板以及该树脂多层基板的制造方法
JP2013110230A (ja) * 2011-11-18 2013-06-06 Fujitsu Ltd 積層回路基板の製造方法、積層回路基板、および電子機器
JP2014131029A (ja) * 2012-12-31 2014-07-10 Samsung Electro-Mechanics Co Ltd 回路基板及びその製造方法
JP2014232853A (ja) * 2013-05-30 2014-12-11 京セラ株式会社 多層配線基板およびプローブカード用基板
JP2015008261A (ja) * 2013-05-28 2015-01-15 京セラサーキットソリューションズ株式会社 配線基板およびその製造方法
KR20150057373A (ko) * 2013-11-19 2015-05-28 삼성전기주식회사 회로기판, 회로기판 제조방법 및 2단 비아 구조
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
JP2015213199A (ja) * 2015-08-11 2015-11-26 京セラ株式会社 部品内蔵基板
JPWO2015064668A1 (ja) * 2013-10-29 2017-03-09 京セラ株式会社 配線基板、これを用いた実装構造体および積層シート
WO2018092480A1 (ja) * 2016-11-17 2018-05-24 大日本印刷株式会社 貫通電極基板、貫通電極基板を用いた半導体装置、および貫通電極基板の製造方法
JP2020013976A (ja) * 2018-07-12 2020-01-23 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板
JP2020021928A (ja) * 2018-07-30 2020-02-06 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147069A1 (en) * 2009-12-18 2011-06-23 International Business Machines Corporation Multi-tiered Circuit Board and Method of Manufacture
JP2011228676A (ja) * 2010-03-29 2011-11-10 Kyocera Corp 配線基板およびその実装構造体
JP5585426B2 (ja) * 2010-12-07 2014-09-10 Ｔｄｋ株式会社 配線板、電子部品内蔵基板、配線板の製造方法及び電子部品内蔵基板の製造方法
JP2014045071A (ja) * 2012-08-27 2014-03-13 Ibiden Co Ltd プリント配線板及びその製造方法
KR101483875B1 (ko) * 2013-07-31 2015-01-16 삼성전기주식회사 글라스 코어기판 및 그 제조방법
EP2914071A1 (en) * 2014-02-28 2015-09-02 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Heat spreader in multilayer build ups
CN105097847B (zh) * 2015-09-15 2018-10-23 京东方科技集团股份有限公司 一种阵列基板、显示面板及显示装置
WO2019039237A1 (ja) * 2017-08-21 2019-02-28 住友電工プリントサーキット株式会社 プリント配線板
EP3709779A1 (en) * 2019-03-12 2020-09-16 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier and method of manufacturing the same
WO2021025073A1 (ja) * 2019-08-08 2021-02-11 株式会社村田製作所 多層基板の製造方法及び多層基板
KR20220070684A (ko) * 2020-11-23 2022-05-31 삼성전기주식회사 인쇄회로기판

Citations (4)

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JPH09312479A (ja) * 1996-05-23 1997-12-02 Kyocera Corp 多層配線基板
JPH1146066A (ja) * 1997-07-28 1999-02-16 Ibiden Co Ltd 多層プリント配線板
JP2003142823A (ja) * 2001-11-07 2003-05-16 Nippon Mektron Ltd 両面可撓性回路基板の製造法
JP2006253189A (ja) * 2005-03-08 2006-09-21 Fujitsu Ltd 多層回路基板及びその製造方法

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JPH08116174A (ja) 1994-08-25 1996-05-07 Matsushita Electric Ind Co Ltd 回路形成基板およびその製造方法
EP2086299A1 (en) * 1999-06-02 2009-08-05 Ibiden Co., Ltd. Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
US6392301B1 (en) * 1999-10-22 2002-05-21 Intel Corporation Chip package and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09312479A (ja) * 1996-05-23 1997-12-02 Kyocera Corp 多層配線基板
JPH1146066A (ja) * 1997-07-28 1999-02-16 Ibiden Co Ltd 多層プリント配線板
JP2003142823A (ja) * 2001-11-07 2003-05-16 Nippon Mektron Ltd 両面可撓性回路基板の製造法
JP2006253189A (ja) * 2005-03-08 2006-09-21 Fujitsu Ltd 多層回路基板及びその製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
CN102484950A (zh) * 2009-08-24 2012-05-30 株式会社村田制作所 树脂多层基板以及该树脂多层基板的制造方法
JP2011100797A (ja) * 2009-11-04 2011-05-19 Panasonic Electric Works Co Ltd 回路基板
JP2013110230A (ja) * 2011-11-18 2013-06-06 Fujitsu Ltd 積層回路基板の製造方法、積層回路基板、および電子機器
JP2014131029A (ja) * 2012-12-31 2014-07-10 Samsung Electro-Mechanics Co Ltd 回路基板及びその製造方法
JP2015008261A (ja) * 2013-05-28 2015-01-15 京セラサーキットソリューションズ株式会社 配線基板およびその製造方法
JP2014232853A (ja) * 2013-05-30 2014-12-11 京セラ株式会社 多層配線基板およびプローブカード用基板
JPWO2015064668A1 (ja) * 2013-10-29 2017-03-09 京セラ株式会社 配線基板、これを用いた実装構造体および積層シート
KR20150057373A (ko) * 2013-11-19 2015-05-28 삼성전기주식회사 회로기판, 회로기판 제조방법 및 2단 비아 구조
KR102163041B1 (ko) * 2013-11-19 2020-10-08 삼성전기주식회사 회로기판, 회로기판 제조방법 및 2단 비아 구조
JP2015213199A (ja) * 2015-08-11 2015-11-26 京セラ株式会社 部品内蔵基板
WO2018092480A1 (ja) * 2016-11-17 2018-05-24 大日本印刷株式会社 貫通電極基板、貫通電極基板を用いた半導体装置、および貫通電極基板の製造方法
JP2020013976A (ja) * 2018-07-12 2020-01-23 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板
JP2020021928A (ja) * 2018-07-30 2020-02-06 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板

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Publication number Publication date
US20110051386A1 (en) 2011-03-03
US8431832B2 (en) 2013-04-30
JPWO2009069791A1 (ja) 2011-04-21
JP5066192B2 (ja) 2012-11-07

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