WO2009004040A3 - Speicheranordnung und verfahren zum speichern - Google Patents

Speicheranordnung und verfahren zum speichern Download PDF

Info

Publication number
WO2009004040A3
WO2009004040A3 PCT/EP2008/058532 EP2008058532W WO2009004040A3 WO 2009004040 A3 WO2009004040 A3 WO 2009004040A3 EP 2008058532 W EP2008058532 W EP 2008058532W WO 2009004040 A3 WO2009004040 A3 WO 2009004040A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory transistor
memory array
bit line
line signal
bit
Prior art date
Application number
PCT/EP2008/058532
Other languages
English (en)
French (fr)
Other versions
WO2009004040A2 (de
Inventor
Gregor Schatzberger
Andreas Wiesner
Original Assignee
Austriamicrosystems Ag
Gregor Schatzberger
Andreas Wiesner
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems Ag, Gregor Schatzberger, Andreas Wiesner filed Critical Austriamicrosystems Ag
Priority to US12/667,666 priority Critical patent/US8537586B2/en
Publication of WO2009004040A2 publication Critical patent/WO2009004040A2/de
Publication of WO2009004040A3 publication Critical patent/WO2009004040A3/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Eine Speicheranordnung umfasst einen ersten Speichertransistor (11) zum nicht-flüchtigen Speichern eines ersten Bits, einen zweiten Speichertransistor (17) zum nicht-flüchtigen Speichern des ersten Bits in invertierter Form und eine Wortleitung (29), die mit einem Steueranschluss (12) des ersten Speichertransistors (11) und mit einem Steueranschluss (18) des zweiten Speichertransistors (17) verbunden ist. Weiter umfasst die Speicheranordnung einen Leseverstärker (23) mit einem ersten Eingang (24), der mit dem ersten Speichertransistor (11) zur Zuführung eines ersten Bitleitungssignals (BL1) gekoppelt ist, einem zweiten Eingang (25), der mit dem zweiten Speichertransistor (17) zur Zuführung eines zweiten Bitleitungssignals (BL2) gekoppelt ist, und einem Ausgang (26) zum Bereitstellen eines Ausgangssignals (SOUT) in Abhängigkeit des ersten Bitleitungssignals (BL1) und des zweiten Bitleitungssignals (BL2).
PCT/EP2008/058532 2007-07-03 2008-07-02 Speicheranordnung und verfahren zum speichern WO2009004040A2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/667,666 US8537586B2 (en) 2007-07-03 2008-07-02 Memory array and storage method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102007030842.8A DE102007030842B4 (de) 2007-07-03 2007-07-03 Speicheranordnung und Verfahren zum Speichern
DE102007030842.8 2007-07-03

Publications (2)

Publication Number Publication Date
WO2009004040A2 WO2009004040A2 (de) 2009-01-08
WO2009004040A3 true WO2009004040A3 (de) 2009-05-14

Family

ID=40092339

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/058532 WO2009004040A2 (de) 2007-07-03 2008-07-02 Speicheranordnung und verfahren zum speichern

Country Status (3)

Country Link
US (1) US8537586B2 (de)
DE (1) DE102007030842B4 (de)
WO (1) WO2009004040A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3367385B1 (de) 2017-02-28 2020-07-08 ams AG Speicheranordnung und verfahren zum betrieb einer speicheranordnung
TWI722797B (zh) * 2020-02-17 2021-03-21 財團法人工業技術研究院 記憶體內運算器及其運算方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822248A (en) * 1994-11-21 1998-10-13 Sony Corporation Non-volatile semiconductor memory device using folded bit line architecture
US6765825B1 (en) * 2003-03-12 2004-07-20 Ami Semiconductor, Inc. Differential nor memory cell having two floating gate transistors

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758988A (en) 1985-12-12 1988-07-19 Motorola, Inc. Dual array EEPROM for high endurance capability
US4855955A (en) 1988-04-08 1989-08-08 Seeq Technology, Inc. Three transistor high endurance eeprom cell
JP2537264B2 (ja) * 1988-04-13 1996-09-25 株式会社東芝 半導体記憶装置
US5796670A (en) * 1996-11-07 1998-08-18 Ramax Semiconductor, Inc. Nonvolatile dynamic random access memory device
US6771536B2 (en) 2002-02-27 2004-08-03 Sandisk Corporation Operating techniques for reducing program and read disturbs of a non-volatile memory
US6754123B2 (en) * 2002-10-01 2004-06-22 Hewlett-Packard Development Company, Lp. Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having diode isolation
JP2006004477A (ja) * 2004-06-15 2006-01-05 Matsushita Electric Ind Co Ltd 不揮発性半導体記憶装置
DE102004046793B3 (de) 2004-09-27 2006-05-11 Austriamicrosystems Ag Nicht-flüchtiges Speicherelement

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822248A (en) * 1994-11-21 1998-10-13 Sony Corporation Non-volatile semiconductor memory device using folded bit line architecture
US6765825B1 (en) * 2003-03-12 2004-07-20 Ami Semiconductor, Inc. Differential nor memory cell having two floating gate transistors

Also Published As

Publication number Publication date
WO2009004040A2 (de) 2009-01-08
DE102007030842B4 (de) 2015-05-21
DE102007030842A1 (de) 2009-01-08
US8537586B2 (en) 2013-09-17
US20100277966A1 (en) 2010-11-04

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