WO2008142763A1 - 積層型パッケージ、及び、積層型パッケージの形成方法 - Google Patents

積層型パッケージ、及び、積層型パッケージの形成方法 Download PDF

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Publication number
WO2008142763A1
WO2008142763A1 PCT/JP2007/060278 JP2007060278W WO2008142763A1 WO 2008142763 A1 WO2008142763 A1 WO 2008142763A1 JP 2007060278 W JP2007060278 W JP 2007060278W WO 2008142763 A1 WO2008142763 A1 WO 2008142763A1
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Prior art keywords
semiconductor chips
connection terminals
semiconductor chip
stacked package
joining
Prior art date
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PCT/JP2007/060278
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English (en)
French (fr)
Inventor
Masato Ikeda
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Kabushiki Kaisha Nihon Micronics
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Publication date
Application filed by Kabushiki Kaisha Nihon Micronics filed Critical Kabushiki Kaisha Nihon Micronics
Priority to PCT/JP2007/060278 priority Critical patent/WO2008142763A1/ja
Priority to JP2009515032A priority patent/JPWO2008142763A1/ja
Publication of WO2008142763A1 publication Critical patent/WO2008142763A1/ja

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Abstract

　各半導体チップへの回路の割り当てや各半導体チップの接続用端子の位置の自由度が高い、しかも、各半導体チップ間を確実に電気的に接続できる半導体チップモジュールを提供する。 　本発明は、表面に設けられている回路パターンと連結する接続用端子の一部が側面に設けられている、複数の半導体チップを重ね合わせて結合した半導体チップモジュールに関する。そして、相互に結合される２枚の半導体チップ、少なくとも接続用端子が設けられる側面には、結合させる接着剤が結合時の段差を緩和する量だけはみ出しており、各半導体チップにおける側面の接続用端子部分が、はみ出した接着剤部分をも通過する配線パターンによって相互に接続されていることを特徴とする。
PCT/JP2007/060278 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法 WO2008142763A1 (ja)

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PCT/JP2007/060278 WO2008142763A1 (ja) 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法
JP2009515032A JPWO2008142763A1 (ja) 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法

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PCT/JP2007/060278 WO2008142763A1 (ja) 2007-05-18 2007-05-18 積層型パッケージ、及び、積層型パッケージの形成方法

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WO2008142763A1 true WO2008142763A1 (ja) 2008-11-27

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Citations (6)

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