WO2008105315A1 - 磁気メモリチップ装置の製造方法 - Google Patents

磁気メモリチップ装置の製造方法 Download PDF

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Publication number
WO2008105315A1
WO2008105315A1 PCT/JP2008/052976 JP2008052976W WO2008105315A1 WO 2008105315 A1 WO2008105315 A1 WO 2008105315A1 JP 2008052976 W JP2008052976 W JP 2008052976W WO 2008105315 A1 WO2008105315 A1 WO 2008105315A1
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WIPO (PCT)
Prior art keywords
magnetic memory
memory chip
chip device
manufacturing magnetic
silicon wafer
Prior art date
Application number
PCT/JP2008/052976
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English (en)
French (fr)
Inventor
Kazuyuki Misumi
Masahiro Shimizu
Tsuyoshi Koga
Tatsuhiko Akiyama
Tomohiro Murakami
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to JP2009501206A priority Critical patent/JP5062248B2/ja
Priority to US12/525,999 priority patent/US8124425B2/en
Publication of WO2008105315A1 publication Critical patent/WO2008105315A1/ja
Priority to US13/353,004 priority patent/US8524510B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
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    • H01L23/00—Details of semiconductor or other solid state devices
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Abstract

本発明に係る磁気メモリチップ装置の製造方法は、シリコンウェハ上に形成した複数の磁気メモリチップにそれぞれ情報を書き込む工程と、情報を書き込んだ後に、シリコンウェハの裏面に、シリコンよりも透磁率が高い物質からなる厚さ５０μｍ以上の高透磁率板を貼り付ける工程と、高透磁率板を貼り付けた後に、磁気メモリチップごとにシリコンウェハをダイシングする工程とを有する。
PCT/JP2008/052976 2007-02-27 2008-02-21 磁気メモリチップ装置の製造方法 WO2008105315A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009501206A JP5062248B2 (ja) 2007-02-27 2008-02-21 磁気メモリチップ装置の製造方法
US12/525,999 US8124425B2 (en) 2007-02-27 2008-02-21 Method for manufacturing magnetic memory chip device
US13/353,004 US8524510B2 (en) 2007-02-27 2012-01-18 Method for manufacturing magnetic memory chip device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-047822 2007-02-27
JP2007047822 2007-02-27

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/525,999 A-371-Of-International US8124425B2 (en) 2007-02-27 2008-02-21 Method for manufacturing magnetic memory chip device
US13/353,004 Division US8524510B2 (en) 2007-02-27 2012-01-18 Method for manufacturing magnetic memory chip device

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WO2008105315A1 true WO2008105315A1 (ja) 2008-09-04

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PCT/JP2008/052976 WO2008105315A1 (ja) 2007-02-27 2008-02-21 磁気メモリチップ装置の製造方法

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US (2) US8124425B2 (ja)
JP (2) JP5062248B2 (ja)
TW (1) TWI509602B (ja)
WO (1) WO2008105315A1 (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010123666A (ja) * 2008-11-18 2010-06-03 Renesas Technology Corp 半導体装置およびその製造方法
JP2010153760A (ja) * 2008-12-26 2010-07-08 Renesas Technology Corp 半導体装置およびその製造方法
JP2010245106A (ja) * 2009-04-01 2010-10-28 Renesas Electronics Corp 磁気記憶装置
JP2011216622A (ja) * 2010-03-31 2011-10-27 Renesas Electronics Corp 半導体装置および半導体装置アセンブリ
JP2012124465A (ja) * 2010-11-18 2012-06-28 Nitto Denko Corp フリップチップ型半導体裏面用フィルム、ダイシングテープ一体型半導体裏面用フィルム、フリップチップ型半導体裏面用フィルムの製造方法、及び、半導体装置
JP2013118407A (ja) * 2013-03-06 2013-06-13 Renesas Electronics Corp 半導体装置の製造方法
JP2014112691A (ja) * 2013-12-26 2014-06-19 Renesas Electronics Corp 半導体装置の製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013069807A (ja) * 2011-09-21 2013-04-18 Shinko Electric Ind Co Ltd 半導体パッケージ及びその製造方法
US9385305B2 (en) 2013-02-19 2016-07-05 Qualcomm Incorporated STT-MRAM design enhanced by switching current induced magnetic field
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