WO2008087701A1 - 三次元半導体集積回路装置及びその製造方法 - Google Patents

三次元半導体集積回路装置及びその製造方法 Download PDF

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Publication number
WO2008087701A1
WO2008087701A1 PCT/JP2007/050447 JP2007050447W WO2008087701A1 WO 2008087701 A1 WO2008087701 A1 WO 2008087701A1 JP 2007050447 W JP2007050447 W JP 2007050447W WO 2008087701 A1 WO2008087701 A1 WO 2008087701A1
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chip
base
integrated circuit
circuit device
semiconductor integrated
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PCT/JP2007/050447
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English (en)
French (fr)
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Manabu Bonkohara
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Zycube Co., Ltd.
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Priority to PCT/JP2007/050447 priority Critical patent/WO2008087701A1/ja
Priority to JP2008553903A priority patent/JP5027823B2/ja
Priority to US12/523,118 priority patent/US8907459B2/en
Publication of WO2008087701A1 publication Critical patent/WO2008087701A1/ja

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Abstract

　半導体チップの大きさに関する制約を除去できる三次元半導体集積回路装置とその製造方法を提供する。 　固体回路１２を有しベース１０より小さい半導体チップ１３をベース１０上に積層する。第１充填材１４でチップ１３を埋め込み、第１充填材１４をベース１０と略同一の外形（輪郭）にする。チップ１３の内部にその全部または一部をその厚さ方向に貫通する複数の埋込電極１５を形成する。固体回路１６を有しベース１０より小さい半導体チップ１７を、チップ１３上に積層する。第２充填材１８でチップ１７を埋め込み、第２充填材１８をベース１０と略同一の外形にする。チップ１７の内部にその全部または一部をその厚さ方向に貫通する複数の埋込電極１９を形成する。第１及び第２の充填材１４、１８はそれぞれ、埋込電極１５、１９の形成の際に要求される加工性と熱膨張係数がチップ１３、１７と同等である。
PCT/JP2007/050447 2007-01-15 2007-01-15 三次元半導体集積回路装置及びその製造方法 WO2008087701A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/050447 WO2008087701A1 (ja) 2007-01-15 2007-01-15 三次元半導体集積回路装置及びその製造方法
JP2008553903A JP5027823B2 (ja) 2007-01-15 2007-01-15 三次元半導体集積回路装置及びその製造方法
US12/523,118 US8907459B2 (en) 2007-01-15 2007-01-15 Three-dimensional semiconductor integrated circuit device and method of fabricating the same

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PCT/JP2007/050447 WO2008087701A1 (ja) 2007-01-15 2007-01-15 三次元半導体集積回路装置及びその製造方法

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JP (1) JP5027823B2 (ja)
WO (1) WO2008087701A1 (ja)

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* Cited by examiner, † Cited by third party
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JP2010232648A (ja) * 2009-03-04 2010-10-14 Nec Corp 半導体装置及びその製造方法
US10125289B2 (en) 2013-03-28 2018-11-13 Mitsubishi Chemical Corporation Composition for interlayer filler of layered semiconductor device, layered semiconductor device, and process for producing layered semiconductor device
JP2018534783A (ja) * 2015-11-14 2018-11-22 東京エレクトロン株式会社 希ｔｍａｈを使用してマイクロエレクトロニック基板を処理する方法

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* Cited by examiner, † Cited by third party
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US8222078B2 (en) 2009-07-22 2012-07-17 Alpha And Omega Semiconductor Incorporated Chip scale surface mounted semiconductor device package and process of manufacture
KR20160083977A (ko) * 2015-01-02 2016-07-13 삼성전자주식회사 반도체 패키지
CN109119426B (zh) * 2018-09-28 2024-04-16 长江存储科技有限责任公司 3d存储器件
KR20210035546A (ko) * 2019-09-24 2021-04-01 삼성전자주식회사 반도체 패키지
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