WO2008105204A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

Info

Publication number
WO2008105204A1
WO2008105204A1 PCT/JP2008/051090 JP2008051090W WO2008105204A1 WO 2008105204 A1 WO2008105204 A1 WO 2008105204A1 JP 2008051090 W JP2008051090 W JP 2008051090W WO 2008105204 A1 WO2008105204 A1 WO 2008105204A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
chemical formula
represented
oxide
semiconductor device
Prior art date
Application number
PCT/JP2008/051090
Other languages
English (en)
French (fr)
Inventor
Wensheng Wang
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to CN2008800065920A priority Critical patent/CN101641782B/zh
Priority to JP2009501154A priority patent/JP5104850B2/ja
Priority to KR1020097016930A priority patent/KR101084408B1/ko
Publication of WO2008105204A1 publication Critical patent/WO2008105204A1/ja
Priority to US12/548,911 priority patent/US8405188B2/en
Priority to US13/780,177 priority patent/US8664011B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

強誘電体キャパシタを構成するキャパシタ上部電極の結晶性を改善すること。キャパシタ上部電極は、組成パラメータｘ１を使って化学式ＡＯｘ1（Ａ：金属元素）で表され実際の組成が組成パラメータｘ２を使って化学式ＡＯｘ2で表される第１酸化物よりなる第１の層５７と、第１の層５７上に形成され、組成パラメータｙ１を使って化学式ＢＯｙ1で表され実際の組成が組成パラメータｙ２を使って化学式ＢＯｙ２（Ｂ：金属元素）で表される第２酸化物であって、石垣状或いは柱状に接合される結晶からなり、第１の層５７より酸化の割合が高く構成され、組成パラメータｘ１、ｘ２、ｙ１およびｙ２の間には、関係（ｙ２／ｙ１）＞（ｘ２／ｘ１）が成立する第２の層５８と、第２の層５８上に形成され且つ貴金属膜又は貴金属を含む合金或いはそれらの酸化物よりなる第３の層５９とを有する。
PCT/JP2008/051090 2007-02-28 2008-01-25 半導体装置及びその製造方法 WO2008105204A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN2008800065920A CN101641782B (zh) 2007-02-28 2008-01-25 半导体器件及其制造方法
JP2009501154A JP5104850B2 (ja) 2007-02-28 2008-01-25 半導体装置の製造方法
KR1020097016930A KR101084408B1 (ko) 2007-02-28 2008-01-25 반도체 장치 및 그 제조방법
US12/548,911 US8405188B2 (en) 2007-02-28 2009-08-27 Semiconductor device and method of manufacturing the semiconductor device
US13/780,177 US8664011B2 (en) 2007-02-28 2013-02-28 Semiconductor device and method of manufacturing the semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPPCT/JP2007/053836 2007-02-28
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/548,911 Continuation US8405188B2 (en) 2007-02-28 2009-08-27 Semiconductor device and method of manufacturing the semiconductor device

Publications (1)

Publication Number Publication Date
WO2008105204A1 true WO2008105204A1 (ja) 2008-09-04

Family

ID=39720944

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法
PCT/JP2008/051090 WO2008105204A1 (ja) 2007-02-28 2008-01-25 半導体装置及びその製造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/053836 WO2008105100A1 (ja) 2007-02-28 2007-02-28 半導体装置及びその製造方法

Country Status (4)

Country Link
US (2) US8405188B2 (ja)
KR (1) KR101084408B1 (ja)
CN (1) CN101641782B (ja)
WO (2) WO2008105100A1 (ja)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101830193B1 (ko) * 2010-07-02 2018-02-20 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US8780628B2 (en) * 2011-09-23 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit including a voltage divider and methods of operating the same
JP5845866B2 (ja) * 2011-12-07 2016-01-20 富士通セミコンダクター株式会社 半導体装置の製造方法
WO2014094882A1 (en) * 2012-12-21 2014-06-26 European Space Agency Additive manufacturing method using focused light heating source
JP2015133392A (ja) * 2014-01-10 2015-07-23 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US9711454B2 (en) * 2015-08-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through via structure for step coverage improvement
US10319635B2 (en) * 2017-05-25 2019-06-11 Sandisk Technologies Llc Interconnect structure containing a metal slilicide hydrogen diffusion barrier and method of making thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110934A (ja) * 2000-09-29 2002-04-12 Fujitsu Ltd 半導体装置およびその製造方法
JP2002203948A (ja) * 2001-01-05 2002-07-19 Matsushita Electric Ind Co Ltd 半導体装置
JP2002324894A (ja) * 2001-04-25 2002-11-08 Fujitsu Ltd 半導体装置およびその製造方法
JP2004296929A (ja) * 2003-03-27 2004-10-21 Seiko Epson Corp 強誘電体キャパシタの製造方法、強誘電体キャパシタ、記憶素子、電子素子、メモリ装置及び電子機器
JP2006073648A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3299909B2 (ja) 1997-02-25 2002-07-08 シャープ株式会社 酸化物導電体を用いた多層構造電極
JP3109485B2 (ja) 1998-08-03 2000-11-13 日本電気株式会社 金属酸化物誘電体膜の気相成長方法
JP3159255B2 (ja) 1998-09-16 2001-04-23 日本電気株式会社 強誘電体容量で用いる電極のスパッタ成長方法
JP3545279B2 (ja) 1999-10-26 2004-07-21 富士通株式会社 強誘電体キャパシタ、その製造方法、および半導体装置
US6887716B2 (en) * 2000-12-20 2005-05-03 Fujitsu Limited Process for producing high quality PZT films for ferroelectric memory integrated circuits
JP4050004B2 (ja) 2001-03-28 2008-02-20 富士通株式会社 半導体装置及びその製造方法
JP4428500B2 (ja) * 2001-07-13 2010-03-10 富士通マイクロエレクトロニクス株式会社 容量素子及びその製造方法
JP2003204043A (ja) * 2001-10-24 2003-07-18 Fujitsu Ltd 半導体装置及びその製造方法
JP4657545B2 (ja) 2001-12-28 2011-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4316188B2 (ja) 2002-05-29 2009-08-19 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
JP4153333B2 (ja) 2003-03-10 2008-09-24 株式会社アルバック 酸化物薄膜の製造方法
JP2005183842A (ja) 2003-12-22 2005-07-07 Fujitsu Ltd 半導体装置の製造方法
US20050161717A1 (en) * 2004-01-28 2005-07-28 Fujitsu Limited Semiconductor device and method of fabricating the same
JP2006128274A (ja) 2004-10-27 2006-05-18 Seiko Epson Corp 強誘電体キャパシタおよび強誘電体メモリの製造方法
JP2006222227A (ja) * 2005-02-09 2006-08-24 Fujitsu Ltd 半導体装置及びその製造方法
KR100663356B1 (ko) * 2005-02-14 2007-01-02 삼성전자주식회사 부분적 화학기계적 연마공정을 갖는 강유전체 메모리 소자제조방법들
JP2006245457A (ja) * 2005-03-07 2006-09-14 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP5076890B2 (ja) 2005-06-17 2012-11-21 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002110934A (ja) * 2000-09-29 2002-04-12 Fujitsu Ltd 半導体装置およびその製造方法
JP2002203948A (ja) * 2001-01-05 2002-07-19 Matsushita Electric Ind Co Ltd 半導体装置
JP2002324894A (ja) * 2001-04-25 2002-11-08 Fujitsu Ltd 半導体装置およびその製造方法
JP2004296929A (ja) * 2003-03-27 2004-10-21 Seiko Epson Corp 強誘電体キャパシタの製造方法、強誘電体キャパシタ、記憶素子、電子素子、メモリ装置及び電子機器
JP2006073648A (ja) * 2004-08-31 2006-03-16 Fujitsu Ltd 半導体装置及びその製造方法

Also Published As

Publication number Publication date
CN101641782A (zh) 2010-02-03
KR20090110908A (ko) 2009-10-23
KR101084408B1 (ko) 2011-11-18
US8664011B2 (en) 2014-03-04
US8405188B2 (en) 2013-03-26
US20090315144A1 (en) 2009-12-24
US20130177997A1 (en) 2013-07-11
WO2008105100A1 (ja) 2008-09-04
CN101641782B (zh) 2012-10-10

Similar Documents

Publication Publication Date Title
WO2008105204A1 (ja) 半導体装置及びその製造方法
WO2005092796A3 (en) Titanium-containing perovskite compound and production method thereof
TW200746388A (en) Complex oxide laminate, method of manufacturing complex oxide laminate, and device
TW550530B (en) Display device and method of driving the same
WO2008111188A1 (ja) 半導体装置及びその製造方法
JP2009094449A (ja) 圧電素子
JP2010134466A5 (ja) 液晶表示装置の作製方法
EP1602636A3 (en) Precursor composition, method for manufacturing precursor composition, method for manufacturing ferroelectric film, piezoelectric element, semiconductor device, piezoelectric actuator, ink jet recording head, and ink jet printer
JP2009117785A (ja) 圧電薄膜付き基板
JP2010219509A5 (ja)
Chang et al. Achieving atomistic control in materials processing by plasma–surface interactions
JP2007535171A5 (ja)
WO2012112927A3 (en) Methods of forming semiconductor films including i2-ii-iv-vi4 and i2-(ii,iv)-iv-vi4 semiconductor films and electronic devices including the semiconductor films
TW200834198A (en) Display device and method of producing the same
Nam et al. Effect of CuO on the sintering temperature and piezoelectric properties of MnO2-doped 0.75 Pb (Zr0. 47Ti0. 53) O3–0.25 Pb (Zn1/3Nb2/3) O3 ceramics
WO2008114423A1 (ja) 半導体装置およびその製造方法
WO2013012192A3 (en) Single-phase lithium-deficient lithium multicomponent transition metal oxide having a layered crystal structure and a method for producing the same
WO2016152419A1 (ja) 強誘電体薄膜積層基板、強誘電体薄膜素子、および強誘電体薄膜積層基板の製造方法
RU2009117697A (ru) Распыляемая мишень на основе оксида титана для прозрачной проводящей пленки, способ получения такой пленки и состав для использования в этом способе
JP2006182642A5 (ja) 強誘電体キャパシタの製造方法、強誘電体メモリの製造方法、圧電素子の製造方法、圧電アクチュエータの製造方法、及び液体噴射ヘッドの製造方法
JP6065022B2 (ja) 誘電体デバイスの製造方法
EP1630855A3 (en) Semiconductor device and method for manufacturing the same
TW200623461A (en) Compound semiconductor luminescent device
CN103208477B (zh) 金红石结构氧化钛的制备方法及其叠层结构
Zhang et al. Robust switchable polarization and coupled electronic characteristics of magnesium-doped zinc oxide

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880006592.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08710591

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2009501154

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020097016930

Country of ref document: KR

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08710591

Country of ref document: EP

Kind code of ref document: A1