WO2008093487A1 - インバータ回路 - Google Patents

インバータ回路 Download PDF

Info

Publication number
WO2008093487A1
WO2008093487A1 PCT/JP2008/000004 JP2008000004W WO2008093487A1 WO 2008093487 A1 WO2008093487 A1 WO 2008093487A1 JP 2008000004 W JP2008000004 W JP 2008000004W WO 2008093487 A1 WO2008093487 A1 WO 2008093487A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
output
receives
input
input signal
Prior art date
Application number
PCT/JP2008/000004
Other languages
English (en)
French (fr)
Inventor
Kouichi Yamada
Original Assignee
Sanyo Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co., Ltd. filed Critical Sanyo Electric Co., Ltd.
Priority to US12/293,701 priority Critical patent/US7961013B2/en
Priority to CN2008800000714A priority patent/CN101542905B/zh
Publication of WO2008093487A1 publication Critical patent/WO2008093487A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

　第１スイッチＭ１は入力信号を受ける。第２スイッチＭ２は、第１スイッチＭ１と並列に、入力信号を受ける。出力電位検知インバータ３０は第１スイッチＭ１と第２スイッチＭ２との接続点から得られる出力信号の電位を検知する。入力スイッチＭ３は、出力電位検知インバータ３０を受けて、第２スイッチＭ２に入力信号を入力するか否かを制御する。出力電位検知インバータ３０は、出力信号の電位が所定の閾値電圧を超えると、入力スイッチＭ３をオフするよう制御する。
PCT/JP2008/000004 2007-01-30 2008-01-08 インバータ回路 WO2008093487A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/293,701 US7961013B2 (en) 2007-01-30 2008-01-08 Inverter circuit
CN2008800000714A CN101542905B (zh) 2007-01-30 2008-01-08 反相器电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-019983 2007-01-30
JP2007019983A JP2008187525A (ja) 2007-01-30 2007-01-30 インバータ回路

Publications (1)

Publication Number Publication Date
WO2008093487A1 true WO2008093487A1 (ja) 2008-08-07

Family

ID=39673801

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000004 WO2008093487A1 (ja) 2007-01-30 2008-01-08 インバータ回路

Country Status (4)

Country Link
US (1) US7961013B2 (ja)
JP (1) JP2008187525A (ja)
CN (1) CN101542905B (ja)
WO (1) WO2008093487A1 (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101076942B (zh) * 2004-12-13 2012-06-13 株式会社半导体能源研究所 半导体装置和使用其的电子用品
CN102185593A (zh) * 2011-03-18 2011-09-14 北京大学 半预充动态电路
US8618857B2 (en) * 2012-03-27 2013-12-31 Monolithic Power Systems, Inc. Delay circuit and associated method
US8773192B2 (en) * 2012-11-28 2014-07-08 Lsi Corporation Overshoot suppression for input/output buffers
US9337841B1 (en) * 2014-10-06 2016-05-10 Xilinx, Inc. Circuits for and methods of providing voltage level shifting in an integrated circuit device
CN108155901B (zh) * 2016-12-05 2023-11-24 中国工程物理研究院电子工程研究所 一种抗参数漂移反相器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145232A (ja) * 1982-02-22 1983-08-30 Nec Corp トランジスタ回路
JPH10190435A (ja) * 1996-12-24 1998-07-21 Toshiba Microelectron Corp 半導体出力回路、ｃｍｏｓ出力回路、端子電位検出回路、及び半導体装置
JP2001251176A (ja) * 2000-03-07 2001-09-14 Matsushita Electric Ind Co Ltd レベルシフト回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05198755A (ja) 1991-08-29 1993-08-06 Mitsubishi Electric Corp 半導体論理回路
US5532617A (en) * 1994-03-25 1996-07-02 Philips Electronics North America Corporation CMOS input with temperature and VCC compensated threshold
US6191615B1 (en) * 1998-03-30 2001-02-20 Nec Corporation Logic circuit having reduced power consumption
JP4450631B2 (ja) * 2004-01-06 2010-04-14 旭化成エレクトロニクス株式会社 Ｅｓｄ保護機能付き信号出力回路
KR100585886B1 (ko) * 2004-01-27 2006-06-01 삼성전자주식회사 동적 문턱 전압을 가지는 반도체 회로
US7126389B1 (en) * 2004-01-27 2006-10-24 Integrated Device Technology, Inc. Method and apparatus for an output buffer with dynamic impedance control
FR2894373B1 (fr) * 2005-12-07 2008-01-04 Atmel Corp Cellule anti-fusible autonome

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145232A (ja) * 1982-02-22 1983-08-30 Nec Corp トランジスタ回路
JPH10190435A (ja) * 1996-12-24 1998-07-21 Toshiba Microelectron Corp 半導体出力回路、ｃｍｏｓ出力回路、端子電位検出回路、及び半導体装置
JP2001251176A (ja) * 2000-03-07 2001-09-14 Matsushita Electric Ind Co Ltd レベルシフト回路

Also Published As

Publication number Publication date
US20100102856A1 (en) 2010-04-29
JP2008187525A (ja) 2008-08-14
CN101542905B (zh) 2012-02-08
US7961013B2 (en) 2011-06-14
CN101542905A (zh) 2009-09-23

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