WO2008090816A1 - マスクパターン設計方法および半導体装置の製造方法 - Google Patents

マスクパターン設計方法および半導体装置の製造方法 Download PDF

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Publication number
WO2008090816A1
WO2008090816A1 PCT/JP2008/050598 JP2008050598W WO2008090816A1 WO 2008090816 A1 WO2008090816 A1 WO 2008090816A1 JP 2008050598 W JP2008050598 W JP 2008050598W WO 2008090816 A1 WO2008090816 A1 WO 2008090816A1
Authority
WO
WIPO (PCT)
Prior art keywords
opc
mask pattern
cell
ope
canceller
Prior art date
Application number
PCT/JP2008/050598
Other languages
English (en)
French (fr)
Inventor
Hirokazu Nosato
Tetsuaki Matsunawa
Hidenori Sakanashi
Tetsuya Higuchi
Original Assignee
National Institute Of Advanced Industrial Science And Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Institute Of Advanced Industrial Science And Technology filed Critical National Institute Of Advanced Industrial Science And Technology
Priority to JP2008555036A priority Critical patent/JP4883591B2/ja
Publication of WO2008090816A1 publication Critical patent/WO2008090816A1/ja

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　ＯＰＣ（光近接効果補正）処理されたセルライブラリを用いるマスクパターンの設計方法において、ＯＰＣ処理時間の短縮を実現する。 　ＯＰＣ処理されたセルライブラリを用いてマスクパターンを設計する際、セルに形成されたパターンによって発生するＯＰＥ（光近接効果）を抑制するＯＰＥキャンセラーをセルの一部に形成する。ＯＰＥキャンセラーは、セルのパターンと共にフォトマスク上に形成されるが、ウエハ上には転写されない微小パターンの集合体からなる。ＯＰＥキャンセラーを構成する微小パターンの配置、数、形状、光透過率などは、最適化手法やランダムサーチ法などを用いて適宜調整する。
PCT/JP2008/050598 2007-01-26 2008-01-18 マスクパターン設計方法および半導体装置の製造方法 WO2008090816A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008555036A JP4883591B2 (ja) 2007-01-26 2008-01-18 マスクパターン設計方法および半導体装置の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-015761 2007-01-26
JP2007015761 2007-01-26

Publications (1)

Publication Number Publication Date
WO2008090816A1 true WO2008090816A1 (ja) 2008-07-31

Family

ID=39644392

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050598 WO2008090816A1 (ja) 2007-01-26 2008-01-18 マスクパターン設計方法および半導体装置の製造方法

Country Status (2)

Country Link
JP (1) JP4883591B2 (ja)
WO (1) WO2008090816A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015034973A (ja) * 2013-07-10 2015-02-19 キヤノン株式会社 パターンの作成方法、プログラムおよび情報処理装置
US20220180503A1 (en) * 2020-12-07 2022-06-09 Samsung Electronics Co., Ltd. Method of verifying error of optical proximity correction model
CN118131581A (zh) * 2024-05-06 2024-06-04 全芯智造技术有限公司 光学邻近校正方法、电子设备及存储介质

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104423142B (zh) * 2013-08-22 2020-05-05 中芯国际集成电路制造(上海)有限公司 用于光学邻近校正模型的校准数据收集方法和***
US20210064977A1 (en) * 2019-08-29 2021-03-04 Synopsys, Inc. Neural network based mask synthesis for integrated circuits

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0915833A (ja) * 1995-06-30 1997-01-17 Sony Corp 露光用マスク作製装置における走査用データ作成装置及び走査用データの作成方法
JPH1032253A (ja) * 1996-07-15 1998-02-03 Toshiba Corp 半導体装置及びその製造方法、基本セルライブラリ及びその形成方法、マスク
JP2004288685A (ja) * 2003-03-19 2004-10-14 Nec Micro Systems Ltd 半導体集積回路のレイアウト設計方法およびレイアウト設計用プログラム
JP2005084101A (ja) * 2003-09-04 2005-03-31 Toshiba Corp マスクパターンの作製方法、半導体装置の製造方法、マスクパターンの作製システム、セルライブラリ、フォトマスクの製造方法
JP2006139165A (ja) * 2004-11-15 2006-06-01 Seiko Epson Corp セルを記録した記録媒体及び半導体集積回路
JP2006276079A (ja) * 2005-03-28 2006-10-12 National Institute Of Advanced Industrial & Technology 光リソグラフィの光近接補正におけるマスクパターン設計方法および設計装置ならびにこれを用いた半導体装置の製造方法
JP2007080965A (ja) * 2005-09-12 2007-03-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法、これに用いられるライブラリ、記録媒体および半導体製造装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0915833A (ja) * 1995-06-30 1997-01-17 Sony Corp 露光用マスク作製装置における走査用データ作成装置及び走査用データの作成方法
JPH1032253A (ja) * 1996-07-15 1998-02-03 Toshiba Corp 半導体装置及びその製造方法、基本セルライブラリ及びその形成方法、マスク
JP2004288685A (ja) * 2003-03-19 2004-10-14 Nec Micro Systems Ltd 半導体集積回路のレイアウト設計方法およびレイアウト設計用プログラム
JP2005084101A (ja) * 2003-09-04 2005-03-31 Toshiba Corp マスクパターンの作製方法、半導体装置の製造方法、マスクパターンの作製システム、セルライブラリ、フォトマスクの製造方法
JP2006139165A (ja) * 2004-11-15 2006-06-01 Seiko Epson Corp セルを記録した記録媒体及び半導体集積回路
JP2006276079A (ja) * 2005-03-28 2006-10-12 National Institute Of Advanced Industrial & Technology 光リソグラフィの光近接補正におけるマスクパターン設計方法および設計装置ならびにこれを用いた半導体装置の製造方法
JP2007080965A (ja) * 2005-09-12 2007-03-29 Matsushita Electric Ind Co Ltd 半導体装置の製造方法、これに用いられるライブラリ、記録媒体および半導体製造装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015034973A (ja) * 2013-07-10 2015-02-19 キヤノン株式会社 パターンの作成方法、プログラムおよび情報処理装置
US20220180503A1 (en) * 2020-12-07 2022-06-09 Samsung Electronics Co., Ltd. Method of verifying error of optical proximity correction model
US11699227B2 (en) * 2020-12-07 2023-07-11 Samsung Electronics Co., Ltd. Method of verifying error of optical proximity correction model
CN118131581A (zh) * 2024-05-06 2024-06-04 全芯智造技术有限公司 光学邻近校正方法、电子设备及存储介质

Also Published As

Publication number Publication date
JP4883591B2 (ja) 2012-02-22
JPWO2008090816A1 (ja) 2010-05-20

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