WO2008082045A1 - Memory device and method of manufacturing the same - Google Patents

Memory device and method of manufacturing the same Download PDF

Info

Publication number
WO2008082045A1
WO2008082045A1 PCT/KR2007/002883 KR2007002883W WO2008082045A1 WO 2008082045 A1 WO2008082045 A1 WO 2008082045A1 KR 2007002883 W KR2007002883 W KR 2007002883W WO 2008082045 A1 WO2008082045 A1 WO 2008082045A1
Authority
WO
WIPO (PCT)
Prior art keywords
ferroelectric
ferroelectric layer
memory device
memory cell
substrate
Prior art date
Application number
PCT/KR2007/002883
Other languages
French (fr)
Inventor
Byung-Eun Park
Original Assignee
University Of Seoul Foundation Of Industry-Academic Cooperation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020070057575A external-priority patent/KR100876135B1/en
Application filed by University Of Seoul Foundation Of Industry-Academic Cooperation filed Critical University Of Seoul Foundation Of Industry-Academic Cooperation
Publication of WO2008082045A1 publication Critical patent/WO2008082045A1/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
    • G11C13/0016—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Definitions

  • the present invention relates to a memory device capable of reading and writing information and, more particularly, to a memory device capable of non-volatile data storage with a simple structure without using a switching element such as a transistor, and a method of manufacturing the same .
  • ROMs read only memories
  • EPROM electrically programmable ROM
  • EEPROM electrically erasable PROM
  • FROM flash ROM
  • RAMs random access memories
  • SRAM static RAM
  • DRAM dynamic RAM
  • FRAM ferroelectric RAM
  • All of the semiconductor memory devices used at present basically comprises a switching element such as a transistor and a storage element such as a capacitor. These memory devices write, erase and read data by storing and reading a data value in the storage element through the switching element.
  • the conventional semiconductor memory devices have some drawbacks in that they require a lot of manufacturing processes due to the formation of the switching element and the storage element on a wafer and it is difficult to obtain a high density over a predetermined level.
  • the present invention has been made in an effort to solve the above-described problems.
  • the present invention provides a memory device capable of non-volatile data storage with a simple structure without using a switching element or a storage element, and a method of manufacturing the same.
  • a memory device comprising: a substrate; a lower electrode provided on the substrate and formed of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode provided on the ferroelectric layer and formed of a conductive material, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
  • a memory device comprising: a substrate; a lower electrode provided on the substrate and formed of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode provided on the ferroelectric layer and formed of a conductive material, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
  • a memory device comprising: a substrate; a plurality of lower electrodes formed parallel to each other on the substrate; a ferroelectric layer formed on the lower electrodes; and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material .
  • a memory device comprising: a substrate; a plurality of lower electrodes formed parallel to each other on the substrate; a ferroelectric layer formed on the lower electrodes; and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
  • the substrate may be formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material.
  • the organic material may comprise at least one selected from the group consisting of polyimide (PI), polycarbonate (PC) , polyethersulfone (PES) , polyetheretherketone (PEEK) , polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET), pol yvinylchloride (PVC), polyethylene (PE) , ethylene copolymer, polypropylene (PP) , propylene copolymer, poly (4-methyl-l-pentene) (TPX), polyarylate (PAR) , polyacetal (POM) , polyphenyleneoxide (PPO), polysulfone (PSF), polypheny].
  • PI polyimide
  • PC polycarbonate
  • PES polyethersulfone
  • PEEK polyetheretherketone
  • PBT polybutyleneterephthalate
  • PET polyethyleneterephthalate
  • PVC polyethyleneterephthalate
  • PE polyethylene copolymer
  • the inorganic ferroelectric material may comprise at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
  • the inorganic ferroelectric material may be PZT.
  • the mixture may further comprise a suicide, a silicate or any other metal.
  • the organic material may be a polymer ferroelectric materi ⁇ il .
  • the polymer ferroelectric material may comprise at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
  • PVDF polyvinylidene fluoride
  • the polymer ferroelectric material may be PVDF-TrFE.
  • the ferroelectric layer may be formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
  • a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
  • a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first, memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
  • a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
  • a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
  • a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layers of the first and second memory cells are formed of different materials.
  • a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layers of the first and second memory cells are formed of different materials.
  • the memory device may further comprise an insulating layer formed between the first memory cell and the second memory cell.
  • the upper electrode of the first memory cell and the lower electrode of the second memory cell may be ground electrodes .
  • ground cells of the first memory cell and the second memory cell may be formed integrally with each other.
  • the upper electrode of the first memory cell and the lower electrode of the second memory cell may be data electrodes.
  • a method of manufacturing a memory device comprising: forming a lower electrode on a substrate; forming a ferroelectric layer of a mixture of an inorganic ferroelectric material and an organic material on the overall surface of the substrate on which the lower electrode is formed; and forming an upper electrode on the ferroelectric layer.
  • the organic material may be an organic ferroelectric material.
  • a mixed solution of an inorganic ferroelectric solution and an organic solution may be coated on the substrate to form a ferroelectric film, and the ferroelectric film may be heated and baked to form the ferroelectric layer.
  • the mixed solution may comprise a PZT solution and a PVDF-TrFE solution.
  • the PZT solution may be prepared by mixing a PZO solution and a PTO solution.
  • the PVDF-TrFE solution may be prepared by dissolving PVDF-TrFE powder in at least one solvent selected from the group consisting of C 4 H 5 O (THF), C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF) , and C 2 H 6 OS (DMSO) .
  • the ferroelectric layer may be formed by a spin coating method.
  • the ferroelectric layer may be formed by an ink-jet printing method.
  • the ferroelectric layer may be formed by a screen printing method.
  • the method may further comprise etching and removing the ferroelectric layer except for the intersection of the lower electrode and the upper electrode.
  • the process of etching the ferroelectric layer may be performed by a buffered oxide etching (BOE) method.
  • BOE buffered oxide etching
  • the process of etching the ferroelectric layer may be performed by a two-step etching method using BOE and gold etchant .
  • the process of etching the ferroelectric layer may be performed by a reactive ion etching (RIE) method.
  • RIE reactive ion etching
  • the baking temperature may be below 200 ° C.
  • FIG. 1 is an equivalent circuit diagram of a memory device having a 1C structure in accordance with the present invention
  • FIGS. 2A to 6 are graphs showing capacitance-voltage characteristics of ferroelectric materials applied to the present, invention.
  • FIG. 7 is a diagram showing a structure of a memory device in accordance with a first embodiment of the present invention.
  • FIGS. 8A and 8B are diagrams showing a modified structure of the memory device of FIG. 7;
  • FIG. 9 is a cross-sectional view showing a structure of a memory device in accordance with a second embodiment of the present invention.
  • FIGS. 10 and 11 are cross-sectional views showing modified structures of the memory device of FIG. 9.
  • a memory device is to store digital data. Accordingly, if any structure capable of storing data "0" or “1” and reading the stored data can be effectively used as a memory device.
  • a commonly known ferroelectric material has a specific polarization value according to a voltage applied from the outside, and such a polarization value is maintained for a predetermined period of time even in the case where the external power is cut off. According to the study by the present inventor, using the above-described polarization characteristics can realize a memory device having one-capacitor (1C) structure as shown in FIG. 1.
  • the ferroelectric material is used as a ferroelectric layer 13 between a lower electrode 11 and an upper electrode 12.
  • the substrate such as the silicon substrate is not required.
  • the memory device can be realized only by forming a conductive thin film for the formation of the upper and lower electrodes and a ferroelectric thin film, the substrate of a specific material for obtaining the memory device is not required. Accordingly, it is possible to significantly reduce the manufacturing cost of the memory device,.
  • the memory device can be formed on a flexible material such as resin or paper, it is possible to obtain a memory device capable of being folded or rolled up.
  • the inorganic ferroelectric materials include ferroelectric oxides, ferroelectric fluorides such as BaMgF 4 (BMF) , and ferroelectric semiconductors.
  • the organic ferroelectric materials include polymer ferroelectric materials and the like.
  • the ferroelectric oxides include perovskite ferroelectric materials such as PbZr x Tii_ x O 3 (PZT) , BaTiO 3 and PBTiO 3 , pseudo-ilmenite ferroelectric materials such as LiNbO 3 and LiTaO 3 , tungsten-bronze (TB) ferroelectric materials such as PbNb 3 Og and Ba 2 NaNbs0i 5 , ferroelectric materials having a bismuth layer structure such as SrBi 2 Ta 2 ⁇ g (SBT), (Bi, La) 4 Ti 3 Oi 2 (BLT) and Bi 4 Ti 3 Oi 2 , pyrochlore ferroelectric materials such as La 2 Ti 2 O 7 , and ferroelectric materials such as RMnO 3 , Pb 5 Ge 3 On (PGO) and BiFeO 3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu ,
  • R rare earth element
  • the ferroelectric semiconductors include 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe.
  • the polymer ferroelectric materials include polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
  • the inorganic ferroelectric materials including the ferroelectric oxides, the ferroelectric fluorides and the ferroelectric semiconductors have dielectric constants greater than those of the organic ferroelectric materials. Accordingly, the generally proposed ferroelectric field-effect transistor (FET) or ferroelectric memory device employs the inorganic ferroeLectric materials for forming the ferroelectric layer.
  • FET ferroelectric field-effect transistor
  • the above-described inorganic ferroelectric materials require a high temperature treatment above 500 " C, for example, to be formed on a substrate.
  • a ferroelectric layer or a ferroelectric thin film is formed through the high temperature treatment on the substrate, there are limitations associated with using the flexible material such as resin or paper. That is, the materials capable of being used as the substrate of the memory device are limited.
  • a mixture of an inorganic ferroelectric material and an organic material or an organic ferroelectric material is used as the material for the ferroelectric layer.
  • the inorganic ferroelectric materials are formed at higher temperatures, while their dielectric constants are high.
  • the organic materials including the organic ferroelectric materials are formed at lower temperatures, while their dielectric constants are relatively low. Accordingly, when mixing the inorganic ferroelectric material with the organic material or the organic ferroelectric material, it is possible to obtain a ferroelectric material having a dielectric constant above a predetermined value and formed at a much lower temperature.
  • methods of forming mixed solutions of the inorganic ferroelectric material and the organic material or the organic ferroelectric material are as follows: 1. Mixing an inorganic powder with an organic powder and dissolving the mixed powders in a solvent to form a mixed solution;
  • the inorganic ferroelectric material and the organic material may be mixed with each other as follows:
  • the organic materials mixed with the inorganic ferroelectric material include, a monomer, an oligomer, a polymer, and a copolymer.
  • an organic material having a high dielectric constant may be used.
  • the organic materials having a high dielectric constant include polyvinylpyrrolidone (PVP), polycarbonate (PC) , polyvinyl chloride (PVC) , polystyrene (PS) , epoxy, polymethylmethacrylate (PMMA), polyimide (PI), polyethylene (PE) , polyvinyl alcohol (PVA) , polyhexamethylene adipamide (nylon 66), polyetherketoneketone (PEKK), and the like.
  • the organic materials include a nonpolar organic material, such as fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly ( ⁇ -methyl styrene) , poly ( ⁇ -vinylnaphthalene) , poly (vinyltoluene) , polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-l-pentene) , poly (tetrafluoroethylene) , poly (chlorotrifluoroethylene) , poly (2-methyl-l, 3-butadiene) , poly (p-xylylene) , poly( ⁇ - ⁇ - ⁇ ' ⁇ ⁇ ' -tetrafluoro-p-xylylene) , poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate] , pol y (cyclohexyl methacrylate) , poly ((2-
  • organic semi-conducting materials that can be used in this invention include soluble compounds and soluble derivatives of compounds of the following list: conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene) , polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as anthracene, tetracene, chrysene, pentacene, pyrene, perylene, coronene; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P) , p- quinquephenyl (p-5P) , p-sexiphenyl (p- ⁇ P) ; conjugated heterocyclic polymers such as poly (3-substituted thiophene) , poly (3, 4-bisubstituted thiophene), polybenzothiophene, polyisothianapthene, poly (N-substi
  • the mixture ratio of the inorganic material and the organic material it is possible to appropriately set the mixture ratio of the inorganic material and the organic material. If the mixture ratio of the inorganic ferroelectric material is increased, the formation temperature is increased while the dielectric constant of the mixture is increased, whereas if the mixture ratio of the inorganic ferroelectric material is decreased, the formation temperature is lowered while the dielectric constant of the mixture is reduced.
  • the ferroelectric layer is formed using a mixed solution of an inorganic material and an organic material, it is possible to easily form the ferroelectric layer by an ink-jet printing, spin coating or screen printing method;
  • FIGS. 2A to 6 are graphs showing polarization characteristics of ferroelectric layers formed of an inorganic ferroelectric material and an organic ferroelectric material such as PbZr x Tii- x O 3 (PZT) and PVDF- TrFE mixed in predetermined ratios .
  • the ferroelectric layer was formed in such a manner that a PZT solution and a PVDF-TrFE solution were mixed in a predetermined ratio to form a mixed solution, the mixed solution was coated on a silicon wafer by a spin coating method, and the resulting silicon wafer was heated in the temperature range of 150 to 200 °C on a hot plate for a predetermined period of time.
  • the PZT solution was prepared by mixing a PZO solution and a PTO solution, in which the PZO solution was formed by mixing a zirconium propoxide solution with a mixed solution of a 2-methoxyethanol solution and a lead acetate trihydrate solution and the PTO solution was formed by mixing a titanium isopropoxide solution with the mixed solution of the 2-methoxyethanol solution and the lead acetate trihydrate solution.
  • the PVDF-TrFE solution was prepared by dissolving PVDF-TrFE powder in a solvent such as C 4 H 5 O (THF), C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF), and C 2 H 6 OS (DMSO).
  • a solvent such as C 4 H 5 O (THF), C 4 H 8 O (MEK), C 3 H 6 O (acetone), C 3 H 7 NO (DMF), and C 2 H 6 OS (DMSO).
  • FIG. 2 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:1
  • FIG. 3 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 2:1
  • FIG. 4 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 3:1
  • FIG. 5 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:2
  • FIG. 6 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:3.
  • the thickness of the ferroelectric layer was 50 nm; in FIGS. 2B, 3B, 4B, 5 and 6, the thickness of the ferroelectric layer was 75 nm; and in FIG. 2C, the thickness of the ferroelectric layer was 100 nm.
  • the characteristic curves represented as A show the polarization characteristics in which the formation temperature of the ferroelectric layer was 190 ° C
  • the characteristic curves represented as B show the polarization characteristics in which the formation temperature of the ferroelectric layer was 170 ° C
  • the characteristic curves represented as C show the polarization characteristics in which the formation temperature of the ferroelectric layer was 150 ° C.
  • FIG. 7 is a diagram showing a structure of a memory device in accordance with a first embodiment of the present invention.
  • a plurality of lower electrodes 71 and a plurality of upper electrodes 73 are arranged to intersect each other on a substrate 70, and a ferroelectric layer 72 is provided at each intersection of the lower electrodes 71 and the upper electrodes 73.
  • the substrate 70 may be formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material such as flexible plastic.
  • the available organic materials may include polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET), polyvinylchloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4- methyl-1-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO) , polysulfone (PSF) , polyphenylenesulfide (PPS) , polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL), polystyrene (PS), AS resin, ABS resin, polymethylmethacrylate (PMMA) , fluorocarbon resin, phenol
  • the substrate 70 may be formed of any kinds of materials, not limited to specific ones.
  • the lower electrode 71 and the upper electrode 73 may be formed of a material selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 ) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
  • conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO 3 )
  • conductive metal oxides conductive metal alloys
  • the ferroelectric layer 72 may be formed of a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material, and a mixture further comprising a suicide, a silicate or any other metal.
  • a drive device for driving the respective electrodes and a sense amplifier for residing the polarization values of the ferroelectric layer 72 may be electrically coupled to the lower and upper electrodes 71 and 73 in the same manner as the general memory device.
  • the lower electrodes 71 are formed on the substrate 70 in a commonly used method.
  • a ferroelectric solution in accordance with the present invention is coated on the above structure by an ink-jet printing, spin coating or screen printing method, and the resulting structure is baked at a temperature below 200 ° C, for example, thus forming a ferroelectric film.
  • an etching process is performed by a buffered oxide etching (BOE) , two-step etching using BOE and gold etchant, or reactive ion etching (RIE) method to remove the ferroelectric film except for the intersections of the lower electrodes 71 and the upper electrodes 73, thus formincj the ferroelectric layer 72.
  • BOE buffered oxide etching
  • RIE reactive ion etching
  • the upper electrodes 73 are formed on the resulting structure in a commonly used method.
  • FIGS. 8A and 8B are diagrams showing a modified structure of the memory device of FIG. 7, in which FIG. 8A is a plan view and FIG. 8B is a cross-sectional view thereof.
  • the ferroelectric layer 72 is formed at each intersection of the lower electrodes 71 and the upper electrodes 73, constituting the capacitors; however, in this embodiment as shown in FIGS. 8A and 8B, a ferroelectric layer 82 is formed on the overall surface of a plurality of lower electrodes 81 arranged in the horizontal direction, and a plurality of upper electrodes 83 is formed on the top of the ferroelectric layer 82 in the vertical direction to intersect the plurality of lower electrodes 81.
  • the ferroelectric layer 82 is formed on the overall surface of the lower electrodes formed on a substrate 80 in this embodiment, the formation process of the ferroelectric layer 82 is very simplified. Moreover, since each of the intersections of the lower electrodes 81 and the upper electrodes 83 functions as a capacitor, the operation of the present embodiment is substantially the same as that of the embodiment shown in FIG. 7. Moreover, since the materials of the substrate 80, lower and upper electrodes 81 and 83 and ferroelectric layer 82 are substantially the same as those of the embodiment shown in FIG. 7, their detailed description will be omitted.
  • the memory devices in accordance with the above embodiments have the 1C structure.
  • the memory device of the present invention has a simpler structure than the conventional memory structure including the transistor and the: capacitor or the memory device having the IT structure. Moreover, it is possible to form a greater number of memory devices in the same area. Moreover, since the memory devices in accordance with the above embodiments do not need the transistor that requires a complicated process to form a memory device, the manufacturing process of the memory device is very simplified.
  • FIG. 9 is a cross-sectional view showing a structure of a memory device in accordance with a second embodiment of the present invention.
  • a plurality of first memory cells 110 is formed on a substrate 100, and an insulating layer 120 of polyimide (PI), for example, is coated on the overall surface of the first memory cells 110.
  • PI polyimide
  • the substrate 100 may be formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material such as flexible plastic, the same as the embodiments of FIGS . 7 and 8.
  • the first and second memory cells 110 and 130 are formed in the same structure as those of FIGS. 7 and 8. That is, the first and second memory cells 110 and 130 are formed such that lower electrodes 111 and 131 are arranged to interest upper electrodes 113 and 133 and ferroelectric layers 112 and 132 are formed between the electrodes.
  • the electrode 11 connected to a ground in the memory cell composed of a capacity is referred to as a ground electrode and the electrode 13 connected to a data output is referred to as a data eLectrode
  • the lower electrodes 111 and 131 correspond to the ground electrode
  • the upper electrodes 113 and 133 correspond to the data electrode.
  • the upper and lower electrodes are referred to as the data and ground electrodes, respectively.
  • the ferroelectric layers 112 and 132 formed between the ground electrodes 111 and 131 and the data electrodes 113 and 133 are formed restrictively at the intersections of the ground electrodes 111 and 133 and the data electrodes 113 and 133 as shown in FIG. 7, or formed to coat the overall surface of the ground electrodes 111 and 131 as shown in FIG. 8.
  • the first memory cell 110 may be formed so that the ferroelectric layer 112 is formed only at the intersection of both electrodes 111 and 131
  • the second memory cell 120 may be formed so that the ferroelectric layer 132 is formed to coat the overall surface of the ground electrode 131.
  • the first memory cell 110 may be formed so that the ferroelectric layer 112 is formed to coat the overall surface of the ground electrode 111
  • the second memory cell 130 may be formed so that the ferroelectric layer 332 is formed only at the intersection of both electrodes 131 and 133.
  • the ferroelectric layers 112 and 132 may be formed of a mixture of an inorganic ferroelectric material and an organic material as described above.
  • the ferroelectric layer 112 and the ferroelectric layer 132 may not be formed of the same material, but may be formed of different materials, if necessary.
  • the ferroelectric material 112 may be formed of a mixture of an inorganic ferroelectric material and an organic material
  • the ferroelectric layer 132 may be formed of a mixture of an inorganic ferroelectric material and an organic ferroelectric material
  • the ferroelectric layers 112 and 132 may be formed of any kind of ferroelectric mixture provided by the present invention. Moreover, although the description has been given to the case where the memory cells are formed in a double layer in this embodiment, it is possible to form the memory cells in a multiple layer in the same manner.
  • the memory cells 110 and 130 are stacked with the insulating layer 120 interposed therebetween, it is possible to form the memory cells in quantity in the same area.
  • FIG. 10 is a cross-sectional view showing a modified structure of the memory device of FIG. 9, in which substantially the same elements as those of FIG. 9 have the same reference numerals and their detailed description will be omitted.
  • the ground electrodes 111 and 131 are formed as the lower electrodes, and the data electrodes 113 and 133 are formed as the upper electrodes.
  • the ground electrode 111 of the first memory cell 110 is formed as the upper electrode, and the data electrode 113 is formed as the lower electrode.
  • the ground electrodes 111 and 131 of the first and second memory cells 110 and 130 are arranged adjacent to each other through the insulating layer 120. Accordingly, it is possible to prevent the charge from being accumulated unnecessarily between the first and second memory cells 110 and 130.
  • FIG. 11 is a cross-sectional view showing a modified structure of the memory device of FIG. 9, in which substantially the same elements as those of FIGS. 9 and 10 have the same reference numerals and their detailed description will be omitted.
  • the ground electrode 111 of the first memory cell 110 and the ground electrode 131 of the second memory cell 130 are arranged adjacent to each other through the insulating layer 120.
  • the insulating layer 120 is eliminated, and the ground electrodes 111 and 131 of the first and second memory cells 110 and 130 are formed in a single layer.
  • an insulating layer may be formed on the overall surface of the second memory cell 130 and then the corresponding memory cell may be formed in the same manner.
  • the present invention it is possible to realize a memory device having a simple structure without using a switching element to achieve high density and low cost and capable of using various kinds of substrates such as an organic material or paper, and a method of manufacturing the same.

Abstract

Disclosed herein are a memory device formed in a simple structure without using a switching element such as a transistor and providing a non-volatile storage, and a method of manufacturing the same. The memory device in accordance with the present invention includes: a substrate 70; a plurality of lower electrodes 71 formed parallel to each other on the substrate 70; a ferroelectric layer 72 formed on the lower electrodes; and a plurality of upper electrodes 73 formed to intersect the lower electrodes 71, the ferroelectric layer 72 being composed of a mixture of an inorganic ferroelectric material and an organic material.

Description

[DESCRIPTION!
[invention Title]
MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
[Technical Field]
The present invention relates to a memory device capable of reading and writing information and, more particularly, to a memory device capable of non-volatile data storage with a simple structure without using a switching element such as a transistor, and a method of manufacturing the same .
[Background Art]
At present, various kinds of memory devices using semiconductor devices are used. Such memory devices include read only memories (ROMs) such as an electrically programmable ROM (EPROM) , an electrically erasable PROM (EEPROM) and a flash ROM (FROM) , and random access memories (RAMs) such as a static RAM (SRAM), a dynamic RAM (DRAM) and a ferroelectric RAM (FRAM) .
All of the semiconductor memory devices used at present basically comprises a switching element such as a transistor and a storage element such as a capacitor. These memory devices write, erase and read data by storing and reading a data value in the storage element through the switching element.
Accordingly, the conventional semiconductor memory devices have some drawbacks in that they require a lot of manufacturing processes due to the formation of the switching element and the storage element on a wafer and it is difficult to obtain a high density over a predetermined level.
[Disclosure] [Technical Problem]
Accordingly, the present invention has been made in an effort to solve the above-described problems. The present invention provides a memory device capable of non-volatile data storage with a simple structure without using a switching element or a storage element, and a method of manufacturing the same.
[Technical Solution]
In accordance with a first aspect of the present invention, there is provided a memory device comprising: a substrate; a lower electrode provided on the substrate and formed of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode provided on the ferroelectric layer and formed of a conductive material, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
In accordance with a second aspect of the present invention, there is provides a memory device comprising: a substrate; a lower electrode provided on the substrate and formed of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode provided on the ferroelectric layer and formed of a conductive material, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
In accordance with a third aspect of the present invention, there is provides a memory device comprising: a substrate; a plurality of lower electrodes formed parallel to each other on the substrate; a ferroelectric layer formed on the lower electrodes; and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material .
In accordance with a fourth aspect of the present invention, there is provides a memory device comprising: a substrate; a plurality of lower electrodes formed parallel to each other on the substrate; a ferroelectric layer formed on the lower electrodes; and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
The substrate may be formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material.
The organic material may comprise at least one selected from the group consisting of polyimide (PI), polycarbonate (PC) , polyethersulfone (PES) , polyetheretherketone (PEEK) , polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET), pol yvinylchloride (PVC), polyethylene (PE) , ethylene copolymer, polypropylene (PP) , propylene copolymer, poly (4-methyl-l-pentene) (TPX), polyarylate (PAR) , polyacetal (POM) , polyphenyleneoxide (PPO), polysulfone (PSF), polypheny]. enesulfide (PPS), polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL) , polystyrene (PS), AS resin, ABS resin, polymethylmethacrylate (PMMA), fluorocarbon resin, phenol-formaldehyde (PF) resin, melamine-formaldehyde (MF) resin, urea-formaldehyde (UF) resin, unsaturated polyester (UP) resin, epoxy (EP) resin, diallylphthalate (DAP) resin, polyurethane (PUR) , polyamide (PA) , silicon (SI) resin or their mixtures and compounds. The inorganic ferroelectric material may comprise at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture thereof.
The inorganic ferroelectric material may be PZT. The mixture may further comprise a suicide, a silicate or any other metal.
The organic material may be a polymer ferroelectric materiεil .
The polymer ferroelectric material may comprise at least one selected from the group consisting of polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano- polymer, and polymer or copolymer thereof.
The polymer ferroelectric material may be PVDF-TrFE. The ferroelectric layer may be formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
In accordance with a fifth aspect of the present invention, there is provides a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
In accordance with a sixth aspect of the present invention, there is provides a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first, memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material. In accordance with a seventh aspect of the present invention, there is provides a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
In accordance with an eighth aspect of the present invention, there is provides a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
In accordance with a ninth aspect of the present invention, there is provides a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layers of the first and second memory cells are formed of different materials.
In accordance with a tenth aspect of the present invention, there is provides a memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layers of the first and second memory cells are formed of different materials.
The memory device may further comprise an insulating layer formed between the first memory cell and the second memory cell.
The upper electrode of the first memory cell and the lower electrode of the second memory cell may be ground electrodes .
The ground cells of the first memory cell and the second memory cell may be formed integrally with each other.
The upper electrode of the first memory cell and the lower electrode of the second memory cell may be data electrodes.
In accordance with an eleventh aspect of the present invention, there is provides a method of manufacturing a memory device, the method comprising: forming a lower electrode on a substrate; forming a ferroelectric layer of a mixture of an inorganic ferroelectric material and an organic material on the overall surface of the substrate on which the lower electrode is formed; and forming an upper electrode on the ferroelectric layer. The organic material may be an organic ferroelectric material.
In the process of forming the ferroelectric layer, a mixed solution of an inorganic ferroelectric solution and an organic solution may be coated on the substrate to form a ferroelectric film, and the ferroelectric film may be heated and baked to form the ferroelectric layer.
The mixed solution may comprise a PZT solution and a PVDF-TrFE solution.
The PZT solution may be prepared by mixing a PZO solution and a PTO solution.
The PVDF-TrFE solution may be prepared by dissolving PVDF-TrFE powder in at least one solvent selected from the group consisting of C4H5O (THF), C4H8O (MEK), C3H6O (acetone), C3H7NO (DMF) , and C2H6OS (DMSO) . The ferroelectric layer may be formed by a spin coating method.
The ferroelectric layer may be formed by an ink-jet printing method.
The ferroelectric layer may be formed by a screen printing method.
The method may further comprise etching and removing the ferroelectric layer except for the intersection of the lower electrode and the upper electrode.
The process of etching the ferroelectric layer may be performed by a buffered oxide etching (BOE) method.
The process of etching the ferroelectric layer may be performed by a two-step etching method using BOE and gold etchant .
The process of etching the ferroelectric layer may be performed by a reactive ion etching (RIE) method.
The baking temperature may be below 200°C.
[Description of Drawings]
FIG. 1 is an equivalent circuit diagram of a memory device having a 1C structure in accordance with the present invention;
FIGS. 2A to 6 are graphs showing capacitance-voltage characteristics of ferroelectric materials applied to the present, invention; FIG. 7 is a diagram showing a structure of a memory device in accordance with a first embodiment of the present invention;
FIGS. 8A and 8B are diagrams showing a modified structure of the memory device of FIG. 7; FIG. 9 is a cross-sectional view showing a structure of a memory device in accordance with a second embodiment of the present invention; and
FIGS. 10 and 11 are cross-sectional views showing modified structures of the memory device of FIG. 9.
[Mode for Invention]
Hereinafter, preferred embodiments in accordance with the present invention will be described with reference to the accompanying drawings. The preferred embodiments are provided so that those skilled in the art can sufficiently understand the present invention, but can be modified in various forms and the scope of the present invention is not limited to the preferred embodiments.
First, the basic concept of the present invention will be described below.
In general, a memory device is to store digital data. Accordingly, if any structure capable of storing data "0" or "1" and reading the stored data can be effectively used as a memory device. At present, a commonly known ferroelectric material has a specific polarization value according to a voltage applied from the outside, and such a polarization value is maintained for a predetermined period of time even in the case where the external power is cut off. According to the study by the present inventor, using the above-described polarization characteristics can realize a memory device having one-capacitor (1C) structure as shown in FIG. 1. Of course, in the structure of FIG. 1, the ferroelectric material is used as a ferroelectric layer 13 between a lower electrode 11 and an upper electrode 12.
Recently, there have been various attempts to realize a memory device having one-transistor (IT) structure using the ferroelectric material. However, in order to form a transistor on a silicon substrate, for example, a drain region, a source region and a channel region should be first formed on the substrate and then electrodes should be formed on the drain and source regions and a gate layer. Accordingly, a plurality of manufacturing processes is required. However, the formation of the capacitor can be made with a simple manufacturing process in which a dielectric layer is formed on a lower electrode and then an upper electrode is formed thereon. Moreover, since the capacitor structure requires a space smaller than that required by the transistor structure, it is possible to form a larger number of elements in the same space. Moreover, since it is not necessary to form the drain, source and channel regions for the formation of the transistor in the structure of FIG. 1, differently from the conventional memory structure, the substrate such as the silicon substrate is not required. In other words, in the structure of FIG. 1, since the memory device can be realized only by forming a conductive thin film for the formation of the upper and lower electrodes and a ferroelectric thin film, the substrate of a specific material for obtaining the memory device is not required. Accordingly, it is possible to significantly reduce the manufacturing cost of the memory device,. Moreover, since the memory device can be formed on a flexible material such as resin or paper, it is possible to obtain a memory device capable of being folded or rolled up.
However, in order to apply the above-described concept, an appropriate ferroelectric material is required.
At present, there are known various materials showing ferroelectric characteristics. Such materials are broadly classified into inorganic materials and organic materials. The inorganic ferroelectric materials include ferroelectric oxides, ferroelectric fluorides such as BaMgF4 (BMF) , and ferroelectric semiconductors. The organic ferroelectric materials include polymer ferroelectric materials and the like. The ferroelectric oxides include perovskite ferroelectric materials such as PbZrxTii_xO3 (PZT) , BaTiO3 and PBTiO3, pseudo-ilmenite ferroelectric materials such as LiNbO3 and LiTaO3, tungsten-bronze (TB) ferroelectric materials such as PbNb3Og and Ba2NaNbs0i5, ferroelectric materials having a bismuth layer structure such as SrBi2Ta2θg (SBT), (Bi, La)4Ti3Oi2 (BLT) and Bi4Ti3Oi2, pyrochlore ferroelectric materials such as La2Ti2O7, and ferroelectric materials such as RMnO3, Pb5Ge3On (PGO) and BiFeO3 (BFO) including a rare earth element (R) such as Y, Er, Ho, Tm, Yb and Lu ,
Moreover, the ferroelectric semiconductors include 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe and CdFeSe. Furthermore, the polymer ferroelectric materials include polyvinylidene fluoride (PVDF) , PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd-numbered nylon, cyano-polymer, and polymer or copolymer thereof.
In general, the inorganic ferroelectric materials including the ferroelectric oxides, the ferroelectric fluorides and the ferroelectric semiconductors have dielectric constants greater than those of the organic ferroelectric materials. Accordingly, the generally proposed ferroelectric field-effect transistor (FET) or ferroelectric memory device employs the inorganic ferroeLectric materials for forming the ferroelectric layer.
However, the above-described inorganic ferroelectric materials require a high temperature treatment above 500 "C, for example, to be formed on a substrate. In the case where a ferroelectric layer or a ferroelectric thin film is formed through the high temperature treatment on the substrate, there are limitations associated with using the flexible material such as resin or paper. That is, the materials capable of being used as the substrate of the memory device are limited.
In the present invention, a mixture of an inorganic ferroelectric material and an organic material or an organic ferroelectric material is used as the material for the ferroelectric layer. According to the study by the present inventor, the inorganic ferroelectric materials are formed at higher temperatures, while their dielectric constants are high. However, the organic materials including the organic ferroelectric materials are formed at lower temperatures, while their dielectric constants are relatively low. Accordingly, when mixing the inorganic ferroelectric material with the organic material or the organic ferroelectric material, it is possible to obtain a ferroelectric material having a dielectric constant above a predetermined value and formed at a much lower temperature. In this case, methods of forming mixed solutions of the inorganic ferroelectric material and the organic material or the organic ferroelectric material are as follows: 1. Mixing an inorganic powder with an organic powder and dissolving the mixed powders in a solvent to form a mixed solution;
2. Dissolving an organic powder in an inorganic solution to form a mixed solution; 3. Dissolving an inorganic powder in an organic solution to form a mixed solution; and
4. Mixing an organic solution with an inorganic solution to form a mixed solution.
Moreover, the inorganic ferroelectric material and the organic material may be mixed with each other as follows:
1. Mixing an inorganic ferroelectric material with an organic material;
2. Mixing an inorganic ferroelectric material with an organic ferroelectric material; 3. Mixing a solid solution of an inorganic ferroelectric material with an organic material; 4. Mixing a solid solution of an inorganic ferroelectric material with an organic ferroelectric material; and 5. Mixing the aforementioned mixture with a suicide, a silicate or another metal.
Of course, the above mixing methods are not limited to specific methods and any method that can appropriately mix the inorganic material with the organic material may be employed.
The organic materials mixed with the inorganic ferroelectric material include, a monomer, an oligomer, a polymer, and a copolymer. Preferably, an organic material having a high dielectric constant may be used. The organic materials having a high dielectric constant include polyvinylpyrrolidone (PVP), polycarbonate (PC) , polyvinyl chloride (PVC) , polystyrene (PS) , epoxy, polymethylmethacrylate (PMMA), polyimide (PI), polyethylene (PE) , polyvinyl alcohol (PVA) , polyhexamethylene adipamide (nylon 66), polyetherketoneketone (PEKK), and the like. Moreover, the organic materials include a nonpolar organic material, such as fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly (α-methyl styrene) , poly (α-vinylnaphthalene) , poly (vinyltoluene) , polyethylene, cis-polybutadiene, polypropylene, polyisoprene, poly (4-methyl-l-pentene) , poly (tetrafluoroethylene) , poly (chlorotrifluoroethylene) , poly (2-methyl-l, 3-butadiene) , poly (p-xylylene) , poly(α-α-α'~ α ' -tetrafluoro-p-xylylene) , poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate] , pol y (cyclohexyl methacrylate) , poly (chlorostyrene) , poly (2, β-dimethyl-1, 4- phenylene ether), polyisobutylene, poly (vinyl cyclohexane) , poly(arylene ether), and polyphenylene, or copolymers having a low dielectric constant, such as poly (ethylene/tetrafluoroethylene) , poly (ethylene/chlorotrifluoroethylene) , fluorinated ethylene/propylene copolymer, polystyrene-co-α-methyl styrene, ethylene/ethyl acrylate copolymer, poly (styrene/10%butadiene) , poly (styrene/15%butadiene) , poly (styrene/2, 4-dimethylstyrene) , Cytop, Teflon AF, and polypropylene-co-1-butene .
Other organic semi-conducting materials that can be used in this invention include soluble compounds and soluble derivatives of compounds of the following list: conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene) , polyfluorene including oligomers of those conjugated hydrocarbon polymers; condensed aromatic hydrocarbons such as anthracene, tetracene, chrysene, pentacene, pyrene, perylene, coronene; oligomeric para substituted phenylenes such as p-quaterphenyl (p-4P) , p- quinquephenyl (p-5P) , p-sexiphenyl (p-βP) ; conjugated heterocyclic polymers such as poly (3-substituted thiophene) , poly (3, 4-bisubstituted thiophene), polybenzothiophene, polyisothianapthene, poly (N-substituted pyrrole), poly(3- substituted pyrrole), poly (3, 4-bisubstituted pyrrole), polyfuran, polypyridine, poly-1, 3, 4-oxadiazoles, polyisothianaphthene, poly (N-substituted aniline), poly(2- substituted aniline), poly (3-substituted aniline), poly (2,3- bisubstituted aniline) , polyazulene, polypyrene; pyrazoline compounds; polyselenophene; polybenzofuran; polyindole; polypyridazine; benzidine compounds; stilbene compounds; triazines; substituted metallo- or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines, or fluoronaphthalocyanines; C60 and C70 fullerenes; N, N'- dialkyl, substituted dialkyl, diaryl or substituted diaryl- 1, 4, 5, 8-naphthalenetetracarboxylic diimide; N, N ' -dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10- perylenetetracarboxylicdiimide; bathophenanthroline; diphenoquinones; 1, 3, 4-oxadiazoles; 11,11,12,12- tetracyanonaptho-2, β-quinodimethane; α,α' -bis (dithieno [3, 2- b2 ' , 3 ' -d] thiophene) ; 2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthradithiophene; and 2,2'- bibenzo [ 1 , 2-b : 4 , 5-b ' ] dithiophene .
It is possible to appropriately set the mixture ratio of the inorganic material and the organic material. If the mixture ratio of the inorganic ferroelectric material is increased, the formation temperature is increased while the dielectric constant of the mixture is increased, whereas if the mixture ratio of the inorganic ferroelectric material is decreased, the formation temperature is lowered while the dielectric constant of the mixture is reduced.
The ferroelectric materials employed in the present invention have the following characteristics:
1. Since the ferroelectric layer is formed using a mixed solution of an inorganic material and an organic material, it is possible to easily form the ferroelectric layer by an ink-jet printing, spin coating or screen printing method; and
2. Since the formation temperature of the ferroelectric layer is lowered, it is possible to form the field-effect transistor or ferroelectric memory device on various kinds of substrates such as an organic material or paper instead of the existing silicon substrate. Meanwhile, FIGS. 2A to 6 are graphs showing polarization characteristics of ferroelectric layers formed of an inorganic ferroelectric material and an organic ferroelectric material such as PbZrxTii-xO3 (PZT) and PVDF- TrFE mixed in predetermined ratios .
Here, the ferroelectric layer was formed in such a manner that a PZT solution and a PVDF-TrFE solution were mixed in a predetermined ratio to form a mixed solution, the mixed solution was coated on a silicon wafer by a spin coating method, and the resulting silicon wafer was heated in the temperature range of 150 to 200 °C on a hot plate for a predetermined period of time. Moreover, the PZT solution was prepared by mixing a PZO solution and a PTO solution, in which the PZO solution was formed by mixing a zirconium propoxide solution with a mixed solution of a 2-methoxyethanol solution and a lead acetate trihydrate solution and the PTO solution was formed by mixing a titanium isopropoxide solution with the mixed solution of the 2-methoxyethanol solution and the lead acetate trihydrate solution.
The PVDF-TrFE solution was prepared by dissolving PVDF-TrFE powder in a solvent such as C4H5O (THF), C4H8O (MEK), C3H6O (acetone), C3H7NO (DMF), and C2H6OS (DMSO).
FIG. 2 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:1, FIG. 3 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 2:1, FIG. 4 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 3:1, FIG. 5 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:2, and FIG. 6 shows the polarization characteristics in which the mixed ratio of the PZT and PVDF-TrFE was 1:3.
In FIGS. 2A, 3A and 4A, the thickness of the ferroelectric layer was 50 nm; in FIGS. 2B, 3B, 4B, 5 and 6, the thickness of the ferroelectric layer was 75 nm; and in FIG. 2C, the thickness of the ferroelectric layer was 100 nm. Moreover, in FIGS. 2 to 6, the characteristic curves represented as A show the polarization characteristics in which the formation temperature of the ferroelectric layer was 190 °C, the characteristic curves represented as B show the polarization characteristics in which the formation temperature of the ferroelectric layer was 170 °C, and the characteristic curves represented as C show the polarization characteristics in which the formation temperature of the ferroelectric layer was 150°C. Referring to FIGS. 2 to 6, in the case where the mixed ratio of the PZT and PVDF-TrFE was 1:1 or in the case where the mixed ratio of the PVDF-TrFE was greater than that of the PZT, generally good polarization characteristics were shown in the temperature range of ] 50 to 190°C, and the higher the mixed ratio of the PZT was, the better the polarization characteristics were shown at higher temperatures .
Moreover, the higher the thickness of the ferroelectric layer, the lower the polarization value, i.e., the capacitance value, whereas the greater the size of the memory window.
Especially, it was remarkable that, even in the case where the mixed ratio of the PZT and PVDF-TrFE was changed or in the case where the formation temperature was set to a temperature below about 200 "C, excellent hysteresis characteristics were shown.
FIG. 7 is a diagram showing a structure of a memory device in accordance with a first embodiment of the present invention. In FIG. 7, a plurality of lower electrodes 71 and a plurality of upper electrodes 73 are arranged to intersect each other on a substrate 70, and a ferroelectric layer 72 is provided at each intersection of the lower electrodes 71 and the upper electrodes 73. Here, the substrate 70 may be formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material such as flexible plastic. Moreover, the available organic materials may include polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET), polyvinylchloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4- methyl-1-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO) , polysulfone (PSF) , polyphenylenesulfide (PPS) , polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL), polystyrene (PS), AS resin, ABS resin, polymethylmethacrylate (PMMA) , fluorocarbon resin, phenol-formaldehyde (PF) resin, melamine-formaldehyde (MF) resin, urea-formaldehyde (UF) resin, unsaturated polyester (UP) resin, epoxy (EP) resin, diallylphthalate (DAP) resin, polyurethane (PUR), polyamide (PA), silicon (SI) resin or their mixtures and compounds.
Of course, the substrate 70 may be formed of any kinds of materials, not limited to specific ones.
The lower electrode 71 and the upper electrode 73 may be formed of a material selected from the group consisting of conductive metals including gold (Au) , silver (Ag) , aluminum (Al), platinum (Pt), indium tin oxide (ITO), and strontiumtitanate (SrTiO3) , conductive metal oxides, conductive metal alloys, and conductive metal compounds and, further, conductive organics with a conductive polymer as a substrate such as polyaniline and poly (3,4- ethylenedioxythiophene) /poly (styrenesulfonate) (PEDOT/PSS) , conductive organic mixtures, conductive organic compounds, and conductive organic multilayer materials.
Moreover, the ferroelectric layer 72 may be formed of a mixture of an inorganic ferroelectric material or a solid solution thereof and an organic material or an organic ferroelectric material, and a mixture further comprising a suicide, a silicate or any other metal.
Although not depicted in the figure, a drive device for driving the respective electrodes and a sense amplifier for residing the polarization values of the ferroelectric layer 72 may be electrically coupled to the lower and upper electrodes 71 and 73 in the same manner as the general memory device.
In manufacturing the above-described memory device, the lower electrodes 71 are formed on the substrate 70 in a commonly used method.
Then, a ferroelectric solution in accordance with the present invention is coated on the above structure by an ink-jet printing, spin coating or screen printing method, and the resulting structure is baked at a temperature below 200°C, for example, thus forming a ferroelectric film.
Subsequently, an etching process is performed by a buffered oxide etching (BOE) , two-step etching using BOE and gold etchant, or reactive ion etching (RIE) method to remove the ferroelectric film except for the intersections of the lower electrodes 71 and the upper electrodes 73, thus formincj the ferroelectric layer 72.
Next, the upper electrodes 73 are formed on the resulting structure in a commonly used method.
FIGS. 8A and 8B are diagrams showing a modified structure of the memory device of FIG. 7, in which FIG. 8A is a plan view and FIG. 8B is a cross-sectional view thereof. In the above embodiment as shown in FIG. 7, the ferroelectric layer 72 is formed at each intersection of the lower electrodes 71 and the upper electrodes 73, constituting the capacitors; however, in this embodiment as shown in FIGS. 8A and 8B, a ferroelectric layer 82 is formed on the overall surface of a plurality of lower electrodes 81 arranged in the horizontal direction, and a plurality of upper electrodes 83 is formed on the top of the ferroelectric layer 82 in the vertical direction to intersect the plurality of lower electrodes 81.
Since the ferroelectric layer 82 is formed on the overall surface of the lower electrodes formed on a substrate 80 in this embodiment, the formation process of the ferroelectric layer 82 is very simplified. Moreover, since each of the intersections of the lower electrodes 81 and the upper electrodes 83 functions as a capacitor, the operation of the present embodiment is substantially the same as that of the embodiment shown in FIG. 7. Moreover, since the materials of the substrate 80, lower and upper electrodes 81 and 83 and ferroelectric layer 82 are substantially the same as those of the embodiment shown in FIG. 7, their detailed description will be omitted. The memory devices in accordance with the above embodiments have the 1C structure. Accordingly, the memory device of the present invention has a simpler structure than the conventional memory structure including the transistor and the: capacitor or the memory device having the IT structure. Moreover, it is possible to form a greater number of memory devices in the same area. Moreover, since the memory devices in accordance with the above embodiments do not need the transistor that requires a complicated process to form a memory device, the manufacturing process of the memory device is very simplified.
FIG. 9 is a cross-sectional view showing a structure of a memory device in accordance with a second embodiment of the present invention. In FIG. 9, a plurality of first memory cells 110 is formed on a substrate 100, and an insulating layer 120 of polyimide (PI), for example, is coated on the overall surface of the first memory cells 110. Then, a plurality of second memory cells 130 is formed on the insulating layer 120.
The substrate 100 may be formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material such as flexible plastic, the same as the embodiments of FIGS . 7 and 8.
The first and second memory cells 110 and 130 are formed in the same structure as those of FIGS. 7 and 8. That is, the first and second memory cells 110 and 130 are formed such that lower electrodes 111 and 131 are arranged to interest upper electrodes 113 and 133 and ferroelectric layers 112 and 132 are formed between the electrodes. In the equivalent circuit of FIG. 1, if the electrode 11 connected to a ground in the memory cell composed of a capacity is referred to as a ground electrode and the electrode 13 connected to a data output is referred to as a data eLectrode, the lower electrodes 111 and 131 correspond to the ground electrode and the upper electrodes 113 and 133 correspond to the data electrode. Hereinafter, the upper and lower electrodes are referred to as the data and ground electrodes, respectively.
Meanwhile, the ferroelectric layers 112 and 132 formed between the ground electrodes 111 and 131 and the data electrodes 113 and 133 are formed restrictively at the intersections of the ground electrodes 111 and 133 and the data electrodes 113 and 133 as shown in FIG. 7, or formed to coat the overall surface of the ground electrodes 111 and 131 as shown in FIG. 8. The first memory cell 110 may be formed so that the ferroelectric layer 112 is formed only at the intersection of both electrodes 111 and 131, and the second memory cell 120 may be formed so that the ferroelectric layer 132 is formed to coat the overall surface of the ground electrode 131. Contrarily, the first memory cell 110 may be formed so that the ferroelectric layer 112 is formed to coat the overall surface of the ground electrode 111, and the second memory cell 130 may be formed so that the ferroelectric layer 332 is formed only at the intersection of both electrodes 131 and 133. Especially, the ferroelectric layers 112 and 132 may be formed of a mixture of an inorganic ferroelectric material and an organic material as described above. Of course, even in this case, the ferroelectric layer 112 and the ferroelectric layer 132 may not be formed of the same material, but may be formed of different materials, if necessary. For example, the ferroelectric material 112 may be formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layer 132 may be formed of a mixture of an inorganic ferroelectric material and an organic ferroelectric material
That is, the ferroelectric layers 112 and 132 may be formed of any kind of ferroelectric mixture provided by the present invention. Moreover, although the description has been given to the case where the memory cells are formed in a double layer in this embodiment, it is possible to form the memory cells in a multiple layer in the same manner.
In the above embodiment, since the memory cells 110 and 130 are stacked with the insulating layer 120 interposed therebetween, it is possible to form the memory cells in quantity in the same area.
Meanwhile, since the data electrode 113 of the first memory cell 110 is coupled to the ground electrode 131 of the second memory cell 130 through the insulating layer 120 in this embodiment, the data electrode 113 and the ground electrode 131 forms a capacitor. Accordingly, there may be an error in writing and reading data to and from the first or second memory cell 110 and 130 due to the capacitor. FIG. 10 is a cross-sectional view showing a modified structure of the memory device of FIG. 9, in which substantially the same elements as those of FIG. 9 have the same reference numerals and their detailed description will be omitted. In FIG. 9, in forming the first and second memory cells 110 and 130, the ground electrodes 111 and 131 are formed as the lower electrodes, and the data electrodes 113 and 133 are formed as the upper electrodes. However, in this embodiment, the ground electrode 111 of the first memory cell 110 is formed as the upper electrode, and the data electrode 113 is formed as the lower electrode.
Like this, the ground electrodes 111 and 131 of the first and second memory cells 110 and 130 are arranged adjacent to each other through the insulating layer 120. Accordingly, it is possible to prevent the charge from being accumulated unnecessarily between the first and second memory cells 110 and 130.
Moreover, in the case where another memory cell is formed on the second memory cell 130 through an insulating layer in this embodiment, it is preferable that a lower electrode of the corresponding memory cell be formed as the data electrode and an upper electrode thereof be formed as the ground electrode so that the data electrodes between both memory cells may be arranged adjacent to each other. Meanwhile, FIG. 11 is a cross-sectional view showing a modified structure of the memory device of FIG. 9, in which substantially the same elements as those of FIGS. 9 and 10 have the same reference numerals and their detailed description will be omitted. In FIG. 10, the ground electrode 111 of the first memory cell 110 and the ground electrode 131 of the second memory cell 130 are arranged adjacent to each other through the insulating layer 120. However, in this embodiment as shown in FIG. 11, the insulating layer 120 is eliminated, and the ground electrodes 111 and 131 of the first and second memory cells 110 and 130 are formed in a single layer.
Meanwhile, in the case where another memory cell is stacked on the second memory cell 130 in this embodiment as shown in FIG. 11, an insulating layer may be formed on the overall surface of the second memory cell 130 and then the corresponding memory cell may be formed in the same manner.
As described above, according to the above-described embodiments of the present invention, it is possible to form a plurality of memory cells on a substrate by sequentially stacking one memory cell on top of the other memory cell. Accordingly, it is possible to form the memory cells in quantity in the same area, compared with the conventional methods .
The invention has been described in detail with reference to preferred embodiments thereof. However, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
[industrial Applicability]
As described above, according to the present invention, it is possible to realize a memory device having a simple structure without using a switching element to achieve high density and low cost and capable of using various kinds of substrates such as an organic material or paper, and a method of manufacturing the same.

Claims

[CLAIMS]
[Claim l]
A memory device comprising: a substrate; a lower electrode provided on the substrate and formed of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode provided on the ferroelectric layer and formed of a conductive material, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material .
[Claim 2]
The memory device of claim 1, wherein the lower and upper electrodes are formed of a conductive organic material
[Claim 3] The memory device of claim 1, wherein the substrate is formed of a Si wafer, a Ge wafer, paper, paper coated with parylene, or an organic material.
[Claim 4] The memory device of claim 3, wherein the organic material comprises at least one selected from the group consisting of polyimide (PI), polycarbonate (PC), polyethersulfone (PES) , polyetheretherketone (PEEK) , polybutyleneterephthalate (PBT) , polyethyleneterephthalate (PET), polyvinylchloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4- methyl-1-pentene) (TPX) , polyarylate (PAR), polyacetal (POM), polyphenyleneoxide (PPO) , polysulfone (PSF) , polyphenylenesulfide (PPS) , polyvinylidenechloride (PVDC) , polyvinylacetate (PVAC) , polyvinylalcohol (PVA) , polyvinylacetal (PVAL), polystyrene (PS), AS resin, ABS resin, polymethylmethacrylate (PMMA) , fluorocarbon resin, phenol-formaldehyde (PF) resin, me] amine-formaldehyde (MF) resin, urea-formaldehyde (UF) resin, unsaturated polyester (UP) resin, epoxy (EP) resin, dial] ylphthalate (DAP) resin, polyurethane (PUR), polyamide (PA), silicon (SI) resin or their mixtures and compounds .
[Claim 5] The memory device of claim 1, wherein the inorganic ferroelectric material comprises at least one selected from the group consisting of a ferroelectric oxide, a ferroelectric fluoride, a ferroelectric semiconductor, and a mixture; thereof. [Claim β]
The memory device of claim 1, wherein the inorganic ferroelectric material is PZT.
[Claim 7]
The memory device of claim 1, wherein the mixture further comprises a suicide, a silicate or any other metal.
[Claim 8] The memory device of claim 1, wherein the organic material is a polymer ferroelectric material.
[Claim 9]
The memory device of claim 8, wherein the polymer ferroelectric material comprises at least one selected from the group consisting of polyvinylidene fluoride (PVDF), PVDF polymer, PVDF copolymer, PVDF terpolymer and, further, odd- numbered nylon, cyano-polymer, and polymer or copolymer thereof .
[Claim 10]
The memory device of claim 8, wherein the polymer ferroelectric material is PVDF-TrFE.
[Claim ll] The memory device of claim 1, wherein the ferroelectric layer is formed by heating and baking a mixed solution of an inorganic ferroelectric solution and an organic solution.
[Claim 12]
A memory device comprising: a substrate; a lower electrode provided on the substrate and formed of a conductive material; a ferroelectric layer provided on the lower electrode; and an upper electrode provided on the ferroelectric layer and formed of a conductive material , wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material .
[Claim 13] The memory device of claim 12, wherein the mixture further comprises a suicide, a silicate or any other metal.
[Claim 14]
A memory device comprising: a substrate; a plurality of lower electrodes formed parallel to each other on the substrate; a ferroelectric layer formed on the lower electrodes; and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material.
[Claim 15]
The memory device of claim 14, wherein the ferroelectric layer is formed at each intersection of the lower electrodes and the upper electrodes.
[Claim lβ]
The memory device of claim 14, wherein the lower and upper electrodes are formed of a conductive organic material
[Claim 17]
The memory device of claim 14, wherein the substrate is formed of a Si wafer, a Ge wafei , paper, paper coated with parylene, or an organic material. [Claim 18]
A memory device comprising: a substrate; a plurality of lower electrodes formed parallel to each other on the substrate; a ferroelectric layer formed on the lower electrodes; and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
[Claim 19]
The memory device of claim 18, wherein the mixture further comprises a suicide, a silicate or any other metal.
[Claim 20] A method of manufacturing a memory device, the method comprising: forming a lower electrode on a substrate; forming a ferroelectric layer of a mixture of an inorganic ferroelectric material and an organic material on the overall surface of the substrate on which the lower electrode is formed; and forming an upper electrode on the ferroelectric layer.
[Claim 2l] The method of claim 20, wherein the organic material is an organic ferroelectric material.
[Claim 22]
The method of claim 20, wherein, in forming the ferroelectric layer, a mixed solution of an inorganic ferroelectric solution and an organic solution is coated on the substrate to form a ferroelectric film, and the ferroelectric film is heated and baked to form the ferroelectric layer.
[Claim 23]
The method of claim 22, wherein the mixed solution comprises a PZT solution and a PVDF-TrFE solution.
[Claim 24]
The method of claim 23, wherein the PZT solution is prepared by mixing a PZO solution and a PTO solution.
[Claim 25] The method of claim 23, wherein the PVDF-TrFE solution is prepared by dissolving PVDF-TrFE] powder in at least one solvent selected from the group consisting of C4H5O ( THF) , C4H8O (MEK) , C3H6O ( acetone ) , C3H7NO ( DMF) , and C2H6OS ( DMSO ) .
[Claim 26]
The method of claim 22, wherein the ferroelectric layer is formed by a spin coating method.
[Claim 27] The method of claim 22, wherein the ferroelectric layer is formed by an ink-jet printing method.
[Claim 28]
The method of claim 22, wherein the ferroelectric layer is formed by a screen printing method.
[Claim 29]
The method of claim 20, further comprising etching and removing the ferroelectric layer except for the intersection of the lower electrode and the upper electrode.
[Claim 30]
The method of claim 29, wherein etching the ferroelectric layer is performed by a buffered oxide etching (BOE) method. [Claim 31]
The method of claim 29, wherein etching the ferroelectric layer is performed by a two-step etching method using BOE and gold etchant.
[Claim 32]
The method of claim 29, wherein etching the ferroelectric layer is performed by a reactive ion etching (RIE) method.
[Claim 33]
The method of claim 20, wherein the baking temperature is below 200°C.
[Claim 34]
A memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material .
[Claim 35]
The memory device of claim 34, further comprising an insulating layer formed between the first memory cell and the second memory cell.
[Claim 36]
The memory device of claim 34, wherein the upper electrode of the first memory cell and the lower electrode of the second memory cell are ground electrodes.
[Claim 37]
The memory device of claim 34, wherein the ground cells of the first memory cell and the second memory cell are formed integrally with each other.
[Claim 38]
The memory device of claim 34, wherein the upper electrode of the first memory cell and the lower electrode of the second memory cell are data electrodes.
[Claim 39] A memory device comprising: a. first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
[Claim 40] A memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material .
[Claim 41] A memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material.
[Claim 42] A memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a lower electrode formed of a conductive material, a ferroelectric layer provided on the lower electrode, and an upper electrode provided on the ferroelectric layer and formed of a conductive material, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layers of the first and second memory cells are formed of different materials.
[Claim 43] A memory device comprising: a first memory cell formed on a substrate; and a second memory cell formed on the top of the first memory cell, wherein the first and second memory cells include a plurality of lower electrodes formed parallel to each other on the substrate, a ferroelectric layer formed on the lower electrodes, and a plurality of upper electrodes formed parallel to each other on the ferroelectric layer and intersecting the plurality of lower electrodes, and wherein the ferroelectric layer is formed of a mixture of an inorganic ferroelectric material and an organic material, and the ferroelectric layers of the first and second memory cells are formed of different materials.
PCT/KR2007/002883 2006-12-29 2007-06-14 Memory device and method of manufacturing the same WO2008082045A1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR10-2006-0138752 2006-12-29
KR10-2006-0138735 2006-12-29
KR20060138735 2006-12-29
KR20060138752 2006-12-29
KR1020070057575A KR100876135B1 (en) 2006-12-29 2007-06-13 Memory device and manufacturing method thereof
KR10-2007-0057575 2007-06-13

Publications (1)

Publication Number Publication Date
WO2008082045A1 true WO2008082045A1 (en) 2008-07-10

Family

ID=39588695

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2007/002883 WO2008082045A1 (en) 2006-12-29 2007-06-14 Memory device and method of manufacturing the same

Country Status (1)

Country Link
WO (1) WO2008082045A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017079511A1 (en) * 2015-11-06 2017-05-11 Carver Scientific, Inc. Electroentropic memory device
US10403440B2 (en) 2016-12-02 2019-09-03 Carver Scientific, Inc. Capacitive energy storage device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942776A (en) * 1997-03-07 1999-08-24 Sharp Laboratories Of America, Inc. Shallow junction ferroelectric memory cell and method of making the same
US6236076B1 (en) * 1999-04-29 2001-05-22 Symetrix Corporation Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942776A (en) * 1997-03-07 1999-08-24 Sharp Laboratories Of America, Inc. Shallow junction ferroelectric memory cell and method of making the same
US6236076B1 (en) * 1999-04-29 2001-05-22 Symetrix Corporation Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017079511A1 (en) * 2015-11-06 2017-05-11 Carver Scientific, Inc. Electroentropic memory device
US9679630B2 (en) 2015-11-06 2017-06-13 Carver Scientific, Inc. Electroentropic memory device
US10403440B2 (en) 2016-12-02 2019-09-03 Carver Scientific, Inc. Capacitive energy storage device
US10622159B2 (en) 2016-12-02 2020-04-14 Carver Scientific, Inc. Capacitive energy storage device
US10903015B2 (en) 2016-12-02 2021-01-26 Carver Scientific, Inc. Capacitive energy storage device
US10984958B2 (en) 2016-12-02 2021-04-20 Carver Scientific, Inc. Capacitive energy storage device

Similar Documents

Publication Publication Date Title
Ling et al. Polymer electronic memories: Materials, devices and mechanisms
Heremans et al. Polymer and organic nonvolatile memory devices
KR100876136B1 (en) Field Effect Transistor and Ferroelectric Memory Device Having MFC Structure and Manufacturing Method Thereof
US20080128682A1 (en) Ferrodielectric Memory Device And Method For Manufacturing The Same
KR100876135B1 (en) Memory device and manufacturing method thereof
US20100215836A1 (en) Ferroelectric material and method of forming ferroelectric layer using the same
JP5241489B2 (en) Method for manufacturing ferroelectric memory device
WO2008126961A1 (en) Mfmis-fet, mfmis-ferroelectric memory device, and methods of manufacturing the same
US7619268B2 (en) Fast remanent resistive ferroelectric memory
KR101559995B1 (en) MFMS-FET ferroelectric memory device and Methods of manufacturing the same
WO2008082045A1 (en) Memory device and method of manufacturing the same
KR20080097977A (en) Ferroelectric memory device, fet, and methods of manufacturing the same
KR100851538B1 (en) FET, ferroelectric memory device, and methods of manufacturing the same
WO2008082046A1 (en) Ferroelectric memory device, fet, and methods of manufacturing the same
US20080027196A1 (en) Organic Material For Ferroelectric Semiconductor Device
WO2008082047A1 (en) Fet, ferroelectric memory device, and methods of manufacturing the same
KR100877429B1 (en) Ferroelectric memory device
KR20130021836A (en) Ferroelectric memory device, fet, and methods of manufacturing the same
WO2008082044A1 (en) Fet, ferroelectric memory device, and methods of manufacturing the same
KR20080095232A (en) Ferroelectric memory device and methods of manufacturing the same
KR100877428B1 (en) FET, ferroelectric memory device, and methods of manufacturing the same
KR101449755B1 (en) Ferroelectric material and method of forming ferroelectric layer using the same
KR20080108960A (en) Ferroelectric material and method of forming ferroelectric layer using the same
KR20100005627A (en) Bfo based ferroelectric material and manufacturing method thereof
JP5440852B2 (en) MFMS field effect transistor and ferroelectric memory device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07746917

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07746917

Country of ref document: EP

Kind code of ref document: A1