WO2008069485A1 - Dispositifs électroniques contenant des nanotubes de carbone à structure verticale et procédé de fabrication - Google Patents

Dispositifs électroniques contenant des nanotubes de carbone à structure verticale et procédé de fabrication Download PDF

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Publication number
WO2008069485A1
WO2008069485A1 PCT/KR2007/006028 KR2007006028W WO2008069485A1 WO 2008069485 A1 WO2008069485 A1 WO 2008069485A1 KR 2007006028 W KR2007006028 W KR 2007006028W WO 2008069485 A1 WO2008069485 A1 WO 2008069485A1
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WO
WIPO (PCT)
Prior art keywords
insulating layer
forming
silicon
gate
carbon nanotube
Prior art date
Application number
PCT/KR2007/006028
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English (en)
Inventor
Woo Seok Cheong
Jin Ho Lee
Original Assignee
Electronics And Telecommunications Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020070057150A external-priority patent/KR100820174B1/ko
Application filed by Electronics And Telecommunications Research Institute filed Critical Electronics And Telecommunications Research Institute
Priority to US12/517,803 priority Critical patent/US7989286B2/en
Publication of WO2008069485A1 publication Critical patent/WO2008069485A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present invention relates to a method of manufacturing an electronic device using carbon nanotubes (CNTs), and more particularly, to a method of manufacturing an electronic device having a vertical CNT channel grown by a selective vertical growth technique.
  • CNTs carbon nanotubes
  • the present invention has been produced from the work supported by the IT R&D program of MIC (Ministry of Information and Communication) /ITTA (Institute for Information Technology Advancement) [2005-S-073-02, Development of semiconductor circuit design based on the nano-scaled device] in Korea. Background Art
  • FIG. 1 illustrates a conventional electronic device using horizontal CNTs.
  • a conventional CNT electronic device 100 includes a silicon substrate 101, an oxide 102 formed thereon, a source 103 and a drain 104 formed over the oxide 102, a CNT channel 105 formed between the source 103 and the drain 104 to horizontally connect the source 103 with the drain 104, and a gate 106 formed on the CNT channel 105.
  • the present invention is directed to a method of manufacturing an electronic device which can arrange carbon nanotubes (CNTs) in accurate positions and improve a contact characteristic of the CNT by including a vertical CNT channel formed by a selective vertical growth technique of the CNTs.
  • One aspect of the present invention provides a method of manufacturing an electronic device using a vertical carbon nanotube (CNT), including the steps of: (a) preparing a substrate on which a silicon source is formed; (b) forming a first insulating layer on the substrate, and etching the first insulating layer such that a top surface of the silicon source is exposed; (c) forming a second insulating layer on the silicon source, and forming a gate by patterning the second insulating layer; (d) forming a third insulating layer on the gate, and forming a through hole in which a carbon nanotube channel is to be formed by etching the third insulating layer and the second insulating layer; (e) forming a fourth insulating layer surrounding the gate on the through hole and the third insulating layer, and forming a spacer by etching the fourth insulating layer; (f) forming a metal catalyst on the silicon source; (g) vertically growing the carbon nanotube channel on the silicon source using the metal catalyst;
  • the substrate may be a silicon on insulator (SOI) substrate or a poly crystalline silicon substrate.
  • SOI silicon on insulator
  • Step (c) may include the steps of: coating the second insulating layer with photoresist
  • Step (d) may include the steps of: coating the third insulating layer with PR, and patterning the PR by exposure; etching the second and third insulating layers to form the through hole; and removing the PR on the third insulating layer.
  • Step (f) may include the steps of: forming a metal catalyst particle in the air and dropping it onto the silicon source and the third insulating layer; annealing the metal catalyst particle in a vacuum; and removing the metal particles on the third insulating layer.
  • Step (i) may include the steps of: coating the fifth insulating layer with PR, and patterning the fifth insulating layer by exposure; etching the fifth insulating layer until an end portion of the CNT is exposed; removing the PR on the fifth insulating layer; and forming a silicon drain on the fifth insulating layer.
  • Step (c) may include the steps of: coating the second insulating layer with PR, and patterning the PR by exposure; etching the second insulating layer using the patterned PR to form gate holes at both sides of the silicon source, respectively, and removing the PR; and forming a gate material over the second insulating layer and in the gate hole.
  • Step (i) may include the steps of: coating the fifth insulating layer with PR, and patterning the fifth insulating layer by exposure; etching the fifth insulating layer until an end portion of the CNT is exposed; removing the PR on the fifth insulating layer; cleaning an etched surface of the fifth insulating layer; and forming a drain by selectively growing silicon on the etched surface.
  • the metal catalyst in step (g) may be one of Fe, Ni, Pt, Pd, Cu, Au and Al.
  • the gate material in step (c) may be one of metal, suicide, and doped silicon.
  • Another aspect of the present invention provides an electronic device using a vertical
  • CNT including: a silicon source formed on a substrate; a first insulating layer exposing a top surface of the silicon source and formed on the substrate; a second insulating layer formed on the first insulating layer and having a through hole exposing the silicon source; at least one carbon nanotube grown perpendicular to a top surface of the silicon source exposed through the through hole; at least one gate formed parallel to the growth direction of the carbon nanotube to be in contact with the through hole; and a silicon drain connected to an end portion of the carbon nanotube exposed through the through hole.
  • the gate may be formed of one of metal, suicide, and doped silicon.
  • the substrate may be an SOI substrate or a polycrystalline silicon substrate.
  • the length of the CNT may be 50 to 250nm.
  • the silicon drain may be formed by a selective silicon growth technique.
  • the through hole in which the CNT is formed may be filled with an insulating layer.
  • the present invention uses a carbon nanotube (CNT) having a vertical structure, and applies a selective silicon growth technique, thereby solving an arrangement problem of CNTs having a horizontal structure.
  • CNT carbon nanotube
  • the CNT is formed in a vertical structure, it can realize a highly integrated device more than twice that formed in a horizontal structure, and a dual gate structure can be simply formed by disposing gates at both sides of a CNT channel.
  • the CNTs can be connected to each other, thereby simplifying processes, improving a contact characteristic, and increasing reliability of the process of manufacturing an electronic device using CNTs to increase a ripple effect on related technology in the future.
  • FIG. 1 illustrates a conventional electronic device using horizontal carbon nanotubes
  • FIGS. 2A to 5D are cross-sectional views illustrating a process of manufacturing an electronic device according to an exemplary embodiment of the present invention.
  • FIG. 6A to 6C are cross-sectional views illustrating a process of manufacturing a dual gate electronic device according to another exemplary embodiment of the present invention.
  • FIG. 7 illustrates a silicon drain formed by selective silicon growth.
  • FIGS. 2A to 5D are cross-sectional views illustrating a process of manufacturing a vertical CNT electronic device according to an exemplary embodiment of the present invention.
  • a substrate 1 is first prepared.
  • the substrate 1 is usually a silicon on insulator (SOI) substrate in which a silicon layer Ia is formed on a lower insulating layer Ib.
  • SOI silicon on insulator
  • the substrate 1 can be a polycrystalline silicon substrate formed by thermally oxidizing a silicon surface.
  • the lower insulating layer Ib may be formed of oxide or nitride.
  • a photoresist (PR) 2a is coated on the substrate 1 and patterned by exposure and patterning to form a PR pattern 2 for forming a silicon source.
  • the silicon layer Ia is etched using the patterned PR 2, thereby forming a silicon source 3.
  • a dry etching process is used, and an ashing process is performed to remove the PR pattern 2.
  • O ashing is used.
  • the patterned silicon source 3 has a height and width of 10 to lOOnm, respectively.
  • a first insulating layer 4 is formed on the substrate 1 having the silicon source 3.
  • the first insulating layer 4 may be formed of oxide or nitride to cover the entire silicon source 3.
  • the first insulating layer 4 formed to cover the silicon source 3 is etched, thereby exposing a top surface of the silicon source 3.
  • the first insulating layer 4 is removed by blanket etching or chemical mechanical polishing (CMP).
  • a second insulating layer 5 may be formed to a thickness of 20 to 200nm on the first insulating layer 4 having the silicon source 3 whose top surface is exposed.
  • the second insulating layer 5 is formed using an oxide layer having good vertical etchability by high density plasma (HDP) deposition, or by flowing a coated boro-phospho silicate glass (BPSG) layer.
  • a photoresist (PR) 6 is coated on the second insulating layer 5, and then patterned to form an opening 6a for forming a gate electrode.
  • the opening 6a for forming a gate electrode may have a width of 10 to lOOnm.
  • a contact hole 5a is formed in the second insulating layer 5 using the PR pattern 6 having the opening 6a as an etch mask by dry etching.
  • the first insulating layer 4 is different from the second insulating layer 5 (for example, the first insulating layer is a nitride layer, and the second insulating layer is an oxide layer), the first insulating layer 4 is not affected during the etching of the second insulating layer 5.
  • both the insulating layers 4 and 5 are formed of the same material, the first insulating layer 4 may get damaged during the etching of the second insulating layer 5, so the second insulating layer 5 is etched by dry etching having a high etch selectivity in order not to damage the first insulating layer 4.
  • the gate material 7a may be one of metal (tungsten (W), a W alloy, etc.), suicide (W-silicide, nickel (Ni)-silicide, etc.) and doped silicon.
  • a gate 7 is formed by removing the gate material 7 a formed on the second insulating layer 5, except for the gate material 7 a in the contact hole 5 a, by blanket-etching or CMP.
  • a third insulating layer 8 is deposited on the second insulating layer 5.
  • the third insulating layer 8 may be formed of oxide or nitride.
  • a PR pattern 9 having an opening 9a is formed on the third insulating layer 8.
  • the opening 9a is formed to be spaced apart from the gate 7, and the third insulating layer 8 and the second insulating layer 5 are dry-etched using the PR pattern 9 having the opening 9a, thereby forming a contact hole 8a.
  • only the third insulating layer 8 and the second insulating layer 5 are etched not to damage the silicon source 3.
  • a fourth insulating layer 10 having good step coverage is formed on the exposed silicon source 3 and the third insulating layer 8.
  • the fourth insulating layer 10 may be formed to a thickness of 5 to 50nm using a nitride layer or an oxide layer.
  • the fourth insulating layer 10 is etched to form a spacer 11.
  • the spacer 11 may be formed to a thickness of 2 to 20nm not to expose the gate 7. After that, a cleaning process is performed to remove etching damage to the silicon source due to etching, because the etching damage may affect contact characteristics between the CNT and silicon.
  • FIG. 4C is a cross-sectional view illustrating a process of forming a metal catalyst particle.
  • the metal catalyst particle 12 may be formed of metal such as iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), copper (Cu), gold (Au) or aluminum (Al), and may have a diameter of 2 to 20nm.
  • the metal catalyst particle is formed in the air and then dropped onto the substrate. After that, the particle is annealed in a vacuum at a temperature of 500 0 C or less, and thus the metal catalyst particle 12 and the silicon source 3 are strongly bonded to each other.
  • the annealing is performed at too high a temperature or for too long a time, the metal catalyst particle 12 can penetrate into the silicon.
  • an ultra-sonic cleaning or laser shock cleaning process is performed to remove the metal catalyst particles 12 from the third insulating layer 8.
  • a CNT 13 is vertically grown after leaving the metal catalyst particle 12 only on the silicon source 3.
  • the CNT 13 may be 50 to 250nm long, and may be grown to be a single wall CNT (SWCNT).
  • the CNT growth methods (which include chemical vapor deposition (CVD), vapor phase growth, plasma enhanced chemical vapor deposition (PECVD), arc-discharging and laser deposition) may have a slow growth rate and precisely control the CNT's length.
  • the spacer 11 is removed by etching, and a fifth insulating layer 14 having good step coverage is formed.
  • the fifth insulating layer 14 may be formed of oxide or nitride.
  • PR photoresist
  • the fifth insulating layer 14 is etched to expose an end portion of the CNT 13 vertically formed, and the PR pattern 15 is removed.
  • a silicon drain 16 is deposited on the fifth insulating layer 14 to be connected with the CNT 13.
  • the silicon on the fifth insulating layer 14 is removed by blanket-etching or CMP.
  • FIGS. 2A to 5D The method of manufacturing a vertical CNT electronic device has been described with reference to FIGS. 2A to 5D, according to an exemplary embodiment of the present invention.
  • a method according to another exemplary embodiment of the present invention will now be described with reference to FIGS. 6 A to 6C, and FIG. 7.
  • FIGS. 6A to 6C are cross-sectional views illustrating a process of manufacturing a vertical CNT electronic device having a dual gate.
  • a PR patterning process 17 is performed to form an opening 17a, thereby forming two gates at both sides of the silicon source.
  • a contact hole 5a is formed in a second insulating layer 5 using the PR pattern 17 by dry etching, as illustrated in FIG. 3B, and then is filled with a gate material 7 a.
  • FIG. 6C illustrates a completed vertical CNT electronic device having a dual gate.
  • FIG. 7 illustrates a drain formed by a selective silicon growth technique.
  • a fifth insulating layer 14 is etched, cleaned and then grown by the selective silicon growth technique as illustrated in FIG. 5B.
  • the selective silicon growth technique the process of blanket- etching a silicon thin film after forming the silicon thin film may be omitted. Since the CNT is a conductor, a drain 18 can be filled with silicon by the selective silicon growth.

Abstract

L'invention concerne un dispositif électronique dans lequel sont utilisés des nanotubes de carbone (CNT) et son procédé de fabrication. Le procédé de fabrication du dispositif électronique à CNT vertical consiste (a) à préparer un substrat sur lequel est formée une source de silicium; (b) à former une couche isolante sur le substrat et à graver la première couche isolante de manière à exposer une surface supérieure de la source de silicium; (c) à former une deuxième couche isolante sur la source de silicium et à former une porte par modelage de la deuxième couche isolante; (d) à former une troisième couche isolante sur la porte et à former un trou de passage dans lequel doit être formé un canal de nanotube de carbone par gravure de la troisième couche isolante et de la deuxième couche isolante; (e) à former une quatrième couche isolante entourant la porte sur le trou de passage et la troisième couche isolante et à former un élément séparateur par gravure de la quatrième couche isolante; (f) à former un catalyseur métallique sur la source de silicium; (g) à former de manière verticale le canal du nanotube de carbone sur la source de silicium à l'aide du catalyseur métallique; (h) à former une cinquième couche isolante sur le trou de passage dans lequel est formé le nanotube de carbone et la troisième couche isolante; et (i) à modeler la cinquième couche isolante de manière à exposer le canal de nanotube de carbone et à former un drain de silicium. Le problème de disposition des CNT horizontaux peut être résolu par application de CNT verticaux et par utilisation d'une technique de croissance de silicium sélective.
PCT/KR2007/006028 2006-12-05 2007-11-27 Dispositifs électroniques contenant des nanotubes de carbone à structure verticale et procédé de fabrication WO2008069485A1 (fr)

Priority Applications (1)

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US12/517,803 US7989286B2 (en) 2006-12-05 2007-11-27 Electronic devices using carbon nanotubes having vertical structure and the manufacturing method thereof

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KR10-2006-0122354 2006-12-05
KR20060122354 2006-12-05
KR10-2007-0057150 2007-06-12
KR1020070057150A KR100820174B1 (ko) 2006-12-05 2007-06-12 수직구조의 탄소나노튜브를 이용한 전자소자 및 그제조방법

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2329502A1 (fr) * 2008-09-29 2011-06-08 Wentworth Laboratories, Inc. Cartes-sondes comprenant des sondes à nanotubes et procédés de façonnage
US9267968B2 (en) 2010-12-09 2016-02-23 Wentworth Laboratories, Inc. Probe card assemblies and probe pins including carbon nanotubes

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566704B2 (en) * 2000-06-27 2003-05-20 Samsung Electronics Co., Ltd. Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
US20050167655A1 (en) * 2004-01-29 2005-08-04 International Business Machines Corporation Vertical nanotube semiconductor device structures and methods of forming the same
US6930343B2 (en) * 2002-11-15 2005-08-16 Samsung Electronics Co., Ltd. Nonvolatile memory device utilizing a vertical nanotube
US20060249726A1 (en) * 2005-05-07 2006-11-09 Samsung Electronics Co., Ltd. Semiconductor devices including nano tubes and methods of operating and fabricating the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6566704B2 (en) * 2000-06-27 2003-05-20 Samsung Electronics Co., Ltd. Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
US6930343B2 (en) * 2002-11-15 2005-08-16 Samsung Electronics Co., Ltd. Nonvolatile memory device utilizing a vertical nanotube
US20050167655A1 (en) * 2004-01-29 2005-08-04 International Business Machines Corporation Vertical nanotube semiconductor device structures and methods of forming the same
US20060249726A1 (en) * 2005-05-07 2006-11-09 Samsung Electronics Co., Ltd. Semiconductor devices including nano tubes and methods of operating and fabricating the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2329502A1 (fr) * 2008-09-29 2011-06-08 Wentworth Laboratories, Inc. Cartes-sondes comprenant des sondes à nanotubes et procédés de façonnage
EP2329502A4 (fr) * 2008-09-29 2012-08-22 Wentworth Lab Inc Cartes-sondes comprenant des sondes à nanotubes et procédés de façonnage
US9851378B2 (en) 2008-09-29 2017-12-26 Wentworth Laboratories Inc. Methods of fabricating probe cards including nanotubes
US10234480B2 (en) 2008-09-29 2019-03-19 Wentworth Laboratories, Inc. Methods of fabricating probe cards including nanotubes
US9267968B2 (en) 2010-12-09 2016-02-23 Wentworth Laboratories, Inc. Probe card assemblies and probe pins including carbon nanotubes

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