WO2008019605A1 - Procédé et dispositif permettant d'améliorer les performances de maintien d'impulsions pour la synchronisation des heures satellites - Google Patents

Procédé et dispositif permettant d'améliorer les performances de maintien d'impulsions pour la synchronisation des heures satellites Download PDF

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Publication number
WO2008019605A1
WO2008019605A1 PCT/CN2007/070326 CN2007070326W WO2008019605A1 WO 2008019605 A1 WO2008019605 A1 WO 2008019605A1 CN 2007070326 W CN2007070326 W CN 2007070326W WO 2008019605 A1 WO2008019605 A1 WO 2008019605A1
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WIPO (PCT)
Prior art keywords
phase difference
local
pulse
satellite
phase
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PCT/CN2007/070326
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English (en)
Chinese (zh)
Inventor
Quanhong Ma
Xiaotie Zhang
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Huawei Technologies Co., Ltd.
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Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Publication of WO2008019605A1 publication Critical patent/WO2008019605A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/204—Multiple access
    • H04B7/212—Time-division multiple access [TDMA]
    • H04B7/2125—Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Definitions

  • the present invention relates to satellite timing techniques in the field of wireless communications, and more particularly to methods and apparatus for improving satellite time synchronization pulse retention performance.
  • GPS Global Positioning System
  • GLONASS Global Navigation Satellite System
  • Beidou Navigation System The currently widely used satellite navigation systems are: Global Positioning System (GPS), Global Navigation Satellite System (GLONASS), and Beidou Navigation System. They all use navigation satellites for time measurement and ranging, and can perform all-dimensional real-time three-dimensional navigation and positioning in sea, land and air. Due to their high accuracy, weatherability and wide coverage, satellite navigation systems play an important role in precision navigation, command and dispatch.
  • satellite navigation systems are navigation positioning and timing.
  • the user is equipped with a satellite receiver, it can receive signals from space satellites in real time and in real time, thus obtaining accurate navigation and positioning information and accurate time information, including time, year, month, day, hour, minute and second.
  • satellite time synchronization pulse signal that is, 1PPS (second pulse) signal. Since the satellite is equipped with a helium atomic clock, it has high frequency accuracy and time accuracy.
  • any device needs a clock to provide its operating frequency, so clock performance is an important factor affecting device performance.
  • the performance of the clock is usually improved by increasing the quality of the external sync signal.
  • a conventional method of generating a clock frequency is to utilize a crystal and an atomic clock.
  • crystals will age and be susceptible to changes in the external environment. Long-term precision drift affects the frequency of their output.
  • Atomic clocks also have deviations after long-term use and require periodic calibration, so neither can provide high-quality external synchronization signals. Satellites regularly correct their own clocks, so their clocks are stable for a long time and have characteristics that are insensitive to changes in external physical factors. At present, many products use satellite signals as external synchronization signals to obtain accurate frequencies and achieve precise timing.
  • the local clock for each product is referenced to the satellite clock and is as synchronized as possible with the satellite.
  • the usual practice is: After receiving the 1PPS and absolute time information of the satellite, the satellite card forwards the received information to the system, and then the system processes it accordingly, thereby realizing the time synchronization of the entire network. Satellite signals are temporarily lost when the satellite card receiving antenna is suspended due to interference from the Earth's magnetic field or weather.
  • the local clock can be used to track the satellite clock signal, and the satellite time synchronization pulse can be maintained, so that the system can work normally for a period of time after losing the satellite signal.
  • the length of the hold time is determined by the frequency accuracy of the local clock.
  • Communication equipment usually uses a crystal oscillator as the local clock.
  • the allowable deviation of the output frequency of the crystal with respect to the nominal frequency is referred to as the frequency accuracy of the crystal.
  • the crystal oscillator can be divided into a common crystal oscillator (PXO), a temperature compensated crystal oscillator (TCXO), a voltage controlled crystal oscillator (VCXO), and a constant temperature crystal oscillator (OCXO).
  • the ordinary crystal oscillator is a crystal oscillator that does not take temperature compensation measures.
  • the frequency stability depends on the performance of the crystal used inside. It is generally used as a vibration source or intermediate signal in ordinary places, and is the cheapest product in the crystal oscillator;
  • the crystal oscillator adopts measures to compensate the crystal frequency-temperature characteristics inside the crystal oscillator to meet the stability requirement in a wide temperature range, due to its good startup characteristics, low power consumption, small size, and environmental adaptability. Strong and many other advantages, it has been widely used;
  • Voltage-controlled crystal oscillator is a crystal oscillator that can change the crystal oscillator output frequency by adjusting the applied voltage. It is mainly used for phase-locked loop or frequency trimming, and its frequency control.
  • Range and linearity mainly depend on the combination of varactor diode and crystal parameters used in the circuit; the constant temperature crystal oscillator adopts precise temperature control, so that the circuit components and crystals work at the temperature of the zero temperature coefficient point of the crystal, and the frequency stability of the medium precision product 8 ⁇ 10- about 10-7, the frequency stability of product precision in the order of 10-9 or more, mainly used Rate or standard signal source.
  • a constant temperature crystal oscillator is generally selected as the local clock source.
  • the local clock is synchronized with the satellite time synchronization pulse signal.
  • the clock signal output from the constant temperature crystal oscillator is divided into two paths, one through the frequency divider to generate the local 1PPS signal, and the other used as the 1Hz (Hz) phase detector.
  • the counting clock of the module that is, the time interval for controlling the two adjacent phases. Since the implementation of the frequency divider is the counting frequency division, the counter in the frequency divider is decremented by one count from the initial value of the counting. When the counting value is a certain value, the output signal state of the frequency divider changes, so the frequency is divided.
  • the phase of the local 1PPS signal can be changed by adjusting the initial value of the divider.
  • the frequency-divided local 1PPS signal and the satellite 1PPS signal are phase-detected in the 1Hz phase-detection module.
  • the CPU adjusts the initial value of the frequency divider to adjust the phase of the local 1PPS signal to achieve local
  • the 1PPS signal tracks the satellite 1PPS signal.
  • the satellite 1PPS signal is input to the 1PPS signal loss detection module, and the module provides information to the CPU whether the satellite time synchronization pulse is lost.
  • the purpose of inputting the local 1PPS signal to the CPU is to: facilitate the CPU to use the 1PPS for timing.
  • a frequency multiplication module can be added between the constant temperature crystal oscillator and the frequency division module of the scheme to improve the effect of the local 1PPS signal to track the satellite 1PPS signal.
  • the local 1PPS can be aligned to the satellite's 1PPS signal to a certain extent, the phase deviation of the local 1PPS signal and the satellite 1PPS signal in the above scheme is relatively large, which is only locally.
  • the phase deviation between the 1PPS signal and the satellite 1PPS signal is too large to a preset phase correction threshold, the local 1PPS signal is forcibly corrected so that the local 1PPS signal and the satellite 1PPS signal are in phase, and the local 1PPS is not controlled from the source.
  • the phase deviation of the signal from the satellite 1PPS signal It can be seen that the above scheme still has low performance for maintaining the satellite time synchronization pulse.
  • the embodiments of the present invention provide a method and apparatus for improving the time synchronization pulse retention performance of a satellite, reducing the rate of phase difference increase, and reducing the number of local 1PPS phase corrections per unit time under the same phase difference tolerance. , greatly extending the phase hold time of the local 1PPS signal to the satellite time synchronization pulse.
  • a method for improving satellite time synchronization pulse retention performance provided by an embodiment of the present invention includes the following steps:
  • the period of the local second pulse is adjusted according to the rate value of the phase difference change.
  • Embodiments of the present invention also provide an apparatus for improving satellite time synchronization pulse retention performance, including a frequency divider and a 1 Hz phase detection module, and a CPU module for reading a local second pulse and a satellite second pulse from a 1 Hz phase detection module.
  • the phase difference between the two when the rate value of the phase difference change is greater than or equal to the correction threshold of the phase difference change rate, adjusts the mode of the frequency divider according to the rate value of the phase difference change.
  • the period of the local 1PPS pulse is adjusted to compensate for the negative influence of the aging frequency deviation of the constant temperature crystal on the phase shift of the local 1PPS pulse, thereby reducing the unit from the cost.
  • the phase offset of the local IPPS pulse relative to the satellite IPPS pulse during the time under the same phase difference tolerance, reduce the number of local 1PPS phase corrections per unit time, and increase the local 1PPS hold time;
  • the hardware of the satellite time synchronization pulse hold function is implemented by adding a small number of software algorithms without adding any hardware modules. Therefore, the hardware structure is relatively simple and the cost is low.
  • the software algorithm of the embodiment of the present invention is relatively simple and easy to implement.
  • FIG. 1 is a schematic diagram of the implementation of satellite time synchronization pulse retention performance in the prior art.
  • Figure 2 is a plot of the difference between the local 1PPS and the satellite 1PPS signal in the absence of phase correction and modulo correction.
  • Figure 3 is a plot of the difference between the local 1PPS and the satellite 1PPS signal in the presence of phase correction.
  • Figure 4 is a plot of the difference between the local 1PPS and the satellite 1PPS signal after the mode correction of the divider.
  • Figure 5 is a flow chart of a specific embodiment of the present invention.
  • a small amount of software algorithm is added to the hardware in FIG. 1 by using the characteristic that the constant temperature crystal oscillator has a fixed output frequency in a short time, and the phase difference between the local 1PPS and the satellite 1PPS is solved from the source by the mode correction technique of the frequency divider.
  • the cumulative problem is to reduce the rate of phase difference increase. Under the same phase difference tolerance, the number of local 1PPS phase corrections per unit time is reduced, and the local 1PPS hold time is increased.
  • the short-term stability of the constant-temperature crystal oscillator is very good, it can be approximated that the output frequency of the constant-temperature crystal oscillator is fixed in a short time.
  • the actual output frequency of the constant temperature crystal oscillator cannot be absolutely equal to its nominal frequency, and the difference between the two is recorded as AF. It can be considered constant in a short time.
  • the phase of the signal is the integral of the frequency, if there is no phase correction and modulo correction of the CPU to the divider, as shown in Figure 2, the phase difference between the local 1PPS and the satellite 1PPS will increase linearly with time and eventually exceed the system. Difference tolerance.
  • the system sets a phase difference correction threshold that is less than the phase difference tolerance.
  • Figure 3 shows the phase-time relationship between the local 1PPS and the satellite 1PPS signal in the presence of phase correction, between the local 1PPS and the satellite 1PPS.
  • a method for improving satellite time synchronization pulse retention performance includes the following steps:
  • Step 501 The CPU sets a correction threshold of the phase difference correction threshold and the phase difference change rate.
  • the CPU sets the value of the phase difference correction threshold as a criterion for judging whether phase correction of the frequency divider is required in the subsequent step; the CPU sets the correction threshold of the phase difference change rate as a mode for determining whether the frequency divider needs to be performed in the subsequent step.
  • the standard of calibration is a standard of calibration.
  • Step 502 The CPU reads the phase difference between the local 1PPS and the satellite 1PPS every second. ⁇
  • the CPU After the local 1PPS and the satellite 1PPS are phase-detected in the 1Hz phase-detection module, the CPU reads the phase difference between the two from the output of the 1Hz phase-detection module.
  • Step 503 The CPU determines whether the phase difference is greater than or equal to the phase difference correction threshold. If yes, step 504 is performed; otherwise, step 502 is returned.
  • Step 504 The CPU corrects the phase of the local 1PPS, and the correction amount is equal to the phase difference correction threshold.
  • the specific process of the CPU to correct the phase of the local 1PPS signal in this step is: The CPU corrects according to the phase difference
  • the value of the threshold is calculated and the initial value of the divider is adjusted so that the phase of the local 1PPS signal is close to the phase of the satellite 1PPS signal.
  • step 502 the method further includes the following steps:
  • Step 513 The CPU records and stores N+1 phase differences from step 502 in the FIFO.
  • a FIFO memory of depth N+1 is built in the CPU for recording and storing the phase difference between the local 1PPS and the satellite 1PPS.
  • the CPU records and stores N+1 phase readings between the local 1PPS and the satellite 1PPS from the output of the 1Hz phase detector module, ie ⁇ , ⁇ 2
  • FIFO memory stores the phase differences in chronological order, the earlier phase difference is placed in the front, and the subsequent phase difference is placed in the back. After the stored phase difference reaches its depth, then the new phase is placed. When the difference occurs, the FIFO memory will discard the first phase difference. Therefore, the latest difference is always recorded and stored in the FIFO memory.
  • Step 514 The CPU calculates an average rate value of the phase difference change.
  • the CPU calculates the rate of change of the phase difference, which is the amount that the mode of the frequency divider needs to be adjusted.
  • the rate of change of the phase difference is equal to the amount of phase difference change per unit time.
  • the CPU first calculates the difference ⁇ ⁇ ⁇ . ⁇ of the adjacent phase difference. Since the CPU reads the phase difference between the local 1PPS and the satellite 1PPS from the output of the 1 Hz phase detection module every second, the phase difference change rate is equal to the difference between adjacent phase differences. which is
  • the error caused by the interference of the random phase noise can be reduced by averaging the difference between the adjacent phase differences of the ⁇ group ( ⁇ - ⁇ .!), so The difference between the adjacent phase differences of the group is averaged to obtain the average rate value of the phase difference change, that is,
  • phase correction will cause the phase jump of the local 1PPS, in order to more accurately determine the average rate value of the phase difference change, this factor needs to be eliminated. Therefore, when calculating the average rate value of the phase difference change, it is considered to filter out several The largest and smallest "difference between adjacent phase differences".
  • Step 515 The CPU determines whether the average rate value of the phase difference change is greater than or equal to the correction threshold of the phase difference change rate. If yes, step 516 is performed; otherwise, the process returns to step 513.
  • Step 516 The CPU adjusts the mode of the frequency divider according to the average rate value of the phase difference change.
  • the CPU corrects the mode of the frequency divider according to the calculated value of the average rate value of the phase difference change, and the correction amount is equal to the average rate value of the phase difference change ( ⁇ ⁇ +
  • Step 517 Clear the phase difference stored in the FIFO memory.
  • the CPU when the average rate value of the phase difference change between the local 1PPS and the satellite 1PPS is greater than or equal to the correction threshold of the phase difference change rate, the CPU performs mode correction on the frequency divider, and the correction amount is equal to the average rate value of the phase difference change.
  • the mode correction of the frequency divider cannot completely solve the problem, because the mode correction can only correct the frequency deviation of an integer number of Hz, and the remaining frequency deviation can be neglected compared with the nominal frequency ( For example, at a nominal frequency of 100,000,000, the maximum value of this error is 10E-8.), and the influence on the phase difference is small.
  • phase difference accumulation caused by this frequency deviation is the root of the local 1PPS phase that cannot be permanently maintained ( The slope of the phase offset curve in Figure 4 is not 0).
  • the mode correction by the frequency divider has greatly reduced the rate of phase difference increase, which can greatly improve the performance of the local 1PPS to the satellite 1PPS signal. Therefore, the technical solution in this embodiment passes the phase correction and assists the mode correction of the frequency divider, so that the system can still maintain the synchronization of the local 1PPS and the satellite 1PPS after a long period of operation.
  • the storage medium may be a read only memory, a random access memory, a magnetic disk, an optical disk, or the like.
  • the embodiment of the present invention compensates for the impact of the local clock source frequency deviation on the local 1PPS by correcting the period of the local 1PPS, and reduces the phase offset of the local 1PPS relative to the satellite 1PPS per unit time, and increases the local 1PPS holding time.
  • the embodiment of the present invention does not need to change existing hardware, and is simple to implement and low in cost.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Electric Clocks (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un procédé et un dispositif destinés à améliorer les performances de maintien d'impulsions pour la synchronisation des heures satellites. Le procédé comprend les étapes suivantes: calcul de la valeur du taux de variation de la différence de phase entre l'impulsion locale par seconde et l'impulsion satellite par seconde; réglage de la période de l'impulsion locale par seconde en fonction de la valeur du taux de variation de la différence de phase, lorsque ce dernier est supérieur ou égal à un seuil de correction du taux de variation de la différence de phase. Lors de l'ajout de la correction d'un module d'un diviseur de fréquence, le problème d'accumulation des différences de phase entre le 1PPS local et le 1PPS satellite peut être résolu et le taux d'augmentation de la différence de phase diminue; et lorsque le seuil de correction de différence de phase est similaire, les périodes de la correction de phase du 1PPS local par unité temporelle diminuent et le temps de maintien du 1PPS local augmente.
PCT/CN2007/070326 2006-08-11 2007-07-19 Procédé et dispositif permettant d'améliorer les performances de maintien d'impulsions pour la synchronisation des heures satellites WO2008019605A1 (fr)

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EP2897001A3 (fr) * 2014-01-15 2016-06-29 The Boeing Company Surveillance d'horloge atomique multi-niveaux/multi-seuils/multi-persistance GPS/GNSS
CN106656451A (zh) * 2016-12-29 2017-05-10 中国科学院西安光学精密机械研究所 一种基于卫星授时***的守时、授时精度测试装置及方法
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EP2897001A3 (fr) * 2014-01-15 2016-06-29 The Boeing Company Surveillance d'horloge atomique multi-niveaux/multi-seuils/multi-persistance GPS/GNSS
CN106656451B (zh) * 2016-12-29 2023-06-09 中国科学院西安光学精密机械研究所 一种基于卫星授时***的守时、授时精度测试装置及方法
CN106656451A (zh) * 2016-12-29 2017-05-10 中国科学院西安光学精密机械研究所 一种基于卫星授时***的守时、授时精度测试装置及方法
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