WO2008001742A1 - Substrate structure manufacturing method, substrate structure, electron emitting element, electron emitting element manufacturing method, electron source, image display device, and laminated chip - Google Patents

Substrate structure manufacturing method, substrate structure, electron emitting element, electron emitting element manufacturing method, electron source, image display device, and laminated chip Download PDF

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Publication number
WO2008001742A1
WO2008001742A1 PCT/JP2007/062744 JP2007062744W WO2008001742A1 WO 2008001742 A1 WO2008001742 A1 WO 2008001742A1 JP 2007062744 W JP2007062744 W JP 2007062744W WO 2008001742 A1 WO2008001742 A1 WO 2008001742A1
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WO
WIPO (PCT)
Prior art keywords
substrate
hole
manufacturing
substrate structure
insert
Prior art date
Application number
PCT/JP2007/062744
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French (fr)
Japanese (ja)
Inventor
Yusuke Taki
Masaomi Kameyama
Akira Tanaka
Tomoyuki Yasukawa
Masato Suzuki
Hyunjung Lee
Hitoshi Shiku
Tomokazu Matsue
Original Assignee
Nikon Corporation
Tohoku University
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Publication of WO2008001742A1 publication Critical patent/WO2008001742A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00—Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02—Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • H01J29/04—Cathodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00—Cathode ray tubes; Electron beam tubes
    • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123—Flat display tubes
    • H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
    • H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/304—Field emission cathodes
    • H01J2201/30446—Field emission cathodes characterised by the emitter material
    • H01J2201/30453—Carbon types
    • H01J2201/30469—Carbon nanotubes (CNTs)

Definitions

  • Substrate structure manufacturing method substrate structure, electron-emitting device, electron-emitting device manufacturing method, electron source, image display device, and multilayer chip
  • the present invention relates to a substrate structure and a manufacturing method thereof, an electron-emitting device and a manufacturing method thereof, an electron source, an image display device, and a multilayer chip.
  • CNT Carbon nanotubes
  • CNTs are generally elongated fibrous (columnar) carbon materials having a diameter of about 0.5 to about OOnm and a length of about 1 to about 100 ⁇ m.
  • FEDs field emission displays
  • CNTs are mixed in a resin such as a thermoplastic polyimide resin, and a thermoplastic polyimide resin composition pellet is obtained. It is known that a thin film having a thickness of about 500 xm or less (for example, 100 xm, 20 ⁇ m, etc.) is manufactured by extrusion molding or the like.
  • an object of the present invention is to provide a substrate structure in which CNTs and other fine particles are uniformly dispersed and arranged in the whole or a part of the substrate, or arranged at an arbitrary position or region in the substrate, And a method of manufacturing the substrate structure.
  • a first step of preparing a substrate having at least one fine hole a second step of installing an electrode and immersing the substrate in a dispersion medium including a plurality of inserts, And a third step of applying a predetermined voltage to the electrode.
  • a substrate having a diameter of 5 nm to at least one hole in a range of ⁇ ⁇ ⁇ and a thickness in a range of 1 ⁇ m to lmm, and a conductive layer.
  • a substrate structure comprising: at least one insert inserted into the hole having a semiconductive property.
  • a substrate structure that emits electrons when a voltage is applied for example, A substrate structure comprising at least one substrate having at least one minute hole and at least one insert inserted into the minute hole as an electrode of the substrate structure. Is done.
  • CNTs and other conductors are inserted into the holes of the substrate in which a plurality of holes are provided in an array perpendicular to the substrate surface.
  • the conductor is accurately vertically aligned in the substrate, and a substrate structure (for example, an electron-emitting device) suitable as an electron source such as FED is damaged. It can be easily manufactured without letting it go.
  • a substrate structure for example, a conductive sheet
  • a substrate structure for example, a conductive sheet
  • the present invention it is possible to obtain a substrate structure in which CNTs, other fine particles, and the like are uniformly distributed in the whole or a part of the substrate, or are arranged in any position or region in the substrate. Can do.
  • FIG. 1 is a flowchart showing a method for manufacturing a substrate structure according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a substrate having a vertical through hole according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a state where an insert is inserted into the hole of the substrate shown in FIG.
  • FIG. 4 is a cross-sectional view showing a substrate having random through holes according to an embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a state in which an insert is inserted into the hole of the substrate shown in FIG.
  • FIG. 6 is a cross-sectional view showing a substrate having through holes obliquely crossed in a certain direction according to an embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing a state where the insert is inserted into the hole of the substrate shown in FIG.
  • FIG. 8 is a cross-sectional view showing a substrate having random recessed holes according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view showing a state where the insert is inserted into the hole of the substrate shown in FIG.
  • FIG. 10 is a cross-sectional view showing a substrate having a vertical depression hole according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a state where the insert is inserted into the hole of the substrate shown in FIG.
  • FIG. 12 is a diagram schematically showing a dielectrophoresis apparatus according to an embodiment of the present invention.
  • FIG. 13 is a diagram showing an electric field intensity distribution according to the embodiment of the present invention.
  • FIG. 14 is a diagram showing the relationship between applied frequency and dielectrophoretic force for metallic SWCNTs according to an embodiment of the present invention.
  • FIG. 15 is a diagram showing the relationship between applied frequency and dielectrophoretic force for semiconductor SWCNTs according to an embodiment of the present invention.
  • FIG. 16 is a graph showing conductivity and dielectric constant of metal SWCNTs and the like.
  • FIG. 17 is a diagram showing a schematic configuration of an FED according to an embodiment of the present invention.
  • FIG. 18 is a diagram (SEM photograph) showing a cross section of a substrate structure manufactured using the manufacturing method of the embodiment of the present invention.
  • FIG. 19 is an enlarged view of a part of FIG.
  • FIG. 20 is a diagram (SEM photograph) of a cross section of a substrate used in a manufacturing method according to an embodiment of the present invention, as seen in an oblique direction force.
  • FIG. 21 is a diagram (SEM photograph) of a cross section of a substrate structure manufactured using the manufacturing method according to the embodiment of the present invention, viewed from an oblique direction.
  • FIG. 22 is an enlarged view of a part of FIG.
  • FIG. 1 shows an outline of a method for manufacturing a substrate structure according to an embodiment of the present invention. It is a flowchart which shows an abbreviation.
  • This substrate preparation process includes a step of forming a hole in a thin plate or sheet or film base material (a plate-like body having no holes).
  • a substrate in which holes are formed at the same time as the manufacture of the substrate. In this case, the step of forming holes later is not necessary.
  • the base material of the substrate an insulating material may be used, and a semiconductive material may be used depending on the intended use.
  • the intermediate of 10 6 to the semi-conductive and electrical conductivity at room temperature is a metal insulator: refers to the nature of 10_ 7 SZM about a is material, the electrical conductivity of the semiconducting material and the insulating Less than the rate, the nature of the substance, and the conductivity described later refers to the nature of the substance greater than the electrical conductivity of the semiconductive substance.
  • a base material of the insulating substrate for example, a flexible transparent resin film such as polycarbonate, Teflon (registered trademark), polyethylene terephthalate, or the like can be used.
  • the base material of the substrate is not limited to such a transparent resin film having flexibility, and may not be flexible and may not be a resin that is not transparent.
  • an inorganic oxide such as aluminum oxide, magnesium oxide, titanium oxide, or silicon oxide may be used.
  • the material of the substrate (substrate base material) is appropriately selected according to the use of the substrate structure.
  • the thickness of the substrate (substrate base material) is selected according to the use of the substrate structure to be manufactured and the size of the insert described later, and is not particularly limited. Can do.
  • the term “flexibility” means that the function is not impaired even when a predetermined force that can be bent is applied to the substrate. Flexibility is evaluated by the bending resistance of the substrate. can do.
  • polycarbonate, Teflon (registered trademark) or poly (ethylene terephthalate) are preferred to have high resistance and bending resistance.
  • a method of forming a plurality of holes in the substrate base material used in the hole forming step various methods can be adopted depending on the diameter and direction of the hole to be formed, but a relatively small diameter (diameter 5 Onm
  • a method of etching by ion irradiation or fast neutron irradiation can be used.
  • the holes may be formed by an anodic oxidation method.
  • relatively large diameter (diameter In the case of about 50 nm or more)
  • a method of immersing in a predetermined etching solution by masking the portion other than the portion to be the hole may be used.
  • ion irradiation etching or the like may be performed while rotating and vibrating the substrate.
  • the diameter of the hole is selected according to the use of the substrate structure to be manufactured, the size and material of the insert to be described later, the dispersion medium in which the insert is dispersed, and the diameter is, for example, 5 nm to: lOO zm Can be of the order.
  • the cross-sectional shape of the hole to be formed is circular here, but may be an ellipse or other shapes.
  • the number of holes to be formed is arbitrarily set according to the use of the substrate structure to be manufactured, and may be one or more. Here, the number of holes is assumed to be plural (many).
  • the density (interval, etc.) in the case of forming a plurality of holes is appropriately selected in consideration of the use of the substrate structure to be manufactured and the strength of the substrate base material.
  • the hole to be formed may be a through hole penetrating the substrate or a recessed hole that does not penetrate the substrate.
  • the type and depth of the hole depends on the use of the substrate structure to be manufactured. It will be selected as appropriate.
  • the direction of the hole to be formed is selected according to the use of the substrate structure to be manufactured, etc., and may be substantially perpendicular to the substrate surface (substrate surface). You may be in contact.
  • each hole may be in the same direction (ie, parallel to each other) or in different directions.
  • the through hole may be formed by forming a recessed hole from one surface side of the substrate base material and performing back etching or the like from the other surface side.
  • all the holes may be randomly formed in an unspecified direction, or the plurality of holes may be divided into a plurality of gnoles, Within the group, the directions may be parallel to each other and different between the groups. Adjacent holes may or may not be in communication with each other. Cross communication means that the holes that contact P intersect each other and are connected to each other at the intersection.
  • the hole to be formed does not have to be linear, and all or part of the hole may be curved or bent.
  • all the holes 21 are formed so as to be orthogonal to the surface (substrate surface) of the substrate 20, FIG. As shown in the adjacent The holes 21 are formed in random directions so that the holes 21 are in cross communication with each other. As shown in FIG. 6, the adjacent holes 21 are obliquely crossed with respect to the substrate surface so that they are regularly cross connected. What was formed can be illustrated. As a specific example of a substrate having a plurality of recessed holes, as shown in FIG. 8, adjacent holes 21 are formed in a random direction so as to cross each other, as shown in FIG. An example is one in which all the holes 21 are formed so as to be orthogonal to the surface (substrate surface) of the substrate 20.
  • a step of immersing the substrate in a dispersion medium in which a plurality of inserted bodies are dispersed is performed (S12).
  • fine particles nano fine particles having conductive or semiconductive properties are used, and the fine particles may be fibrous substances such as CNTs depending on the use of the substrate structure to be manufactured.
  • Metal fine particles such as gold are used.
  • the CNTs may be single-walled CNTs (SWCNTs), double-walled CNTs (DWCNTs), triple-walled CNTs (3WCNTs), multi-walled CNTs (MWCNTs), or a mixture of these. Any of the semiconductor CNTs that have properties.
  • the size of the CNTs is, for example, a diameter of about 1 nm to several tens of nm and a length of about 1 ⁇ m.
  • the insert may be a cell, for example.
  • polymeric resins can be used as inserts.
  • the upper limit of the size of the insert is set in a range that is smaller than the hole in relation to the size of the hole formed in the substrate, and the lower limit of the size of the insert is too small. Since the brown motion of the insert is prioritized and dielectrophoresis may not be possible, the size exceeds that.
  • the insert material may be PbSe, PbTe, HgSe, HgTe, ZnS, ZnSe, CdS, CdSe, CdTe, CdS Se, GaAsP, InAsP, and GaInP.
  • Examples include nO, CaMnO, and La Ca MnO.
  • the solution ⁇ bodies are dispersed, pure water (deionized water) or pure water to surfactant (e.g., t W een20 (TM)) be used that was contained predetermined volume% it can.
  • the content of the tween 20 in a solution containing tween 20 in deionized water is, for example, 2
  • An example of the product% can be exemplified.
  • a surfactant to be contained in deionized water a nonionic surfactant, an ionic surfactant or the like may be used.
  • a method of immersing the substrate in a dispersion medium in which a plurality of inserts are dispersed in a solution a method of dropping droplets of the dispersion medium on the substrate is used.
  • the substrate is immersed in the dispersion medium 10 with a pair of electrodes (upper electrode 30, lower electrode 40) provided in the dielectrophoresis apparatus having the configuration shown in FIG.
  • a step of installing so as to sandwich the substrate 20 is performed (S13).
  • the electrodes 30 and 40 conductive glass formed by depositing metal oxide films (for example, IT O: Indium Tin Oxide) 32 and 42 on the surfaces of the glass substrates 31 and 41 by physical vapor deposition or chemical vapor deposition is used. be able to
  • An insulating film 43 having an opening 44 at a predetermined position is patterned on the metal oxide film 42 of the lower electrode 40, and the lower surface of the substrate 20 is connected to the lower electrode 40 via the insulating film 43. To be faced.
  • the position of the opening 44 of the insulating film 43 is set corresponding to the region where the hole into which the insert of the substrate 20 is to be inserted exists when the insert is inserted into the hole of the substrate 20 by dielectrophoresis described later. ing.
  • step of installing the force electrodes 30, 40 described as performing the step of installing the electrodes 30, 40 (S13) after the step of immersing the substrate in the dispersion medium (S12) (S13) After performing step 13), a step of immersing the substrate in the dispersion medium (S12) may be performed.
  • the AC power supply 50 of FIG. 12 is operated to apply an AC voltage between the electrodes 30 and 40 (S14).
  • a force in this case, a positive dielectrophoretic force
  • a force is applied to the inserted body in the dispersion medium 10 based on the principle of dielectrophoresis. Is inserted into the hole in the board 20.
  • the frequency of the AC voltage applied between the electrodes 30 and 40 is, for example, in the range of 1 kHz to 100 MHz, depending on the dielectric constant of the dispersion medium and the dielectric constant of the insert. It is set appropriately so that a positive dielectrophoretic force acts. It should be noted that the insert inserted into the hole 21 of the substrate 20 can be extracted outside the hole 21 by setting the frequency high so that a negative dielectrophoretic force acts. In addition, the maximum value of the applied frequency is not much If the frequency is too high, the dispersion medium may boil, so the frequency is set sufficiently lower than the boiling frequency.
  • the AC voltage applied between the electrodes 30 and 40 is set, for example, within a range of 1 to:! OOVpp.
  • the higher the applied voltage the greater the dielectrophoretic force acting on the insert, and the speed required to insert the insert into the hole in the substrate can be increased.
  • the electric field strength is too high, bubbles may be generated due to electrolysis, so it is necessary to set the voltage to a level that does not generate the bubbles.
  • the inserted body is a cell, if a high voltage is applied, the cell may be killed. Therefore, although the insertion requires a long time, a low voltage (for example, several micro to It is desirable to carry out at several millimeters Vpp).
  • a is the particle radius [m]
  • ⁇ is the dielectric constant [F / m]
  • the subscripts p and m are the particle and dispersion medium, respectively.
  • E is the electric field (V / m)
  • Re [f (x)] is an operator that extracts only the real part of the complex number f (x). ⁇
  • the content of Re [] in Equation (1) is called Clausius-Mossotti factor (CM factor: ⁇ ( ⁇ )) and represents the degree of polarization.
  • this CM factor depends on the conductivity and dielectric constant of the dispersion medium and particles, and the frequency to be applied, and takes values from -0.5 to 1.0.
  • the direction of dielectrophoretic force depends on the CM factor. That is, when the real part of the CM factor is positive, the dielectrophoretic force is positive, positive dielectrophoresis that induces particles to act on the larger electric field strength, and in the negative case The electrophoretic force becomes negative, and the negative dielectrophoretic force that induces particles acts on the weaker electric field strength.
  • FIG. 13 shows the result of the electric field intensity distribution by the finite element simulation performed by the inventors of the present invention.
  • 20 is a substrate
  • 21 is a hole in the substrate
  • 10 and 10 are dispersion media.
  • the electrodes 30 and 40 are located outside (upper and lower) of the dispersion media 10 and 10, respectively.
  • Fig. 13 shows a simulation result assuming that a DC voltage (10V) is applied between the electrodes. Even when an AC voltage is applied, it is considered that a similar electric field strength distribution is exhibited.
  • the figure shows that the electric field strength is weaker than the inside of the hole 21 in the dispersion medium outside the hole 21 (shown by the number 12) where the electric field strength is strong inside the hole 21 of the substrate 20 (shown by the number 11). Is shown.
  • the portion between the hole 21 where the electric field strength is strong and the adjacent hole 21 is the same as the inside of hole 21. This shows that the electric field strength is weaker than the outside of the hole 21 (indicated by reference numeral 12).
  • the electric field strength in the inside of the hole 21 of the substrate 20 is stronger than that in the dispersion medium outside the hole 21, so that it is dispersed in the dispersion medium by applying a positive dielectrophoretic force. It is understood that the inserted insert (particle) can be guided and inserted into the hole 21 of the substrate 20.
  • Figure 14 shows the relationship between the dielectrophoretic force (vertical axis) and the frequency (horizontal axis) when metallic SWCNTs are used as the particles to be dielectrophoresed and pure water containing tween20 is used as the dispersion medium. It is a figure which shows the result of lacing.
  • dispersion media pure water containing 2% by volume of tween20 and pure water containing 0.2% by volume of tween20. The former is shown by a one-dot chain line and the latter is used. It is shown with a solid line.
  • FIG. 15 shows the relationship between the dielectrophoretic force (vertical axis) and the frequency (horizontal axis) when semiconductor SWCNTs are used as the particles to be dielectrophoresed and pure water containing tween20 is used as the dispersion medium. It is a figure which shows the result of simulation. Two types of dispersion media are used: pure water containing 2 parts by volume of tween20 and pure water containing 0.2% by volume of tween20. The former is a dotted line and the latter is a solid line. Show. In addition, what is displayed in the upper right part in FIG. 15 is an enlarged view of the part having a frequency of 10 5 to 10 8 Hz.
  • a positive dielectrophoretic force is generated at a frequency of about 10 6 Hz to 10 7 ⁇ (1 ⁇ to 10 MHz) or less, and 1 MHz to : It is understood that a negative dielectrophoretic force is generated when the frequency is about 10 MHz or higher. This result is considered to have the same tendency with other semiconductor particles, which is the force of semiconductor SWCNTs.
  • the positive dielectrophoretic force is large when the frequency is about 10 4 Hz to l 0 z (10 kHz to 100 kHz) or less.
  • a frequency of about 10 kHz to 100 kHz or less it is preferable to apply a frequency of about 10 6 ⁇ (1 ⁇ ) or more. It is understood that when semiconductor particles are removed from the hole in the substrate, a frequency of about 10 6 ⁇ (1 ⁇ ) or more should be applied in order to exert a negative dielectrophoretic force.
  • a removal process for removing the electrodes 30, 40 is performed (S16), and a cleaning process is performed as a post-processing (S17).
  • the cleaning process the dispersion used for the dielectrophoresis Wash off the adhering material adhering to the substrate surface using a medium (a non-dispersed material). The cleaning step may be omitted if it is not necessary.
  • a heating and cooling process is performed (S18), and the series of processes is completed.
  • the heating and cooling process is, for example, gold as an insert
  • the metal particles are used, the metal particles inserted into the holes of the substrate are heated and melted to be integrated with each other, and the insert is fixed in the holes.
  • the heating / cooling process may be omitted if it is not necessary.
  • a drying process is performed in which the substrate after electrode removal or cleaning is naturally dried.
  • the vicinity of the opening of the hole in the substrate that is, the vicinity of the portion where the inner wall of the hole intersects the substrate surface (surface) is the same as the inside of the hole. Since the electric field strength is relatively high, the inserted body (particles) may remain in the vicinity of the opening of the hole and hinder the penetration of the inserted body into the hole. In order to cope with this problem, it is desirable to make the hole diameter of the board near the surface of the board (near the opening) larger than the inside of the board (smooth shape such as an arc shape or chamfered shape). .
  • etching may be performed using a predetermined etching solution after forming the hole in the substrate.
  • a predetermined etching solution For example, when aluminum oxide is used as the substrate, it is possible to obtain a desired shape by dissolving the vicinity of the opening of the hole by using an alkaline etching solution and washing after an appropriate period of time. .
  • an electroconductive film is manufactured using the manufacturing method of the board
  • a flexible transparent resin film such as polycarbonate or polyethylene terephthalate is used as the substrate (base material), and as shown in Fig. 4, a plurality of through-holes are formed randomly (disorderly) at an equal density.
  • the formation density is set in relation to the diameter of the through-holes so that the through-holes located next to or in the vicinity of each other are appropriately crossed and communicated with each other.
  • CNTs as a fibrous material are used here.
  • metal particles such as gold particles may be used.
  • the CNTs used here may be any of SWCNTs, DWCNTs, 3WC NTs, MWCNTs, and mixtures thereof, but it is desirable that they contain a large amount of metallic CNTs.
  • Examples of the dispersion medium include pure water, nonionic surfactant aqueous solution, and ionic surfactant aqueous solution. Either an organic solvent such as a liquid or an aqueous solution containing tween 20 may be used.
  • an organic solvent such as a liquid or an aqueous solution containing tween 20 may be used.
  • the diameter of the through hole should be set within the range of 10nm to: OOnm. On the other hand, if multiple CNTs are inserted into one through hole, the diameter of the through hole may be set to lOOnm or more.
  • the CNTs 22 are dispersed at a uniform density over the entire area of the substrate 20 without causing the CNTs 22 to agglomerate in a local area in the substrate 20. is doing.
  • the through holes 21 are connected to each other, the inserted NTs 22 are in contact with each other. Therefore, the entire substrate has conductivity.
  • the conductivity of the conductive film to be manufactured can be adjusted, and a conductive film having a desired conductivity can be obtained.
  • the diameter and the formation density of the through-holes 21 are locally changed in accordance with this, so that the conductivity having locally different conductivities is obtained. It is also possible to obtain a film.
  • the substrate 20 having the through holes 21 present in a disorderly manner as shown in FIG. 4 is used, but the substrate 20 having the through holes 21 formed with a predetermined tendency as shown in FIG. 6 is used.
  • a conductive film in which CNTs 22 are inserted into the through holes 21 can be obtained.
  • the substrate 20 having the through holes 21 substantially orthogonal to the surface (substrate surface) of the substrate 20 as shown in FIG. 2, as shown in FIG. It is possible to obtain a conductive film in which CNTs 22 are inserted, and this conductive film has conductivity in a direction perpendicular to the substrate surface and does not have conductivity in a direction along the substrate surface. It becomes an oriented conductive film.
  • the hole formed in the substrate is not limited to the through hole. As shown in FIG. 8, it is also possible to use a hole in which a depressed hole 21 having a predetermined depth is formed on the surface of the substrate 20. In this case, as shown in FIG. 9, a conductive film having conductivity only on the surface layer of the substrate can be obtained. You can.
  • a conductive film can be manufactured using the method for manufacturing a substrate structure according to the present embodiment, and the desired specifications can be obtained by appropriately changing and adjusting the specifications of the holes formed in the substrate. It is possible to easily produce a conductive film having the following performance.
  • the flexible transparent conductive film produced in this way can be used as a transparent electrode for electronic paper, a flexible display, a flat panel display, and the like. Note that, here, a transparent film having flexibility is used as the substrate, but it may or may not have flexibility. Further, in the above-described example, a conductive film having uniform conductivity can be obtained only in one or a plurality of local regions in the force film exemplifying a conductive film having conductivity uniformly throughout the substrate. it can.
  • an FED field emission display
  • an inorganic oxide substrate such as aluminum oxide is used as the substrate (base material).
  • a substrate in which through holes are formed at substantially equal intervals with respect to the substrate surface. Is used. The diameter of the through holes and the distance between the through holes may be adjusted according to the brightness and definition when used for FED.
  • CNTs as a fibrous material are used.
  • the CNTs used here may be SWCNTs, DWCNTs, 3WCNTs, MWCNTs, or a mixture of these, but in order to keep the in-plane electron emission density constant, CNTs aligned with a specific number of graph ensheets. It is desirable to use
  • any of organic solvents such as pure water, nonionic surfactant aqueous solution, ionic surfactant aqueous solution, and tween20-containing aqueous solution may be used.
  • This substrate is installed in the dielectrophoresis device of FIG. 12 according to the flowchart of FIG. 1 , and between the electrodes: L 00 kHz to i
  • the diameter of the through hole should be set within the range of 10-50 Onm. In addition, if only one CNTs is inserted into one through hole, the diameter of the through hole should be set in the range of 10nm to 100nm. This and Conversely, when inserting multiple CNTs into one through hole, the diameter of the through hole should be 100 ⁇ m or more.
  • the substrate structure (electron-emitting device) manufactured in this way is evenly spaced over the entire substrate without the CNT s22 being unevenly distributed in the local region in the substrate 20.
  • CNTsl 11 as an insert protrudes from the surface (upper surface and lower surface) of the substrate.
  • etching with an alkaline solution or the like to remove a predetermined amount of the surface of the substrate is performed.
  • an FED electron-emitting device can be manufactured by using the method for manufacturing a substrate structure according to this embodiment, and the diameters and arrangement intervals of holes formed in the substrate can be appropriately changed. Thus, an electron-emitting device having desired performance can be easily manufactured.
  • FIG. 17 is an enlarged view of a main part of the FED including the electron-emitting device manufactured by using the manufacturing method described above.
  • reference numeral 100 denotes an emitter substrate (emitter electrode).
  • a large number of CNT si 11 are inserted into the through-holes of the substrate manufactured using the manufacturing method described above.
  • the electron-emitting devices 110 are arranged in a matrix. These electron-emitting devices 110 can be fixed on the emitter substrate 100 by, for example, sticking using a conductive paste.
  • An insulating layer 120 is formed between the portions of the emitter substrate 100 where the electron-emitting devices 110 are disposed, and a gate electrode 130 is provided on the insulating layer 120.
  • Anode substrates 140 are provided at predetermined intervals through a spacer so as to face the emitter substrate 100.
  • the anode substrate 140 is a transparent electrode made of ITO or the like, and a phosphor layer (RGB phosphor) 141 is formed on the surface (inner surface) facing the electron-emitting device 110.
  • the portion between the emitter substrate 100 and the anode substrate 140 is in a vacuum state.
  • a DC voltage is applied between the emitter substrate 100 and the anode substrate 140 by the DC power supply 150, electrons are emitted from the electron-emitting device 110 and collide with the phosphor layer 141 to excite and emit light. Display is made.
  • An electron-emitting device manufactured using the method for manufacturing a substrate structure according to this embodiment CNTs are evenly distributed in the substrate without being unevenly distributed, and are aligned perpendicular to the substrate surface, so when used as an FED electron-emitting device, extremely good electron emission characteristics are achieved. FED having extremely good display performance with no variation in brightness and definition can be obtained. In addition, since the number of graph sheets of CNTs has been made uniform, this also makes it possible to make the brightness and life almost constant.
  • SiP system in package
  • SiP is a device (laminated chip) in which a plurality of LSIs (chips) including memory, CPU, and other circuits are stacked three-dimensionally and mounted in a single package.
  • LSIs LSIs
  • wire bonding is used for the connection between the layers, it is difficult to increase the speed and the number of wires is limited.
  • each layer (each chip, for example, the first chip and the second chip) of the multilayer chip can be three-dimensionally connected.
  • holes are formed in advance in portions to be via holes or through holes for interlayer connection.
  • metal CNTs or gold fine particles as the insert, and inserting the insert into the hole using the dielectrophoresis apparatus of FIG. 12, via holes or through holes for interlayer connection can be easily created. Is possible.
  • the signal wiring length can be shortened, the wiring resistance can be reduced, the number of wirings can be increased, and high performance and low power consumption can be achieved. It is also possible to mount the circuit components in such a way that each insert is connected to each other by inserting the insert into a circuit hole using semiconductor CNTs or other semiconductors and inserting it into the hole in the substrate.
  • CNTs are grown by being oriented perpendicular to the electrode substrate, and the CNTs bumps and the flip chip are joined.
  • the manufacturing conditions of the CNTs are limited by the properties of the electrode substrate. There is a possibility that the shape of CNTs that can be produced is limited, and the electrode substrate is exposed to high-temperature carbon deposition conditions, so that the material of the electrode substrate may deteriorate.
  • metal CNTs are inserted into the through holes of the substrate having the through holes as shown in FIG. 2, and the substrate as shown in FIG.
  • the cells are dispersed in a dispersion medium as an insert, and the insert is inserted into the hole using, for example, the dielectrophoresis apparatus shown in FIG. 12 on a substrate having a depression hole as shown in FIG.
  • a cell specimen as shown in FIG. 11 can also be created.
  • the applied voltage be as small as possible so as not to adversely affect the cells.
  • Example 1 Example 1
  • FIG. 18 and FIG. 19 are diagrams (SEM photographs) showing the results of experiments performed by the inventors of the present application, and FIG. 18 is a cross-sectional view of a substrate structure manufactured using the manufacturing method of the present embodiment.
  • FIG. 19 is an enlarged sectional view of the upper right 25 / im portion of FIG. This experiment was performed using a substrate having fine holes as a substrate, a dispersion medium in which the insert was dispersed in pure water, and the dielectrophoresis apparatus shown in FIG.
  • the material of the substrate is aluminum oxide (alumina), the substrate The thickness of the substrate is 60 ⁇ , the substrate size is 25 mm in diameter, and the hole diameter is 200 nm.
  • the insert is a gold microparticle (gold colloid) with a particle size of lOOnm.
  • a dispersion medium 100 / L in which the insert was dispersed in pure water at a dispersion concentration of 1.1 ⁇ 10 12 particles / mL was used.
  • As a method of immersing the substrate in the dispersion medium a method of dropping a droplet of the dispersion medium onto the substrate was used.
  • the AC voltage applied between the electrodes is 31 Vpp, and the frequency is 70 kHz.
  • the AC voltage was applied for 5 minutes.
  • the conductivity of gold is 45.2 X 10 6 S / m, and the dielectric constant of pure water is 81 ⁇ .
  • FIGS. 20 to 22 are diagrams (SEM photographs) showing the results of experiments conducted by the inventors of the present application, and FIG. 20 shows the substrate (inserted body inserted) used in the manufacturing method of the present embodiment.
  • FIG. 21 is an oblique image of the cross section of the substrate structure inserted with the insert using the manufacturing method according to the embodiment of the present invention, and FIG. It is the figure which expanded a part of. This experiment was carried out using a dielectrophoresis apparatus shown in FIG. 12, using a substrate having fine holes as a substrate, using a dispersion medium in which a filler was dispersed in pure water.
  • the substrate material is polycarbonate, the substrate thickness is 60 x m, the substrate size is 25mm in diameter, and the hole diameter is lOOnm.
  • the inclusions are MWCNTs.
  • a dispersion medium (20 ⁇ L) in which the filler was dispersed in pure water at a dispersion concentration of 5 mg / mL was used.
  • As a method of immersing the substrate in the dispersion medium a method of dropping a droplet of the dispersion medium onto the substrate was used.
  • the AC voltage applied between the electrodes is 20 Vpp, and the frequency is 55 kHz. The AC voltage was applied for 5 minutes.
  • MWCNTs are inserted from the surface of the substrate to the inside, and conductivity can be expressed throughout the substrate.
  • the MWCNTs were fixed in the substrate holes by natural drying.

Abstract

Provided is a substrate structure manufacturing method comprising a first step (S11) of preparing a substrate having at least one fine hole, a second step (S12, S13) of mounting electrodes and immersing the substrate into a dispersing medium containing a plurality of inserts, and a third step (S14) of applying a predetermined voltage to the electrodes.

Description

明 細 書  Specification
基板構造体の製造方法、基板構造体、電子放出素子、電子放出素子の 製造方法、電子源、画像表示装置、及び積層チップ  Substrate structure manufacturing method, substrate structure, electron-emitting device, electron-emitting device manufacturing method, electron source, image display device, and multilayer chip
技術分野  Technical field
[0001] 本発明は、基板構造体及びその製造方法、電子放出素子及びその製造方法、電 子源、画像表示装置、及び積層チップに関する。  The present invention relates to a substrate structure and a manufacturing method thereof, an electron-emitting device and a manufacturing method thereof, an electron source, an image display device, and a multilayer chip.
背景技術  Background art
[0002] ナノテクロジ一の中核としてカーボンナノチューブ（以下、 1本を指す場合には CNT 、複数本及び集合体を指す場合には CNTsともいう）が脚光を浴びている。 CNTsは 、一般に、直径 0. 5〜： !OOnm程度、長さが 1〜： 100 μ m程度の細長い繊維状（柱状 )の炭素材料である。 CNTsは、例えば、フィールド'ェミッション 'ディスプレイ（FED : Field Emission Display)等の画像表示装置の電界放出型電子源への応用が研 究されている。 CNTsを用いた電界放出型電子源の製造方法としては、各種の提案 がなされてレ、るが、電極に直接 CNTsを成長させる方法や別途製造された電極上に 付着させる方法等が知られている。  [0002] Carbon nanotubes (hereinafter referred to as CNT when referring to one, and also referred to as CNTs when referring to an aggregate) are attracting attention as the core of nanotechnology. CNTs are generally elongated fibrous (columnar) carbon materials having a diameter of about 0.5 to about OOnm and a length of about 1 to about 100 μm. Application of CNTs to field emission electron sources in image display devices such as field emission displays (FEDs) has been studied. Although various proposals have been made as methods for manufacturing a field emission electron source using CNTs, methods for growing CNTs directly on an electrode and methods for depositing on a separately manufactured electrode are known. Yes.
[0003] 電極に直接 CNTsを成長させる方法としては、例えば、 日本国特表 2002— 53080 5号公報、 日本国特開 2001— 15077号公報に示されているように、電極基板表面 の所定の位置に触媒を付着させて化学蒸着法（CVD : chemical vapor depositi on)を用いて、電極に垂直配向した CNTsを成長させる方法がある。また、別途調製 した CNTsを電極に付着させる方法としては、例えば、 日本国特開平 11 260249 号公報に記載されているように、 CNTsを導電性ペーストと混ぜ、スクリーン印刷で電 極にパターン形成する方法、あるいは、例えば、 日本国特開 2000— 340098号公 報に記載されているように、 CNTsを溶剤やバインダーと混ぜ、スピンコート法等を用 いて電極上に CNTs層を形成する方法等が知られている。  [0003] As a method for directly growing CNTs on an electrode, for example, as shown in Japanese Patent Special Publication No. 2002-530805 and Japanese Unexamined Patent Publication No. 2001-15077, a predetermined surface There is a method of growing CNTs vertically aligned on an electrode using a chemical vapor deposition (CVD) method by attaching a catalyst to the position. In addition, as a method of attaching separately prepared CNTs to an electrode, for example, as described in Japanese Patent Application Laid-Open No. 11 260249, CNTs are mixed with a conductive paste, and a pattern is formed on an electrode by screen printing. For example, as described in Japanese Unexamined Patent Publication No. 2000-340098, there is a method in which CNTs are mixed with a solvent or a binder, and a CNTs layer is formed on an electrode using a spin coating method or the like. Are known.
[0004] し力しながら、電極に直接 CNTsを成長させる方法では、配向は統一できるものの、 CNTsの製造条件が、電極基板の性質で制限されるため、製造できる CNTs形状が 制限される可能性があるとともに、電極基板は、高温の炭素析出条件下に曝されるた め、電極基板の材質が劣化する場合があるという問題がある。また、別途製造した C NTsを電極に付着させる方法では、 CNTsのようなナノスケールの物質は、導電性べ 一スト等の流動性物質に均一に混合させるのは難しぐ不均一に混ざったままの状 態で電極に付着させると、電極上の各電子源に含まれる CNTsの密度が一定でない 等により、画像表示装置としてはむらのある画像になってしまうという問題がある。 [0004] However, in the method of growing CNTs directly on the electrode, the orientation can be unified, but the manufacturing conditions of CNTs are limited by the properties of the electrode substrate, so the shape of CNTs that can be manufactured may be limited. And the electrode substrate is exposed to high temperature carbon deposition conditions. Therefore, there is a problem that the material of the electrode substrate may deteriorate. In addition, in the method of attaching separately manufactured CNTs to the electrode, nanoscale materials such as CNTs remain difficult to mix uniformly with a fluid material such as a conductive best and remain non-uniformly mixed. If attached to the electrode in this state, the density of CNTs contained in each electron source on the electrode is not constant, resulting in an uneven image display device.
[0005] また、 CNTsは、例えば電子ペーパー、フレキシブル表示板、フラットパネルデイス プレイ等の画像表示装置の透明電極等に用いることもできる導電性フィルムへの応 用も研究されている。このような導電性フィルムとしては、例えば、 日本国特開 2004 — 346143号公報に記載されているように、熱可塑性ポリイミド樹脂等の樹脂に CNT sを混入させて、熱可塑性ポリイミド樹脂組成物ペレットを製造し、これを押出成形法 等により、肉厚が 500 x m程度以下（例えば、 100 x m、 20 μ m等）の薄肉フィルムと したものが知られている。  [0005] In addition, the application of CNTs to conductive films that can be used for transparent electrodes of image display devices such as electronic paper, flexible display boards, and flat panel displays has also been studied. As such a conductive film, for example, as described in Japanese Unexamined Patent Application Publication No. 2004-346143, CNT s is mixed in a resin such as a thermoplastic polyimide resin, and a thermoplastic polyimide resin composition pellet is obtained. It is known that a thin film having a thickness of about 500 xm or less (for example, 100 xm, 20 μm, etc.) is manufactured by extrusion molding or the like.
[0006] し力しながら、このような樹脂に CNTsを混入した後にフィルム状に成形する方法で は、上述もしたように、 CNTsは一部に凝集してしまうことがあり、流動性物質中に均 一に混合させるのは難しい。このため、導電性がフィルム全面に渡って一様とならな レ、ことがあり、画像表示装置としてはむらのある画像になってしまうという問題がある。 発明の開示  [0006] However, in the method of forming a film after mixing CNTs into such a resin, as described above, CNTs may agglomerate in part, and in a fluid substance, It is difficult to mix evenly. For this reason, there is a problem that the conductivity is not uniform over the entire surface of the film, and the image display device has a problem of unevenness. Disclosure of the invention
[0007] よって本発明の目的は、 CNTsやその他の微粒子等を基板中の全体若しくは一部 の領域に均質に分散配置させ、又は基板中の任意の位置若しくは領域に配置させ た基板構造体、及びその基板構造体の製造方法を得ることである。  [0007] Therefore, an object of the present invention is to provide a substrate structure in which CNTs and other fine particles are uniformly dispersed and arranged in the whole or a part of the substrate, or arranged at an arbitrary position or region in the substrate, And a method of manufacturing the substrate structure.
[0008] 本発明によると、少なくとも 1つの微細な穴を有する基板を準備する第 1工程と、電 極を設置し、前記基板を複数の挿入体を含む分散媒に浸す第 2工程と、前記電極に 所定の電圧を印加する第 3工程とを備える基板構造体の製造方法が提供される。  [0008] According to the present invention, a first step of preparing a substrate having at least one fine hole, a second step of installing an electrode and immersing the substrate in a dispersion medium including a plurality of inserts, And a third step of applying a predetermined voltage to the electrode.
[0009] また、本発明によると、直径が 5nm〜： ΙΟΟ μ πιの範囲内の少なくとも 1つの穴が存 在するとともに、厚さが 1 μ m〜lmmの範囲内である基板と、導電性又は半導電性 の性質を有する、前記穴に挿入された少なくとも 1つの挿入体と、を備える基板構造 体が提供される。  [0009] Further, according to the present invention, there is provided a substrate having a diameter of 5 nm to at least one hole in a range of ΙΟΟ μ πι and a thickness in a range of 1 μm to lmm, and a conductive layer. Alternatively, there is provided a substrate structure comprising: at least one insert inserted into the hole having a semiconductive property.
[0010] さらに、本発明によると、電圧を印加することで電子を放出する基板構造体 (例えば 、電子放出素子）であって、少なくとも 1つの微細な穴を有する基板と、その基板構造 体の電極として、その微細な穴に挿入された少なくとも 1つの挿入体と、を備える基板 構造体が提供される。 Furthermore, according to the present invention, a substrate structure that emits electrons when a voltage is applied (for example, A substrate structure comprising at least one substrate having at least one minute hole and at least one insert inserted into the minute hole as an electrode of the substrate structure. Is done.
[0011] 複数の揷入体 (例えば、微粒子）を含む分散媒に基板を浸して電場を与えると、分 散媒と揷入体との分極率の相違により誘起双極子モーメントが発生し、揷入体の両 側に形成される電場強度の差が誘起双極子が及ぼす力の差となって、該揷入体に 力が作用して、この力の方向に該揷入体が移動する。一方、微細な穴を有する基板 を分散媒中に浸して所定方向から同様に電場を与えると、穴の外側部分と穴の内側 部分とで、電界強度分布に差が生じるため、分散媒中の揷入体を基板の穴の中に誘 導-挿入することが可能である。従って、基板の穴の数、方向、大きさ（直径）、深さ、 位置等の仕様を適宜に選定して、本発明の製造方法を用いて当該基板の穴に揷入 体を揷入することにより、当該基板の仕様に応じて、挿入体を適宜に備えた所望の基 板構造体を製造することができる。  [0011] When an electric field is applied by immersing a substrate in a dispersion medium containing a plurality of inclusions (for example, fine particles), an induced dipole moment is generated due to the difference in polarizability between the dispersion medium and the inclusions. The difference in electric field strength formed on both sides of the entrance becomes the difference in force exerted by the induced dipole, and the force acts on the insert and the insert moves in the direction of this force. On the other hand, if a substrate with fine holes is immersed in a dispersion medium and an electric field is applied in the same direction from a predetermined direction, the electric field strength distribution differs between the outer part of the hole and the inner part of the hole. It is possible to guide-insert the insert into the hole in the board. Accordingly, the specifications of the number, direction, size (diameter), depth, position, etc. of the hole in the substrate are appropriately selected, and the insert is inserted into the hole in the substrate using the manufacturing method of the present invention. Thus, a desired substrate structure having an insert appropriately can be manufactured according to the specifications of the substrate.
[0012] 特に限定されないが、例えば、後述する実施形態に示すように、その基板面に垂直 に複数の穴を配列的に設けた基板の当該穴に、 CNTs、その他の導電体を挿入体と して挿入することにより、基板内に該導電体が正確に垂直配向されることになり、 FE D等の電子源として好適な基板構造体 (例えば、電子放出素子）を、電極基板等を 損傷させたりすることなぐ容易に製造することができる。また、特に限定されないが、 例えば、複数の穴を互いの一部が交差連通するように設けた基板を用い、挿入体と して CNTs等の導電体を用いることにより、該挿入体が基板の全面に渡って一様に 分散配置された基板構造体 (例えば、導電性シート)を得ることができる。  [0012] Although not particularly limited, for example, as shown in an embodiment to be described later, CNTs and other conductors are inserted into the holes of the substrate in which a plurality of holes are provided in an array perpendicular to the substrate surface. In this case, the conductor is accurately vertically aligned in the substrate, and a substrate structure (for example, an electron-emitting device) suitable as an electron source such as FED is damaged. It can be easily manufactured without letting it go. In addition, although not particularly limited, for example, a substrate in which a plurality of holes are provided so that a part of each other crosses and communicates with each other, and a conductive material such as CNTs is used as the insert. A substrate structure (for example, a conductive sheet) that is uniformly distributed over the entire surface can be obtained.
[0013] 本発明によると、 CNTsやその他の微粒子等を基板中の全体若しくは一部の領域 に均質に分散配置させ、又は基板中の任意の位置若しくは領域に配置させた基板 構造体を得ることができる。 According to the present invention, it is possible to obtain a substrate structure in which CNTs, other fine particles, and the like are uniformly distributed in the whole or a part of the substrate, or are arranged in any position or region in the substrate. Can do.
図面の簡単な説明  Brief Description of Drawings
[0014] [図 1]本発明の実施形態に係る基板構造体の製造方法を示すフローチャートである。  FIG. 1 is a flowchart showing a method for manufacturing a substrate structure according to an embodiment of the present invention.
[図 2]本発明の実施形態の垂直な貫通穴を有する基板を示す断面図である。  FIG. 2 is a cross-sectional view showing a substrate having a vertical through hole according to an embodiment of the present invention.
[図 3]図 2に示す基板の穴に挿入体が挿入された状態を示す断面図である。 [図 4]本発明の実施形態のランダムな貫通穴を有する基板を示す断面図である。 3 is a cross-sectional view showing a state where an insert is inserted into the hole of the substrate shown in FIG. FIG. 4 is a cross-sectional view showing a substrate having random through holes according to an embodiment of the present invention.
[図 5]図 4に示す基板の穴に挿入体が挿入された状態を示す断面図である。 5 is a cross-sectional view showing a state in which an insert is inserted into the hole of the substrate shown in FIG.
[図 6]本発明の実施形態の一定の方向に斜交した貫通穴を有する基板を示す断面 図である。 FIG. 6 is a cross-sectional view showing a substrate having through holes obliquely crossed in a certain direction according to an embodiment of the present invention.
[図 7]図 6に示す基板の穴に揷入体が挿入された状態を示す断面図である。  FIG. 7 is a cross-sectional view showing a state where the insert is inserted into the hole of the substrate shown in FIG.
[図 8]本発明の実施形態のランダムな陥没穴を有する基板を示す断面図である。 FIG. 8 is a cross-sectional view showing a substrate having random recessed holes according to an embodiment of the present invention.
[図 9]図 8に示す基板の穴に揷入体が挿入された状態を示す断面図である。 FIG. 9 is a cross-sectional view showing a state where the insert is inserted into the hole of the substrate shown in FIG.
[図 10]本発明の実施形態の垂直な陥没穴を有する基板を示す断面図である。 FIG. 10 is a cross-sectional view showing a substrate having a vertical depression hole according to an embodiment of the present invention.
[図 11]図 10に示す基板の穴に揷入体が挿入された状態を示す断面図である。 FIG. 11 is a cross-sectional view showing a state where the insert is inserted into the hole of the substrate shown in FIG.
[図 12]本発明の実施形態に係る誘電泳動装置の概略を示す図である。 FIG. 12 is a diagram schematically showing a dielectrophoresis apparatus according to an embodiment of the present invention.
[図 13]本発明の実施形態の電界強度分布を示す図である。 FIG. 13 is a diagram showing an electric field intensity distribution according to the embodiment of the present invention.
[図 14]本発明の実施形態の金属 SWCNTsについての印加周波数と誘電泳動力と の関係を示す図である。  FIG. 14 is a diagram showing the relationship between applied frequency and dielectrophoretic force for metallic SWCNTs according to an embodiment of the present invention.
[図 15]本発明の実施形態の半導体 SWCNTsについての印加周波数と誘電泳動力 との関係を示す図である。  FIG. 15 is a diagram showing the relationship between applied frequency and dielectrophoretic force for semiconductor SWCNTs according to an embodiment of the present invention.
[図 16]金属 SWCNTs等の導電率及び誘電率を示す図である。  FIG. 16 is a graph showing conductivity and dielectric constant of metal SWCNTs and the like.
[図 17]本発明の実施形態の FEDの概略構成を示す図である。  FIG. 17 is a diagram showing a schematic configuration of an FED according to an embodiment of the present invention.
[図 18]本発明の実施形態の製造方法を用いて製造された基板構造体の断面を示す 図（SEM写真）である。  FIG. 18 is a diagram (SEM photograph) showing a cross section of a substrate structure manufactured using the manufacturing method of the embodiment of the present invention.
[図 19]図 18の一部を拡大した図である。  FIG. 19 is an enlarged view of a part of FIG.
[図 20]本発明の実施形態の製造方法に用いた基板の断面を斜め方向力 見た図（S EM写真）である。  FIG. 20 is a diagram (SEM photograph) of a cross section of a substrate used in a manufacturing method according to an embodiment of the present invention, as seen in an oblique direction force.
[図 21]本発明の実施形態の製造方法を用いて製造された基板構造体の断面を斜め 方向から見た図（SEM写真）である。  FIG. 21 is a diagram (SEM photograph) of a cross section of a substrate structure manufactured using the manufacturing method according to the embodiment of the present invention, viewed from an oblique direction.
[図 22]図 21の一部を拡大した図である。 FIG. 22 is an enlarged view of a part of FIG.
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
以下、本発明の実施形態に係る基板構造体の製造方法を、図面を参照して詳細 に説明することにする。図 1は本発明の実施形態に係る基板構造体の製造方法の概 略を示すフローチャートである。 Hereinafter, a method for manufacturing a substrate structure according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an outline of a method for manufacturing a substrate structure according to an embodiment of the present invention. It is a flowchart which shows an abbreviation.
[0016] まず、穴を有する基板 (メンプレン)を準備する工程を行う（Sl l)。この基板準備ェ 程には、薄板状又はシート若しくはフィルム状の母材（穴の存在しない板状体）に穴 を形成する工程が含まれる。但し、基板母材に穴を後から形成するのではなぐ基板 の製造と同時に穴を形成した基板を用いてもよぐこの場合には、後から穴を形成す る工程は不要である。基板の母材としては、ここでは、絶縁性のものを用レ、るものとす る力 用途に応じて、半導電性のものを用いてもよい。  First, a step of preparing a substrate (membrane) having holes is performed (Sl l). This substrate preparation process includes a step of forming a hole in a thin plate or sheet or film base material (a plate-like body having no holes). However, instead of forming holes in the substrate base material later, it is possible to use a substrate in which holes are formed at the same time as the manufacture of the substrate. In this case, the step of forming holes later is not necessary. Here, as the base material of the substrate, an insulating material may be used, and a semiconductive material may be used depending on the intended use.
[0017] なお、半導電性とは室温における電気伝導率が金属と絶縁体の中間の 106〜： 10_7 SZm程度である物質の性質をいい、絶縁性とは半導電性物質の電気伝導率よりも 小さレ、物質の性質をレ、レ、、後述する導電性とは半導電性物質の電気伝導率よりも大 きい物質の性質をレ、う。 [0017] The intermediate of 10 6 to the semi-conductive and electrical conductivity at room temperature is a metal insulator: refers to the nature of 10_ 7 SZM about a is material, the electrical conductivity of the semiconducting material and the insulating Less than the rate, the nature of the substance, and the conductivity described later refers to the nature of the substance greater than the electrical conductivity of the semiconductive substance.
[0018] 絶縁性の基板の母材としては、例えば、ポリカーボネート、テフロン (登録商標）、ポ リエチレンテレフタレート等の可撓性を有する透明樹脂フィルムを用いることができる [0018] As a base material of the insulating substrate, for example, a flexible transparent resin film such as polycarbonate, Teflon (registered trademark), polyethylene terephthalate, or the like can be used.
。基板の母材としては、このような可撓性を有する透明樹脂フィルムに限られず、可 撓性を有していなくてもよく、透明でなくてもよぐ樹脂でなくてもよい。例えば、酸化 アルミニウム、酸化マグネシウム、酸化チタン、酸化珪素等の無機酸化物を用いても よい。要するに、基板 (基板母材)の材質は、基板構造体の用途等に応じて適宜に選 定される。基板 (基板母材）の厚さとしては、製造される基板構造体の用途や後述す る挿入体の大きさに応じて選定され、特に限定されないが、 l i m〜lmm程度のも のを用いることができる。なお、本願明細書中において、可撓性とは、基板に折り曲 げるような所定の力を加えても機能が損なわれないことをいい、可撓性は該基板の耐 屈曲性で評価することができる。例えば、ポリカーボネイト、テフロン (登録商標）ゃポ リエチレンテレフタレートなど以上の高レ、耐屈曲性があることが望ましレ、。 . The base material of the substrate is not limited to such a transparent resin film having flexibility, and may not be flexible and may not be a resin that is not transparent. For example, an inorganic oxide such as aluminum oxide, magnesium oxide, titanium oxide, or silicon oxide may be used. In short, the material of the substrate (substrate base material) is appropriately selected according to the use of the substrate structure. The thickness of the substrate (substrate base material) is selected according to the use of the substrate structure to be manufactured and the size of the insert described later, and is not particularly limited. Can do. In the present specification, the term “flexibility” means that the function is not impaired even when a predetermined force that can be bent is applied to the substrate. Flexibility is evaluated by the bending resistance of the substrate. can do. For example, polycarbonate, Teflon (registered trademark) or poly (ethylene terephthalate) are preferred to have high resistance and bending resistance.
[0019] 穴形成工程で用いる基板母材に対する複数の穴の形成方法としては、形成する穴 の直径や方向に応じて各種の方法を採用することができるが、比較的に小径（直径 5 Onm程度以下）の穴を形成する場合には、例えば、イオン照射や高速中性子照射に よりエッチングする方法を用いることができる。基板母材として酸化アルミニウムを用 レ、る場合には、陽極酸化法によって穴を形成してもよい。また、比較的に大径（直径 50nm程度以上）の場合には、穴となるべき部分以外をマスクして所定のエッチング 液に浸す方法を用いてもよい。なお、複数の穴をランダム（形成方向が不特定）に形 成する場合には、基板を回転なレ、し振動させながらイオン照射エッチング等を行えば よい。 [0019] As a method of forming a plurality of holes in the substrate base material used in the hole forming step, various methods can be adopted depending on the diameter and direction of the hole to be formed, but a relatively small diameter (diameter 5 Onm For example, a method of etching by ion irradiation or fast neutron irradiation can be used. When aluminum oxide is used as the substrate base material, the holes may be formed by an anodic oxidation method. Also, relatively large diameter (diameter In the case of about 50 nm or more), a method of immersing in a predetermined etching solution by masking the portion other than the portion to be the hole may be used. In the case where a plurality of holes are formed randomly (the formation direction is unspecified), ion irradiation etching or the like may be performed while rotating and vibrating the substrate.
[0020] 穴の直径は、製造すべき基板構造体の用途、後述する挿入体の大きさや材質、揷 入体が分散される分散媒等に応じて選定され、例えば、直径 5nm〜： lOO z m程度の ものとすることができる。なお、形成する穴の断面形状は、ここでは円形とするが、楕 円やその他の形状であってもよい。形成する穴の数は、製造すべき基板構造体の用 途に応じて、任意に設定され、 1個以上であればよい。ここでは、穴の数は、複数（多 数)であるものとする。穴を複数形成する場合の密度（間隔等）は、製造すべき基板 構造体の用途及び基板母材の強度等をも勘案して適宜に選定される。  [0020] The diameter of the hole is selected according to the use of the substrate structure to be manufactured, the size and material of the insert to be described later, the dispersion medium in which the insert is dispersed, and the diameter is, for example, 5 nm to: lOO zm Can be of the order. The cross-sectional shape of the hole to be formed is circular here, but may be an ellipse or other shapes. The number of holes to be formed is arbitrarily set according to the use of the substrate structure to be manufactured, and may be one or more. Here, the number of holes is assumed to be plural (many). The density (interval, etc.) in the case of forming a plurality of holes is appropriately selected in consideration of the use of the substrate structure to be manufactured and the strength of the substrate base material.
[0021] 形成する穴は、基板を貫通する貫通穴であってもよいし、基板を貫通しない陥没穴 であってもよぐ穴の種類や深さは、製造すべき基板構造体の用途に応じて適宜に 選定される。形成する穴の方向は、製造すべき基板構造体の用途等に応じて選定さ れ、基板の表面（基板面）に対して実質的に垂直であってもよぐ該基板面に対して 斜交していてもよい。複数の穴を形成する場合の各穴の相互の関係としては、全て の穴について同じ方向（即ち、互いに平行）であってもよぐ互いに異なる方向であつ てもよレ、。なお、基板母材にその一方の面側から陥没穴を形成し、他方の面側から バックエッチング等を行うことにより、貫通穴を形成するようにしてもよい。  [0021] The hole to be formed may be a through hole penetrating the substrate or a recessed hole that does not penetrate the substrate. The type and depth of the hole depends on the use of the substrate structure to be manufactured. It will be selected as appropriate. The direction of the hole to be formed is selected according to the use of the substrate structure to be manufactured, etc., and may be substantially perpendicular to the substrate surface (substrate surface). You may be in contact. When forming a plurality of holes, each hole may be in the same direction (ie, parallel to each other) or in different directions. The through hole may be formed by forming a recessed hole from one surface side of the substrate base material and performing back etching or the like from the other surface side.
[0022] 複数の穴を互いに異なる方向に形成する場合に、全ての穴を不特定の方向にラン ダム（無秩序）に形成してもよいし、あるいは複数の穴を複数のグノレープに分けて、グ ループ内では互いに平行で各グループ間で異なる方向にしてもよい。隣接する穴同 士は、互いに交差連通していてもよぐ互いに交差連通していなくてもよい。なお、交 差連通とは、 P 接する穴同士が互いに交差しており、当該交差部分において互いに 繋がっていることを意味する。形成する穴は、直線形状でなくてもよぐその全部又は 一部が湾曲ないし折れ曲がつていてもよい。  [0022] When a plurality of holes are formed in different directions, all the holes may be randomly formed in an unspecified direction, or the plurality of holes may be divided into a plurality of gnoles, Within the group, the directions may be parallel to each other and different between the groups. Adjacent holes may or may not be in communication with each other. Cross communication means that the holes that contact P intersect each other and are connected to each other at the intersection. The hole to be formed does not have to be linear, and all or part of the hole may be curved or bent.
[0023] 複数の貫通穴を有する基板の具体例としては、図 2に示すように、全ての穴 21を基 板 20の表面（基板面）に対して直交するように形成したもの、図 4に示すように、隣接 する穴 21同士が互いに交差連通するように互いにランダムな方向に形成したもの、 図 6に示すように、隣接する穴 21同士が規則的に交差連通するように基板面に対し て斜交して形成したもの等を例示することができる。また、複数の陥没穴を有する基 板の具体例としては、図 8に示すように、隣接する穴 21同士が互いに交差連通する ようにランダムな方向に形成したもの、図 10に示すように、全ての穴 21を基板 20の 表面（基板面）に対して直交するように形成したもの等を例示することができる。 As a specific example of a substrate having a plurality of through holes, as shown in FIG. 2, all the holes 21 are formed so as to be orthogonal to the surface (substrate surface) of the substrate 20, FIG. As shown in the adjacent The holes 21 are formed in random directions so that the holes 21 are in cross communication with each other. As shown in FIG. 6, the adjacent holes 21 are obliquely crossed with respect to the substrate surface so that they are regularly cross connected. What was formed can be illustrated. As a specific example of a substrate having a plurality of recessed holes, as shown in FIG. 8, adjacent holes 21 are formed in a random direction so as to cross each other, as shown in FIG. An example is one in which all the holes 21 are formed so as to be orthogonal to the surface (substrate surface) of the substrate 20.
[0024] 穴を有する基板を準備する工程が終了したならば、複数の揷入体が分散された分 散媒に当該基板を浸す工程を行う（S12)。挿入体としては、導電性又は半導電性の 性質を有する微粒子 (ナノ微粒子）が用いられ、当該微粒子としては、製造すべき基 板構造体の用途等に応じて、 CNTsのような繊維状物質や金等の金属微粒子等が 採用される。 CNTsとしては、単層 CNTs (SWCNTs)、二層 CNTs (DWCNTs)、三 層 CNTs (3WCNTs)、多層 CNTs (MWCNTs)又はこれらの混在したものの何れ でもよく、金属的性質を有する金属 CNTs、半導体的性質を有する半導体 CNTsの 何れでもよレ、。 CNTsの大きさは、例えば、直径が lnm〜数十 nm程度、長さが 1 μ m程度である。なお、挿入体は、例えば、細胞のようなものであってもよい。また、挿 入体として高分子の樹脂も対象とすることができる。  [0024] When the step of preparing the substrate having holes is completed, a step of immersing the substrate in a dispersion medium in which a plurality of inserted bodies are dispersed is performed (S12). As the insert, fine particles (nano fine particles) having conductive or semiconductive properties are used, and the fine particles may be fibrous substances such as CNTs depending on the use of the substrate structure to be manufactured. Metal fine particles such as gold are used. The CNTs may be single-walled CNTs (SWCNTs), double-walled CNTs (DWCNTs), triple-walled CNTs (3WCNTs), multi-walled CNTs (MWCNTs), or a mixture of these. Any of the semiconductor CNTs that have properties. The size of the CNTs is, for example, a diameter of about 1 nm to several tens of nm and a length of about 1 μm. The insert may be a cell, for example. In addition, polymeric resins can be used as inserts.
[0025] 挿入体の大きさの上限は、基板に形成する穴の大きさとの関係で該穴よりも小さレ、 範囲で設定され、挿入体の大きさの下限は、あまりに小さい場合には該挿入体のブ ラウン運動が優先されてしまい、誘電泳動できないことがあるので、それを超える大き さである。  [0025] The upper limit of the size of the insert is set in a range that is smaller than the hole in relation to the size of the hole formed in the substrate, and the lower limit of the size of the insert is too small. Since the brown motion of the insert is prioritized and dielectrophoresis may not be possible, the size exceeds that.
[0026] 挿入体の材質としては、上述したもの以外に、 PbSe, PbTe, HgSe, HgTe, ZnS , ZnSe, CdS, CdSe, CdTe, CdS Se , GaAs P， InAs P， Ga In P  [0026] In addition to the materials described above, the insert material may be PbSe, PbTe, HgSe, HgTe, ZnS, ZnSe, CdS, CdSe, CdTe, CdS Se, GaAsP, InAsP, and GaInP.
l -X X 1 -X X 1 -X X 1 -X X l -X X 1 -X X 1 -X X 1 -X X
, Ga In As, Ga In , As P， GaN, GaP, GaAs, InP, InAs, Si, Ge， Si , Ga In As, Ga In, As P, GaN, GaP, GaAs, InP, InAs, Si, Ge, Si
1 -X X 1 -X X 1 -X X 1 1 -X X 1 -X X 1 -X X 1
Ge， BaTiO， PbZrO , Pb Zr Ti 〇， Ba Sr TiO , SrTiO， ZnO， LaMGe, BaTiO, PbZrO, Pb Zr Ti ○, Ba Sr TiO, SrTiO, ZnO, LaM
-X X 3 3 X y 1 y 3 X 1 -X 3 3 -X X 3 3 X y 1 y 3 X 1 -X 3 3
n〇， CaMnO， La Ca MnO等を例示することができる。  Examples include nO, CaMnO, and La Ca MnO.
3 3 1 -X X 3  3 3 1 -X X 3
[0027] 揷入体が分散される溶液としては、純水（脱イオン水）あるいは純水に界面活性剤 ( 例えば、 tWeen20 (商標））を所定体積％含有させたものを用いることができる。脱ィ オン水に tween20を含有させた溶液の該 tween20の含有量としては、例えば、 2体 積％程度を例示することができる。脱イオン水に含有させる界面活性剤としては、非 イオン性界面活性剤、イオン性界面活性剤等を用いてもよい。複数の挿入体を溶液 中に分散させてなる分散媒に対して基板を浸す方法としては、基板に分散媒の液滴 を滴下する方法を用いる。但し、所定の容器内に収容された分散媒中に基板を挿入 して浸す方法等を用いてもょレ、。 [0027] The solution揷入bodies are dispersed, pure water (deionized water) or pure water to surfactant (e.g., t W een20 (TM)) be used that was contained predetermined volume% it can. The content of the tween 20 in a solution containing tween 20 in deionized water is, for example, 2 An example of the product% can be exemplified. As a surfactant to be contained in deionized water, a nonionic surfactant, an ionic surfactant or the like may be used. As a method of immersing the substrate in a dispersion medium in which a plurality of inserts are dispersed in a solution, a method of dropping droplets of the dispersion medium on the substrate is used. However, it is possible to use a method in which the substrate is immersed in a dispersion medium contained in a predetermined container.
[0028] 基板を分散媒に浸す工程が終了したならば、図 12に示すような構成を有する誘電 泳動装置が備える一対の電極（上部電極 30，下部電極 40)で、分散媒 10に浸した 基板 20を挟み込むように設置する工程を行う（S 13)。電極 30, 40としては、ガラス 基板 31 , 41の表面に物理蒸着法や化学蒸着法等によって金属酸化膜 (例えば、 IT O : Indium Tin Oxide) 32, 42を蒸着してなる導電性ガラスを用いることができる [0028] When the step of immersing the substrate in the dispersion medium is completed, the substrate is immersed in the dispersion medium 10 with a pair of electrodes (upper electrode 30, lower electrode 40) provided in the dielectrophoresis apparatus having the configuration shown in FIG. A step of installing so as to sandwich the substrate 20 is performed (S13). As the electrodes 30 and 40, conductive glass formed by depositing metal oxide films (for example, IT O: Indium Tin Oxide) 32 and 42 on the surfaces of the glass substrates 31 and 41 by physical vapor deposition or chemical vapor deposition is used. be able to
[0029] 下部電極 40の金属酸化膜 42上には、所定の位置に開口部 44を有する絶縁膜 43 がパターユングされており、基板 20の下面は下部電極 40に、この絶縁膜 43を介して 対面されるようになっている。絶縁膜 43の開口部 44の位置は、後述する誘電泳動に より基板 20の穴に挿入体を挿入する際に、基板 20の挿入体を挿入すべき穴が存在 する領域に対応して設定されている。なお、ここでは、分散媒に基板を浸す工程（S1 2)を行った後に、電極 30, 40を設置する工程（S13)を行うものとして説明した力 電 極 30, 40を設置する工程（S 13)を行った後に、分散媒に基板を浸す工程（S 12)を 行うようにしてもよい。 An insulating film 43 having an opening 44 at a predetermined position is patterned on the metal oxide film 42 of the lower electrode 40, and the lower surface of the substrate 20 is connected to the lower electrode 40 via the insulating film 43. To be faced. The position of the opening 44 of the insulating film 43 is set corresponding to the region where the hole into which the insert of the substrate 20 is to be inserted exists when the insert is inserted into the hole of the substrate 20 by dielectrophoresis described later. ing. Here, the step of installing the force electrodes 30, 40 described as performing the step of installing the electrodes 30, 40 (S13) after the step of immersing the substrate in the dispersion medium (S12) (S13) After performing step 13), a step of immersing the substrate in the dispersion medium (S12) may be performed.
[0030] 次に、図 12の交流電源 50を作動させて、両電極 30, 40間に交流電圧を印加する 工程を行う（S14)。両電極 30, 40間に交流電圧を印加することにより、分散媒 10中 の揷入体に誘電泳動の原理に基づいて力（ここでは正の誘電泳動力）を作用させて 、該揷入体を基板 20の穴中に誘導 '挿入する。  Next, the AC power supply 50 of FIG. 12 is operated to apply an AC voltage between the electrodes 30 and 40 (S14). By applying an AC voltage between the electrodes 30, 40, a force (in this case, a positive dielectrophoretic force) is applied to the inserted body in the dispersion medium 10 based on the principle of dielectrophoresis. Is inserted into the hole in the board 20.
[0031] 両電極 30, 40間に印加する交流電圧の周波数は、例えば lkHz〜100MHzの範 囲内で、分散媒の誘電率及び揷入体の誘電率に応じて、分散媒中の挿入体に正の 誘電泳動力が作用するように適宜に設定される。なお、負の誘電泳動力が作用する ように周波数を高く設定することにより、基板 20の穴 21内に挿入された揷入体を、該 穴 21の外部に抜き去ることも可能である。また、印加する周波数の最大値は、あまり に高い周波数であると、分散媒が沸騰してしまうことがあるため、該沸騰する周波数よ りも十分に低い周波数に設定される。 [0031] The frequency of the AC voltage applied between the electrodes 30 and 40 is, for example, in the range of 1 kHz to 100 MHz, depending on the dielectric constant of the dispersion medium and the dielectric constant of the insert. It is set appropriately so that a positive dielectrophoretic force acts. It should be noted that the insert inserted into the hole 21 of the substrate 20 can be extracted outside the hole 21 by setting the frequency high so that a negative dielectrophoretic force acts. In addition, the maximum value of the applied frequency is not much If the frequency is too high, the dispersion medium may boil, so the frequency is set sufficiently lower than the boiling frequency.
[0032] 両電極 30, 40間に印加する交流電圧は、例えば 1〜： !OOVppの範囲内で設定さ れる。印加する電圧は高い方が、揷入体に作用する誘電泳動力が大きくなり、基板 の穴に対する揷入体の挿入に要する速度を早くすることが可能である。但し、電界強 度が高すぎると、電気分解により気泡が発生することがあるので、該気泡が発生しな い程度の電圧以下に設定する必要がある。また、揷入体が細胞である場合には、高 い電圧を印加すると、細胞が死滅することがあるので、揷入に長時間を要することに はなるが、低電圧（例えば、数マイクロ〜数ミリ Vpp程度）で行うことが望ましい。  [0032] The AC voltage applied between the electrodes 30 and 40 is set, for example, within a range of 1 to:! OOVpp. The higher the applied voltage, the greater the dielectrophoretic force acting on the insert, and the speed required to insert the insert into the hole in the substrate can be increased. However, if the electric field strength is too high, bubbles may be generated due to electrolysis, so it is necessary to set the voltage to a level that does not generate the bubbles. In addition, when the inserted body is a cell, if a high voltage is applied, the cell may be killed. Therefore, although the insertion requires a long time, a low voltage (for example, several micro to It is desirable to carry out at several millimeters Vpp).
[0033] ここで、誘電泳動の原理にっレ、て、簡単に説明する。粒子を溶液に分散してなる分 散媒に電場を与えると、分散媒と粒子との分極率の相違により誘起双極子モーメント が発生し、粒子の両側に形成される電場強度の差が誘起双極子が及ぼす力の差と なって、該粒子に力が作用して、この力の方向に該粒子が移動する。このときに働く 誘電泳動力 F は次式で表されることが知られている。  Here, the principle of dielectrophoresis will be briefly described. When an electric field is applied to the dispersion medium in which particles are dispersed in a solution, an induced dipole moment is generated due to the difference in polarizability between the dispersion medium and the particles, and the difference in electric field strength formed on both sides of the particles is induced dipoles. The force acts on the particle as a difference in force exerted by the child, and the particle moves in the direction of the force. It is known that the dielectrophoretic force F acting at this time is expressed by the following equation.
DEP  DEP
[0034] F =2π ε a e [(丄ー丄 ） /(丄 +2丄 ）] VE2 …ひ） [0034] F = 2π ε ae [(丄 ー 丄) / (丄 +2 丄)] VE 2 … hi)
DEP m ^ m  DEP m ^ m
式（1)中の、 aは粒子の半径 [m]、 εは誘電率 [F/m]、添え字 p及び mはそれぞ れ粒子、分散媒を示してレ、る。 Eは電界 (V/m)、 Re [f (x) ]は複素数 f (x)の実数部 分だけを取り出す演算子である。丄は、  In equation (1), a is the particle radius [m], ε is the dielectric constant [F / m], and the subscripts p and m are the particle and dispersion medium, respectively. E is the electric field (V / m), and Re [f (x)] is an operator that extracts only the real part of the complex number f (x).丄
丄= ε - ( σ /ω )} …（2)  丄 = ε-(σ / ω)} (2)
で定義される複素誘電率である。 σは導電率 [S/m]、 ω ( = 2πί)は角周波数 [Hz ]、 fは印加周波数 [Hz]を表している。 jは虚数単位である。式（1)中の Re[ ]の中身 は、 Clausius— Mossotti因子（CM因子： Κ(ω))と呼ばれ、分極の程度を表してい る。  Is a complex dielectric constant defined by σ represents conductivity [S / m], ω (= 2πί) represents angular frequency [Hz], and f represents applied frequency [Hz]. j is an imaginary unit. The content of Re [] in Equation (1) is called Clausius-Mossotti factor (CM factor: Κ (ω)) and represents the degree of polarization.
[0035] Κ(ω) = (丄—丄 ） Ζ (丄 +2丄 ） --- (3)  [0035] Κ (ω) = (丄 — 丄) Ζ (丄 +2 丄) --- (3)
m m  m m
式（2)、式 (3)より、この CM因子は、分散媒及び粒子の導電率、誘電率、更に印 加する周波数に依存し、 -0. 5〜： 1. 0の値をとる。式（1)から誘電泳動力の方向は、 CM因子に依存する。即ち、 CM因子の実部が正の場合には誘電泳動力は正となり 、電場強度の大きい方に粒子を誘導する正の誘電泳動が作用し、負の場合には誘 電泳動力は負となり、電場強度の弱い方に粒子を誘導する負の誘電泳動力が作用 する。 From Equations (2) and (3), this CM factor depends on the conductivity and dielectric constant of the dispersion medium and particles, and the frequency to be applied, and takes values from -0.5 to 1.0. From equation (1), the direction of dielectrophoretic force depends on the CM factor. That is, when the real part of the CM factor is positive, the dielectrophoretic force is positive, positive dielectrophoresis that induces particles to act on the larger electric field strength, and in the negative case The electrophoretic force becomes negative, and the negative dielectrophoretic force that induces particles acts on the weaker electric field strength.
[0036] ところで、微細な穴を有する基板を分散媒中に浸して同様に電場を与えると、穴の 外側部分と穴の内側部分とで、電界強度分布に差が生じることが、本願発明者らに よる研究の結果、明らかになった。図 13は本願発明者らが実施した有限要素シミュレ ーシヨンによる電界強度分布の結果を示している。同図中において、 20は基板であり 、 21は該基板に存在する穴であり、 10, 10は分散媒である。図示は省略しているが 、分散媒 10, 10の外側（上下）にそれぞれ電極 30, 40が位置している。  [0036] By the way, if a substrate having fine holes is immersed in a dispersion medium and an electric field is applied in the same manner, a difference in electric field strength distribution occurs between the outer part of the hole and the inner part of the hole. As a result of their research, it became clear. FIG. 13 shows the result of the electric field intensity distribution by the finite element simulation performed by the inventors of the present invention. In the figure, 20 is a substrate, 21 is a hole in the substrate, and 10 and 10 are dispersion media. Although not shown, the electrodes 30 and 40 are located outside (upper and lower) of the dispersion media 10 and 10, respectively.
[0037] 図 13は、電極間に直流電圧（10V)を印加したものとしてのシミュレーション結果で あるが、交流電圧を印加した場合であっても、同様な電界強度分布を示すものと考え られる。同図は、基板 20の穴 21の内部（番号 11で示す）で電界強度が強ぐ該穴 21 の外部（番号 12で示す）の分散媒中では電界強度が穴 21の内部よりも弱いことを示 している。また、穴 21の開口部近傍 (番号 13で示す）では、穴 21の内部と同様に電 界強度が強ぐ穴 21とこれに隣接する穴 21との間の部分 (番号 14で示す）は電界強 度が該穴 21の外部（番号 12で示す）よりも更に弱くなつていることを示している。  [0037] Fig. 13 shows a simulation result assuming that a DC voltage (10V) is applied between the electrodes. Even when an AC voltage is applied, it is considered that a similar electric field strength distribution is exhibited. The figure shows that the electric field strength is weaker than the inside of the hole 21 in the dispersion medium outside the hole 21 (shown by the number 12) where the electric field strength is strong inside the hole 21 of the substrate 20 (shown by the number 11). Is shown. In addition, in the vicinity of the opening of hole 21 (indicated by reference numeral 13), the portion between the hole 21 where the electric field strength is strong and the adjacent hole 21 (indicated by reference numeral 14) is the same as the inside of hole 21. This shows that the electric field strength is weaker than the outside of the hole 21 (indicated by reference numeral 12).
[0038] このように、基板 20の穴 21の内部は、穴 21の外側の分散媒中よりも電界強度が強 いので、正の誘電泳動力を作用させることにより、分散媒中に分散された挿入体 (粒 子）を基板 20の穴 21の内部に誘導 '挿入することができることが理解される。  [0038] In this way, the electric field strength in the inside of the hole 21 of the substrate 20 is stronger than that in the dispersion medium outside the hole 21, so that it is dispersed in the dispersion medium by applying a positive dielectrophoretic force. It is understood that the inserted insert (particle) can be guided and inserted into the hole 21 of the substrate 20.
[0039] 図 14は誘電泳動させる粒子として金属 SWCNTsを用レ、、分散媒として tween20 を含有する純水を用いた場合の誘電泳動力（縦軸)と周波数 (横軸)との関係をシミュ レーシヨンした結果を示す図である。分散媒としては、純水に tween20を 2体積％含 有させたものと、純水に tween20を 0. 2体積％含有させたものの 2種類を用レ、、前 者を一点鎖線で、後者を実線で示している。同図から明らかなように、金属 SWCNT sの場合には、印加する周波数にかかわらず、常に正の誘電泳動力が生じることが理 解される。同図から 105Hz〜106Hz (100kHz〜lMHz)程度以下である場合に、正 の誘電泳動力が大きいことが理解される。この結果は、金属 SWCNTsの場合である が、金等の金属粒子においても同様の傾向になるものと考えられる。一般に、金属の 場合には 100kHz〜lMHz程度以下の周波数を印加するのが好ましい。 [0040] また、図 15は誘電泳動させる粒子として半導体 SWCNTsを用い、分散媒として tw een20を含有する純水を用いた場合の誘電泳動力（縦軸）と周波数 (横軸）との関係 をシミュレーションした結果を示す図である。分散媒としては、純水に tween20を 2体 積％含有させたものと、純水に tween20を 0. 2体積％含有させたものの 2種類を用 レ、、前者を点線で、後者を実線で示している。なお、図 15中、右上の部分に表示さ れているのは、周波数 105〜108Hzの部分を拡大表示した図である。 [0039] Figure 14 shows the relationship between the dielectrophoretic force (vertical axis) and the frequency (horizontal axis) when metallic SWCNTs are used as the particles to be dielectrophoresed and pure water containing tween20 is used as the dispersion medium. It is a figure which shows the result of lacing. There are two types of dispersion media: pure water containing 2% by volume of tween20 and pure water containing 0.2% by volume of tween20. The former is shown by a one-dot chain line and the latter is used. It is shown with a solid line. As is clear from the figure, in the case of metal SWCNTs, it is understood that a positive dielectrophoretic force is always generated regardless of the applied frequency. From the figure, it is understood that the positive dielectrophoretic force is large when the frequency is about 10 5 Hz to 10 6 Hz (100 kHz to lMHz) or less. This result is in the case of metallic SWCNTs, but it is considered that the same tendency is observed for metallic particles such as gold. In general, in the case of metal, it is preferable to apply a frequency of about 100 kHz to 1 MHz or less. [0040] Fig. 15 shows the relationship between the dielectrophoretic force (vertical axis) and the frequency (horizontal axis) when semiconductor SWCNTs are used as the particles to be dielectrophoresed and pure water containing tween20 is used as the dispersion medium. It is a figure which shows the result of simulation. Two types of dispersion media are used: pure water containing 2 parts by volume of tween20 and pure water containing 0.2% by volume of tween20. The former is a dotted line and the latter is a solid line. Show. In addition, what is displayed in the upper right part in FIG. 15 is an enlarged view of the part having a frequency of 10 5 to 10 8 Hz.
[0041] 同図から明らかなように、半導体 SWCNTsの場合には、 106Hz〜： 107Ηζ (1ΜΗζ 〜： 10MHz)程度以下の周波数の場合には正の誘電泳動力が生じ、 1MHz〜： 10M Hz程度以上の周波数の場合には負の誘電泳動力が生じることが理解される。この結 果は、半導体 SWCNTsの場合である力 他の半導体粒子においても同様の傾向に なるものと考えられる。揷入体を基板の穴に揷入する場合には、同図から 104Hz〜l 0 z (10kHz〜： 100kHz)程度以下の周波数である場合に、正の誘電泳動力が大 きいので、半導体の場合には 10kHz〜： 100kHz程度以下の周波数を印加するのが 好ましレ、。なお、半導体粒子を基板の穴から抜き去る場合には、負の誘電泳動力を 作用させるために、 106Ηζ (1ΜΗζ)程度以上の周波数を印加すればよいことが理解 される。 [0041] As is apparent from the figure, in the case of semiconductor SWCNTs, a positive dielectrophoretic force is generated at a frequency of about 10 6 Hz to 10 7 Ηζ (1 ΜΗζ to 10 MHz) or less, and 1 MHz to : It is understood that a negative dielectrophoretic force is generated when the frequency is about 10 MHz or higher. This result is considered to have the same tendency with other semiconductor particles, which is the force of semiconductor SWCNTs. When inserting the insert into the hole in the board, the positive dielectrophoretic force is large when the frequency is about 10 4 Hz to l 0 z (10 kHz to 100 kHz) or less. In the case of semiconductors, it is preferable to apply a frequency of about 10 kHz to 100 kHz or less. It is understood that when semiconductor particles are removed from the hole in the substrate, a frequency of about 10 6 Ηζ (1 ΜΗζ) or more should be applied in order to exert a negative dielectrophoretic force.
[0042] なお、金属 SWCNTs、半導体 SWCNTs、 0. 2体積％の tween20を純水に含有 させた分散媒、及び 2体積％の tween20を純水に含有させた分散媒の導電率、誘 電率を図 16に示す。  [0042] Electrical conductivity and electrical conductivity of metallic SWCNTs, semiconductor SWCNTs, a dispersion medium containing 0.2 vol% tween20 in pure water, and a dispersion medium containing 2 vol% tween20 in pure water. Figure 16 shows.
[0043] 図 1の S14で両電極 30, 40間に交流電圧の印加を開始してから、所定の時間が経 過したか否力を判断し (S15)、所定の時間が経過していない場合には、更に交流電 圧の印加を継続し、所定の時間が経過したならば、電圧の印加を停止する。電圧の 印加時間は、一例として 5〜 12分程度である。  [0043] It is determined whether or not a predetermined time has elapsed since the start of application of the AC voltage between the electrodes 30 and 40 in S14 of FIG. 1 (S15), and the predetermined time has not elapsed. In such a case, the application of the AC voltage is further continued, and the application of the voltage is stopped when a predetermined time has elapsed. The voltage application time is about 5 to 12 minutes as an example.
[0044] 交流電圧の印加が終了したならば、電極 30， 40を取り外す取外工程を行い（S16) 、後処理として、洗浄工程を行う (S17) 0洗浄工程では、誘電泳動に用いた分散媒（ 揷入体が分散されていなレ、もの）を用いて基板表面に付着している揷入体を洗い落 とす。洗浄工程は必要がない場合には省略してもよい。その後、加熱'冷却工程を行 つて（S18)、一連の処理を終了する。加熱'冷却工程は、例えば、揷入体として金等 の金属粒子を用いた場合に、基板の穴内に挿入されている金属粒子を加熱'溶融さ せて互いに一体化させるとともに、穴内に挿入体を固定するために行われる。加熱 · 冷却工程は必要がない場合には省略してもよい。この場合には、必要に応じて、電 極の取り外し後又は洗浄後の基板を自然乾燥させる乾燥工程を行う。 [0044] When the application of the AC voltage is completed, a removal process for removing the electrodes 30, 40 is performed (S16), and a cleaning process is performed as a post-processing (S17). 0 In the cleaning process, the dispersion used for the dielectrophoresis Wash off the adhering material adhering to the substrate surface using a medium (a non-dispersed material). The cleaning step may be omitted if it is not necessary. Thereafter, a heating and cooling process is performed (S18), and the series of processes is completed. The heating and cooling process is, for example, gold as an insert When the metal particles are used, the metal particles inserted into the holes of the substrate are heated and melted to be integrated with each other, and the insert is fixed in the holes. The heating / cooling process may be omitted if it is not necessary. In this case, if necessary, a drying process is performed in which the substrate after electrode removal or cleaning is naturally dried.
[0045] ところで、図 13を参照して説明したように、基板の穴の開口部近傍、即ち、穴の内 壁と基板面 (表面）との交差する部分の近傍は、穴の内部と同様に電界強度が比較 的に強いため、揷入体 (粒子）が当該穴の開口部近傍に滞留し、穴内部への揷入体 の進入の妨げとなることが懸念される。この問題に対処するため、基板の穴の径を基 板表面の近傍（開口部近傍)で、基板内部より大きい形状（円弧状、面取り形状等の 滑らかな形状）とすることが望ましレ、。このような滑らかな形状とすることにより、揷入体 が開口部近傍で滞留することが少なくなり、穴の奥部まで揷入体を十分に進入 ·充填 させることが可能になる。このような穴の開口部近傍を大きい形状とする加工方法とし ては、基板に穴を形成した後に、所定のエッチング液を用いてエッチングを行えばよ レ、。例えば、基板として酸化アルミニウムを用いる場合には、アルカリ性のエッチング 溶液を用いることにより、穴の開口部近傍を溶かし、適宜な時間の経過後に洗浄する ことにより、所望の形状とすることが可能である。  By the way, as described with reference to FIG. 13, the vicinity of the opening of the hole in the substrate, that is, the vicinity of the portion where the inner wall of the hole intersects the substrate surface (surface) is the same as the inside of the hole. Since the electric field strength is relatively high, the inserted body (particles) may remain in the vicinity of the opening of the hole and hinder the penetration of the inserted body into the hole. In order to cope with this problem, it is desirable to make the hole diameter of the board near the surface of the board (near the opening) larger than the inside of the board (smooth shape such as an arc shape or chamfered shape). . By adopting such a smooth shape, the insert is less likely to stay in the vicinity of the opening, and the insert can be sufficiently entered and filled to the back of the hole. As a processing method for making the vicinity of the opening of such a hole large, etching may be performed using a predetermined etching solution after forming the hole in the substrate. For example, when aluminum oxide is used as the substrate, it is possible to obtain a desired shape by dissolving the vicinity of the opening of the hole by using an alkaline etching solution and washing after an appropriate period of time. .
[0046] [導電性透明フィルムの製造]  [0046] [Manufacture of conductive transparent film]
次に、上述した基板構造体の製造方法を用いて、導電性フィルムを製造する場合 について説明する。ここでは、基板 (母材）として、ポリカーボネート、ポリエチレンテレ フタレート等の可撓性を有する透明樹脂フィルムを用い、図 4に示すように、複数の 貫通穴をランダム（無秩序）に均等な密度で形成する。但し、無秩序とは言っても、隣 接ないし近傍に位置する貫通穴同士が適宜に互いに交差連通するように、貫通穴の 直径との関係で形成密度を設定する。  Next, the case where an electroconductive film is manufactured using the manufacturing method of the board | substrate structure mentioned above is demonstrated. Here, a flexible transparent resin film such as polycarbonate or polyethylene terephthalate is used as the substrate (base material), and as shown in Fig. 4, a plurality of through-holes are formed randomly (disorderly) at an equal density. To do. However, the formation density is set in relation to the diameter of the through-holes so that the through-holes located next to or in the vicinity of each other are appropriately crossed and communicated with each other.
[0047] 揷入体としては、ここでは、繊維状物質としての CNTsを用いる。但し、金粒子等の 金属粒子を用いてもよレ、。ここで使用する CNTsは、 SWCNTs、 DWCNTs, 3WC NTs, MWCNTs、これらの混合物の何れであってもよレ、が、金属性の CNTsを多く 含有することが望ましい。  [0047] As the insert, CNTs as a fibrous material are used here. However, metal particles such as gold particles may be used. The CNTs used here may be any of SWCNTs, DWCNTs, 3WC NTs, MWCNTs, and mixtures thereof, but it is desirable that they contain a large amount of metallic CNTs.
[0048] 分散媒としては、純水、非イオン性界面活性剤水溶液、イオン性界面活性剤水溶 液、 tween20含有水溶液等の有機溶媒の何れを用いてもよい。図 4の基板を、図 1 のフローチャートに従って、図 12の誘電泳動装置に設置して、電極間に 100kHz〜 1MHzの周波数範囲の高周波を印加すると、分散媒中に分散している CNTsには 正の誘電泳動力が働いて、 CNTsが貫通穴の中に移動する。貫通穴の直径は 10〜 500nm程度の範囲内で設定するとよレ、。また、 1つの貫通穴に 1本の CNTsだけを 揷入させる場合には、貫通穴の直径を 10nm〜： !OOnmの範囲で設定すればよい。 これと逆に複数本の CNTsを 1つの貫通穴に挿入させる場合には、貫通穴の直径を lOOnm以上とすればよい。 [0048] Examples of the dispersion medium include pure water, nonionic surfactant aqueous solution, and ionic surfactant aqueous solution. Either an organic solvent such as a liquid or an aqueous solution containing tween 20 may be used. When the substrate of Fig. 4 is installed in the dielectrophoresis device of Fig. 12 according to the flowchart of Fig. 1 and a high frequency in the frequency range of 100kHz to 1MHz is applied between the electrodes, it is positive for the CNTs dispersed in the dispersion medium. The dielectrophoretic force of CNTs works and CNTs move into the through holes. The diameter of the through hole should be set within the range of 10 to 500nm. If only one CNTs is inserted into one through hole, the diameter of the through hole should be set within the range of 10nm to: OOnm. On the other hand, if multiple CNTs are inserted into one through hole, the diameter of the through hole may be set to lOOnm or more.
[0049] このようにして製造された導電性フィルムには、図 5に示すように、 CNTs22が基板 20内の局所領域に著しく凝集することはなぐ基板 20の全域に渡って均等な密度で 分散している。し力、も、貫通穴 21同士は互いに繋がっているので、揷入されている C NTs22同士は互いに接触 '導通している。従って、基板全体が導電性を有している 。貫通穴の直径及び貫通穴の形成密度を調整すれば、製造すべき導電性フィルム の導電率を調整することも可能であり、所望導電率を有する導電性フィルムを得るこ とができる。なお、基板 20内の局所領域に積極的に凝集させたい場合には、貫通穴 21の直径及び形成密度をこれに応じて局所的に変化させることにより、局所的に導 電率の異なる導電性フィルムを得ることも可能である。 [0049] In the conductive film manufactured in this way, as shown in Fig. 5, the CNTs 22 are dispersed at a uniform density over the entire area of the substrate 20 without causing the CNTs 22 to agglomerate in a local area in the substrate 20. is doing. However, since the through holes 21 are connected to each other, the inserted NTs 22 are in contact with each other. Therefore, the entire substrate has conductivity. By adjusting the diameter of the through holes and the formation density of the through holes, the conductivity of the conductive film to be manufactured can be adjusted, and a conductive film having a desired conductivity can be obtained. If it is desired to actively agglomerate in a local region in the substrate 20, the diameter and the formation density of the through-holes 21 are locally changed in accordance with this, so that the conductivity having locally different conductivities is obtained. It is also possible to obtain a film.
[0050] なお、ここでは、図 4に示すような無秩序に存在する貫通穴 21を有する基板 20を用 いたが、図 6に示すような所定の傾向をもって形成された貫通穴 21を有する基板 20 を用いてもよぐこれにより、図 7に示すように、貫通穴 21内に CNTs22が挿入された 導電性フィルムを得ることができる。また、図 2に示すような基板 20の表面（基板面） に対して実質的に直交する貫通穴 21を有する基板 20を用いることにより、図 3に示 すように、各貫通穴 21内に CNTs22がそれぞれ挿入された導電性フィルムを得るこ とができ、この導電性フィルムは、基板面に対して直交する方向に導電性を有し、基 板面に沿う方向には導電性を有しない配向導電性フィルムとなる。  [0050] Note that, here, the substrate 20 having the through holes 21 present in a disorderly manner as shown in FIG. 4 is used, but the substrate 20 having the through holes 21 formed with a predetermined tendency as shown in FIG. 6 is used. Thus, as shown in FIG. 7, a conductive film in which CNTs 22 are inserted into the through holes 21 can be obtained. In addition, by using the substrate 20 having the through holes 21 substantially orthogonal to the surface (substrate surface) of the substrate 20 as shown in FIG. 2, as shown in FIG. It is possible to obtain a conductive film in which CNTs 22 are inserted, and this conductive film has conductivity in a direction perpendicular to the substrate surface and does not have conductivity in a direction along the substrate surface. It becomes an oriented conductive film.
[0051] また、基板に形成される穴は貫通穴に限られるわけではなぐ図 8に示すように、基 板 20の表面に所定の深さの陥没穴 21を形成したものを用いることもでき、この場合 には図 9に示すように、基板の表面層にのみ導電性を有する導電性フィルムを得るこ とができる。 [0051] In addition, the hole formed in the substrate is not limited to the through hole. As shown in FIG. 8, it is also possible to use a hole in which a depressed hole 21 having a predetermined depth is formed on the surface of the substrate 20. In this case, as shown in FIG. 9, a conductive film having conductivity only on the surface layer of the substrate can be obtained. You can.
[0052] このように、本実施形態に係る基板構造体の製造方法を用いて、導電性フィルムを 製造することができ、基板に形成する穴の仕様等を適宜に変更調整することにより、 所望の性能を有する導電性フィルムを容易に製造することが可能である。このように して製造された可撓性を有する透明導電性フィルムは、例えば、電子ペーパー、フレ キシブルディスプレイ、フラットパネルディスプレイ等の透明電極として用いることがで きる。なお、基板として、ここでは、可撓性を有する透明フィルムを用いたが、可撓性 を有しなくてもよぐ透明でなくてもよい。また、上述した例では、基板全体に均一に 導電性を有する導電性フィルムを例示した力 フィルム内の単一又は複数の局所領 域のみに、均一に導電性を有する導電性フィルムを得ることもできる。  [0052] As described above, a conductive film can be manufactured using the method for manufacturing a substrate structure according to the present embodiment, and the desired specifications can be obtained by appropriately changing and adjusting the specifications of the holes formed in the substrate. It is possible to easily produce a conductive film having the following performance. The flexible transparent conductive film produced in this way can be used as a transparent electrode for electronic paper, a flexible display, a flat panel display, and the like. Note that, here, a transparent film having flexibility is used as the substrate, but it may or may not have flexibility. Further, in the above-described example, a conductive film having uniform conductivity can be obtained only in one or a plurality of local regions in the force film exemplifying a conductive film having conductivity uniformly throughout the substrate. it can.
[0053] [FEDの電子源の製造]  [0053] [FED electron source production]
次に、上述した基板構造体の製造方法を用レ、て FED (フィールド ·ェミッション'ディ スプレイ）の電子源（電界放出アレイ）を製造する場合にっレ、て説明する。ここでは、 基板 (母材）として、酸化アルミニウム等の無機酸化物基板を用レ、、図 2に示すように 、貫通穴が基板面に対して実質的に垂直に等間隔で形成された基板を用いる。貫 通穴の直径及び貫通穴間の間隔は、 FEDに利用する際に、輝度及び精細度に応じ て、調整すればよい。  Next, the manufacturing method of the substrate structure described above will be used to manufacture an FED (field emission display) electron source (field emission array). Here, an inorganic oxide substrate such as aluminum oxide is used as the substrate (base material). As shown in FIG. 2, a substrate in which through holes are formed at substantially equal intervals with respect to the substrate surface. Is used. The diameter of the through holes and the distance between the through holes may be adjusted according to the brightness and definition when used for FED.
[0054] 挿入体としては、ここでは、繊維状物質としての CNTsを用いる。ここで使用する C NTsは、 SWCNTs、 DWCNTs、 3WCNTs、 MWCNTs,これらの混合物の何れで あってもよいが、面内の電子放出密度を一定にするため、特定のグラフエンシート数 に揃えた CNTsを用いることが望ましい。  [0054] As the insert, here, CNTs as a fibrous material are used. The CNTs used here may be SWCNTs, DWCNTs, 3WCNTs, MWCNTs, or a mixture of these, but in order to keep the in-plane electron emission density constant, CNTs aligned with a specific number of graph ensheets. It is desirable to use
[0055] 分散媒としては、純水、非イオン性界面活性剤水溶液、イオン性界面活性剤水溶 液、 tween20含有水溶液等の有機溶媒の何れを用いてもよい。この基板を、図 1の フローチャートに従って、図 1 2の誘電泳動装置に設置して、電極間に: L00kHz〜i [0055] As the dispersion medium, any of organic solvents such as pure water, nonionic surfactant aqueous solution, ionic surfactant aqueous solution, and tween20-containing aqueous solution may be used. This substrate is installed in the dielectrophoresis device of FIG. 12 according to the flowchart of FIG. 1 , and between the electrodes: L 00 kHz to i
MHzの周波数範囲の高周波を印加すると、分散媒中に分散している CNTsには正 の誘電泳動力が働いて、 CNTsが貫通穴の中に移動する。貫通穴の直径は 10〜50 Onm程度の範囲内で設定するとよレ、。また、 1つの貫通穴に 1本の CNTsだけを揷入 させる場合には、貫通穴の直径を 10nm〜100nmの範囲で設定すればよレ、。これと 逆に複数本の CNTsを 1つの貫通穴に挿入させる場合には、貫通穴の直径を 100η m以上とすればよい。 When a high frequency in the MHz frequency range is applied, positive dielectrophoretic force acts on the CNTs dispersed in the dispersion medium, and the CNTs move into the through holes. The diameter of the through hole should be set within the range of 10-50 Onm. In addition, if only one CNTs is inserted into one through hole, the diameter of the through hole should be set in the range of 10nm to 100nm. This and Conversely, when inserting multiple CNTs into one through hole, the diameter of the through hole should be 100 ηm or more.
[0056] このようにして製造された基板構造体 (電子放出素子）は、図 3に示すように、 CNT s22が基板 20内の局所領域に偏在することはなぐ基板全域に渡って均等な間隔で 垂直配向されている。なお、電子放出素子としては、基板の表面（上面、下面）から揷 入体としての CNTsl 11が突出してレ、た方がょレ、。このように揷入体を突出させる場 合には、基板の貫通穴に CNTsを揷入した後に、アルカリ溶液等でエッチングして基 板の表面を所定量だけ除去すればょレ、。  As shown in FIG. 3, the substrate structure (electron-emitting device) manufactured in this way is evenly spaced over the entire substrate without the CNT s22 being unevenly distributed in the local region in the substrate 20. In vertical alignment. As an electron-emitting device, CNTsl 11 as an insert protrudes from the surface (upper surface and lower surface) of the substrate. In order to make the insert protrude in this way, after inserting CNTs into the through hole of the substrate, etching with an alkaline solution or the like to remove a predetermined amount of the surface of the substrate.
[0057] このように、本実施形態に係る基板構造体の製造方法を用いて、 FEDの電子放出 素子を製造することができ、基板に形成する穴の直径や配列間隔等を適宜に変更調 整することにより、所望の性能を有する電子放出素子を容易に製造することが可能で ある。  As described above, an FED electron-emitting device can be manufactured by using the method for manufacturing a substrate structure according to this embodiment, and the diameters and arrangement intervals of holes formed in the substrate can be appropriately changed. Thus, an electron-emitting device having desired performance can be easily manufactured.
[0058] 図 17は、上述した製造方法を用いて製造された電子放出素子を備える FEDの要 部を拡大した図である。同図において、 100はェミッタ基板（ェミッタ電極）であり、エミ ッタ基板 100上には、上述した製造方法を用いて製造された、基板の貫通穴に CNT si 11を挿入してなる多数の電子放出素子 110がマトリックス状に配置されてレ、る。こ れらの電子放出素子 110のェミッタ基板 100上への固定は、例えば導電性ペースト を用いて貼着することにより行うことができる。ェミッタ基板 100の電子放出素子 110 が配置された部分の間の部分には、絶縁層 120が形成されており、絶縁層 120上に ゲート電極 130が設けられている。  FIG. 17 is an enlarged view of a main part of the FED including the electron-emitting device manufactured by using the manufacturing method described above. In the figure, reference numeral 100 denotes an emitter substrate (emitter electrode). On the emitter substrate 100, a large number of CNT si 11 are inserted into the through-holes of the substrate manufactured using the manufacturing method described above. The electron-emitting devices 110 are arranged in a matrix. These electron-emitting devices 110 can be fixed on the emitter substrate 100 by, for example, sticking using a conductive paste. An insulating layer 120 is formed between the portions of the emitter substrate 100 where the electron-emitting devices 110 are disposed, and a gate electrode 130 is provided on the insulating layer 120.
[0059] ェミッタ基板 100に対向するように、スぺーサーを介して所定の間隔で、アノード基 板 140が設けられている。アノード基板 140は IT〇等からなる透明電極であり、その 表面（内面）の電子放出素子 110に対面する部分には蛍光体層（RGB蛍光体） 141 が形成されている。ェミッタ基板 100とアノード基板 140の間の部分は真空状態とな つている。直流電源 150により、ェミッタ基板 100とアノード基板 140の間に直流電圧 を印加すると、電子放出素子 110から電子が放出され、蛍光体層 141に衝突して蛍 光体を励起 '発光させることにより、表示がなされる。  [0059] Anode substrates 140 are provided at predetermined intervals through a spacer so as to face the emitter substrate 100. The anode substrate 140 is a transparent electrode made of ITO or the like, and a phosphor layer (RGB phosphor) 141 is formed on the surface (inner surface) facing the electron-emitting device 110. The portion between the emitter substrate 100 and the anode substrate 140 is in a vacuum state. When a DC voltage is applied between the emitter substrate 100 and the anode substrate 140 by the DC power supply 150, electrons are emitted from the electron-emitting device 110 and collide with the phosphor layer 141 to excite and emit light. Display is made.
[0060] 本実施形態に係る基板構造体の製造方法を用いて製造された電子放出素子は、 基板内で CNTsが偏在することなく均等に分散配置されているとともに、基板面に対 して垂直配向されているので、 FEDの電子放出素子として採用した場合に、極めて 良好な電子放出特性を実現することができ、輝度や精細度にばらつきがなぐ極めて 良好な表示性能を有する FEDを得ることができる。また、 CNTsのグラフヱンシート数 を揃えたので、これによつても、輝度や寿命をほぼ一定にすることができる。 [0060] An electron-emitting device manufactured using the method for manufacturing a substrate structure according to this embodiment CNTs are evenly distributed in the substrate without being unevenly distributed, and are aligned perpendicular to the substrate surface, so when used as an FED electron-emitting device, extremely good electron emission characteristics are achieved. FED having extremely good display performance with no variation in brightness and definition can be obtained. In addition, since the number of graph sheets of CNTs has been made uniform, this also makes it possible to make the brightness and life almost constant.
[0061] [積層チップ]  [0061] [Multilayer chip]
近時、 LSIを積層化する技術として、例えば、 SiP (system in package)等が注 目を集めている。 SiPは、メモリ、 CPU,その他の回路等を含む複数の LSI (チップ） を三次元的に積層して一つのパッケージに実装したデバイス (積層チップ）である。し かし、層間の接続には、ワイヤ ·ボンディングが用いられるため、高速化が難しぐしか も配線の本数も限られ、薄型化が難しいという課題を抱えているのが実情である。  Recently, for example, SiP (system in package) has attracted attention as a technology for stacking LSIs. SiP is a device (laminated chip) in which a plurality of LSIs (chips) including memory, CPU, and other circuits are stacked three-dimensionally and mounted in a single package. However, since wire bonding is used for the connection between the layers, it is difficult to increase the speed and the number of wires is limited.
[0062] 本実施形態に係る基板構造体の製造方法を応用して、積層チップの各層（各チッ プ、例えば第 1チップと第 2チップ）間を三次元的に接続することが可能である。積層 チップを構成する各チップ又は積層チップ自体を基板として、層間接続用のビアホ ール又はスルーホールとなるべき部分に穴を予め形成する。挿入体として、例えば金 属 CNTsや金微粒子を用い、図 12の誘電泳動装置を用いて、当該穴内に挿入体を 挿入することにより、層間接続用のビアホール又はスルーホールを容易に作成するこ とが可能である。  [0062] By applying the substrate structure manufacturing method according to the present embodiment, each layer (each chip, for example, the first chip and the second chip) of the multilayer chip can be three-dimensionally connected. . Using each chip constituting the multilayer chip or the multilayer chip itself as a substrate, holes are formed in advance in portions to be via holes or through holes for interlayer connection. By using, for example, metal CNTs or gold fine particles as the insert, and inserting the insert into the hole using the dielectrophoresis apparatus of FIG. 12, via holes or through holes for interlayer connection can be easily created. Is possible.
[0063] これにより、信号配線長を短くすることができ、配線抵抗を小さくできるとともに、配 線数も増大させることができ、高性能化や低消費電力化を図ることが可能となる。な お、挿入体を半導体 CNTsやその他の半導体等を用いて回路部品とし、基板の穴に 挿入することにより、各層間を連絡する形で、回路部品を実装することも可能である。  Thereby, the signal wiring length can be shortened, the wiring resistance can be reduced, the number of wirings can be increased, and high performance and low power consumption can be achieved. It is also possible to mount the circuit components in such a way that each insert is connected to each other by inserting the insert into a circuit hole using semiconductor CNTs or other semiconductors and inserting it into the hole in the substrate.
[0064] [高周波高出力増幅器]  [0064] [High-frequency high-power amplifier]
次世代以降の無線通信システムに向けた高性能な高周波高出力増幅器の実現が 要請されており、フェイスアップ構造の増幅器では、トランジスタチップの電極とパッケ ージの電極を電気接続する金属ワイヤーのインダクタンスが問題となっている。その 解決策として、トランジスタチップを裏返し、チップ電極とパッケージ電極を金等の短 い金属バンプ (突起電極）で接続するフリップチップ構造が提案されている。しかしな がら、高出力増幅器の場合、高出力トランジスタで発生した大量の熱を逃がすには、 従来の金属バンプでは放熱性の点で不十分であった。このため、 CNTsを高周波高 出力増幅器の放熱基板に用いることで、放熱性と高い増幅率を同時に実現する技術 が提案されている。 Realization of high-performance, high-frequency, high-power amplifiers for next-generation and subsequent wireless communication systems is demanded. In face-up amplifiers, the inductance of the metal wire that electrically connects the electrode of the transistor chip and the electrode of the package Is a problem. As a solution, a flip chip structure has been proposed in which the transistor chip is turned over and the chip electrode and the package electrode are connected by a short metal bump (projection electrode) such as gold. But However, in the case of high-power amplifiers, conventional metal bumps are insufficient in terms of heat dissipation to release a large amount of heat generated by high-power transistors. For this reason, a technology has been proposed that uses CNTs as a heat dissipation substrate for a high-frequency, high-power amplifier to simultaneously achieve heat dissipation and a high gain.
[0065] この技術では、電極基板に垂直に配向させて CNTsを成長させて、 CNTsバンプと フリップチップとを接合していた。このように電極基板に CNTsを直接成長させる方法 では、電子源を構成する場合の課題として上述した通り、配向は統一できるものの、 CNTsの製造条件が、電極基板の性質で制限されるため、製造できる CNTs形状が 制限される可能性があるとともに、電極基板は、高温の炭素析出条件下に曝されるた め、電極基板の材質が劣化する場合があるという問題がある。  [0065] In this technique, CNTs are grown by being oriented perpendicular to the electrode substrate, and the CNTs bumps and the flip chip are joined. As described above, in the method of directly growing CNTs on the electrode substrate as described above, although the orientation can be unified as described above as the problem in configuring the electron source, the manufacturing conditions of the CNTs are limited by the properties of the electrode substrate. There is a possibility that the shape of CNTs that can be produced is limited, and the electrode substrate is exposed to high-temperature carbon deposition conditions, so that the material of the electrode substrate may deteriorate.
[0066] 本実施形態に係る基板構造体の製造方法を用いて、図 2に示したような貫通穴を 有する基板の該貫通穴に金属 CNTsを揷入して、図 3に示すような基板構造体を製 造し、この基板構造体を介して、パッケージ電極上にフリップチップを支持することに より、上述したような問題を生じることなぐ放熱性と高い増幅率を同時に且つ容易に 実現すること力できる。  [0066] Using the method for manufacturing a substrate structure according to the present embodiment, metal CNTs are inserted into the through holes of the substrate having the through holes as shown in FIG. 2, and the substrate as shown in FIG. By manufacturing the structure and supporting the flip chip on the package electrode through this substrate structure, heat dissipation without causing the problems described above and high gain can be realized simultaneously and easily. I can do it.
[0067] [細胞標本等]  [0067] [Cell specimen, etc.]
細胞を挿入体として分散媒中に分散させ、例えば、図 10に示すような陥没穴を有 する基板に、図 12の誘電泳動装置を用いて、当該穴内に挿入体を挿入することによ り、図 11に示すような細胞標本等を作成することもできる。この場合の印加電圧として は、細胞に悪影響を与えない程度に小さい電圧とすることが望ましい。印加する周波 数を適宜に選定する等により、複数種類の細胞を分散させた分散媒中の特定の細 胞のみを基板の穴に挿入して細胞標本等を作成することも可能であると考えられる。 実施例 1  The cells are dispersed in a dispersion medium as an insert, and the insert is inserted into the hole using, for example, the dielectrophoresis apparatus shown in FIG. 12 on a substrate having a depression hole as shown in FIG. A cell specimen as shown in FIG. 11 can also be created. In this case, it is desirable that the applied voltage be as small as possible so as not to adversely affect the cells. It is also possible to create cell specimens etc. by inserting only specific cells in a dispersion medium in which multiple types of cells are dispersed into the holes in the substrate by appropriately selecting the frequency to be applied. It is done. Example 1
[0068] 図 18及び図 19は、本願発明者らが実施した実験結果を示す図（SEM写真）であり 、図 18は本実施形態の製造方法を用いて製造された基板構造体の断面図、図 19 は図 18の右上 25 /i m部分を拡大した断面図である。この実験は、基板として、微細 な穴を有する基板を用い、挿入体を純水に分散させた分散媒を用い、図 12に示した 誘電泳動装置を用いて、実施した。基板の材質は酸化アルミニウム（アルミナ）、基板 の厚さは 60 μ ΐη、基板の大きさは直径 25mm、穴の直径は 200nmである。挿入体 は金の微粒子（金コロイド）であり、粒子径は lOOnmである。純水に該挿入体を、分 散濃度 1. 1 X 1012粒子/ mLで分散させた分散媒 100 / Lを使用した。基板を分散 媒に浸す方法としては、分散媒の液滴を基板に滴下する方法を用いた。電極間に印 加した交流電圧は 31Vppであり、周波数は 70kHzである。交流電圧の印加時間は 5 分とした。なお、金の導電率は 45. 2 X 106S/m,純水の誘電率は 81 ε である。 FIG. 18 and FIG. 19 are diagrams (SEM photographs) showing the results of experiments performed by the inventors of the present application, and FIG. 18 is a cross-sectional view of a substrate structure manufactured using the manufacturing method of the present embodiment. FIG. 19 is an enlarged sectional view of the upper right 25 / im portion of FIG. This experiment was performed using a substrate having fine holes as a substrate, a dispersion medium in which the insert was dispersed in pure water, and the dielectrophoresis apparatus shown in FIG. The material of the substrate is aluminum oxide (alumina), the substrate The thickness of the substrate is 60 μΐη, the substrate size is 25 mm in diameter, and the hole diameter is 200 nm. The insert is a gold microparticle (gold colloid) with a particle size of lOOnm. A dispersion medium 100 / L in which the insert was dispersed in pure water at a dispersion concentration of 1.1 × 10 12 particles / mL was used. As a method of immersing the substrate in the dispersion medium, a method of dropping a droplet of the dispersion medium onto the substrate was used. The AC voltage applied between the electrodes is 31 Vpp, and the frequency is 70 kHz. The AC voltage was applied for 5 minutes. The conductivity of gold is 45.2 X 10 6 S / m, and the dielectric constant of pure water is 81 ε.
0  0
[0069] これらの図に示されているように、基板の穴中に金微粒子が揷入されていることが わかる。なお、本願発明者らは、毛細管現象により、基板の穴中に分散媒中の金微 粒子が入り込むかどうかについても実験を行レ、、毛細管現象によっては、金微粒子 が基板の穴中に入り込むことはないことを確認している。また、このような金微粒子を 揷入体とする場合には、揷入体が基板の穴内になるベく隙間無く入り込むことが理想 ではあるが、そうならない場合には、誘電泳動による揷入体の基板の穴内への揷入 の後に、加熱処理をして、金微粒子を溶融させた後に冷却することにより、穴内部の 金微粒子を互いに一体化させて穴の形状に沿った柱状体ないし繊維状の固体とす るとともに、基板の穴に固定することが望ましい。  [0069] As shown in these figures, it can be seen that gold fine particles are inserted into the holes of the substrate. The inventors of the present application also conducted an experiment on whether or not the gold fine particles in the dispersion medium enter the hole of the substrate due to the capillary phenomenon. Depending on the capillary phenomenon, the gold fine particles enter the hole of the substrate. I have confirmed that there is no such thing. In addition, when such gold fine particles are used as an insert, it is ideal that the insert enters into the hole of the substrate without any gap, but if this is not the case, the insert by dielectric electrophoresis is used. After the glass substrate is inserted into the hole of the substrate, heat treatment is performed to melt the gold fine particles and then cooling, so that the gold fine particles inside the hole are integrated with each other to form a columnar body or fiber along the shape of the hole. It is desirable to fix it in a hole in the substrate.
実施例 2  Example 2
[0070] 図 20乃至図 22は、本願発明者らが実施した実験結果を示す図（SEM写真）であり 、図 20は本実施形態の製造方法に用いた基板 (揷入体が挿入されていない）の断 面を斜めから撮像した図、図 21は本発明の実施形態の製造方法を用いて挿入体が 揷入された基板構造体の断面を斜めから撮像した図、図 22は図 21の一部を拡大し た図である。この実験は、基板として、微細な穴を有する基板を用い、揷入体を純水 に分散させた分散媒を用い、図 12に示した誘電泳動装置を用いて、実施した。基板 の材質はポリカーボネート、基板の厚さは 60 x m、基板の大きさは直径 25mm、穴の 直径は lOOnmである。揷入体は MWCNTsである。純水に該揷入体を、分散濃度 5 mg/mLで分散させた分散媒 20 μ Lを使用した。基板を分散媒に浸す方法としては 、分散媒の液滴を基板に滴下する方法を用いた。電極間に印加した交流電圧は 20 Vppであり、周波数は 55kHzである。交流電圧の印加時間は 5分とした。  FIGS. 20 to 22 are diagrams (SEM photographs) showing the results of experiments conducted by the inventors of the present application, and FIG. 20 shows the substrate (inserted body inserted) used in the manufacturing method of the present embodiment. FIG. 21 is an oblique image of the cross section of the substrate structure inserted with the insert using the manufacturing method according to the embodiment of the present invention, and FIG. It is the figure which expanded a part of. This experiment was carried out using a dielectrophoresis apparatus shown in FIG. 12, using a substrate having fine holes as a substrate, using a dispersion medium in which a filler was dispersed in pure water. The substrate material is polycarbonate, the substrate thickness is 60 x m, the substrate size is 25mm in diameter, and the hole diameter is lOOnm. The inclusions are MWCNTs. A dispersion medium (20 μL) in which the filler was dispersed in pure water at a dispersion concentration of 5 mg / mL was used. As a method of immersing the substrate in the dispersion medium, a method of dropping a droplet of the dispersion medium onto the substrate was used. The AC voltage applied between the electrodes is 20 Vpp, and the frequency is 55 kHz. The AC voltage was applied for 5 minutes.
[0071] これらの図（特に、図 21中に楕円で示す部分及び図 22中に矢印で示す部分）に示 されているように、基板の表面から内部まで MWCNTsが挿入されていることが理解 でき、基板全体に渡って導電性が発現できている。なお、 MWCNTsの基板の穴へ の固定は、 自然乾燥させることにより行った。 [0071] As shown in these drawings (particularly, the part indicated by an ellipse in FIG. 21 and the part indicated by an arrow in FIG. 22). As shown in the figure, it can be seen that MWCNTs are inserted from the surface of the substrate to the inside, and conductivity can be expressed throughout the substrate. The MWCNTs were fixed in the substrate holes by natural drying.
[0072] なお、以上説明した実施形態及び実施例は、本発明の理解を容易にするために記 載されたものであって、本発明を限定するために記載されたものではなレ、。したがつ て、上記の実施形態及び実施例に開示された各要素は、本発明の技術的範囲に属 する全ての設計変更や均等物をも含む趣旨である。 It should be noted that the embodiments and examples described above are described for easy understanding of the present invention, and are not described for limiting the present invention. Therefore, each element disclosed in the above embodiments and examples is intended to include all design changes and equivalents belonging to the technical scope of the present invention.
[0073] 本開示は、 2006年 6月 29日に提出された日本国特許出願第 2006— 179751号 に含まれた主題に関連し、その開示の全てはここに参照事項として明白に組み込ま れる。 [0073] This disclosure relates to the subject matter contained in Japanese Patent Application No. 2006-179751 filed on June 29, 2006, the entire disclosure of which is expressly incorporated herein by reference.

Claims

請求の範囲 The scope of the claims
[I] 少なくとも 1つの微細な穴を有する基板を準備する第 1工程と、  [I] a first step of preparing a substrate having at least one fine hole;
電極を設置し、前記基板を複数の挿入体を含む分散媒に浸す第 2工程と、 前記電極に所定の電圧を印加する第 3工程と、  A second step of installing an electrode and immersing the substrate in a dispersion medium containing a plurality of inserts; a third step of applying a predetermined voltage to the electrode;
を備える基板構造体の製造方法。  A method for manufacturing a substrate structure comprising:
[2] 前記第 1工程は、前記基板に前記穴を形成する工程を含む請求項 1に記載の基板 構造体の製造方法。 [2] The method for manufacturing a substrate structure according to claim 1, wherein the first step includes a step of forming the hole in the substrate.
[3] 前記第 3工程は、前記基板に交流電圧を印加する工程を含む請求項 1又は 2に記 載の基板構造体の製造方法。  [3] The method for manufacturing a substrate structure according to claim 1 or 2, wherein the third step includes a step of applying an AC voltage to the substrate.
[4] 前記交流電圧の周波数は、前記挿入体の誘電率と前記分散媒の誘電率との関係 から、前記挿入体に正の誘電泳動力が作用する範囲内に設定される請求項 3に記 載の基板構造体の製造方法。 [4] The frequency of the AC voltage is set within a range in which a positive dielectrophoretic force acts on the insert from the relationship between the dielectric constant of the insert and the dielectric constant of the dispersion medium. A manufacturing method of the described substrate structure.
[5] 前記交流電圧の周波数は、 1kHz〜： 100MHzの範囲内である請求項 3又は 4に記 載の基板構造体の製造方法。 [5] The method for manufacturing a substrate structure according to claim 3 or 4, wherein the frequency of the AC voltage is within a range of 1 kHz to 100 MHz.
[6] 前記基板は、複数の前記穴を有する請求項：!〜 5の何れか一項に記載の基板構造 体の製造方法。 [6] The method for manufacturing a substrate structure according to any one of [5] to [5], wherein the substrate has a plurality of the holes.
[7] 前記穴は、前記基板を貫通する貫通穴である請求項:!〜 6の何れか一項に記載の 基板構造体の製造方法。  [7] The method for manufacturing a substrate structure according to any one of [6] to [6], wherein the hole is a through-hole penetrating the substrate.
[8] 前記穴は、前記基板の表面層に設けられた陥没穴である請求項 1〜6の何れか一 項に記載の基板構造体の製造方法。 [8] The method for manufacturing a substrate structure according to any one of [1] to [6], wherein the hole is a depressed hole provided in a surface layer of the substrate.
[9] 前記穴は、前記穴の径が前記基板の表面近傍で、前記基板の内部より大きい形状 である請求項:!〜 8の何れか一項に記載の基板構造体の製造方法。 [9] The method for manufacturing a substrate structure according to any one of [8] to [8], wherein the hole has a shape in which the diameter of the hole is near the surface of the substrate and is larger than the inside of the substrate.
[10] 前記基板の厚さは、 1 μ m〜lmmの範囲内であるとともに、前記穴の直径は、 5nm[10] The thickness of the substrate is in the range of 1 μm to lmm, and the diameter of the hole is 5 nm.
〜100 μ mの範囲内である請求項 1〜9の何れか一項に記載の基板構造体の製造 方法。 The method for producing a substrate structure according to any one of claims 1 to 9, wherein the method is in a range of ~ 100 µm.
[II] 前記基板は、絶縁性の材料からなる請求項 1〜： 10の何れか一項に記載の基板構 造体の製造方法。  [II] The method for manufacturing a substrate structure according to any one of claims 1 to 10, wherein the substrate is made of an insulating material.
[12] 前記挿入体は、導電性又は半導電性の材料からなる請求項 1〜： 11の何れか一項 に記載の基板構造体の製造方法。 12. The insert according to any one of claims 1 to 11, wherein the insert is made of a conductive or semiconductive material. The manufacturing method of the board | substrate structure of description.
[13] 前記挿入体は、繊維状物質又は微粒子状物質である請求項:!〜 12の何れか一項 に記載の基板構造体の製造方法。  [13] The method for manufacturing a substrate structure according to any one of [12] to [12], wherein the insert is a fibrous substance or a particulate substance.
[14] 前記第 3工程の後、加熱して接合する工程を含む請求項 1〜： 13の何れか一項に記 載の基板構造体の製造方法。 [14] The method for manufacturing a substrate structure according to any one of [1] to [13], further including a step of heating and bonding after the third step.
[15] 前記揷入体は、前記基板の内部に均一に存在している請求項 1〜： 14の何れか一 項に記載の基板構造体の製造方法。 [15] The method for manufacturing a substrate structure according to any one of [1] to [14], wherein the insert is uniformly present inside the substrate.
[16] 前記揷入体は、カーボンナノチューブである請求項 1〜： 15の何れか一項に記載の 基板構造体の製造方法。 [16] The method for producing a substrate structure according to any one of [1] to [15], wherein the insert is a carbon nanotube.
[17] 前記揷入体は、金属の微粒子である請求項 1〜： 15の何れか一項に記載の基板構 造体の製造方法。 [17] The method for producing a substrate structure according to any one of [1] to [15], wherein the insert is a fine metal particle.
[18] 前記穴は、近接する少なくとも 1つの前記穴と互いに交差連通するように設けられ ている請求項:!〜 17の何れか一項に記載の基板構造体の製造方法。  [18] The method for manufacturing a substrate structure according to any one of [18] to [17], wherein the hole is provided so as to cross and communicate with at least one of the adjacent holes.
[19] 前記穴は、前記基板の表面に対して斜め方向に存在している請求項 1〜： 18の何 れか一項に記載の基板構造体の製造方法。 [19] The method for manufacturing a substrate structure according to any one of [1] to [18], wherein the hole exists in an oblique direction with respect to a surface of the substrate.
[20] 前記穴は、前記基板の表面に対して垂直方向に存在している請求項:!〜 17の何 れか一項に記載の基板構造体の製造方法。 [20] The method for manufacturing a substrate structure according to any one of [18] to [17], wherein the hole exists in a direction perpendicular to a surface of the substrate.
[21] 可撓性を有する、 [21] have flexibility,
請求項 18又は 19に記載の製造方法を用いて製造された基板構造体。  A substrate structure manufactured using the manufacturing method according to claim 18 or 19.
[22] 可撓性を有する、 [22] flexible
請求項 20に記載の製造方法を用いて製造された基板構造体。  21. A substrate structure manufactured using the manufacturing method according to claim 20.
[23] 請求項 20に記載の製造方法を用いて製造された電子放出素子。 23. An electron-emitting device manufactured using the manufacturing method according to claim 20.
[24] 請求項 20に記載の製造方法を備える電子放出素子の製造方法。 24. A method for manufacturing an electron-emitting device, comprising the manufacturing method according to claim 20.
[25] 請求項 23に記載の電子放出素子を少なくとも 1つ有する電子源。 25. An electron source having at least one electron-emitting device according to claim 23.
[26] 複数の接続端子を有する、少なくとも 2つのチップがあって、 [26] There are at least two chips having a plurality of connection terminals,
第 1チップと第 2チップとの間に前記基板が存在する、  The substrate is present between the first chip and the second chip;
請求項 20に記載の製造方法を用いて製造された積層チップ。  21. A multilayer chip manufactured using the manufacturing method according to claim 20.
[27] 請求項 1〜20の何れか一項に記載の製造方法を用いて製造された基板構造体。 [27] A substrate structure manufactured using the manufacturing method according to any one of [1] to [20].
[28] 直径が 5nm〜： 100 μ mの範囲内の少なくとも 1つの穴が存在するとともに、厚さが 1 β m〜 lmmの範囲内である基板と、 [28] a substrate having a diameter of 5 nm to: at least one hole in the range of 100 μm and a thickness in the range of 1 β m to lmm;
導電性又は半導電性の性質を有する、前記穴に挿入された少なくとも 1つの挿入 体と、  At least one insert inserted into the hole having conductive or semi-conductive properties;
を備える基板構造体。  A substrate structure comprising:
[29] 前記基板は、前記穴を複数有する請求項 28に記載の基板構造体。 29. The substrate structure according to claim 28, wherein the substrate has a plurality of the holes.
[30] 前記穴は、近接する少なくとも 1つの前記穴と互いに交差連通するように形成され ている請求項 29に記載の基板構造体。 30. The substrate structure according to claim 29, wherein the hole is formed so as to cross and communicate with at least one of the adjacent holes.
[31] 前記穴は、前記基板の表面に対して斜め方向に形成されている請求項 28〜30の 何れか一項に記載の基板構造体。 [31] The substrate structure according to any one of claims 28 to 30, wherein the hole is formed in an oblique direction with respect to a surface of the substrate.
[32] 前記穴は、前記基板の表面に対して略垂直方向に形成されている請求項 28又は [32] The hole is formed in a direction substantially perpendicular to a surface of the substrate.
29に記載の基板構造体。  30. The substrate structure according to 29.
[33] 前記基板の表面に対して交差する方向に、導電性又は半導電性の性質を有する 請求項 30又は 31に記載の基板構造体。 33. The substrate structure according to claim 30, wherein the substrate structure has a conductive or semiconductive property in a direction intersecting with a surface of the substrate.
[34] 前記基板の表面に対して略垂直方向に、導電性又は半導電性の性質を有する請 求項 32に記載の基板構造体。 [34] The substrate structure according to claim 32, which has a conductive or semiconductive property in a direction substantially perpendicular to the surface of the substrate.
[35] 前記挿入体は、カーボンナノチューブである請求項 28〜34の何れか一項に記載 の基板構造体。 [35] The substrate structure according to any one of [28] to [34], wherein the insert is a carbon nanotube.
[36] 前記挿入体は、金の微粒子である請求項 28〜34の何れか一項に記載の基板構 造体。  [36] The substrate structure according to any one of [28] to [34], wherein the insert is a fine gold particle.
[37] 電圧を印加することで電子を放出する電子放出素子であって、  [37] An electron-emitting device that emits electrons by applying a voltage,
少なくとも 1つの微細な穴を有する基板と、  A substrate having at least one fine hole;
前記電子放出素子の電極として、前記微細な穴に挿入された少なくとも 1つの揷入 体と、  At least one insertion body inserted into the fine hole as an electrode of the electron-emitting device;
を備える電子放出素子。  An electron-emitting device comprising:
[38] 前記揷入体は、前記基板の表面に対して、前記揷入体の一部が突出して前記穴 に揷入されている請求項 37に記載の電子放出素子。 38. The electron-emitting device according to claim 37, wherein the insert is partly protruded from the surface of the substrate and inserted into the hole.
[39] 前記穴は、前記穴の径が前記基板の表面近傍で、前記基板の内部より大きい形状 である請求項 37又は 38に記載の電子放出素子。 [39] The hole has a shape in which the diameter of the hole is near the surface of the substrate and is larger than the inside of the substrate. The electron-emitting device according to claim 37 or 38.
[40] 前記穴は、前記基板の表面に対して略垂直方向に存在している請求項 37〜39の 何れか一項に記載の電子放出素子。 [40] The electron-emitting device according to any one of [37] to [39], wherein the hole exists in a direction substantially perpendicular to the surface of the substrate.
[41] 前記揷入体は、カーボンナノチューブである請求項 37〜40の何れか一項に記載 の電子放出素子。 41. The electron-emitting device according to any one of claims 37 to 40, wherein the insert is a carbon nanotube.
[42] 前記揷入体は、所定層の多層カーボンナノチューブである請求項 37〜40の何れ か一項に記載の電子放出素子。  42. The electron-emitting device according to any one of claims 37 to 40, wherein the insert is a multi-layer carbon nanotube of a predetermined layer.
[43] 前記揷入体は、単層カーボンナノチューブである請求項 37〜40の何れか一項に 記載の電子放出素子。 [43] The electron-emitting device according to any one of [37] to [40], wherein the insert is a single-walled carbon nanotube.
[44] 前記揷入体は、金の微粒子である請求項 37〜40の何れか一項に記載の電子放 出素子。  [44] The electron-emitting device according to any one of [37] to [40], wherein the insert is a gold fine particle.
[45] 電界放出型の画像表示装置であって、  [45] A field emission type image display device,
請求項 37〜44の何れか一項に記載の電子放出素子を少なくとも 1つ有する電子 源と、  An electron source comprising at least one electron-emitting device according to any one of claims 37 to 44,
前記電子源と対面する位置に配置される蛍光体層と、  A phosphor layer disposed at a position facing the electron source;
を備える画像表示装置。  An image display device comprising:
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TWI727169B (en) * 2017-05-18 2021-05-11 日商夏普股份有限公司 Electron emitting element and manufacturing method thereof

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