TW200811306A - Substrate structure manufacturing method, substrate structure, electron emitting element, electron emitting element manufacturing method, electron source, image display device, and laminated chip - Google Patents

Substrate structure manufacturing method, substrate structure, electron emitting element, electron emitting element manufacturing method, electron source, image display device, and laminated chip Download PDF

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Publication number
TW200811306A
TW200811306A TW096122262A TW96122262A TW200811306A TW 200811306 A TW200811306 A TW 200811306A TW 096122262 A TW096122262 A TW 096122262A TW 96122262 A TW96122262 A TW 96122262A TW 200811306 A TW200811306 A TW 200811306A
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TW
Taiwan
Prior art keywords
substrate
substrate structure
manufacturing
hole
insert
Prior art date
Application number
TW096122262A
Other languages
Chinese (zh)
Inventor
Yusuke Taki
Masaomi Kameyama
Akira Tanaka
Tomoyuki Yasukawa
Masato Suzuki
Hyunjung Lee
Hitoshi Shiku
Tomokazu Matsue
Original Assignee
Nikon Corp
Univ Tohoku
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Publication date
Application filed by Nikon Corp, Univ Tohoku filed Critical Nikon Corp
Publication of TW200811306A publication Critical patent/TW200811306A/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • H01J29/04Cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00Cathode ray tubes; Electron beam tubes
    • H01J31/08Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123Flat display tubes
    • H01J31/125Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
    • H01J31/127Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00Electrodes common to discharge tubes
    • H01J2201/30Cold cathodes
    • H01J2201/304Field emission cathodes
    • H01J2201/30446Field emission cathodes characterised by the emitter material
    • H01J2201/30453Carbon types
    • H01J2201/30469Carbon nanotubes (CNTs)

Abstract

Provided is a substrate structure manufacturing method comprising a first step (S11) of preparing a substrate having at least one fine hole, a second step (S12, S13) of mounting electrodes and immersing the substrate into a dispersing medium containing a plurality of inserts, and a third step (S14) of applying a predetermined voltage to the electrodes.

Description

200811306 九、發明說明: 【名务明所屬射牙領±或】 發明領域 本發明係有關於一種基板結構物及其製造方法、電子 5放出元件及其製造方法、電子源、圖像顯示裝置及層積晶 發明背景 作為奈米技術之核心,碳奈米管(以下,提及1條時亦 1〇 可稱為CNT,提及複數條及集合體時,亦稱為cNTs)正受到 注目。CNTs—般為直徑0.5〜100nm左右,長度1〜i〇〇pm之細 長纖維狀(柱狀)之碳材料。目前正研究CNTs在場發射顯示 器(FED : Field Emission Display)等圖像顯示裝置之電場放 出式電子源之應用。使用CNTs之電場放出式電子源之製造 方法有各種提案,已知有於電極直接使CNTs成長之方法或 附著於另外製造之電極上之方法等。 於電極直接使CNTs成長之方法有如日本專利公告公 報2002-530805號、日本專利公開公報2001-15077號所示, 使用使觸媒附著於電極基板表面之預定位置之化學蒸鏡法 20 (CVD : chemical vapor deposition),使垂直定向之CNTs於 電極成長之方法。又,另外製造之CNTs附著於電極之方法 有如曰本專利公開公報平11 -260249號所記載,使CNTs與導 電膏混合,以網版印刷於電極形成圖形之方法。或者,如 曰本專利公開公報2000-340098號所記載,使CNTs與溶劑或 6 200811306 黏合劑昆合,使用旋轉塗布法等,於電極上形成^^層之 方法等。 然而,在使CNTs直接於電極成長之方法中,定向雖可 、、充但由於CNTs之製造條件為電極基板之性質所限制, 5故有限制可製造之CNTs形狀之可能性,同時,由於電極基 板曝路在高溫之碳析出條件下,故有電極基板之材質惡化 之問題。在使另外製造之CNTs附著於電極之方法中,如 CNTs般奈米級之物質不易均一地與導電膏等流動性物質 混合,故以直接不均一混合之狀態,附著於電極時,因電 10極上之各電子源所含之CNTs之密度非一定,故作為圖像顯 示裝置有形成有斑點之圖像之問題。 亦研究CNTs在可用於電子紙、撓性顯示板、平面面板 顯示器等圖像顯示裝置之透明電極等之導電膜的應用。此 種導電膜如日本專利公開公報2004-346143號所記載,於熱 15 可塑性聚醯亞胺樹脂等樹脂混入CNTs,製造熱可塑性聚醯 亞胺樹脂組成物顆粒,將之以擠壓成型法等,形成厚度 500μηι左右以下(例如ΙΟΟμιη、20μπι等)之薄膜。 然而,於此種樹脂混入CNTs後,成形成膜狀之方法 中,亦如上述,CNTs—部份凝集,而不易均等地混入流動 20 性物質中。因此,有導電性在膜全面不一致之情形,作為 圖像顯示裝置有形成有斑點之圖像之問題。 【發明内容】 發明揭示 是故,本發明之目的係使CNTs或其他微粒子等均質地 200811306 分散配置於基板全體或一部份區域,或者配置於基板中之 任何位置或區域之基板結構物及基板結構物之製造方法。 根據本發明,提供一種基板結構物之製造方法,其具 有:準備具有至少1個細微子之基板之第1步驟、設置電極, 5 並將前述基板浸於含有複數***體之分散介質之第2步 驟、及於前述電極施加預定電壓之第3步驟。 根據本發明,提供一種基板結構物,其係包含有基板 及至少1個***體,該基板係存在至少1個直徑在 5nm〜ΙΟΟμπι之範圍内之孔,同時,厚度在1μιη〜lmm之範圍 10内者,该***體係具有導電性或半導電性之性質並***至 前述孔者。 再者,根據本發明,提供一種基板結構物(例如電子放 出元件),其係藉施加電壓,放出電子,並包含有基板及至 少1個***體,該基板係具有至少丨個細微孔者;該***體 15係作為該基板結構物之電極而***至前述細微孔者。 菖將基板〉文於包含複數***體(例如微粒子)之分散介 質,而賦與電場時,因分散介質與***體之極化率之不同, 產生誘發偶極子力矩,形成於***體兩側之電場強度之差 成為誘發偶極子所影響之力之差,力作用於該***體,該 20***體於此力之方向移動。另一方面,當將具有微細孔之 基板浸於分散介質中,從預定方向同樣地賦與電場時,由 於孔之外側部份與孔之内側部份在電場強度分布產生差, 故可將分散介質中之插人體引導插人至基板之孔中。因 而,藉適當選定基板之孔數、方向、大小(直捏)、深度、位 200811306 置等規格,使用本發明之製造方法,將***體***至該基 板之孔,而可依該基板之規格,製造適當地具有***體之 所期基板結構物。 雖未特定限定,但如後述實施形態所示,於將複數孔 5垂直地排列設置於其基板面之基板之該孔將CNTs、其他導 、 電體作為***體而***,可將該導電體正確地垂直定向於 、 基板内,而可在不損傷電極基板等下,‘輕易製造適合作為 _ FED等之電子源之基板結構物(例如電子放出元件)。雖未特 別限定,但藉使用將複數孔設置成一部份相互交叉連通之 10基板,使用CNTS等之導電體作為***體,可獲得該***體 在基板全面一致地分散配置之基板結構物(例如導電片)。 根據本發明,可獲得使CNTs或其他微粒子等均質地分 散配置於基板全體或一部份區域,或者配置於基板中之任 何位置或區域之基板結構物。 15 圖式簡單說明 ^ 第1圖係顯示本發明實施形態之基板結構物之製造方 法之流程圖。 第2圖係顯示具有本發明實施形態之垂直貫穿孔之基 - 板的挺面圖。 - 2〇 第3圖係顯示***體***至第2圖所示之基板之孔的狀 態之截面圖。 第4圖係顯示具有本發明實施形態之隨機之貫穿孔之 基板的截面圖。 第5圖係顯示***體***至第4圖所示之基板之孔的狀 9 200811306 態之截面圖。 第6圖係顥示具有本發明實施形態之於一定方向傾斜 相交之貫穿孔之基板的截面圖。 第7圖係顯示***體***至第6圖所示之基板之孔的狀 • 5 態之截面圖。 、 第8圖係顯示具有本發明實施形態之隨機之凹陷孔之 、 基板的截面圖。 第9圖係顯示***體***至第8圖所示之基板之孔的狀 參 態之截面圖。 10 第1〇圖係顯示具有本發明實施形態之垂直凹陷孔之基 板的截面圖。 第11圖係顯示***體***至第10圖所示之基板之孔的 狀態之截面圖。 第12圖係顯示本發明實施形態之介電泳裝置之概略 15 者。 Φ 第13圖係顯示本發明實施形態之電場強度分布者。 第14圖係顯示本發明實施形態之金屬SWCNTs之施加 頻率及介電泳力之關係者。 — 第15圖係顯示本發明實施形態之半導體S W C N Ts之施 -20加頻率及介電泳力之關係者。 第16圖係顯示金屬SWCNTs等之導電率及介電常數者。 第17圖係顯示本發明實施形態之FED之概略結構者。 第18圖係顯示使用本發明實施形態之製造方法製造之 基板結構物之截面者(SEM照片)。 10 200811306 第19圖係將第18圖之一部份擴大者。 第20圖係顯示從傾斜方向觀看用於本發明實施形態之 製造方法之基板截面者(SEM照片)。 第21圖係顯示從傾斜方向觀看使用本發明實施形態之 5 製造方法製造之基板結構物之截面者(SEM照片)。 第22圖係將第21圖之一部份擴大者。 用以實施發明之最佳形態 以下,參照圖式,詳細說明本發明實施形態之基板結 10構物之製造方法。第1圖係顯示本發明實施形態之基板結構 物之製造方法之流程圖。 首先,進行準備具有孔之基板(薄膜)之步驟(S11)。此 基板準備步驟具有於薄板狀、片狀或膜狀之母材(無孔之板 狀體)形成孔之步驟。惟,在基板母材不從後面形成孔,使 5用與基板製造同時地形成孔之基板亦可,此時,便不需從 後面形成孔之步驟。基板之母材在此使用絕緣性者,亦可 依用途,使用半導電性者。 此外,半導電性係指在室溫之電傳導率為金屬與絕緣 體中間之1〇6〜l〇-7S/m左右之物質的性質,絕緣性係指小於 半%性物質之電傳導率之物質的性質,後述導電性係指 於半導電性物質之電傳導率之物質的性質。 絕緣性基板之母材可使用聚碳酸酯、特氟隆(註冊商 丁)來對笨一曱酸乙二醇酯等具可撓性之透明樹脂膜。基 板之母材不限於此種具可撓性之透明樹脂薄膜,不具可撓 200811306 ί生亦可非透明亦可,非樹脂亦可。舉例言之,亦可使用 氧化#呂、氧化鎂、氧化鈦、氧化石夕等無機氧化物。主要是 • 基板(基板母材)之材質可依基板結構物之用途等適當選 _ 定。基板(基板母材)之厚度依製造之基板結構物之用途或後 5述之***體大小來選定,可使用1|im〜imm左右者。另,在 、 本案說明書中,可撓性係指即使於基板施加如彎折般之預 定力,亦無損功能,可撓性可以該基板之财彎折性評價。 _ 舉例吕之,宜具有聚碳酸醋、特敦隆(註冊商標)或聚對笨二 甲酸乙一醇酯等以上之高耐彎曲性。 1〇 肖在孔形成步驟使用之基板母材形成複數孔之方法可 依形成孔之直徑或方向,採用各種方法,當形成較小直徑 (直徑50nm左右以下)之孔時,可使用以離子照射或高速中 子照射蝕刻之方法。當使用氧化鋁作為基板母材時,可以 陽極氧化法形成孔。又,當形成較大直徑(直徑5〇nm左右以 15上)時,可使將要形成孔之部份以外之部份遮蔽,浸於預定 • 蝕刻液之方法。此外,隨機地(形成方向不特定)形成複數孔 日守 面旋轉乃至振動基板,一面進行離子照射蚀刻即可。 孔之直徑依要製造之基板結構物之用途、後述***體 • 之大小或材料、分散***體之分散介質等來選定,例如可 „ 20為直徑5nm〜ΙΟΟμιη左右者。此外,形成之孔之截面形狀在 此為圓形,亦可為橢圓形或其他形狀。形成之孔數依要製 造之基板結構物之用途,任意地設定,為丨個以上即可。在 此’孔數為複數(多數)。形成複數孔時之密度(間隔等)亦考 慮要製造之基板結構物之用途及基板母材之強度等,而適 12 200811306 當選定。 要形成之孔可為貫穿基板之貫穿孔,亦可為不貫穿基 板之凹陷孔,孔之種類及深度依要製造之基板結構物之用 途,適當地選定。形成之孔之方向依要製造之基板結構物 5之用途等選定,可相對於基板表面(基板面)實質地垂直,亦 可相對於該基板面傾斜相交。形成複數孔時之各孔之相互 關係可為所有孔為相同方向(即,相互平行),亦可各為不同 方向。此外,亦可藉於基板母材從其一面側形成凹陷孔, 另一面側進行蝕刻等,形成貫穿孔。 1〇 當於相互不同之方向形成複數孔時,亦可於不特定之 方向隨機(無秩序)地形成所有孔,或者,亦可將複數孔分成 複數組,在組内相互平行,在各組間為不同方向。相鄰之 孔間可相互交叉連通,亦可不相互交又連通。此外,交又 連通係指相鄰之各孔相互交叉,在該堯叉部份相互連接。 15 形成之孔亦可非直線狀,亦可全部或一部份彎曲乃至彎折。 具有複數貫穿孔之基板之具體例有如第2圖所示,將所 有孔21形成相對於基板20表面(基板面)垂直相交者,如第4 圖所示,於隨機之方向形成相鄰之孔21相互交叉連通者, 如第6圖所示,相鄰之孔21以規則性地交叉連通之狀態相對 20 於基板面傾斜相交而形成者。又,具有複數凹陷孔之基板 之具體例有如第8圖所示,相鄰之孔21以相互垂直交叉連通 之狀態於隨機之方向形成者,如第10圖所示,將所有孔21 形成相對於基板20之表面(基板面)垂直相交者。 當準備具有孔之基板之步驟結束後,進行將該基板浸 13 200811306 ' 5 於分散有複數***體之分散介質之步驟(S12)。***體使用 具有導電性或半導電性性質之微粒子(奈米微粒子),該微 粒子依要製造之基板結構物之用途等,採用如CNTs之纖維 狀物質或金屬等之金屬微粒子。CNTs可為單層CNTs (SW CNTs)、二層 CNTs (DW CNTs)、三層 CNTs (3WCNTs)、多 層CNTs (MW CNTs)或混合該等者之任一者,亦可為具有金 屬性質之金屬CNTs、具有半導體性質之半導體CNTs之任一 • 者。CNTs之大小為直徑Inm〜數十nm左右,長度Ιμιη左右。 此外,***體可為細胞。***體亦可以高分子樹脂為對象。 10 ***體之大小之上限在與形成於基板之孔之大小關係 上,設定在較該孔小之範圍,***體大小之下限若太小時, 該***體之布朗運動優先,而無法介電泳,故為超過此之 大小。 ***體之材質除了上述者外,可為PbSe、PbTe、HgSe、 15 • HgTe、ZnS、ZnSe、CdS、CdSe、CdTe、CdSkSex、GaAsk Px、InAsi-xPx、Ga^JiixP、Ga^xIrixAs、Gai-Jm、Asi-xPx、 GaN、GaP、GaAs、InP、InAs、Si、Ge、Sii_xGex、BaTi03、 PbZr03、PbxZryTipyC^、BaxSrkTiOs、SrTi03、ZnO、LaMn03、 CaMn03、LakCaxMnC^ 等。 20 分散***體之溶液可使用純水(無離子水)或於純水含 有界面活性劑(例如tween20(商標))預定體積%者。於無離子 水含有tween20之溶液之該tween20之含有量可為2體積%左 右。無離子水含有之界面活性劑亦可使用非離子性界面活 性劑、離子性界面活性劑等。對使複數***體分散於溶液 14 200811306 中之分散介質浸泡基板之方法係使用於基板滴下分散介質 之液滴之方法。惟,亦可使用於收容於預定容器内之分散 介質中***基板後浸泡之方法等。 當將基板浸於分散介質之步驟結束後,進行設置成以 5具有弟12圖所示之結構之介電泳裝置包含的一對電極(上 部電極30、下部電極40),夾持浸於分散介質1〇之基板2〇之 步驟(S13)。電極30、40可使用於玻璃基板31、41表面以物 理蒸鍍法或化學蒸鍍法等蒸鍍金屬氧化膜(例如IT〇 : Indium Tin Oxide) 32、42而成之導電性玻璃。 10 於下部電極40之金屬氧化膜42上將預定位置具開口部 44之絕緣膜43圖案化,基板2〇之下面藉由此絕緣膜43與下 部電極40相對。絕緣膜43之開口部44之位置係對應於以後 述介電泳,將***體***至基板20之孔時,應***基板2〇 之***體之孔存在之區域來設定。此外,在此,說明了進 15行將基板次於分散介質之步驟(S12)後,進行設置電極3〇、 40之步驟(S13) ’亦可於進行電極3〇、4〇之步驟(§13)後,進 行將基板浸於分散介質之步驟(S12)。 接著,進行使弟12圖之交流電極5〇作動,以於兩電極 30、40間施加交流電壓之步驟(S14)。藉於兩電極3〇、牝間 20施加交流電壓,在分散介質忉中之***體,依介電泳之原 理,使力(在此為正介電泳力)作用,而將該***體引導*** 至基板20之孔中。 於兩電極30、40施加之交流電壓之頻率在lkHz〜 100MHz之範圍内,依分散介質之介電常數及***體之介電 15 200811306 1數適§地設定成在正介電泳力作用於分散介質中之插 —此外’亦可藉將頻率設定較高,以使負介電泳力作 ^而將插人至基板2G之孔21内之插人體拔除至該孔21之 。由於施加之頻率之最大值為太高之頻率時’有分散 5介質彿騰之情形,故設定成遠較該沸騰之頻率低之頻率。 ;兩书極30、40施加之交流電壓設定在丨〜丨⑼乂卯之範 知加之电壓南者作用於***體之介電泳力增大,可 使***體對基板孔之***所需之速度加快。惟,由於當電 場強度過高時。因電分解,而產生氣泡,故需設定在不產 10生該氣泡之程度之電壓以下。又,若***體為細胞,當施 加=電壓時,由於有細胞死亡之情形,故***需長時間, 而且在低電壓(例如數微〜數亳Vpp左右)進行。 在此就71笔/永之原理簡單地說明。當在將粒子分散 於溶液之分散介質賦與電場時,因分散介質與粒子之極化 15率之不同,產生誘發偶極子力矩,形成於粒子兩側之電場 強度之差成為誘發偶極子力矩所影響之力之差,力作用於 該粒子,該粒子於此力之方向移動。已知此時作用之介電 泳力fdep可以下式表示。 FDEP=2 7r ^a3Re[(^^/(^2je^]VE2 -(i) 2〇 在式⑴中,3表示粒子之半徑[m],ε表示介電常數 [F/m],附加字p&m分別表示粒子、分散介質。ε係電場 [V/m],Re[f(x)]係僅取出複數f⑷之實數部份之演算子。e 係以 16 200811306 一疋義之複介電常數。σ表示導電率[s/m],〇(=2疋〇表 不角頻率[Hz],f表示施加頻率[Ηζ]。』係虛數單位。式⑴ 如□之内部稱為Clausius-Mossotti因子(cm因子· Κ(ω)) ’表示極化之程度。 ^^H^^)/(£E+2£m)...(3)200811306 IX. DESCRIPTION OF THE INVENTION: [Description of a substrate structure and its manufacturing method, an electronic 5 emission device, a method for manufacturing the same, an electron source, an image display device, and BACKGROUND OF THE INVENTION As a core of the nanotechnology, carbon nanotubes (hereinafter, when one is mentioned, one can also be called CNT, and when a plurality of bars and aggregates are also referred to as cNTs), attention is being paid. The CNTs are generally fine fibrous (columnar) carbon materials having a diameter of about 0.5 to 100 nm and a length of 1 to i pm. The application of CNTs to an electric field discharge type electron source of an image display device such as a field emission display (FED) is currently under study. There are various proposals for a method for producing an electric field discharge type electron source using CNTs, and a method of directly growing CNTs by an electrode or a method of attaching to an electrode manufactured separately is known. The method of directly growing the CNTs by the electrode is as shown in Japanese Patent Publication No. 2002-530805, and Japanese Patent Laid-Open Publication No. 2001-15077, using a chemical vapor microscopy method (CVD: 20) for attaching a catalyst to a predetermined position on the surface of the electrode substrate. Chemical vapor deposition) A method of growing vertically oriented CNTs on an electrode. Further, a method of attaching the separately produced CNTs to the electrode is as described in Japanese Laid-Open Patent Publication No. Hei No. Hei 11-260249, which is a method in which CNTs are mixed with a conductive paste and screen-printed on an electrode to form a pattern. Alternatively, as described in Japanese Laid-Open Patent Publication No. 2000-340098, a method of forming a layer on an electrode by a spin coating method or the like using a CNTs in combination with a solvent or a binder of 6200811306 is used. However, in the method of growing CNTs directly to the electrode, the orientation can be adjusted, but the manufacturing conditions of the CNTs are limited by the properties of the electrode substrate, so there is a possibility of limiting the shape of the CNTs that can be manufactured, and at the same time, due to the electrode Since the substrate exposure is under high temperature carbon deposition conditions, the material of the electrode substrate is deteriorated. In the method of attaching the separately manufactured CNTs to the electrode, the nano-scale material such as CNTs is not easily uniformly mixed with the fluidity substance such as the conductive paste, and therefore, when directly attached to the electrode in a state of being unevenly mixed, the electricity is 10 Since the density of the CNTs contained in each of the electron sources on the pole is not constant, there is a problem that the image display device has an image in which spots are formed. The application of CNTs to conductive films such as transparent electrodes of image display devices such as electronic paper, flexible display panels, and flat panel displays has also been studied. Such a conductive film is described in Japanese Laid-Open Patent Publication No. 2004-346143, and a resin such as a thermoplastic 15 polyimine resin is mixed with CNTs to produce a pellet of a thermoplastic polyimine resin composition, which is extruded or the like. A film having a thickness of about 500 μm or less (for example, ΙΟΟμηη, 20 μm, etc.) is formed. However, in the method of forming a film after the resin is mixed into the CNTs, as described above, the CNTs are partially agglomerated and are not easily mixed into the flowable substance. Therefore, there is a problem that the conductivity is completely inconsistent in the film, and there is a problem that an image is formed as an image display device. SUMMARY OF THE INVENTION The present invention is directed to a substrate structure and a substrate in which CNTs or other fine particles are uniformly disposed in a whole or a part of a substrate, or disposed at any position or region in a substrate. Method of manufacturing a structure. According to the present invention, there is provided a method of manufacturing a substrate structure comprising: a first step of preparing a substrate having at least one fine electrode; and providing an electrode, 5 and immersing the substrate in a dispersion medium containing a plurality of interposers; And a third step of applying a predetermined voltage to the electrode. According to the present invention, there is provided a substrate structure comprising a substrate and at least one interposer, wherein the substrate has at least one hole having a diameter in the range of 5 nm to ΙΟΟμπι, and a thickness in the range of 1 μm to 1 mm. Internally, the insertion system has the property of being conductive or semi-conductive and is inserted into the aforementioned pores. Furthermore, according to the present invention, there is provided a substrate structure (for example, an electron emission element) which emits electrons by applying a voltage, and includes a substrate and at least one interposer having at least one fine hole The insert body 15 is inserted into the fine pores as an electrode of the substrate structure. The substrate is made of a dispersion medium containing a plurality of interposing bodies (for example, fine particles), and when an electric field is applied, an induced dipole moment is generated due to a difference in polarizability between the dispersion medium and the interposer, and is formed on both sides of the interposer. The difference in electric field strength is the difference between the forces that induce the dipole, and the force acts on the insert, which moves in the direction of this force. On the other hand, when the substrate having the fine pores is immersed in the dispersion medium and the electric field is equally applied from a predetermined direction, the distribution of the electric field intensity is poor due to the difference between the outer portion of the pore and the inner portion of the pore. The inserted body in the medium guides the insertion into the hole of the substrate. Therefore, by appropriately selecting the number of holes, the direction, the size (straight pinch), the depth, the bit 200811306, etc. of the substrate, the insert body is inserted into the hole of the substrate by using the manufacturing method of the present invention, and the size of the substrate can be adjusted according to the specifications of the substrate. A substrate structure suitably having an insert body is fabricated. Although not specifically limited, as described in the embodiment below, the CNTs and other conductive bodies are inserted as inserts in the holes in which the plurality of holes 5 are vertically arranged on the substrate surface, and the conductors can be inserted. It is correctly oriented vertically in the substrate, and it is possible to easily manufacture a substrate structure (for example, an electron emission element) suitable as an electron source of _FED or the like without damaging the electrode substrate or the like. Although it is not particularly limited, by using a plurality of substrates in which a plurality of holes are connected to each other, and a conductor such as CNTS is used as an interposer, a substrate structure in which the interposer is uniformly distributed on the substrate can be obtained (for example, Conductive sheet). According to the present invention, it is possible to obtain a substrate structure in which CNTs or other fine particles are uniformly dispersed in the entire substrate or a part of the region, or at any position or region in the substrate. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of manufacturing a substrate structure according to an embodiment of the present invention. Fig. 2 is a front elevational view showing a base-plate having a vertical through hole according to an embodiment of the present invention. - 2〇 Fig. 3 is a cross-sectional view showing a state in which the insert body is inserted into the hole of the substrate shown in Fig. 2. Fig. 4 is a cross-sectional view showing a substrate having a random through-hole according to an embodiment of the present invention. Fig. 5 is a cross-sectional view showing the state of the insertion hole inserted into the hole of the substrate shown in Fig. 4 in the state of 200811306. Fig. 6 is a cross-sectional view showing a substrate having through-holes obliquely intersecting in a certain direction in the embodiment of the present invention. Fig. 7 is a cross-sectional view showing the state in which the interposer is inserted into the hole of the substrate shown in Fig. 6. Fig. 8 is a cross-sectional view showing a substrate having a random recessed hole in the embodiment of the present invention. Fig. 9 is a cross-sectional view showing the state in which the insert body is inserted into the hole of the substrate shown in Fig. 8. 10 is a cross-sectional view showing a substrate having a vertical recessed hole in the embodiment of the present invention. Fig. 11 is a cross-sectional view showing a state in which the insertion body is inserted into the hole of the substrate shown in Fig. 10. Fig. 12 is a view showing the outline of a dielectrophoresis apparatus according to an embodiment of the present invention. Φ Fig. 13 shows an electric field intensity distribution of an embodiment of the present invention. Fig. 14 is a view showing the relationship between the application frequency and the dielectrophoretic force of the metal SWCNTs of the embodiment of the present invention. — Fig. 15 is a view showing the relationship between the frequency of the semiconductor S W C N Ts and the dielectrophoretic force of the embodiment of the present invention. Fig. 16 shows the conductivity and dielectric constant of metal SWCNTs and the like. Fig. 17 is a view showing a schematic configuration of an FED according to an embodiment of the present invention. Fig. 18 is a view showing a cross section (SEM photograph) of a substrate structure produced by the production method of the embodiment of the present invention. 10 200811306 Figure 19 is an enlargement of one of the 18th figures. Fig. 20 is a view showing a substrate cross section (SEM photograph) for the manufacturing method of the embodiment of the present invention viewed from an oblique direction. Fig. 21 is a view showing a cross section (SEM photograph) of a substrate structure produced by the manufacturing method of the embodiment 5 of the present invention viewed from an oblique direction. Figure 22 is a partial enlargement of Figure 21. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a method of manufacturing a substrate structure 10 according to an embodiment of the present invention will be described in detail with reference to the drawings. Fig. 1 is a flow chart showing a method of manufacturing a substrate structure according to an embodiment of the present invention. First, a step (S11) of preparing a substrate (film) having a hole is performed. This substrate preparation step has a step of forming a hole in a thin plate-like, sheet-like or film-shaped base material (a non-porous plate-like body). However, the substrate base material is not formed with a hole from the rear side, and the substrate may be formed by forming a hole simultaneously with the substrate production. In this case, the step of forming a hole from the rear side is not required. The base material of the substrate is insulated here, and semiconducting properties may be used depending on the application. In addition, semi-conductivity refers to the property that the electrical conductivity at room temperature is about 1 to 6 〇 -7 S/m between the metal and the insulator, and the insulation refers to the electrical conductivity of less than half of the substance. The nature of the substance, the conductivity described later, refers to the nature of the substance of the electrical conductivity of the semiconducting substance. As the base material of the insulating substrate, polycarbonate or Teflon (registered quotient) can be used for a flexible transparent resin film such as stearic acid ethylene glycol ester. The base material of the substrate is not limited to such a flexible transparent resin film, and it is not flexible. It can also be opaque or non-resin. For example, an inorganic oxide such as oxidized #吕, magnesium oxide, titanium oxide or oxidized stone may also be used. Mainly • The material of the substrate (substrate base material) can be appropriately selected depending on the use of the substrate structure. The thickness of the substrate (substrate base material) is selected depending on the use of the substrate structure to be manufactured or the size of the insert described in the following, and it is possible to use about 1|im~imm. Further, in the specification of the present invention, the flexibility means that even if a predetermined force such as bending is applied to the substrate, the flexibility is not lost, and the flexibility can be evaluated by the financial bending property of the substrate. _ For example, it is preferable to have high bending resistance such as polycarbonate, Tetonlong (registered trademark) or poly(p-butylene glycolate). 1. The method of forming a plurality of holes in the substrate base material used in the hole forming step may be performed by various methods according to the diameter or direction of the formed holes, and when forming a hole having a small diameter (about 50 nm or less in diameter), ion irradiation may be used. Or high-speed neutron irradiation etching method. When alumina is used as the substrate base material, pores can be formed by anodization. Further, when a large diameter (about 5 〇 nm to 15 Å) is formed, a portion other than the portion where the hole is to be formed can be shielded from the predetermined etching liquid. Further, a plurality of holes are formed randomly (the formation direction is not specified), and the surface of the surface is rotated or even the substrate is irradiated, and ion irradiation etching is performed. The diameter of the hole is selected depending on the use of the substrate structure to be manufactured, the size or material of the insert, the dispersion medium of the dispersion insert, and the like, and may be, for example, a diameter of 5 nm to ΙΟΟμηη. The cross-sectional shape is circular here, and may be elliptical or other shapes. The number of holes to be formed may be arbitrarily set depending on the use of the substrate structure to be manufactured, and may be plural or more. Here, the number of holes is plural ( Most of them. The density (interval, etc.) when forming a plurality of holes is also considered in consideration of the use of the substrate structure to be manufactured and the strength of the substrate base material, etc., and is selected in the case of 2008-11306. The hole to be formed may be a through hole penetrating the substrate. It may be a recessed hole that does not penetrate the substrate, and the type and depth of the hole are appropriately selected depending on the use of the substrate structure to be manufactured. The direction of the formed hole depends on the use of the substrate structure 5 to be manufactured, etc., and can be selected. The substrate surface (substrate surface) is substantially perpendicular or obliquely intersected with respect to the substrate surface. The mutual relationship of the holes when forming the plurality of holes may be the same direction for all the holes (ie, In addition, the substrate base material may be formed with a recessed hole from one side thereof, and the other side may be etched or the like to form a through hole. In the case of holes, all the holes may be formed randomly (unordered) in an unspecified direction, or the plural holes may be divided into multiple arrays, which are parallel to each other in the group, and have different directions between the groups. In addition, the cross-connecting means that the adjacent holes intersect each other and are connected to each other at the crotch portion. 15 The holes formed may also be non-linear, or all or one Partially curved or even bent. Specific examples of the substrate having a plurality of through holes are as shown in Fig. 2, and all the holes 21 are formed to intersect perpendicularly with respect to the surface (substrate surface) of the substrate 20, as shown in Fig. 4, at random The direction in which the adjacent holes 21 intersect with each other is formed, and as shown in Fig. 6, the adjacent holes 21 are formed by regularly intersecting with each other in a state of being regularly intersecting with each other. A specific example of the substrate is as shown in Fig. 8. The adjacent holes 21 are formed in a random direction in a state of being vertically intersecting with each other. As shown in Fig. 10, all the holes 21 are formed with respect to the surface of the substrate 20 ( The substrate surface is perpendicularly intersected. After the step of preparing the substrate having the hole is completed, the substrate is immersed in a step (S12) in which the dispersion medium of the plurality of interposers is dispersed. The interposer is electrically conductive or semi-conductive. Microparticles (nanofine particles) of conductive nature, such as fibrous materials such as CNTs or metal fine particles such as metals, depending on the use of the substrate structure to be fabricated, etc. The CNTs may be single-layered CNTs (SW CNTs), Any of the CNTs (DW CNTs), the three CNTs (3WCNTs), the multi-layer CNTs (MW CNTs), or the like, may be any of metal CNTs having metallic properties and semiconductor CNTs having semiconductor properties. By. The size of the CNTs is about Inm to several tens of nm in diameter and about Ιμιη in length. Furthermore, the insert can be a cell. The insert may also be a polymer resin. 10 The upper limit of the size of the insertion body is set to be smaller than the size of the hole formed in the substrate, and if the lower limit of the size of the insertion body is too small, the Brownian motion of the insertion body takes precedence and cannot be dielectrophoresis. Therefore, it is more than this size. In addition to the above, the material of the insert may be PbSe, PbTe, HgSe, 15 • HgTe, ZnS, ZnSe, CdS, CdSe, CdTe, CdSkSex, GaAsk Px, InAsi-xPx, Ga^JiixP, Ga^xIrixAs, Gai- Jm, Asi-xPx, GaN, GaP, GaAs, InP, InAs, Si, Ge, Sii_xGex, BaTi03, PbZr03, PbxZryTipyC^, BaxSrkTiOs, SrTi03, ZnO, LaMn03, CaMn03, LakCaxMnC^, and the like. The solution of the dispersion insert may be pure water (no ionized water) or a predetermined volume% of a surfactant (e.g., tween 20 (trademark)) in pure water. The content of the tween 20 in the solution containing tween 20 in the ion-free water may be about 2% by volume. As the surfactant contained in the ion-free water, a nonionic surfactant, an ionic surfactant or the like can also be used. The method of immersing a substrate in a dispersion medium in which a plurality of intercalating bodies are dispersed in a solution 14 200811306 is a method of dropping a droplet of a dispersion medium onto a substrate. However, it is also possible to use a method of immersing a substrate in a dispersion medium accommodated in a predetermined container, and soaking it. After the step of immersing the substrate in the dispersion medium is completed, a pair of electrodes (upper electrode 30, lower electrode 40) included in the dielectrophoresis device having the structure shown in FIG. The step of the substrate 2 of the medium 1 (S13). The electrodes 30 and 40 can be used as a conductive glass obtained by vapor-depositing metal oxide films (for example, IT〇: Indium Tin Oxide) 32 and 42 on the surfaces of the glass substrates 31 and 41 by a physical vapor deposition method or a chemical vapor deposition method. The insulating film 43 having the opening portion 44 at a predetermined position is patterned on the metal oxide film 42 of the lower electrode 40, and the lower surface of the substrate 2 is opposed to the lower electrode 40 by the insulating film 43. The position of the opening portion 44 of the insulating film 43 corresponds to the later-described dielectrophoresis, and when the interposer is inserted into the hole of the substrate 20, it is set to be inserted in the region where the hole of the interposer of the substrate 2 is present. In addition, here, the step (S13) of setting the electrodes 3A, 40 after the step of substituting the substrate to the dispersion medium (S12) is performed, and the steps of performing the electrodes 3〇, 4〇 may be performed (§ After 13), the step of immersing the substrate in the dispersion medium is carried out (S12). Next, a step of applying an alternating current voltage to the alternating current electrode 5 of the drawing 12 to apply an alternating voltage between the electrodes 30 and 40 is performed (S14). By applying an alternating voltage between the two electrodes 3〇 and the inter-turn 20, the insert in the dispersion medium is subjected to a force (here, a positive dielectrophoretic force) according to the principle of dielectrophoresis, and the insert is guided into the insertion body. In the hole of the substrate 20. The frequency of the alternating voltage applied to the two electrodes 30, 40 is in the range of 1 kHz to 100 MHz, and is set according to the dielectric constant of the dispersion medium and the dielectric of the interposer 15 200811306 1 . Insertion in the medium - in addition, the insertion of the human body inserted into the hole 21 of the substrate 2G can be removed to the hole 21 by setting the frequency higher so that the negative dielectrophoretic force is made. Since the maximum value of the applied frequency is too high, the frequency of the dispersion medium is set to be lower than the frequency of the boiling. The alternating voltage applied by the two books 30, 40 is set in the voltage of 丨~丨(9)乂卯. The voltage applied to the insert increases the dielectrophoretic force of the insert, and the insertion speed of the insert into the substrate hole is required. accelerate. However, because the electric field strength is too high. Since bubbles are generated by electrolysis, it is necessary to set the voltage below the level at which the bubbles are not produced. Further, when the insert is a cell, when a voltage is applied, since the cell is dead, the insertion takes a long time and is performed at a low voltage (for example, a few micro-number 亳Vpp or so). Here, the principle of 71 pens / eternal is simply explained. When an electric field is applied to a dispersion medium in which particles are dispersed in a solution, an induced dipole moment is generated due to a difference in polarization ratio between the dispersion medium and the particles, and a difference in electric field strength formed on both sides of the particles becomes an induced dipole moment. The difference in the force of influence, the force acts on the particle, which moves in the direction of this force. It is known that the dielectric swimming force fdep at this time can be expressed by the following formula. FDEP=2 7r ^a3Re[(^^/(^2je^]VE2 -(i) 2〇 In the formula (1), 3 represents the radius of the particle [m], ε represents the dielectric constant [F/m], additional words p&m denotes particles and dispersion medium respectively. The ε-type electric field [V/m], Re[f(x)] is the operator that only takes the real part of the complex number f(4). The e-system is 16 200811306. σ represents the conductivity [s/m], 〇 (=2疋〇 indicates the angular frequency [Hz], and f represents the applied frequency [Ηζ].” is an imaginary unit. Equation (1) If the interior of the □ is called the Clausius-Mossotti factor (cm factor·Κ(ω)) ' indicates the degree of polarization. ^^H^^)/(£E+2£m)...(3)

從式(2)、式(3)可知,此CM因子依據分散介質及粒子 之^免率、介電常數甚至是施加之頻率,而取-0.5〜ι·0之 值。從式⑴可知,介電泳力之方向與CM因子有關。即, CM因子之貫部為正時,介電泳力㈣正,料粒子之正介 私永作用於電場強度大者,若為負時,則介電泳力為負, 引導粒子之負介電泳力作用於電場強度弱者。 而根據本案發明人等之研究結果可明瞭當將具微細孔 =基板浸於分散介質中,同樣輯與電場時,在孔之外侧 部份舆孔之内側部份,電㈣度分布產生差。第13圖顯示 5本案發明人等執行之有限要件模擬之電場強度分布之結 果在同圖中,20係基板,21係存在於該基板之孔,1〇、 忉係分散介質。雖省略圖式,但電極3〇、4〇分別位於分散 介質10、10之外侧(上下)。 第13圖係於電極間施加直流電壓(1〇v)之模擬結果,若 20為施加交流電壓時,亦顯示相同之電場強度分布。同圖顯 示在基板20之孔21内部(以號碼11顯示)電場強度強,在該孔 21之外部(以號碼12顯示)之分散介質中,電場強度較孔以 之内部弱。並顯示在孔21之開口部附近(以號碼13顯示),與 孔21内部同樣地,電場強度強,孔21與相鄰之孔21間之部 17 200811306 份(以號碼14顯示),電場強度較該孔21之外部(以號碼12顯 示)更弱。 如此,由於基板20之孔21之内部電場強度較孔21之外 侧之分散介質中強,故可理解藉使正介電泳力作用,可將 5分散至分散介質中之***體(粒子)引導***至基板20之孔 21内部。 第14圖係顯示模擬使用金屬為介電泳之粒 子,使用含有tween20之純水作為分散介質時之介電泳力(縱 軸)與頻率(橫軸)之關係的結果者。分散介質使用於純水含 10有2體積%加咖20者及於純水含有0.2體積%tween20者,前 者以點鏈線顯示,後者以實線顯示。從第14圖可知,若為 金屬SWCNTs,不管施加之頻率,平常產生正介電泳力。從 第14圖可理解,若為1 〇5Hz〜106Hz (100kHz〜1 MHz)左右以下 時’正介電泳力大。結果,雖為金屬SWCNTs,在金等金屬 15粒子亦形成相同之傾向。一般為金屬時,宜施加100kHz〜 1MHz左右以下之頻率。 第15圖係顯示模擬使用半導體swCNTs作為介電泳之 粒子,使用含有tween20之純水作為分散介質時之介電泳力 (縱軸)與頻率(橫軸)之關係的結果者。分散介質使用於純水 ° s有2體積%tween20者及於純水含有〇·2體積%tween20者, 前者以點線顯示,後者以實線顯示。此外,在第15圖中, 於右上部伤顯示者係將頻率1〇5〜l〇8Hz之部份擴大顯示者。 從第15圖可理解,若為半導體SWCNTs,在1〇6Hz〜 1〇7Hz (1MHz〜10MHz)左右以下之頻率時,產生正介電泳 18 200811306 力,在1MHz〜10MHz左右以上之頻率時,產生負介電泳力。 結果,雖為半導體SWCNTs,在其他之半導體粒子亦形成相. 同之傾向。若將***體***至基板之孔時,從第15圖可知 若為104Hz〜105Hz(10kHz〜100kHz)左右以下之頻率時,由於 5 正介電泳力大,故若為半導體時,宜施加10kHz〜l〇〇kHz左 、 右以下之頻率。此外,當將半導體從基板之孔拔除時,可 理解為使負介電泳力作用,施加1〇6Ήζ(1ΜΗζ)左右以上之頻 ⑩ 率即可。 此外,於第16圖顯示金屬SWCNTs、半導體SWCNTs、 10於純水含有0·2體積%itween20之分散介質及於純水含有2 體積%之分散介質之導電率、介電常數。 在第1圖之S14,於兩電極30、40間開始交流電壓之施 加後,判斷是否經過預定時間(S15),當未經過預定時間時, 繼續父流電壓之施加,若經過預定時間,則停止電壓之施 15加。電壓之施加時間一例為5〜12分左右。 • 當交流電壓之施加結束時,進行卸除電極30、40之步 驟(S16),後處理係進行洗淨步驟⑻7)。在洗淨步驟中,使 _於介電泳之分散介質(插人體未分散者),洗掉附著於基 板表面之***體。右洗淨步驟非必要時,亦可省略。之後, • Μ進行加熱冷卻步驟(S18),結束—連串之處理。加熱冷卻步 驟係為使用金等金屬粒子作為***體時,使***基板之孔 7之金屬粒子加熱熔融而相互—體化,同時,將***體固 疋於孔内而進行。若加熱冷卻步驟非必要時,亦可省略。 此時,依需要,進行使卸除電極後或洗.淨後之基板自然乾 19 200811306 燥之乾燥步驟。 如參照第13圖所說明,由於基板之孔之開口部附近、 亦即孔之内壁與基板面(表面)之交叉部份附近與孔之内部 同樣地,電場強度較強,故有***體(粒子)停留於該孔之開 5 口部附近,成為***體進入孔内部之阻礙之虞。為因應此 問題’宜呈使基板之孔之直徑在基板表面附近(開口部附近) 較基板内部大之形狀(圓弧狀、倒角狀等圓滑形狀)。藉呈此 種圓滑形狀,***體在開口部附近停留之情形減少,可使 ***體完全進入填充至孔内部。使此種孔之開口部附近大 10之开7狀之加工方法係於基板形成孔後,使用預定之钱刻 液,進行蝕刻即可。舉例言之,使用氧化鋁作為基板時, 藉使用鹼性之蝕刻溶液,可溶解孔之開口部附近,經過適 當之時間後洗淨,可呈所期之形狀。 [導電性透明膜之製造] 15 接著,就使用上述基板結構物之製造方法,製造導電 膜之情形作說明。在此,基板(母材)係使用聚碳酸酯、聚對 苯一甲酸乙二醇酯等具可撓性之透明樹脂膜,如第4圖所 不,以均等之密度隨機地(無秩序)形成複數貫穿孔。惟,雖 說無秩序,仍以與貫穿孔之直徑之關係設定形成密度,相 20鄰乃至位於附近之各貫穿孔適當地相互交叉連通。 ***體在此使用纖維將物質2CNTs。惟,亦可使用金 屬粒子。在此使用之CNTs可為swCNTs、DWCNTs、 3WCNTS、MWCNTS、該等之混合物之任一者,以含有多數 金屬性CNTs為佳。 20 200811306 分散介質可使用純水、非離子性界面活性劑水溶液、 離子性界面活性劑水溶液、含有tWeen20之水溶液等有機溶 媒之任一者。將第4圖之基板根據第1圖之流程圖設置於第 12圖之介電泳裝置,於電極間施M1〇〇kHz〜1MHz之頻率範 5圍之高頻時,正介電泳力作用於分散於分散介質中之 CNTs ’ CNTs於貫穿孔中移動。貫穿孔之直徑設定在 10〜500nm左右之範圍内即可。當於!個貫穿孔内僅***;[條 CNTs日寸’將貫穿孔之直徑設定在i〇nm〜i〇〇nrn之範圍即 可。與此相反地,將複數條CNTs***1個貫穿孔時,貫穿 10 孔之直徑在lOOnm以上即可。 如此進行而製造之導電膜如第5圖所示,cNTs22不致 明顯地凝集於基板20内之局部區域,而是以均等之密度分 散在基板20所有區域。由於各貫穿孔21相互連接,故*** 之CNTs相互接觸導通。因而,基板全體具有導電性。若調 15整貫穿孔之直徑及貫穿孔之形成密度,亦可調整要製造之 導電膜之導電率,而可獲得具所期導電率之導電膜。此外, 當要積極地凝集於基板2〇内之局部區域時,藉使貫穿孔21 之直後及形成密度依此局部地變化,亦可獲得導電率局部 不同之導電膜。 20 此外,在此,使用具如第4圖所示無秩序地存在之貫穿 ^之基板,亦可使用具如第6圖所示以預定傾向形成之貫 牙孔21之基板20,藉此,如第7圖所示,可獲得於貫穿孔u 内***CNTS22之導電膜。又,藉使用第2圖所示具相對於 基板20實質地垂直相交之貫穿孔21之基板2〇,可如第3圖所 21 200811306 不’獲得於各貫穿孔21内分別***有CNTs22之導電膜,此 導電膜成為於相對於基板面垂直相交之方向具導電性,·在 沿基板面之方向不具導電性之定向導電膜。 又,形成於基板之孔不限於貫穿孔,而如第8圖所示, 5亦可使用於基板20之表面形成預定深度之凹陷孔21者,此 時,如第9圖所示,可獲得僅於基板表面層具導電性之導電 膜0 如此,可使用本實施形態之基板結構物之製造方法, 製造導電膜,藉適當地變更調整形成於基板之孔之規格 1〇等,可易製造具所期性能之導電膜。如此進行製造並具可 撓性之透明導電膜可作為電子紙、撓性顯示器、平面面板 顯不器等之透明電極來使用。此外,基板在此使用具可撓 性之透明膜,亦可不具可撓性,亦可為非透明。又,在上 述例中,例示了於基板全體均一具導電性之導電膜,亦可 15獲得僅於膜内之單一或複數局部區域均一地具導電性之導 電膜。 [FED之電子源之製造] 接著’就使用上述基板結構物之製造方法,製造FED(場 發射顯示益)之電子源(電場放出陣列)之情形作說明。在 20此,基板(母材)使用氧化鋁等無機氧化物基板,如第2圖所 示,使用貫穿孔相對於基板面實質垂直地以等間隔形成之 基板。貫穿孔之直徑及貫穿孔間之間隔在用於FED時,依 亮度及精細度調整即可。 ***體在此使用纖維狀物質之CNTs。在此使用之CNTs 22 200811306 可為SWCNTs、DWCNTs、3WCNTs、MWCNTs、該等之混 合物之任一者,為使面内之電子放出密度一定,宜使用特 定之石墨片數一致之CNTs。 ' 分散介質可使用純水、非離子性界面活性劑、離子性 • 5 界面活性劑水溶液、含有tween20之水溶液等有機溶媒之任 一者。將此基板根據第1圖之流程圖設置於第12圖之介電泳 裝置,於電極間施加100kHz〜1MHz之頻率範圍之高頻時, 正介電泳力作用於分散於分散介質中之CNTs,CNTs於貫穿 參 孔中移動。貫穿孔之直控設定在10〜500nm左右之範圍内即 10 可。當於1個貫穿孔内僅***1條CNTs時,將貫穿孔之直徑 設定在10nm〜lOOnm之範圍即可。與此相反地,將複數條 CNTs***1個貫穿孔時,貫穿孔之直徑在100nm以上即可。 如此進行製造之基板結構物(電子放出元件)如第3圖所 示,CNTs 22不致不均地存在於基板20内之局部區域,而是 15 以均等之間隔在基板全區域垂直定向。此外,電子放出元 件以作為***體之CNTslll從基板表面(上面、下面)突出者 胃 較佳。如此使***體突出時,將CNTs***至基板之貫穿 孔後,以鹼性溶液等蝕刻,將基板表面僅去除預定量即可。 如此,可使用本實施形態之基板結構物之製造方法, 20製造FED之電子放出元件,藉適當地變更調整形成於基板 之孔之直徑或排列間隔等,可易製造具所期性能之電子放 出元件。 弟17圖係將具使用上述製造方法而製造之電子放出元 件之FED主要部份擴大者。在此圖中’ 1 〇〇係發射極基板(發 23 200811306 射極電極),在發射極基板100上,將使用上述製造方法製 造並於基板貫穿孔***CNTs之多數電子放出元件110配置 成矩陣狀。該等電子放出元件11〇在發射極基板1〇〇上之固 定可藉使用導電膏來貼合而進行。於發射極基板1〇〇之配置 5電子放出元件110之部份之間的部份形成絕緣層120,於絕 緣層120上設置閘極電極130。 以與發射極基板100相對之狀態,藉由間隔件以預定間 隔,設置正極基板140。正極基板14〇為由ITO等構成之透明 電極,於其表面(内面)之相對於電子放出元件11〇之部份形 10成螢光體層(RGB螢光體)141。發射極基板1〇〇與正極基板 140間之部份呈真空狀態。藉直流電源15〇,於發送射極基 板100與正極基板140間施加直流電壓時,從電子放出元件 110放出電子,撞擊螢光體層141,使螢光體激發發光,而 可顯示。 15 使用本實施形態之基板結構物之製造方法而製造之電 子放出元件在CNTs不致不均地存在於基板内,而均等地分 散配置’同時,相對於基板面垂直定向,故採用作為FED 之電子放出元件時,可實現極為良好之電子放出特性,亮 度或精細度無偏差,而可獲得具極為良好之顯示性能之 2〇 FED。由於使CNTs之石墨片數一致,故藉此,亦可使亮度 或壽命大致一定。 [層積晶片] 近來’作為將LSI層積化之技術諸如SiP (system in package)等受到注目。siP係將包含記憶體、CPU、其他電 24 200811306 路荨之複數LSI (晶片)層和成二維,封裝成1個封包之裝置 (層積晶片)。然而,由於層間之連接使用打線接合,故不易 焉速化,且配線之條數亦受限,有不易薄型化之課題為實 際情形。 5 可應用本實施形恶之基板結構物之製造方法,將声積It can be seen from the formulas (2) and (3) that the CM factor takes a value of -0.5 to ι·0 depending on the dispersion medium and the particle repellency, the dielectric constant, and even the frequency of application. It can be seen from the formula (1) that the direction of the dielectrophoretic force is related to the CM factor. That is, when the CM factor is positive, the dielectrophoretic force (four) is positive, and the positive particles of the material particles always act on the electric field strength. If it is negative, the dielectrophoretic force is negative, and the negative dielectrophoretic force of the particles is guided. Acting on weak electric field strength. According to the findings of the inventors of the present invention, it is understood that when the micropores = substrate are immersed in the dispersion medium, and the electric field is also applied, the electric (four) degree distribution is poor in the inner portion of the pupil outside the hole. Fig. 13 shows the results of the electric field intensity distribution of the finite element simulation performed by the inventors of the present invention. In the same figure, the 20-series substrate and the 21-series are present in the hole of the substrate, and the 〇-type dispersion medium. Although the drawings are omitted, the electrodes 3A and 4〇 are located on the outer sides (upper and lower sides) of the dispersion media 10 and 10, respectively. Figure 13 is a simulation result of applying a DC voltage (1 〇 v) between electrodes. If 20 is an applied AC voltage, the same electric field intensity distribution is also shown. The same figure shows that the electric field intensity is strong inside the hole 21 of the substrate 20 (shown by the numeral 11), and the electric field intensity is weaker than the inside of the hole in the dispersion medium outside the hole 21 (shown by the numeral 12). It is displayed in the vicinity of the opening of the hole 21 (shown by the numeral 13). Similarly to the inside of the hole 21, the electric field intensity is strong, and the portion between the hole 21 and the adjacent hole 21 is 200811306 parts (shown by the number 14), electric field strength. It is weaker than the outside of the hole 21 (shown by the number 12). Thus, since the internal electric field strength of the hole 21 of the substrate 20 is stronger than that of the dispersion medium on the outer side of the hole 21, it can be understood that the insertion body (particle) which is dispersed into the dispersion medium can be guided by the positive dielectrophoretic force. To the inside of the hole 21 of the substrate 20. Fig. 14 is a graph showing the results of simulating the relationship between the dielectrophoretic force (vertical axis) and the frequency (horizontal axis) when a metal using dielectrophoresis is used as a medium for dielectrophoresis. The dispersion medium is used in a pure water containing 10% by volume plus a coffee 20 and in pure water containing 0.2% by weight of tween20, the former being shown by a dotted line and the latter by a solid line. As can be seen from Fig. 14, in the case of metal SWCNTs, a positive dielectrophoretic force is usually generated regardless of the frequency of application. As can be understood from Fig. 14, the positive dielectrophoretic force is large if it is about 1 〇 5 Hz to 106 Hz (100 kHz to 1 MHz) or less. As a result, although metal SWCNTs are formed, the metal 15 particles such as gold tend to be the same. When it is generally metal, it is preferable to apply a frequency of about 100 kHz to 1 MHz or less. Fig. 15 is a graph showing the results of simulating the relationship between the dielectrophoretic force (vertical axis) and the frequency (horizontal axis) when using semiconductor swCNTs as a dielectrophoresis particle and using pure water containing tween20 as a dispersion medium. The dispersion medium is used in pure water ° s with 2 vol% tween 20 and in pure water containing 〇 2 vol% tween 20, the former is shown by dotted lines, the latter is shown by solid lines. In addition, in Fig. 15, the person who shows the upper right injury shows that the frequency is 1〇5~l〇8Hz. As can be understood from Fig. 15, in the case of semiconductor SWCNTs, a positive dielectrophoresis 18 200811306 force is generated at a frequency of about 1 〇 6 Hz to 1 〇 7 Hz (1 MHz to 10 MHz), and a frequency of about 1 MHz to 10 MHz or more is generated. Negative dielectrophoretic force. As a result, although semiconductor SWCNTs are formed, the other semiconductor particles are also formed with the same tendency. When inserting the insert into the hole of the substrate, it can be seen from Fig. 15 that the frequency of the positive and negative dielectrophoresis is large at a frequency of about 104 Hz to 105 Hz (10 kHz to 100 kHz). Therefore, if it is a semiconductor, it is preferable to apply 10 kHz. l〇〇kHz left and right frequencies below. Further, when the semiconductor is removed from the hole of the substrate, it can be understood that the negative dielectrophoretic force acts, and a frequency of about 1 〇 6 Ήζ (1 ΜΗζ) or more is applied. Further, in Fig. 16, the conductivity and dielectric constant of the metal SWCNTs, the semiconductor SWCNTs, 10, the dispersion medium containing 0.2% by volume of itween 20 in pure water, and the dispersion medium containing 2% by volume in pure water are shown. In S14 of Fig. 1, after the application of the alternating voltage is started between the electrodes 30, 40, it is judged whether or not a predetermined time has elapsed (S15), and when the predetermined time has not elapsed, the application of the parental voltage is continued, and if a predetermined time elapses, Stop the voltage application 15 plus. An example of the application time of the voltage is about 5 to 12 minutes. • When the application of the AC voltage is completed, the step of removing the electrodes 30, 40 is performed (S16), and the post-processing is performed by the cleaning step (8) 7). In the washing step, the dispersion medium adhered to the surface of the substrate is washed off by a dispersion medium (not inserted into the human body). The right washing step may be omitted if not necessary. After that, • 加热 performs the heating and cooling step (S18), and ends the series of processes. In the heating and cooling step, when metal particles such as gold are used as the interposer, the metal particles of the holes 7 inserted into the substrate are heated and melted to be mutually melted, and the intercalating body is fixed in the holes. If the heating and cooling step is not necessary, it may be omitted. At this time, if necessary, the substrate is dried after the electrode is removed or after the cleaning, and the drying step is dried. As described with reference to Fig. 13, the vicinity of the opening of the hole of the substrate, that is, the vicinity of the intersection of the inner wall of the hole and the surface of the substrate (surface) is the same as the inside of the hole, and the electric field strength is strong, so that there is an insertion body ( The particles) stay near the opening 5 of the hole and become a hindrance to the insertion of the insert into the interior of the hole. In order to cope with this problem, it is preferable that the diameter of the hole of the substrate is larger (in the vicinity of the opening) than the inside of the substrate (a round shape such as an arc shape or a chamfer shape). By virtue of such a rounded shape, the insertion of the insert near the opening is reduced, and the insert can be completely filled into the inside of the hole. The method of processing the opening of the hole in the vicinity of the opening portion of the hole is formed by forming a hole in the substrate, and then etching is performed using a predetermined amount of the etching liquid. For example, when alumina is used as the substrate, an alkaline etching solution can be used to dissolve the vicinity of the opening of the hole, and after a suitable period of time, it can be washed to have a desired shape. [Production of Conductive Transparent Film] Next, a case where a conductive film is produced by using the above-described method for producing a substrate structure will be described. Here, as the substrate (base material), a flexible transparent resin film such as polycarbonate or polyethylene terephthalate is used, and as shown in FIG. 4, it is randomly (unordered) at an equal density. Multiple through holes. However, even though it is disordered, the density is set in relation to the diameter of the through hole, and the through holes of the phase 20 or even the vicinity are appropriately cross-connected with each other. The insert here uses fibers to bind the substance 2CNTs. However, metal particles can also be used. The CNTs used herein may be any of swCNTs, DWCNTs, 3WCNTS, MWCNTS, and the like, and it is preferred to contain a plurality of metallic CNTs. 20 200811306 Any one of organic solvents such as pure water, a nonionic surfactant aqueous solution, an ionic surfactant aqueous solution, and an aqueous solution containing tWeen20 can be used as the dispersion medium. The substrate of FIG. 4 is placed in the dielectrophoresis apparatus of FIG. 12 according to the flow chart of FIG. 1 , and the positive dielectrophoretic force acts on the high frequency range of the frequency range of M1 〇〇 kHz to 1 MHz between the electrodes. The CNTs 'CNTs dispersed in the dispersion medium move in the through holes. The diameter of the through hole may be set in the range of about 10 to 500 nm. When! Insert only in the through hole; [stripe CNTs] can set the diameter of the through hole to the range of i〇nm~i〇〇nrn. On the contrary, when a plurality of CNTs are inserted into one through hole, the diameter of the through hole 10 may be 100 nm or more. The conductive film produced in this manner is as shown in Fig. 5, and the cNTs 22 are not significantly agglomerated in a partial region in the substrate 20, but are dispersed in all regions of the substrate 20 at an equal density. Since the through holes 21 are connected to each other, the inserted CNTs are in contact with each other. Therefore, the entire substrate has electrical conductivity. If the diameter of the through hole and the formation density of the through hole are adjusted, the conductivity of the conductive film to be manufactured can be adjusted to obtain a conductive film having a desired electrical conductivity. Further, when a local region in the substrate 2 is actively agglomerated, the conductive film having a different conductivity may be obtained by locally changing the formation and density of the through hole 21 in this manner. Further, here, a substrate 20 having a through-hole 21 having a predetermined tendency as shown in Fig. 6 may be used, using a substrate having a through-hole which exists in an orderly manner as shown in Fig. 4, whereby As shown in Fig. 7, a conductive film in which the CNTS 22 is inserted into the through hole u can be obtained. Further, by using the substrate 2A having the through holes 21 substantially perpendicularly intersecting with the substrate 20 as shown in Fig. 2, the conductive of the CNTs 22 can be inserted into each of the through holes 21 as shown in Fig. 3, 200811306. In the film, the conductive film is electrically conductive in a direction perpendicular to the surface of the substrate, and is an electrically conductive film having no conductivity in the direction of the substrate surface. Further, the hole formed in the substrate is not limited to the through hole, and as shown in Fig. 8, 5 may be used to form the recessed hole 21 of a predetermined depth on the surface of the substrate 20. In this case, as shown in Fig. 9, In the method of manufacturing the substrate structure of the present embodiment, the conductive film can be manufactured by the method of manufacturing the substrate structure of the present embodiment, and the size of the hole formed in the substrate can be appropriately changed. Conductive film with the desired properties. The transparent conductive film which is manufactured and has flexibility can be used as a transparent electrode of an electronic paper, a flexible display, a flat panel display or the like. Further, the substrate may be a flexible film which is flexible here, or may be non-flexible or non-transparent. Further, in the above examples, a conductive film having uniform conductivity on the entire substrate is exemplified, and a conductive film which is uniformly conductive only in a single or a plurality of partial regions in the film can be obtained. [Manufacturing of Electron Source of FED] Next, a case will be described in which an electron source (electric field emission array) of FED (Field Emission Display) is produced by using the above-described method for manufacturing a substrate structure. In the case of the substrate (base material), an inorganic oxide substrate such as alumina is used, and as shown in Fig. 2, a substrate in which the through holes are formed at substantially equal intervals with respect to the substrate surface is used. The diameter of the through hole and the interval between the through holes may be adjusted according to the brightness and the fineness when used for the FED. Inserts Here, CNTs of fibrous substances are used. The CNTs 22 200811306 used herein may be any of SWCNTs, DWCNTs, 3WCNTs, MWCNTs, and the like, and in order to make the in-plane electron emission density constant, it is preferable to use a specific number of CNTs having the same number of graphite sheets. The dispersion medium may be any one of pure water, a nonionic surfactant, an ionic surfactant, an aqueous solution of a surfactant, and an organic solvent containing an aqueous solution of tween20. When the substrate is placed in the dielectrophoresis apparatus of FIG. 12 according to the flowchart of FIG. 1, when a high frequency in a frequency range of 100 kHz to 1 MHz is applied between the electrodes, a positive dielectrophoretic force acts on the CNTs dispersed in the dispersion medium. The CNTs move through the pores. The direct control of the through hole is set in the range of about 10 to 500 nm, that is, 10 Å. When only one CNTs is inserted into one through hole, the diameter of the through hole may be set in the range of 10 nm to 100 nm. On the contrary, when a plurality of CNTs are inserted into one through hole, the diameter of the through hole may be 100 nm or more. As described in Fig. 3, the substrate structure (electron emitting element) thus manufactured is not unevenly present in a partial region in the substrate 20, but is vertically oriented at equal intervals throughout the entire substrate. Further, it is preferable that the electron emitting member protrudes from the surface (upper, lower surface) of the substrate as the CNTs 111 of the interposer. When the insert body is protruded in this manner, the CNTs are inserted into the through holes of the substrate, and then etched with an alkaline solution or the like to remove only the predetermined amount of the substrate surface. In this way, the electronic component of the FED can be manufactured by using the method of manufacturing the substrate structure of the present embodiment. By appropriately changing the diameter or arrangement interval of the holes formed in the substrate, it is easy to manufacture the electron emission with the desired performance. element. Figure 17 shows the main part of the FED with an electronic release component manufactured using the above manufacturing method. In the figure, a '1 〇〇-based emitter substrate (transmitted 23 200811306 emitter electrode) is placed on the emitter substrate 100, and a plurality of electron-emitting elements 110 fabricated by the above-described manufacturing method and inserted into the substrate through-holes are arranged in a matrix. shape. The fixing of the electron emitting elements 11 on the emitter substrate 1 can be carried out by bonding with a conductive paste. The portion between the portions of the emitter substrate 1 and the portion of the electron-emitting element 110 is formed with an insulating layer 120, and the gate electrode 130 is provided on the insulating layer 120. The positive electrode substrate 140 is disposed at a predetermined interval by a spacer in a state opposed to the emitter substrate 100. The positive electrode substrate 14A is a transparent electrode made of ITO or the like, and is formed into a phosphor layer (RGB phosphor) 141 on a surface (inner surface) of the surface of the electron emitting element 11A. A portion between the emitter substrate 1A and the positive electrode substrate 140 is in a vacuum state. When a DC voltage is applied between the transmitting emitter substrate 100 and the positive electrode substrate 140 by the DC power source 15 turns, electrons are emitted from the electron emitting element 110, and the phosphor layer 141 is struck to cause the phosphor to emit light to be displayed. 15 The electron emission device manufactured by the method for producing a substrate structure of the present embodiment is used in the substrate in which the CNTs are uniformly distributed in the substrate without being unevenly distributed, and is vertically oriented with respect to the substrate surface. When the component is discharged, extremely good electron emission characteristics can be achieved, and the brightness or fineness is not deviated, and a 2 〇 FED having excellent display performance can be obtained. Since the number of graphite sheets of the CNTs is made uniform, the brightness or the life can be made substantially constant. [Laminated wafer] Recently, as a technique for merging LSIs, such as SiP (system in package), attention has been paid. The siP system includes a memory, a CPU, and a plurality of LSI (wafer) layers of the 200811306 circuit and a two-dimensional device (packaged wafer). However, since the connection between the layers is bonded by wire bonding, it is not easy to speed up, and the number of wirings is also limited, and the problem that it is difficult to be thinned is an actual situation. 5 The method of manufacturing the substrate structure of the present embodiment can be applied to the sound product

晶片之各層(各晶片’例如第1晶片與第2晶片)間連接成三 維。將構成層積晶片之各晶片或層積晶片自身作為基板, 於要成為層間連接之導通孔或通孔之部份預先形成孔。插 入體使用金屬CNTs或金微粒子,使用第12圖之介電泳聲 10置,藉於該孔内******體,可易作成層間連接用 = 孔或通孔。 ' 藉此,可縮短信號配線長,可縮小配線電阻,同時 配線數亦可增大,而可謀求高性能化或低耗費電力。此: 藉使用半導體CN域其解導料作為電路零件, is體插人至基板之孔’可以連絡各層間之形式,封^ 件。 兒略」Each layer of the wafer (each wafer 'e.g., the first wafer and the second wafer) is connected in three dimensions. Each of the wafers or the laminated wafers constituting the laminated wafer is used as a substrate, and holes are formed in advance in portions of the via holes or via holes to be interlayer-connected. The insert body is made of metal CNTs or gold particles, and the dielectrophoretic sound is used in Fig. 12. By inserting the insert into the hole, it is easy to make a hole or a through hole for interlayer connection. This makes it possible to shorten the signal wiring length, reduce the wiring resistance, and increase the number of wirings, thereby achieving high performance or low power consumption. This: By using the semiconductor CN domain as its circuit component, the hole into the substrate can be connected to the form of the layers and sealed. Slightly

[高頻輸出放大器J 20 要求適合:欠世代以狀麟通料、狀高性 出放大器之實現,在面朝上(faee_up)構造之放大器’ 晶體晶片之電極與封包之電極電性連接之金屬電線夺電 成為問題。其解決對策係提出將電晶體晶;ί翻轉,q八k 短金屬凸塊(突起電極),將晶片及封包電極連接 ^ 大ΐΓ輪出放大器時,排出在高輪;: 里…、,習知之金屬凸塊在散熱性之點並不足曰 25 200811306 因此,提出藉將CNTs用於高頻輸出放大器之散熱基板,同 時實現散熱性與高放大率之技術。 此技術係於電極基板垂直地定向,使CNTs成長,接合 CNTs凸塊與覆晶。如此,於電極基板使CNTs直接成長之方 5法中,構成電子源時之課題如上述,雖定向可統一,但由 於CNTs之製造條件為電極基板之性質所限制,故有可製造 之CNTs形狀文限之可能性,同時,由於電極基板在高溫之 石炭析出條件下曝露,故肴電極基板之材質惡化之問題。 使用本實施形態之基板構造體之製造方法,於具第2 10圖所不之貫穿孔之基板之該貫穿孔***金屬(:^1^,製造第 3圖所不之基板結構物,藉由此基板結構物,於封包電極上 支撐覆晶’藉此,在不產生上述問題下,可同時且輕易地 實現散熱性及高放大率。 [細胞標本等] 15 冑細胞料***體,使之分散於分散介質巾,在具有 如第1〇圖所示之凹陷孔之基板,使用第12圖之介電泳裝 置將***體***至該孔内,藉此,亦可作成如第11圖所 示之、、、田胞才不本等。此時之施加電麼宜為小至不對細胞造成 不良〜響之I壓。II適當地選定施加之頻率,可僅將使數 20種細胞分散之分散介質中之特定細胞***至基板之孔,作 成細胞標本等。 【第1實施例】 帛18®及第19圖係顯示本發明人等執行之實驗結果者 (S EM %、片),第丨8圖係使用本實施形態之製造方法而製造之 26 200811306 基板結構物之截面圖,第19圖係將第18圖之右上25μιη部份 擴大之截面圖。此實驗係使用具有細微孔之基板作為基 , 板,並使用使***體於純水分散之分散介質,使用第12圖 • 所示之介電泳裝置而執行。基板之材質為氧化鋁 5 (al臓ina),基板之厚度為6〇μιη,基板之大小為直徑25mm, 、 孔之直徑為200nm。***體為金之微粒子(膠體金),粒子直 徑為lOOnm。使用於純水使該***體以分散濃度11χ1〇ΐ2粒 馨子/mL分散之分散介質ι〇〇μΙ^。將基板浸於分散介質之方法 係使用將分散介質之液滴滴下至基板之方法。於電極間施 10加之父流電壓為31VPP,頻率為70kHz。交流電壓之施加時 間為5分鐘。此外,金之導電率為45 2xl〇6s/m,純水之介 電常數為81ε〇。 如該等圖所不,可知於基板之孔中***金微粒子。此 外,本案發明人等亦對分散介質中之金微粒子是否因毛細 15管現㈣進入基板之孔中進行實驗,而確認了金微粒子未 _ 目毛細官現象進人基板之孔巾。當將此種金微粒子作為插 人體時,***體儘可能無間隙地進入基板之孔内為理想, 右非如此牯,宜於介電泳之***體***至基板之孔内後, 進行加熱處理,使金微粒子熔融後予以冷卻,藉此,使孔 • 20㈣之金微粒子相互一體化,而呈沿孔之形狀之柱狀體乃 至纖維狀之固體,同時,固定於基板之孔。 【第2實施例】 第20至第22圖係顯示本案發明人等執行之實驗結果者 (SEM照片),第2_係從斜向拍_於本實施形態製造方法 27 200811306 之基板(未******體)之戴面者,第21圖係從斜向拍攝使用 本發明實施形態之製造方法而******體之基板結構物截 面者,第22圖係將第21圖之一部份擴大者。此實驗係使用 具微細孔之基板作為基板,並使用使***體於純水分散之 5分散介質,使用第12圖所示之介電泳裝置而執行。基板之 材質為聚碳酸酯,基板之厚度為60μηι,基板之大小為直徑 25mm,孔之直徑為lOOnm。***體。使用使該 ***體以分散濃度5mg/Ml在純水分散之分散介質加“丨。將 基板次於分散介質之方法係使用將分散介質之液滴滴下至 10基板之方法。於電極間施加之交流電壓為20Vpp,頻率為 55kHz。交流電壓之施加時間為5分鐘。 如該等圖(特別是第21圖中以橢圓顯示之部份及第22 圖以箭頭顯示之部份)所示,可理解MWCNTs從基板表面插 入至内部,而可在基板全體發現導電性。此外,MWCNTs 15 在基板之孔之固定係藉自然乾燥來進行。 此外,以上說明之實施形態及實施例係為易理解本發 明而記載者,非限定本發明而記載者。因而,其旨趣為揭 示於上述實施形態及實施例之各要件亦包含本發明技術範 圍所屬之所有設計變更或均等物。 20 本揭示係與2006年6月29曰提申之曰本專利申請案 2006-179751號所含之主題相關,其揭示所有内容在此作為 參照事項而明確地納入。 【圖式簡單說明】 第1圖係顯示本發明實施形態之基板結構物之製造方 28 200811306 法之流程圖。 第2圖係顯示具有本發明實施形態之垂直貫穿孔之基 板的截面圖。 第3圖係顯示***體***至第2圖所示之基板之孔的狀 5 態之截面圖。 第4圖係顯示具有本發明實施形態之隨機之貫穿孔之 基板的截面圖。 φ 第5圖係顯示***體***至第4圖所示之基板之孔的狀 態之截面圖。 10 第6圖係顥示具有本發明實施形態之於一定方向傾斜 相交之貫穿孔之基板的截面圖。 第7圖係顯示***體***至第6圖所示之基板之孔的狀 恶之截面圖。 第8圖係顯示具有本發明實施形態之隨機之凹陷孔之 15 基板的截面圖。 # 第9圖係顯示***體***至第8圖所示之基板之孔的狀 態之截面圖。 第10圖係顯示具有本發明實施形態之垂直凹陷孔之基 " 板的截面圖。 第11圖係顯示***體***至第1〇圖所示之基板之孔的 狀態之截面圖。 第12圖係顯示本發明實施形態之介電泳裝置之概略 者。 第13圖係顯示本發明實施形態之電場強度分布者。 29 200811306 第14圖係顯示本發明實施形態之金屬SWCNTs之施加 頻率及介電泳力之關係者。 、 第15圖係顯示本發明實施形態之半導體S WCNTs之施 • 加頻率及介電泳力之關係者。 5 第16圖係顯示金屬SWCNTs等之導電率及介電常數者。 、 第17圖係顯示本發明實施形態之FED之概略結構者。 第18圖係顯示使用本發明實施形態之製造方法製造之 % 基板結構物之截面者(SEM照片)。 第19圖係將第18圖之一部份擴大者。 弟20圖係顯示從傾斜方向觀看用於本發明實施形態之 製造方法之基板截面者(SEM照片)。 第21圖係顯示從傾斜方向觀看使用本發明實施形態之 製造方法製造之基板結構物之截面者(SE1V[照片)。 第22圖係將第21圖之一部份擴大者。 15 【主要元件符號說明】 10.··分散介質 44···開口部 20...基板 100···發射極基板 21···孔 110···電子放出元件 30.··上部電極 111 …CNTs 31.··玻壤基板 120···絕緣層 32···金屬氧化膜 140···正極電極 40.··下部電極 141…螢光體層 41..·玻螭基板 150…直流電源 42···金屬氧化膜 43..·絕緣膜 S11_S18···步驟 30[High-frequency output amplifier J 20 requirements are suitable: the implementation of the amplifier in the lower generation, the high-efficiency amplifier, the faee_up structure of the amplifier' crystal of the electrode of the crystal chip and the electrode of the package Wire power is a problem. The solution is to propose a crystal crystal; ί flip, q 八k short metal bump (protruding electrode), connect the wafer and the package electrode to the high-frequency wheel when it is turned out of the amplifier;: Metal bumps are not enough at the point of heat dissipation. 200825 200811306 Therefore, a technique of using CNTs for a heat-dissipating substrate of a high-frequency output amplifier while achieving heat dissipation and high amplification is proposed. This technique is based on the vertical alignment of the electrode substrate to grow CNTs and bond the CNTs bumps and flip chips. As described above, in the method of directly growing CNTs on the electrode substrate, the problem of constituting the electron source is as described above, and the orientation can be unified. However, since the manufacturing conditions of the CNTs are limited by the properties of the electrode substrate, the shape of the CNTs can be manufactured. The possibility of limitation, and at the same time, due to the exposure of the electrode substrate under the condition of high temperature charcoal precipitation, the material of the electrode substrate deteriorates. By using the method for manufacturing a substrate structure according to the present embodiment, a metal substrate is inserted into the through hole of the substrate having the through hole of the second embodiment, and the substrate structure of the third embodiment is manufactured by The substrate structure supports the flip chip on the package electrode. Thereby, the heat dissipation and the high magnification can be simultaneously and easily achieved without causing the above problem. [Cell specimen, etc.] 15 胄 cell material insert, so that Disperse in the dispersion medium towel, insert the insert into the hole using the dielectrophoresis device of Fig. 12 on the substrate having the recessed hole as shown in Fig. 1, or as shown in Fig. 11 It is said that the application of electricity, the field cell is not the same. At this time, the application of electricity should be as small as not to cause a bad ~ ringing I. II appropriate selection of the frequency of application, only a few 20 kinds of cells can be dispersed The specific cells in the dispersion medium are inserted into the wells of the substrate to prepare a cell specimen, etc. [First embodiment] 帛18® and Fig. 19 show the results of experiments performed by the present inventors (S EM %, sheets),丨8 is a 26 2 manufactured by the manufacturing method of the present embodiment. 00811306 Cross-sectional view of the substrate structure, Fig. 19 is a cross-sectional view of the upper right 25 μm portion of Fig. 18. This experiment uses a substrate having fine pores as a base, a plate, and is used to disperse the insert in pure water. The dispersion medium is carried out using a dielectrophoresis device as shown in Fig. 12. The material of the substrate is alumina 5 (al臓ina), the thickness of the substrate is 6 μm, and the size of the substrate is 25 mm in diameter, and The diameter of the insert is 200 nm. The insert is gold microparticles (colloidal gold) with a particle diameter of 100 nm. The insert is used in pure water to disperse the dispersion at a concentration of 11 χ 1 〇ΐ 2 馨 馨 / mL mL 。 。 。 。 。. The method of immersing in the dispersion medium is a method of dropping the droplets of the dispersion medium onto the substrate. The parent-applied voltage between the electrodes is 31 VPP and the frequency is 70 kHz. The application time of the alternating voltage is 5 minutes. The rate is 45 2xl〇6s/m, and the dielectric constant of pure water is 81ε〇. As shown in the figures, it is known that gold fine particles are inserted into the pores of the substrate. In addition, the inventors of the present invention also applied gold fine particles in the dispersion medium. whether Since the capillary 15 tube (4) enters the hole of the substrate and is tested, it is confirmed that the gold microparticles are not inserted into the substrate. When the gold microparticles are inserted into the human body, the insertion body is as seamless as possible. It is ideal to enter the hole of the substrate. The right side is not so sturdy. After the insert of the dielectrophoresis is inserted into the hole of the substrate, heat treatment is performed to melt the gold particles and then cool, thereby making the gold particles of the hole 20 (4) The columnar body and the fibrous solid along the shape of the hole are integrated with each other, and are fixed to the hole of the substrate. [Second Embodiment] Figs. 20 to 22 show the results of experiments performed by the inventors of the present invention. (SEM photograph), the second image is taken from the oblique direction, the wearer of the substrate (the insertion body is not inserted) of the manufacturing method 27 of the present embodiment, and the 21st image is used for oblique imaging. The manufacturing method is inserted into the cross-section of the substrate structure of the interposer, and the 22nd drawing is an enlarged part of the 21st drawing. In this experiment, a substrate having micropores was used as a substrate, and a dispersion medium in which the intercalator was dispersed in pure water was used, and the dielectrophoresis apparatus shown in Fig. 12 was used. The material of the substrate was polycarbonate, the thickness of the substrate was 60 μm, the size of the substrate was 25 mm in diameter, and the diameter of the hole was 100 nm. Insert the body. The method of adding the dispersion to a dispersion medium having a dispersion concentration of 5 mg/Ml in pure water is used. The method of substituting the substrate next to the dispersion medium is a method of dropping a droplet of the dispersion medium to 10 substrates. The AC voltage is 20Vpp and the frequency is 55kHz. The application time of the AC voltage is 5 minutes. As shown in these figures (especially the part shown by the ellipse in Figure 21 and the part shown by the arrow in Figure 22), It is understood that MWCNTs are inserted into the inside of the substrate, and conductivity can be found in the entire substrate. Further, the fixing of the MWCNTs 15 to the holes of the substrate is performed by natural drying. Further, the embodiments and examples described above are easy to understand. The invention is not limited to the description of the present invention. Therefore, it is intended that all of the above-described embodiments and examples include all design changes or equivalents belonging to the technical scope of the present invention. The subject matter contained in this patent application No. 2006-179751 is hereby incorporated by reference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method of manufacturing a substrate structure according to an embodiment of the present invention 28 200811306. Fig. 2 is a cross-sectional view showing a substrate having a vertical through hole according to an embodiment of the present invention. A cross-sectional view showing a state in which the interposer is inserted into the hole of the substrate shown in Fig. 2. Fig. 4 is a cross-sectional view showing the substrate having the random through hole of the embodiment of the present invention. A cross-sectional view showing a state in which the interposer is inserted into the hole of the substrate shown in Fig. 4. Fig. 6 is a cross-sectional view showing the substrate having the through-holes obliquely intersecting in a certain direction in the embodiment of the present invention. A cross-sectional view showing the insertion of the insert into the hole of the substrate shown in Fig. 6. Fig. 8 is a cross-sectional view showing the substrate having the random recessed holes of the embodiment of the present invention. #第9图 shows the insertion A cross-sectional view of a state in which a body is inserted into a hole of a substrate shown in Fig. 8. Fig. 10 is a cross-sectional view showing a base plate having a vertical recessed hole according to an embodiment of the present invention. Fig. 11 is a view showing the insertion of the insert into 1st Fig. 12 is a cross-sectional view showing a state of a hole of a substrate according to an embodiment of the present invention. Fig. 13 is a view showing an electric field intensity distribution according to an embodiment of the present invention. 29 200811306 Fig. 14 The relationship between the application frequency and the dielectrophoretic force of the metal SWCNTs according to the embodiment of the present invention is shown. Fig. 15 shows the relationship between the application frequency and the dielectrophoretic force of the semiconductor S WCNTs according to the embodiment of the present invention. The figure shows the conductivity and the dielectric constant of the metal SWCNTs, etc. Fig. 17 shows the schematic structure of the FED according to the embodiment of the present invention. Fig. 18 shows the % substrate structure manufactured by the manufacturing method of the embodiment of the present invention. The cross section of the object (SEM photo). Figure 19 is an enlargement of one of the 18th figures. Fig. 20 is a view showing a substrate cross section (SEM photograph) for viewing the manufacturing method of the embodiment of the present invention from an oblique direction. Fig. 21 is a view showing a cross section of a substrate structure manufactured by the manufacturing method of the embodiment of the present invention (SE1V [photograph]) viewed from an oblique direction. Figure 22 is a partial enlargement of Figure 21. 15 [Description of Main Element Symbols] 10.··Dispersion Medium 44···Opening Port 20...Substrate 100···Emitter Substrate 21··· Hole 110···Electrical Release Element 30··· Upper Electrode 111 ...CNTs 31.··Broaden substrate 120···Insulation layer 32···Metal oxide film 140···Positive electrode 40.·Bottom electrode 141...Fluorescent layer 41..·Bollalt substrate 150...DC power supply 42···Metal oxide film 43..·Insulation film S11_S18···Step 30

Claims (1)

200811306 十、申請專利範圍: 1. 一種基板結構物之製造方法,其具有: 第1步驟,係準備具有至少1個細微孔之基板者; 第2步驟,係設置電極,並將前述基板浸於含有複 5 數***體之分散介質者;及 第3步驟,係於前述電極施加預定電壓者。 2. 如申請專利範圍第1項之基板結構物之製造方法,其中 前述第1步驟具有於前述基板形成前述孔之步驟。 3 ·如申請專利範圍第1項或第2項之基板結構物之製造方 10 法,其中前述第3步驟具有於前述基板施加交流電壓之 步驟。 4. 如申請專利範圍第3項之基板結構物之製造方法,其中 前述交流電壓之頻率從前述***體之介電常數與前述 分散介質之介電常數之關係,設定在正介電泳力作用於 15 前述***體之範圍内。 5. 如申請專利範圍第3項或第4項之基板結構物之製造方 法,其中前述交流電壓之頻率在1kHz〜100MHz之範圍 内。 6. 如申請專利範圍第1項至第5項中任一項之基板結構物 20 之製造方法,其中前述基板具有複數之前述孔。 7. 如申請專利範圍第1項至第6項中任一項之基板結構物 之製造方法,其中前述孔係貫穿前述基板之貫穿孔。 8. 如申請專利範圍第1項至第6項中任一項之基板結構物 之製造方法,其中前述孔係設置於前述基板表面層之凹 31 200811306 陷孔。 9.如申請專利範圍第1項至第8項中任一項之基板結構物 - 之製造方法,其中前述孔呈前述孔之直徑在前述基板之 •表面附近較前述基板内部大之形狀。 5 1〇·如申請專利範圍第1項至第9項中任一項之基板結構物 之製造方法,其中前述基板之厚度在〜1mm之範圍 内,同時,前述孔之直徑在5nm〜ΙΟΟμπι之範圍内。 • U·如申請專利範圍第1項至第10項中任一項之基板結構物 之製造方法,其中前述基板由絕緣性材料構成。 10 12·如申請專利範圍第1項至第11項中任一項之基板結構物 之製造方法,其中前述***體由導電性或半導電性之材 料構成。 13·如申請專利範圍第1項至第12項中任一項之基板結構物 之製造方法,其中前述***體為纖維狀物質或微粒子狀 15 物質。 • 14·如申請專利範圍第1項至第13項中任一項之基板結構物 之製造方法,更包含於前述第3步驟後,進行加熱接合 之步驟。 15·如申請專利範圍第1項至第14項中任一項之基板結構物 20 之製造方法,其中前述***體均一地存在於前述基板内 部。 16·如申請專利範圍第1項至第15項中任一項之基板結構物 之製造方法,其中前述***體為碳奈米管。 Π·如申請專利範圍第1項至第15項中任一項之基板結構物 32 200811306 之製造方法,其中前述***體為金屬之微粒子。 18·如申請專利範圍第1項至第17項中任一項之基板結構物 之製造方法,其中前述孔設置成與鄰近之至少1個前迷 孔互相交叉連通。 5 19.如申請專利範圍第1項至第18項中任一項之基板結構物 之製造方法,其中前述孔存在於相對於前述基板表面傾 斜之方向上。 20·如申請專利範圍第1項至第17項中任一項之基板結構物 之製造方法,其中前述孔存在於相對於前述基板表面垂 10 直之方向上。 21. /種基板結構物,係使用申請專利範圍第18項或第19項 記載之製造方法製造者,其具有可撓性。 22. /種基板結構物,係使用申請專利範圍第20項記載之製 造方法製造者’其具有可撓性。 15 23 /種電子放出元件’係使用申請專利範圍第20項記載之 製造方法製造者。 24. /種電子放出元件之製造方法,係具有申請專利範圍第 2〇項記載之製造方法者。 25. 〆種電子源,係具有至少1個申請專利範圍第23項記載 2〇 之電子放出元件者。 26 /種層積晶片,係使用申請專利範圍第2〇項記載之製造 方法製造者,其包含有具有複數連接端子之至少2個晶 片,且於第1晶片與第2晶片間存在前述基板。 27./種基板結構物,係使用申請專利範圍第1項至第20項 33 200811306 中任一項之基板結構物之製造方法製造者。 28·—種基板結構物,係包含有·· 基板,係存在至少1個直徑在5nm〜ΙΟΟμιη之範圍内 之孔’同時’厚度在Ιμιη〜1mm之範圍内者;及 至少1個***體,係具有導電性或半導電性之性質 並***至前述孔者。 29·如申請專利範圍第28項之基板結構物,其中前述基板具 有複數孔。 30·如申請專利範圍第29項之基板結構物,其中前述孔形成 與鄰近之至少1個前述孔互相交叉連通。 31·如申請專利範圍第28項至第3〇項中任一項之基板結構 物/、中别述孔形成於相對於前述基板表面傾斜之方向 上。 32·如申請專利範圍第28項或第29項之基板結構物,其中前 述孔形成於相對於前述基板表面約略垂直之方向上。 33·如申請專利範,3Ό項或第31項之基板結構物,係於相 對於則述基板表面交叉之方向上具有導電性或半導電 性性質者。 34·如申胃專圍第32項之基板結構物,係於相對於前述 基板表面約略垂直之方向具有導電性或半導電性之性 質者。 35·如申請專利_第28項至第34項中任—項之基板結構 物,其中前述***體為碳奈米管。 36·如申明專利範圍第28項至第34項中任一項之基板結構 34 200811306 物,其中前述***體為金之微粒子。 37. —種電子放出元件,係藉施加電壓,放出電子者,其包 含有: 基板,係具有至少1個細微孔者;及 5 至少1個***體,係作為前述電子放出元件之電極 而***至前述細微孔者。 38. 如申請專利範圍第37項之電子放出元件,其中前述*** 體係一部份相對於前述基板之表面突出,並***至前述 10 39.如申請專利範圍第37項或第38項之電子放出元件,其中 前述孔呈前述孔之直徑在前述基板表面附近較前述基 板内部大之形狀。 40. 如申請專利範圍第37項至第39項中任一項之電子放出 元件,其中前述孔存在於相對於前述基板表面約略垂直 15 之方向上。 41. 如申請專利範圍第37項至第40項中任一項之電子放出 元件,其中前述***體為碳奈米管。 42. 如申請專利範圍第37項至第40項中任一項之電子放出 元件,其中前述***體為具預定層之多層碳奈米管。 20 43.如申請專利範圍第37項至第40項中任一項之電子放出 元件,其中前述***體為單層碳奈米管。 44. 如申請專利範圍第37項至第40項中任一項之電子放出 元件,其中前述***體為金之微粒子。 45. —種圖像顯示裝置,係電場放出型者,其包含有: 35 200811306 電子源,係具有至少1個申請專利範圍第37項至第 44項中任一項記載之電子放出元件者;及 螢光體層,係配置於與前述電子源相對之位置者。 36200811306 X. Patent Application Range: 1. A method for manufacturing a substrate structure, comprising: a first step of preparing a substrate having at least one fine hole; and a second step of arranging an electrode and dipping the substrate And a third step of applying a predetermined voltage to the electrode. 2. The method of manufacturing a substrate structure according to the first aspect of the invention, wherein the first step comprises the step of forming the hole in the substrate. 3. The method of manufacturing a substrate structure according to claim 1 or 2, wherein the third step has a step of applying an alternating voltage to the substrate. 4. The method of manufacturing a substrate structure according to claim 3, wherein the frequency of the alternating voltage is set from a dielectric constant of the interposer to a dielectric constant of the dispersion medium, and a positive dielectrophoretic force is applied to 15 Within the scope of the aforementioned insert. 5. The method of manufacturing a substrate structure according to the third or fourth aspect of the invention, wherein the frequency of the alternating voltage is in the range of 1 kHz to 100 MHz. 6. The method of manufacturing a substrate structure 20 according to any one of claims 1 to 5, wherein the substrate has a plurality of the aforementioned holes. 7. The method of manufacturing a substrate structure according to any one of claims 1 to 6, wherein the hole penetrates through the through hole of the substrate. 8. The method of manufacturing a substrate structure according to any one of claims 1 to 6, wherein the hole is provided in a recess 31 200811306 of the surface layer of the substrate. The method of manufacturing a substrate structure according to any one of claims 1 to 8, wherein the hole has a shape in which a diameter of the hole is larger than a surface of the substrate in a vicinity of a surface of the substrate. The manufacturing method of the substrate structure according to any one of the items 1 to 9, wherein the thickness of the substrate is in the range of 〜1 mm, and the diameter of the hole is 5 nm to ΙΟΟμπι Within the scope. The method of manufacturing a substrate structure according to any one of claims 1 to 10, wherein the substrate is made of an insulating material. The method of manufacturing a substrate structure according to any one of claims 1 to 11, wherein the insert body is made of a conductive or semiconductive material. The method of producing a substrate structure according to any one of claims 1 to 12, wherein the insert is a fibrous substance or a fine particle 15 substance. The method for producing a substrate structure according to any one of claims 1 to 13, further comprising the step of performing heat bonding after the third step. The method of manufacturing a substrate structure 20 according to any one of claims 1 to 14, wherein the insert body is uniformly present inside the substrate. The method of manufacturing a substrate structure according to any one of claims 1 to 15, wherein the insert is a carbon nanotube. The manufacturing method of the substrate structure of any one of the above-mentioned items of the above-mentioned, wherein the said insert is metal microparticles. The method of manufacturing a substrate structure according to any one of claims 1 to 17, wherein the aperture is disposed to be in cross-over communication with at least one of the adjacent front apertures. The method of manufacturing a substrate structure according to any one of claims 1 to 18, wherein the pores are present in a direction inclined with respect to the surface of the substrate. The method of manufacturing a substrate structure according to any one of claims 1 to 17, wherein the hole is present in a direction perpendicular to the surface of the substrate. 21. The substrate structure is manufactured by using the manufacturing method described in claim 18 or claim 19, which has flexibility. 22. The substrate structure is manufactured by the manufacturer of the method of claim 20, which has flexibility. 15 23 / kind of electronic emission element' is manufactured by the manufacturing method described in claim 20 of the patent application. 24. The method of manufacturing an electronic emission device is the one having the manufacturing method described in the second aspect of the patent application. 25. An electron source is one that has at least one electronic emission component described in item 23 of the patent application. The 26/layer laminated wafer is manufactured by the manufacturing method described in the second aspect of the patent application, comprising at least two wafers having a plurality of connection terminals, and the substrate is present between the first wafer and the second wafer. 27. The substrate structure is a manufacturer of a method for producing a substrate structure according to any one of the claims of the first aspect of the invention. The substrate structure includes a substrate having at least one hole having a diameter in the range of 5 nm to ΙΟΟμη while the thickness is in the range of Ιμιη to 1 mm; and at least one insert. It is electrically conductive or semi-conductive and is inserted into the aforementioned pores. The substrate structure of claim 28, wherein the substrate has a plurality of holes. 30. The substrate structure of claim 29, wherein the aperture is formed in cross-over communication with at least one of the adjacent apertures adjacent thereto. The substrate structure according to any one of claims 28 to 3, wherein the hole is formed in a direction inclined with respect to the surface of the substrate. The substrate structure of claim 28 or 29, wherein the aforementioned holes are formed in a direction substantially perpendicular to a surface of the substrate. 33. The patent substrate, the substrate structure of item 3 or item 31, is of a conductive or semi-conductive property with respect to the direction in which the surface of the substrate intersects. 34. The substrate structure of the 32nd item of Shenwei Special is a property having conductivity or semi-conductivity in a direction approximately perpendicular to the surface of the substrate. The substrate structure according to any one of the preceding claims, wherein the insert is a carbon nanotube. The substrate structure of any one of the items 28 to 34, wherein the aforementioned insert is a fine particle of gold. 37. An electronic emission device that emits an electron by applying a voltage, comprising: a substrate having at least one fine hole; and 5 at least one insertion body serving as an electrode of the electron emission element Inserted into the aforementioned fine hole. 38. The electronic discharge component of claim 37, wherein a portion of the insertion system protrudes from a surface of the substrate and is inserted into the foregoing 10 39. Electronic release as in claim 37 or 38 In the element, the hole has a shape in which the diameter of the hole is larger than the inside of the substrate in the vicinity of the surface of the substrate. The electronic discharge element of any one of clauses 37 to 39, wherein the aforementioned hole is present in a direction approximately 15 perpendicular to the surface of the substrate. The electronic discharge element of any one of claims 37 to 40, wherein the aforementioned insert is a carbon nanotube. The electronic discharge element of any one of clauses 37 to 40, wherein the aforementioned insert is a multilayer carbon nanotube having a predetermined layer. The electronic discharge element of any one of clauses 37 to 40, wherein the insert is a single-layer carbon nanotube. 44. The electronic discharge element of any one of clauses 37 to 40, wherein the insert is a fine particle of gold. 45. An image display device, which is an electric field release type, comprising: 35 200811306 an electron source having at least one electronic release component according to any one of claims 37 to 44; And the phosphor layer is disposed at a position opposite to the electron source. 36
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