WO2007132274A2

WO2007132274A2 - High frequency low noise amplifier

Info

Publication number: WO2007132274A2
Application number: PCT/GB2007/050271
Authority: WO
Inventors: Nandi Loganathan
Original assignee: University Of Bradford
Priority date: 2006-05-17
Filing date: 2007-05-17
Publication date: 2007-11-22
Also published as: GB2438312A; WO2007132274A3; GB0709492D0; GB0609739D0

Abstract

A high frequency low noise amplifier comprises a current amplifier stage (216) in parallel with an LC resonator (212) and a cascode stage (214) arranged in series. Optionally, a dynamically variable DC bias voltage Vb1 is applied to a gate of a first transistor M1 in the cascode amplifier (214). The amplifier achieves a large power gain whilst preserving impedance isolation. The P1dB compression point is improved whilst maintaining a good noise factor. The exemplary circuit is simple and cost effective to produce.

Description

HIGH FREQUENCY LOW NOISE AMPLIFIER

The present invention relates in general to a high frequency low noise amplifier. Also, the present invention relates to a transceiver circuit including such a low noise amplifier. Further, the present invention relates to a wireless communication device including such a low noise amplifier.

A low noise amplifier (LNA) is widely used in wireless communications. For example, low noise amplifiers are found in almost all radio frequency (RF) and microwave frequency receivers such as cordless telephones, cellular telephones, Wireless Local Area Networks (WLANs) and satellite downlinks (eg GPS) .

The low noise amplifier is typically used to boost a power of a received signal. The received signal is then passed to later stages of the system to retrieve an information component (data) therefrom.

Ideally, the low noise amplifier introduces as little noise as possible to the received signal. Also, it is desired to avoid distortion of the received signal. Further, it is desired to achieve a high gain whilst maintaining linearity. Further still, it is desired to reduce component cost and simplify construction of the amplifier. In some environments, such as RF, it is desired to optimise a receiver or transceiver circuit for power gain, especially where the received signal is relatively weak. A particular problem arises in relation to a transceiver circuit having a receive channel and a transmit channel. There is a tendency for crosstalk and signal leakage from the transmit channel into the receive channel, which brings unwanted noise onto the received signal. Typically, the transmit channel and the receive channel operate at different frequencies, and a frequency filter, such as a band pass filter, is used to protect the receive channel by excluding the frequency range of transmit channel. However, the filter adds cost to the transceiver system. Further, a relatively high-cost filter is usually required in order to achieve an acceptable noise performance.

Another problem arises in that a low noise amplifier in a receive channel may need to provide different levels of amplification to compensate for fluctuations in received signal strength. That is, more amplification is required for a weak signal than for a strong received signal .

Still another problem arises, particularly in the context of hand-held devices, in that it is desired to achieve amplification whilst minimising power consumption.

Many types of low noise amplifier are already known.

As a first example, US-A-6, 556 , 085 (Korea Advanced

Institute of Science and Technology) discloses a low power low noise amplifier that achieves a high power gain without increasing power consumption, by sharing bias current . As another example, EP-A-1081573 (ST Microelectronics) discloses a cascoded CMOS stage for a low noise amplifier with high-precision biasing circuit providing a split bias to first and second transistors of the cascode stage.

EP-A-1085653 (Chartered Semi-conductor Manufacturing et al) discloses a CMOS tuned cascode RF amplifier with an additional capacitor to boost a circuit Q-factor and improve gain of the amplifier.

An aim of the present invention is to provide a low noise amplifier which addresses at least some of the problems of the prior art, as will be appreciated by the skilled reader from the discussion herein.

An aim of the exemplary embodiments of the present invention is to provide a low noise amplifier which achieves a low noise figure. Other aims of the exemplary embodiments are to improve gain and/or linearity. Still other aims are to reduce component cost and/or simplify operation .

Another aim of the exemplary embodiments of present invention is to provide a transceiver circuit where a receive channel is less vulnerable to noise caused by a transmit channel. Still another aim is reduce system cost and improve an overall system noise figure.

A still further aim is to provide a wireless communication unit, such as in hand held device, incorporating a low noise amplifier. Here, an aim of these exemplary embodiments of the present invention is to reduce cost and complexity of the wireless communication unit .

According to an aspect of the present invention there is provided a low noise amplifier as set forth in the appended claims.

According to another aspect of the present invention there is provided a transceiver circuit as set forth in the appended claims.

According to another aspect of the present invention there is provided a wireless communication unit as set forth in the appended claims.

Optional features of the present invention will be apparent from the dependent claims, and the description which follows.

In one aspect of the present invention there is provided a high frequency low noise amplifier comprising an LC resonator stage in series with a cascode amplifier stage. Also, a current amplifier stage is coupled in parallel with the LC resonator stage and the cascade amplifier stage.

The LC resonator stage comprises at least one capacitance and at least one inductance, which are arranged to provide a high impedance at a predetermined operating frequency. The cascode amplifier stage receives an input signal and, in cooperation with the LC resonator stage, provides a voltage amplified output signal. The current amplifier stage receives the voltage amplified signal and provides a current amplified output of the low noise amplifier. The current amplifier stage also isolates the LC resonator and the cascade amplifier from the output signal.

Preferably, a DC biasing circuit is arranged to provide a variable level DC biasing voltage to a first transistor in the cascade amplifier. Preferably, the DC biasing voltage is dynamically variable.

In one exemplary embodiment, the amplifier is arranged as a differential amplifier having first and second ends. Each end includes a cascode amplifier, and LC resonator and a current amplifier arranged as discussed herein.

The present invention also extends to a transceiver circuit having transmit and receive channels, wherein the receive channel includes a low noise amplifier as discussed herein.

Further, the present invention extends to a wireless communication unit comprising a low noise amplifier and/or a transceiver circuit as discussed herein.

For a better understanding of the invention, and to show how embodiments of the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings in which:

Figure 1 is a schematic view of a wireless communication system including hand held devices as employed in preferred embodiments of the present invention; Figure 2 is a schematic view of a transceiver circuit as employed in preferred embodiments of the present invention;

Figure 3 is a schematic overview of a low noise amplifier according to a preferred embodiment of the present invention;

Figure 4 is a schematic circuit diagram of a low noise amplifier according to a first preferred embodiment of the present invention; and

Figure 5 is a schematic circuit diagram of a low noise amplifier according to a second preferred embodiment.

In the drawings, like reference numerals represent like elements throughout.

Figure 1 shows a wireless communication system as employed in a preferred embodiment of the present invention, wherein one or more wireless communication units 41, 42 are arranged to communicate using radio frequency, microwave or other suitable frequency transmissions. The present invention is applicable in many different fields. As examples, the wireless communication units 41, 42 are cordless telephones (eg DECT), cellular telephones (eg GSM or UTMS), wireless local area network devices (eg WLAN, IEEE802. llb/g or Bluetooth) or satellite communication devices (eg GPS), amongst many others. The wireless communication units 41, 42 are arranged to communicate directly with each other and/or through a master, server or base station 50. Unfortunately, there are many sources of interference and noise for the electronic circuitry within a particular wireless communication unit 41, 42. For example, problems arise when nearby devices operate on the same or similar frequency channels. As examples, the wireless communication units typically operate at frequencies in the range 500MHz to 2GHz and beyond.

Figure 2 is a schematic diagram of a transceiver circuit as employed in preferred embodiment of the present invention .

In Figure 2, the transceiver circuit 10 has a transmit channel 16 and a receive channel 14 each coupled to an antenna 11 such as through a switch unit 12. The transmit channel 16 and the receive channel 14 are controlled by a controller 34.

In some fields, the transmit and receive channels 14, 16 operate alternately. However, in many fields there is a temporal overlap whereby the transmit and receive channels 14, 16 are each coupled to the antenna 11 simultaneously, such that there exists a feedback path or crosstalk between the two channels.

As shown in Figure 2, the transmit channel 16 suitably comprises a digital to analogue converter (DAC) or other encoding device 26, a mixer 28 which modulates an information signal onto a carrier frequency, a power amplifier 30 and a band pass or high pass filter 32. The receive channel 14 suitably comprises a low noise amplifier 20 to amplify a received signal provided from the antenna 11. Typically, the amplified signal is then supplied to a mixer 22 for down conversion to a base band frequency, either directly or through an intermediate frequency. The received signal is then processed to extract an information component such as through an analogue to digital converter (ADC) 24.

In Figure 2, a protective filter 18 is provided in order to exclude unwanted noise frequencies and other interference from the receive channel 14. In particular, it is desired to minimise crosstalk caused by the transmit channel 16. The protective filter 18 is typically a band pass filter. Often, relatively expensive components are required for the band pass filter 18, such as a SAW filter. The protective filter 18 tends to degrade noise performance of the transceiver system 10. Also, the protective filter 18 attenuates the received signal from the antenna 11.

Figure 3 is a schematic block diagram of a low noise amplifier according to a preferred embodiment of the present invention.

Referring to Figure 3, the preferred low noise amplifier 20 comprises an LC resonator section LC 212, a cascode amplifier section (CAS) 214, and a current amplifier section (I-AMP) 216. Also, the amplifier comprises a DC bias circuit (DC-B) 218.

The LC resonator 212 and the cascode amplifier 214 are arranged in series to form a first stage. The current amplifier 216 is arranged in parallel with the LC resonator 212 and the cascode amplifier 214, to form a second stage.

In operation, an input signal P_1n is applied to the cascode amplifier 214. The cascode amplifier 214, in cooperation with the LC resonator 212, applies a voltage gain to the input signal. The voltage amplified signal is then supplied to the current amplifier 216 which provides current amplification to the voltage amplified signal and provides a power amplified output signal P_out •

The circuit configuration of Figure 3 will now be described in more detail with reference to a particular example circuit diagram as shown in Figure 4.

Figure 4 is a schematic circuit diagram of a low noise amplifier according to preferred embodiment of the present invention .

The major components of the preferred low noise amplifier circuit are shown in Figure 4. The LC resonator stage 212 comprises at least one capacitor Cl and at least one inductor Ll, which are arranged in parallel. The LC resonator stage 212 is arranged in series above the cascode stage 214, which comprises transistors Ml and M2 in a cascode architecture. Here, a common source/common gate cascode architecture is employed. The current amplifier stage 216 includes a third transistor M3 whose drain and source are coupled in parallel to the LC resonator and the cascode amplifier 212, 214. In use, a received signal P_1n is applied to the gate of the first cascode transistor Ml. The LC resonator 212 is arranged to provide a maximum impedance at a selected resonant frequency, which is suitably the RF operating frequency of the low noise amplifier. Hence, the LC resonator 212 and the cascode stage 214 provide maximum voltage gain at the resonant frequency. Here, the cascode amplifier 214 is arranged to isolate the voltage gain stage 212, 214.

The current amplifier stage 216 functions both as a current amplifier and as a source follower. Here, these two roles are combined. By acting as a source follower, the second stage 216 provides isolation for the cascode stage 214. The circuit output impedance of the LNA does not reduce the high voltage gain achieved by the first stage 212, 214. A source follower is usually employed solely for the purposes of providing isolation of the circuit output impedance. However, by providing the second stage in parallel, a larger power gain is achieved since a larger drain current is possible.

As also shown in Figure 4, an impedance matching unit 217 is provided in series with the third transistor M3. Most radio frequency circuits expect input and output impedances of 50 Ohms. In the preferred embodiment, the impedance matching circuit 217 provides a 50 Ohm match from the LNA 20 to a subsequent stage, such as the mixer 22 of Figure 2.

Component values of the capacitor Cl and inductor Ll in the LC resonator 212 are ideally selected in order to provide a maximum quality factor Q. The lowest L to C ratio is preferred, so that the capacitance is as large as possible when compared to the inductance L.

The circuit of Figure 4 is suitably a CMOS circuit. Suitably, transistors Ml and M2 are NMOS devices. In this embodiment, transistor M3 is instead a PMOS device. In which case, a coupling capacitor Cc is provided to remove DC. M3 as a PMOS device has lower flicker noise due to lower hole mobility than a comparable NMOS device. There is a slight increase in output impedance. However, in a preferred circuit construction, the bulk of transistor M3 can now be tied to the source, which eliminates non- linearity due to a device body effect.

In summary, the circuit arrangement of Figure 4 provides a larger power gain through the folded second stage 216, whilst maintaining impedance isolation.

DC bias voltages V_bl and V_b2 are applied to transistors Ml and M2 of the cascode amplifier 214, using the DC biasing circuit 218 shown in Figure 3.

In one example embodiment, the DC bias levels V_bi and V_b2 are each preset and remain constant.

In another preferred implementation, the DC biasing circuit 218 is arranged to provide a variable gate bias voltage V_bi to the gate of transistor Ml of the cascode stage 214. Hence, Ml, as well as being a common source amplifier, also is used as a variable attenuator for the circuit input. Varying the DC gate bias voltage V_bi improves linearity of the circuit over a much larger range of input signals P_1n and allows much larger input signals P_1n to be provided to the amplifier.

The power of received signals can vary in magnitude quite considerably. If the power of the input signal is low, then the signal requires a large amount of amplification by the amplifier 20. However, if the power of the received signal is relatively high, then less amplification is required. Using Ml as a variable attenuator is a convenient mechanism to apply a variable amount of amplification to the received signal. Further, altering the DC gate bias voltage V_bl enables the low noise amplifier to provide an output signal P_out of consistent magnitude despite variations in the power of the received signal P_1n.

The cascode stage 214 draws current in series through the transistors M2 and Ml. Hence, controlling the DC bias voltage V_bl of the first transistor Ml also effectively controls current flowing through the common gate transistor M2 as well. For high input signals P_1n, transistor Ml is controlled to shut the channel, which also restricts current available for the cascode stage through M2.

Conveniently, the DC bias voltage V_b2 applied to the second transistor M2 is arranged to ensure that M2 operates in a region of saturation. In the preferred embodiment, DC bias voltage V_b2 of transistor M2 is constant, and is suitably tied to a positive voltage rail Pdd (in an NMOS device) . By operating in the region of saturation, M2 provides maximum transconductance (gm=Iout/Pin) , which together with the LC resonant circuit 212 provides maximum voltage gain Av.

Linearity of the amplifier 20 is conveniently determined with reference to a IdB compression point (PIdB) , which is the point of which the actual gain of the amplifier is IdB below the ideal linear gain. The preferred circuit configuration improves the IdB compression point (PIdB) .

It will be appreciated that by providing transistor M3 in parallel with the first stage 212, 214, current re-use is lost. However, a corresponding benefit is that in providing all of the available current to the second stage 216, the PIdB compression point is considerably improved. Also, by controlling V_bl, the preferred circuit arrangement allows the low noise amplifier to receive a much larger range of signals.

In a practical example, the first stage 212, 214 has a current consumption of the order of 0.6mA. In this configuration, a PIdB compression point of -14dBm is achieved. Also, noise factor and device gain are maintained comparable with existing circuit technologies. In particular the preferred CMOS circuit has comparable performance with other much more expensive manufacturing technologies, such as GaAs SIGE devices.

Figure 5 is a circuit diagram showing another preferred example of the low noise amplifier.

In this example, the amplifier is a differential amplifier. The first and second ends are provided, each comprising an LC resonator, a cascode stage, and a current amplifier stage arranged as discussed above.

A differential input signal is provided at i/pl and i/p2, and a differential amplified output is provided o/pl and o/p2.

Inductors Ll, L2 and L3 form part of an input impedance matching unit, such that the amplifier suitably has an input impedance of 50 Ohms at the operating frequency .

Inductors L4 and capacitors C2 form respective first and second LC resonators. Transistors Ml and M2 form a first cascode stage, while transistors M3 and M4 form a second cascode stage. In this example circuit, inductors L5, L6 and capacitors C3, C4 form part of an output impedance matching circuit, to provide a 50 Ohm output impedance. Resistors Rl and R2 are high impedance resistors. Here, the high impedance resistors R2a and R2b, such as 20 kOhms, allow the current amplifier stages to act also as source followers. Capacitors Cc are each coupling capacitors.

In Figure 5, DC bias voltages V_gi and V_g3 preferably provide dynamically varying DC bias voltages to a first transistor Ml, M3 of each cascode stage.

The differential low noise amplifier of Figure 5 has an even better common mode rejection ratio (CMRR) and an even better dynamic range, compared to the single-ended configuration of Figure 4. In summary, the low noise amplifier described above achieves a large power gain whilst preserving impedence isolation. Further, by using the input stage of the circuit as both the common source amplifier and a variable attenuator, a PIdB compression point is improved whilst maintaining a good noise factor and gain performance.

Another benefit of the preferred circuit arrangement is that bandgap references in the circuit are reduced, which reduces circuit clutter. The circuit of the present invention is simple and cost effective.

Referring again to Figure 2, the low noise amplifier described herein has further benefit when employed in a receiver circuit 14 and/or in a transceiver circuit 10. In particular, improving the LNA 20 reduces load on the protective filter 18. The low noise amplifier 20 is better able to tolerate noise, hence a lower quality and cheaper protective filter 18 may be employed.

In a particularly preferred embodiment, the LNA 20 contributes to a much improved system noise figure.

In applications such as a cellular telephone, the output of the LNA 20 provides a measure of the received signal strength. Suitably, a received signal indicator unit is arranged to determine a received signal level based upon the output of the low noise amplifier 20. The received signal level is used by the controller 34 to adaptably control the power amplifier 30 in the transmit channel 16. That is, where the received signal indicator indicates that a strong signal is being received, then it can be assumed that a lower power transmission signal will also be appropriate, and power gain of the power amplifier 30 is reduced accordingly. Further, when the power amplifier 30 is in a low power mode, the compression point of the low noise amplifier 20 in the receive channel 14 does not need to be so high, because lowering power of the transmit signal reduces crosstalk into the receive channel. As a result, it is also possible to adjust V_bi to lower the compression point for a more sensitive receiver, as a virtuous feedback cycle. Lowering the compression point of the LNA 20 in turn lowers the system noise figure.

This form of dynamic LNA is readily implemented using the preferred circuit arrangements, since only the DC bias voltage V_bl of transistor Ml is altered. Bias voltages to the other circuit components, particularly transistors M2 and M3, are suitably tied to a fixed level.

The low noise amplifier discussed herein also has additional benefits in a wireless communication unit as a whole. For example, cost, complexity, weight and longevity of the wireless communication unit are improved by using the preferred low noise amplifier.

Although a few preferred embodiments have been shown and described, it will be appreciated by those skilled in the art that various changes and modifications might be made without departing from the scope of the invention, as defined in the appended claims.

Attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment (s) . The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A high frequency low noise amplifier, comprising;

an LC resonator stage (212) comprising at least one capacitance (Cl) and at least one inductance (Ll), wherein the LC resonator stage (212) is arranged to provide a high impedance at a predetermined operating frequency;

a cascode amplifier stage (214) coupled in series with the LC resonator stage (212), wherein the cascode amplifier stage (214) is arranged to receive an input signal at the predetermined operating frequency and provide a voltage amplified signal in cooperation with the LC resonator stage (212); and

a current amplifier stage (216) coupled in parallel with both the LC resonator stage (212) and the cascode amplifier stage (214), wherein the current amplifier stage (216) is arranged to provide a power amplified output signal from the voltage amplified signal, and wherein the current amplifier stage (216) isolates the LC resonator stage (212) and the cascode amplifier stage (214) from the power amplified output signal.

2. The amplifier of claim 1, wherein:

the cascode amplifier stage (214) comprises at least a first transistor (Ml) and a second transistor (M2) arranged in cascode; and a DC biasing circuit (218) is arranged to provide a variable level DC biasing voltage (VbI) at least to the first transistor.

3. The amplifier of claim 2, wherein the DC biasing circuit (218) is arranged to dynamically vary the DC biasing voltage applied to the first transistor.

4. The amplifier of claim 3, wherein the DC biasing circuit (218) is arranged to dynamically vary the DC biasing voltage applied to the first transistor according to a magnitude of the received input signal.

5. The amplifier of any preceding claim, wherein:

the cascode amplifier stage (214) is coupled in series with the LC resonator stage (212) between first and second voltage rails; and

the current amplifier stage (216) is coupled between the first and second voltage rails in parallel with the LC resonator stage (212) and the cascode amplifier stage (214) .

6. The amplifier of any preceding claim, further comprising :

a second LC resonator circuit (212), a second cascode stage (214) and a second current amplifier stage (216) arranged in combination with the LC resonator circuit

(212), the cascode stage (214) and the current amplifier stage (216) to provide a differential amplifier.

7. A high frequency low noise amplifier, comprising;

a cascode amplifier circuit (214) including at least a first CMOS transistor (Ml) and a second CMOS transistor (Ml) in a common source common gate cascode arrangement, wherein a gate of the first transistor is arranged to receive an input signal;

an LC resonator circuit (212) arranged in series with the cascode amplifier circuit (214), wherein the LC resonator is coupled to a drain of the second transistor (M2) ; and

a source follower circuit (216) arranged in parallel with the LC resonator circuit (212) and the cascode amplifier circuit (214), the source follower circuit (216) comprising at least a third transistor (M3) having a gate coupled to the drain of the second transistor (M2) to receive a voltage amplified signal, and provide a power amplified output signal in response thereto.

8. The amplifier of claim 7, further comprising:

a DC biasing circuit (218) arranged to apply a fixed DC bias voltage (Vb2, Vb3 ) to a gate of the second transistor (M2) and a gate at the third transistor (M3), and to apply a variable DC bias voltage (VbI) to the gate of the first transistor (Ml) .

9. The amplifier of claim 8, wherein the DC biasing circuit (218) is arranged to apply the variable DC bias voltage to the gate of the first transistor (Ml) according to a magnitude of the input signal.

10. The amplifier of claim 7, 8, or 9, wherein:

the cascode amplifier circuit (214) is coupled in series with the LC resonator circuit (212) between first and second voltage rails; and

the source follower circuit (216) is coupled between the first and second voltage rails in parallel with the LC resonator circuit (212) and the cascode amplifier circuit (214) .

11. The amplifier of any of claims 7 to 10, further comprising :

first and second ends to form a differential amplifier, each end comprising the LC resonator circuit (212), the cascode amplifier circuit (214) and the source follower circuit (216) arranged as set forth in any of claims 7 to 10.

12. A transceiver circuit, comprising:

a transmit channel (16) including a power amplifier (30) arranged to amplify a transmit signal at a predetermined transmit frequency; and

a receive channel (14) including a low noise amplifier (20) arranged to amplify a receive signal at predetermined receiving frequency, wherein the low noise amplifier is arranged as set forth in any of claims 1 to 11.

13. The transceiver circuit of claim 12, further comprising:

a controller (34) arranged to determine a received signal strength from an output of the low noise amplifier (20), and in response adjust an amplification gain of the low noise amplifier (20) .

14. The transceiver circuit of claim 13, wherein the controller (34) is also arranged to adjust a power amplification of the power amplifier (30) in the transmit channel (16) according to the received signal strength.

15. A wireless communication unit (41, 42) comprising the low noise amplifier (20) of any of claims 1 to 11.

16. A wireless communication unit (41, 42) comprising the transceiver circuit (10) of any of claims 12 to 14.