WO2007116476A1 - メモリカードおよびデータの書き込み方法 - Google Patents
メモリカードおよびデータの書き込み方法 Download PDFInfo
- Publication number
- WO2007116476A1 WO2007116476A1 PCT/JP2006/306871 JP2006306871W WO2007116476A1 WO 2007116476 A1 WO2007116476 A1 WO 2007116476A1 JP 2006306871 W JP2006306871 W JP 2006306871W WO 2007116476 A1 WO2007116476 A1 WO 2007116476A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- memory
- memory card
- host device
- memory controller
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
Definitions
- the present invention relates to a data writing technique in a memory card, and more particularly to a technique effective for shortening a data writing time in a memory card using a nonvolatile semiconductor memory.
- memory cards such as SD (Secure Digital) card (registered trademark) and CF (Compact Flash) card (registered trademark) are widely used.
- SD Secure Digital
- CF Compact Flash
- a host such as a personal computer or DSC sets a data capacity to be transferred and a transfer address of transfer data immediately before issuing a write command. Then, after issuing a write command to the memory card, data transfer of the set capacity is performed.
- the memory controller provided in the memory card regards the write command and the subsequent data transfer as one unit, and writes the data capacity in accordance with the contents of the set command to the nonvolatile semiconductor memory To do.
- data is managed in block units determined by a certain size (an erase unit that can erase a plurality of nonvolatile memory cells connected to a word line at once). Yes.
- a page unit write instruction 1S is generated when a page in the order of addresses in the same block occurs multiple times in succession.
- Patent Document 1 JP 2004-264912 A
- the data is divided into data sizes set by the host, and data transfer is repeated along with the write command.
- the host transfers the write command and the divided latter half data to the memory card.
- the memory card writes the latter half of the data to another erased second block, and then copies the remaining data except the latter half of the first block. .
- copy processing occurs in proportion to the number of times the write command is issued. While the memory card is performing the copy process, the host is in a copy process waiting state and cannot perform the data write process, which increases the data write time.
- An object of the present invention is to provide a technique capable of greatly reducing the data writing time by greatly reducing the number of copies in the data writing process.
- the present invention includes a non-volatile semiconductor memory having a plurality of non-volatile memory cells and capable of storing predetermined information, and a memory for instructing an operation of the non-volatile semiconductor memory based on a command issued from the outside.
- the memory controller has a final address in the previous data transfer and a start address in the next data transfer in the data write process arbitrarily divided by the host device. Judgment of whether or not the power is continuous. If the data is continuous, the data write process by the next data transfer is performed after the data written in the previous data transfer without performing the copy process. Is performed continuously.
- the present invention performs copy processing when the last address in the previous data transfer and the start address in the next data transfer are continuously different.
- the copy processing is performed after the data write processing is completed.
- the present invention includes a nonvolatile semiconductor memory having a plurality of nonvolatile memory cells and capable of storing predetermined information, and an operation instruction for the nonvolatile semiconductor memory based on a command issued from the outside.
- the copy process is performed after the data write process is completed.
- FIG. 1 is a block diagram showing a configuration of a memory card according to an embodiment of the present invention.
- FIG. 2 is an explanatory diagram showing a sequence of the host device when data is written to the memory card of FIG.
- FIG. 3 is a flowchart showing an operation when data is written to the memory card of FIG. 1.
- FIG. 4 is an explanatory diagram of an operation sequence showing an example of data writing in the memory card of FIG. 1.
- FIG. 5 is an explanatory diagram of an operation sequence illustrating an example when a host device read command is issued after data is written to the memory card of FIG. 1.
- FIG. 6 is an explanatory diagram showing an operation sequence showing an example when there is no response from the host device after data is written to the memory card of FIG. 1.
- FIG. 7 is an explanatory diagram of an operation sequence showing an example of data write operation in a memory card in which copy processing is performed every time data is written by a write command examined by the present inventors.
- FIG. 8 is a block diagram showing a configuration of a memory card according to another embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
- the memory card 1 is configured such that the host device 2 can be connected to the outside of the memory card 1, for example, a digital camera, a mobile phone, etc.
- the memory card 1 includes a nonvolatile semiconductor memory 3 that can be electrically rewritten and erased as exemplified by a flash memory, and a memory controller 4.
- the memory controller 4 is connected to the host device 2 and controls the non-volatile semiconductor memory 3, reads out programs and data stored in the non-volatile semiconductor memory 3, outputs them to the host device 2, Or instruct the program or data to be written from host device 2.
- FIG. 2 is an explanatory diagram showing a sequence of the host device 2 when data of a certain capacity (data size A) is written into the memory card 1.
- FIG. 2 shows an example in which data B of data size A is divided and transferred into data B1 to B4.
- the host device 2 issues an initial write command, and transfers the write command and data B1 obtained by arbitrarily dividing the data size A to the memory card 1, respectively.
- the memory controller 4 writes the data B1 into any erased block.
- the copy process for copying the original data in the write target block is not performed.
- the host device 2 transfers the second write command and the data B2 obtained by arbitrarily dividing the data size A, respectively.
- the memory controller 4 determines whether or not the last address of the data B1 and the start address of the transfer data that is set by the second write command are consecutive, and the addresses are linked. If it continues, it will be erased! Write data B2 following data B1 to the block.
- the transferred data B2 is written (continuous write) without performing the copy process of copying the original data in the write target block.
- the host device 2 transfers the third write command and the data B3 obtained by arbitrarily dividing the data size A.
- the memory controller 4 determines whether or not the last address of the data B2 and the start address of the data transfer set by the third write command are consecutive, and if the addresses are consecutive, Executes continuous writing of the transferred data B3 without performing copy processing.
- the host device 2 transfers the fourth write command and the data B4 obtained by arbitrarily dividing the data size A, respectively.
- the memory controller 4 determines whether or not the last address of the data B3 and the start address of the data transfer set by the fourth write command are continuous. If the addresses are continuous, the data B4 transferred after the data B3 is continuously written without performing the copy process in this case as well. Then, after the data B4 has been written, the copy process is performed.
- FIG. 3 is a flowchart of the memory card 1 when writing a certain amount of data.
- the memory controller 4 determines whether or not the command is a write command (step S101). In the case of a write command, the memory controller 4 determines whether or not data is being continuously written (FIG. 2) (step S102).
- the memory controller 4 sets the continuous write flag (step S103), receives data transfer from the host device 2, and stores the data in a non-volatile manner. Writing into the emitting semiconductor memory 3 (step S104).
- step S102 when continuous writing is being performed, the memory controller 4 continuously determines the last address in the previous data transfer and the start address of the set transfer data set by the current write command. Then, it is determined whether or not the force is sufficient (step S 1 05).
- step S106 If the addresses are consecutive! /, NA! /, The memory controller 4 performs a copy process (step S106). Subsequently, when the copy process ends, the memory controller 4 clears the continuous write flag (step S107), and then executes the process of step S104.
- step S105 if the addresses are continuous, the memory controller 4 receives the data transfer from the host device 2 and continuously writes additional data to the non-volatile semiconductor memory 3 (step S 108).
- step S109 the memory controller 4 determines whether data is being continuously written. If the command is not being continuously written, the issued command is also executed by the host device 2 (step S110).
- step S109 when data is being continuously written, the memory controller 4 executes a copy process (step S111), and when the copy process is completed, clears the continuous write flag (step S109). 112), the process of step S110 is executed.
- FIG. 4 is an explanatory diagram of an operation sequence showing a normal data write operation example in the memory card 1 and the host device 2.
- FIG. 4 shows an operation sequence in which the write data divided and transferred to the data Dl and D2 and the data D3, which is new write data different from the write data, are written to the memory card 1, respectively. Is.
- FIG. 4 the sequence operation of the host device 2, the memory controller 4, and the nonvolatile semiconductor memory 3 is shown from the left side to the right side, and the elapsed time is shown from the upper side to the lower side. Yes.
- the right side of the nonvolatile semiconductor memory 3 The images of blocks (erased block B and written (written object) block A) in the memory array of the conductive semiconductor memory 3 are shown.
- the host device 2 issues a write command including data transfer information, and transfers the write command and data D1 to the memory controller 4 (sequence SelO, SI Do data transfer information is For example, it consists of setting information such as the transfer start address and transfer capacity.
- the memory controller 4 writes the data D1 to the erased block B (sequence Sel2).
- the memory controller 4 outputs an end command indicating that the writing process is completed to the host device 2 (sequence Sel3).
- the host device 2 issues a write command including data transfer information to the memory controller 4 (sequence Se 14). From the data transfer information, the memory controller 4 determines whether or not it is continuous with the last address of the data D1 start address force data D1 (sequence Se15).
- the memory controller 4 continuously writes the data D2 (sequence Sel6) transferred to the block B in which the data D1 is written (sequence Se 17).
- the memory controller 4 After completing the writing of the data D2, the memory controller 4 outputs an end command to the host device 2 (sequence Sel8). In response to the end command, the host device 2 issues a write command including data transfer information to the memory controller 4 (sequence Sel9).
- the memory controller 4 determines from the data transfer information whether or not it is continuous with the last address of the start address power data D2 of the data D3 (sequence Se20). As described above, data D3 is new data different from data Dl and D2.
- the memory controller 4 starts the copy process (sequence Se21).
- the original data of block A that has been written is copied to block B from the next address after the last address of data D2 to the address before the start address where data D3 is written.
- the host device 2 transfers the data D3 to the memory controller 4 (sequence Se23).
- the memory controller 4 writes the data D3 to the block B (sequence Se24), and outputs an end command to the host device 2 (sequence Se25) when the writing is completed.
- FIG. 5 shows an operation sequence when the host device 2 issues a read command and reads the data D3 after writing the write data divided and transferred to the data Dl and D2. It is.
- FIG. 5 also shows the sequence operations of the host device 2, the memory controller 4, and the non-volatile semiconductor memory 3 from the left side to the right side. Show.
- the host device 2 issues a write command including data transfer information, and transfers the write command and data D1 to the memory controller 4 (sequence SelOl, Sel02).
- the memory controller 4 writes the data D1 into the erased block (sequence Sel03). Thereafter, the memory controller 4 outputs an end command indicating that the writing process has ended to the host device 2 (sequence Sel04).
- the host device 2 issues a write command including data transfer information to the memory controller 4 (sequence Sel05). From the data transfer information, the memory controller 4 determines whether or not it is consecutive with the last address of the data D1 start address force data D1 (sequence Sel06).
- the transferred data D2 (sequence Sel07) is continuously written to the block in which the data D1 is written (sequence Sel08).
- Memory controller 4 outputs an end command to host device 2 after writing data D2 (sequence Sel09).
- the host device 2 issues a read command including data transfer information to the memory controller 4 (sequence Sel 10).
- the memory controller 4 determines that the received command is not a write command (sequence Sel l 1), it starts the copy process (sequence Sel 12).
- the memory controller 4 reads the data D3 from the nonvolatile semiconductor memory 3 based on the data transfer information (sequence Sel 14), and the read data Transfer D3 to host device 2 (sequence Sel 15)
- FIG. 6 shows an operation sequence in the case where there is no response from the host device 2 even after an arbitrary period of time has elapsed after writing the write data divided and transferred to the data Dl and D2. is there.
- FIG. 6 also shows the sequence operations of the host device 2, the memory controller 4, and the nonvolatile semiconductor memory 3 from the left side to the right side, and shows the passage of time from the upper side to the lower side. .
- the host device 2 issues a write command including data transfer information, and transfers the write command and data D1 to the memory controller 4 (sequence Se201, Se202).
- the memory controller 4 writes the data D1 into the erased block (sequence Se203). Thereafter, the memory controller 4 outputs an end command indicating that the writing process has ended to the host device 2 (sequence Se204).
- the host device 2 issues a write command including data transfer information to the memory controller 4 (sequence Se205). From the data transfer information, the memory controller 4 determines whether or not it is continuous with the last address of the start address force data D1 of the data D2 (sequence Se206).
- the transferred data D2 (sequence Se207) is continuously written to the block B in which the data D1 is written (sequence Se208).
- the memory controller 4 After the data D2 has been written, the memory controller 4 outputs an end command to the host device 2 (sequence Se209).
- FIG. 7 shows that copy processing is performed every time data is written by the write command examined by the present inventors. It is explanatory drawing of the operation
- movement sequence which shows the example of data write operation in the memory card performed.
- FIG. 7 the sequence operations of the host device, the memory controller, and the nonvolatile semiconductor memory are shown from the left side to the right side, and the passage of time is shown from the upper side to the lower side.
- the right side of the nonvolatile semiconductor memory shows images of blocks (erased block B and written (write target) block A) in the memory array of the nonvolatile semiconductor memory! /.
- the host device issues a write command including data transfer information, and transfers the write command and data D1 to the memory controller (sequence Se301, Se302).
- the memory controller writes data D1 to erased block B (sequence Se303).
- the memory controller copies the original data of block A that has been written from the next address of the last address of data D1 to the final address of block B to block B (sequence Se304).
- the host device memory card cannot be accessed during this copy process.
- the memory controller When the copy process ends (sequence Se305), the memory controller outputs an end command to the host device (sequence S306). In response, the host device transfers the write command including the data transfer information and data D to the memory controller (sequence Se307, Se308).
- the memory controller writes the data D2 transferred to the newly erased block C from the data transfer information (sequence Se309), and after the data D2 has been written, starts the copy process in block C (sequence Se310). ). In this copying process, the original data of block B other than data D2 is copied to block C.
- the memory controller When the copy process ends (sequence Se311), the memory controller outputs an end command to the host device (sequence Se312), and the writing is ended.
- one copy process occurs in a write operation by one write command. For example, if the size of one block is 128KB and the host writes 2kB of data with one write command In this case, a copy process for 126 kB (128 kB-2 kB), which is a difference in data writing, occurs.
- the write processing time will be very powerful.
- the memory card 1 that performs the continuous writing process shown in the present embodiment even when the continuous data 128 kB is divided every 2 kB and data is written, the above-mentioned 8064 k is performed.
- the data writing time of the memory card 1 can be significantly shortened, and the performance of the memory card 1 can be improved.
- the host device 2 and the memory card 1 may be connected via a memory card reader / writer 5 that controls the reading and writing of the memory card 1.
- the controller 6 provided in the memory card reader / writer 5 controls the continuous writing. This also makes it possible to greatly shorten the data writing time of the memory card 1.
- the present invention is suitable for shortening the data writing time in the memory card.
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008509627A JPWO2007116476A1 (ja) | 2006-03-31 | 2006-03-31 | メモリカードおよびデータの書き込み方法 |
US12/280,011 US20090307427A1 (en) | 2006-03-31 | 2006-03-31 | Memory card and method of writing data |
PCT/JP2006/306871 WO2007116476A1 (ja) | 2006-03-31 | 2006-03-31 | メモリカードおよびデータの書き込み方法 |
Applications Claiming Priority (1)
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PCT/JP2006/306871 WO2007116476A1 (ja) | 2006-03-31 | 2006-03-31 | メモリカードおよびデータの書き込み方法 |
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WO2007116476A1 true WO2007116476A1 (ja) | 2007-10-18 |
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PCT/JP2006/306871 WO2007116476A1 (ja) | 2006-03-31 | 2006-03-31 | メモリカードおよびデータの書き込み方法 |
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US (1) | US20090307427A1 (ja) |
JP (1) | JPWO2007116476A1 (ja) |
WO (1) | WO2007116476A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8688898B2 (en) | 2010-11-30 | 2014-04-01 | Kabushiki Kaisha Toshiba | Memory device configured to execute plural access commands in parallel and memory access method therefor |
US8799605B2 (en) | 2011-09-20 | 2014-08-05 | Kabushiki Kaisha Toshiba | Initializing and writing to a nonvolatile storage device based on a client/server model |
US8843696B2 (en) | 2011-09-21 | 2014-09-23 | Kabushiki Kaisha Toshiba | Memory device and method of controlling the same |
US9183143B2 (en) | 2011-08-01 | 2015-11-10 | Kabushiki Kaisha Toshiba | Memory device that specifies a size of a segment of write data |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120297121A1 (en) * | 2011-05-17 | 2012-11-22 | Sergey Anatolievich Gorobets | Non-Volatile Memory and Method with Small Logical Groups Distributed Among Active SLC and MLC Memory Partitions |
US9141528B2 (en) | 2011-05-17 | 2015-09-22 | Sandisk Technologies Inc. | Tracking and handling of super-hot data in non-volatile memory systems |
US9176864B2 (en) | 2011-05-17 | 2015-11-03 | SanDisk Technologies, Inc. | Non-volatile memory and method having block management with hot/cold data sorting |
KR102498223B1 (ko) * | 2015-10-13 | 2023-02-09 | 삼성전자주식회사 | Ufs 장치의 작동 방법, ufs 호스트의 작동 방법, 및 이들을 포함하는 시스템의 작동 방법 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08171622A (ja) * | 1994-12-19 | 1996-07-02 | Mitsubishi Electric Corp | Pcカード |
JP2002032256A (ja) * | 2000-07-19 | 2002-01-31 | Matsushita Electric Ind Co Ltd | 端末装置 |
JP2002324008A (ja) * | 2001-04-26 | 2002-11-08 | Tdk Corp | メモリコントローラ、メモリコントローラを備えるフラッシュメモリシステム及びフラッシュメモリの制御方法 |
WO2005041207A2 (en) * | 2003-10-29 | 2005-05-06 | Matsushita Electric Industrial Co.,Ltd. | Drive device and related computer program |
JP2005222228A (ja) * | 2004-02-04 | 2005-08-18 | Toshiba Corp | メモリカード及び半導体装置 |
-
2006
- 2006-03-31 JP JP2008509627A patent/JPWO2007116476A1/ja active Pending
- 2006-03-31 US US12/280,011 patent/US20090307427A1/en not_active Abandoned
- 2006-03-31 WO PCT/JP2006/306871 patent/WO2007116476A1/ja active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08171622A (ja) * | 1994-12-19 | 1996-07-02 | Mitsubishi Electric Corp | Pcカード |
JP2002032256A (ja) * | 2000-07-19 | 2002-01-31 | Matsushita Electric Ind Co Ltd | 端末装置 |
JP2002324008A (ja) * | 2001-04-26 | 2002-11-08 | Tdk Corp | メモリコントローラ、メモリコントローラを備えるフラッシュメモリシステム及びフラッシュメモリの制御方法 |
WO2005041207A2 (en) * | 2003-10-29 | 2005-05-06 | Matsushita Electric Industrial Co.,Ltd. | Drive device and related computer program |
JP2005222228A (ja) * | 2004-02-04 | 2005-08-18 | Toshiba Corp | メモリカード及び半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8688898B2 (en) | 2010-11-30 | 2014-04-01 | Kabushiki Kaisha Toshiba | Memory device configured to execute plural access commands in parallel and memory access method therefor |
US9183143B2 (en) | 2011-08-01 | 2015-11-10 | Kabushiki Kaisha Toshiba | Memory device that specifies a size of a segment of write data |
US8799605B2 (en) | 2011-09-20 | 2014-08-05 | Kabushiki Kaisha Toshiba | Initializing and writing to a nonvolatile storage device based on a client/server model |
US8843696B2 (en) | 2011-09-21 | 2014-09-23 | Kabushiki Kaisha Toshiba | Memory device and method of controlling the same |
Also Published As
Publication number | Publication date |
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US20090307427A1 (en) | 2009-12-10 |
JPWO2007116476A1 (ja) | 2009-08-20 |
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