WO2007108129A1 - Solid-state image sensor - Google Patents
Solid-state image sensor Download PDFInfo
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- WO2007108129A1 WO2007108129A1 PCT/JP2006/305861 JP2006305861W WO2007108129A1 WO 2007108129 A1 WO2007108129 A1 WO 2007108129A1 JP 2006305861 W JP2006305861 W JP 2006305861W WO 2007108129 A1 WO2007108129 A1 WO 2007108129A1
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- Prior art keywords
- light receiving
- shared
- circuit
- pixel
- shared circuit
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- 238000003384 imaging method Methods 0.000 claims description 22
- 238000010586 diagram Methods 0.000 description 26
- 239000002184 metal Substances 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
Definitions
- the present invention generally relates to a solid-state imaging device, and more particularly to a layout of a CMOS solid-state imaging device.
- a pixel array is formed by arranging light receiving elements made of photodiodes vertically and horizontally, and a pixel in which charges accumulated by photoelectric conversion are selected by designating rows and columns Force can also be read.
- each pixel is provided with, for example, a reading transistor (amplifier) and a transfer gate that constitute a source follower circuit. The transfer gate is opened by the selection signal, the pixel signal is amplified by the readout transistor, and the amplified pixel signal is read out through the output signal line extending in the column direction.
- Each pixel is provided with a reset transistor for resetting the light receiving element.
- the readout transistors and reset transistors are not provided on a one-to-one basis for each pixel, but for a pixel group having a plurality of pixel forces. It is preferable to provide a set of amplifiers and reset transistors.
- a circuit portion shared by a plurality of pixels is called a shared circuit.
- the transfer gate corresponding to each pixel is used to select one pixel in one pixel group, and shared to select one pixel group from a plurality of pixel groups.
- a configuration in which a selection transistor is provided as part of the circuit.
- FIG. 1 is a diagram showing an example of a conventional layout of a CMOS solid-state imaging device that shares a shared circuit with four pixels.
- the solid-state imaging device in FIG. 1 includes a light receiving unit 10, a transfer gate 11, a shared circuit 12, a shared connection signal line 13, a control signal line 14, and an output signal line 15.
- the light receiving unit 10 is formed of a photodiode, and has a charge according to input light by photoelectric conversion. Accumulate.
- the light receiving unit 10 is coupled to the shared circuit 12 via the transfer gate 11 and the shared connection signal line 13.
- four continuous light receiving units 10 arranged in a vertical line form one pixel group, and all the light receiving units 10 of one pixel group are coupled to one shared circuit 12.
- the shared circuit 12 includes a read transistor, a reset transistor, a selection transistor, and the like.
- the pixel signal read from the light receiving unit 10 via the transfer gate 11 and the shared connection signal line 13 is amplified by the read transistor of the shared circuit 12, and then output to the outside of the pixel array via the output signal line 15. Read out.
- the control signal line 14 transmits a signal for selecting the transfer gate 11, a signal for selecting the shared circuit 12, a signal for resetting the light receiving unit 10 by the reset transistor of the shared circuit 12, and the like.
- FIG. 2 is a diagram showing another example of a conventional layout of a CMOS type solid-state imaging device in which a shared circuit is shared by four pixels.
- FIG. 2 the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
- two vertically continuous pixels and two horizontally continuous pixels are combined to form one pixel group, and all the light receiving units 10 of one pixel group are combined into one shared circuit 12. Combined.
- FIGS. 1 and 2 have a problem in that the arrangement in which the intervals in the vertical direction of the light receiving portions 10 are equally spaced is not spatially uniform. In general, incident light can be detected more efficiently when the pixels are uniformly arranged at equal intervals. When the pixel spacing is not equal and non-uniform as shown in FIGS. 1 and 2, the sensitivity for detecting incident light is degraded.
- FIG. 3 is a diagram showing still another example of a conventional layout of a CMOS-type solid-state imaging device in which a shared circuit is shared by four pixels.
- the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
- FIG. 3 In the configuration of FIG. 3, four consecutive light receiving units 10 arranged in a vertical row form one pixel group, and all the light receiving units 10 of one pixel group are a pair of shared circuits 12-1 and 12. — Combined with 2. That is, one shared circuit 12 in the configuration of FIG. 1 is divided into two shared circuits 12-1 and 12-2 in the configuration of FIG. In this way, by dividing the circuit into two shared circuits 12-1 and 12-2 and distributing the space used for the shared circuit, the configuration of FIG. 3 is compared with the configuration of FIGS. 1 and 2. The intervals of the light receiving parts 10 are made closer to the same interval. [0011] With the layout of FIG. 3, the problem that the detection sensitivity of incident light is deteriorated can be avoided to some extent.
- the dispersion power of the distance from the shared circuit 12-2 to the light receiving unit at the coupling destination is larger in the configuration of FIG. 3 than in the case of FIGS. If the distance to the light receiving part force sharing circuit varies in this way, the electrical characteristics of each pixel will be different! / ⁇ , and the image quality of the captured image will be adversely affected.
- Patent Document 1 shows a configuration in which a transistor for amplifying and transferring a signal is shared by two pixels.
- Patent Document 1 Japanese Unexamined Patent Application Publication No. 2004-14802
- an object of the present invention is to provide a solid-state imaging device having a layout in which pixels are evenly arranged without adversely affecting the image quality of a captured image.
- the solid-state imaging device includes a plurality of first light receiving units arranged in one or a plurality of columns, and a plurality of second light receiving units arranged in one or a plurality of columns different from the one or the plurality of columns.
- a predetermined number of light receiving units and a plurality of first light receiving units are formed to form a plurality of pixel groups, and a first shared circuit coupled to each pixel group in a one-to-one relationship and a plurality of second light receiving units are provided.
- a predetermined number of pixels are grouped together to form a plurality of pixel groups, and each pixel group includes a second shared circuit that is coupled on a one-to-one basis. Between the two adjacent pixel groups configured by the first light receiving unit. Is characterized in that a second shared circuit is arranged.
- the shared circuit force is also received by each light receiving element while realizing uniform arrangement with pixel intervals approximately equal to each other.
- the distance to the part can be made substantially constant.
- FIG. 1 is a diagram showing an example of a conventional layout of a CMOS type solid-state imaging device that shares a shared circuit with four pixels.
- FIG. 2 is a diagram showing another example of a conventional layout of a CMOS-type solid-state imaging device that shares a shared circuit with four pixels.
- FIG. 3 is a diagram showing still another example of a conventional layout of a CMOS-type solid-state imaging device that shares a shared circuit with four pixels.
- FIG. 4 is a diagram showing an example of a configuration of a solid-state imaging device to which the present invention is applied.
- FIG. 5 is a diagram showing a first embodiment of a layout of a pixel array according to the present invention.
- FIG. 6 is a view showing the same layout as the pixel array in FIG. 5 together with a cutting line for cross-sectional illustration.
- FIG. 7 is a cross-sectional view of a pixel array cut along a cutting line AA ′ in FIG.
- FIG. 8 is a cross-sectional view of a pixel array cut along a cutting line BB ′ in FIG.
- FIG. 9 is a cross-sectional view of a pixel array cut along a cutting line CC ′ in FIG.
- FIG. 10 is a cross-sectional view of a pixel array cut along a cutting line DD ′ in FIG.
- FIG. 11 is a cross-sectional view of a pixel array cut along a cutting line EE ′ in FIG.
- FIG. 12 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- FIG. 13 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- FIG. 14 is a diagram showing a second example of the layout of the pixel array according to the present invention.
- FIG. 15 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- FIG. 16 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- FIG. 17 is a diagram showing a third embodiment of the layout of the pixel array according to the present invention.
- FIG. 18A is a diagram showing a fourth example of the layout of the pixel array according to the present invention.
- FIG. 18B is a diagram showing a fourth example of the layout of the pixel array according to the present invention. Explanation of symbols
- FIG. 4 is a diagram showing an example of the configuration of a solid-state imaging device to which the present invention is applied. 4 includes a pixel array 20, a control circuit 21, a shift register 22, a pixel control signal driver 23, a control signal line 24, an output signal line 25, a pixel readout circuit 26, and a bus circuit 27.
- the pixel array 20 is a pixel array formed by arranging light receiving elements made of photodiodes vertically and horizontally.
- the pixel array 20 is provided with a transfer gate corresponding to each pixel on a one-to-one basis, and with a shared circuit including a readout transistor, a reset transistor, and the like shared among a plurality of pixels.
- the control circuit 21 functions to read out image data from the pixel array 20 by controlling each part of the solid-state imaging device.
- the shift register 22 includes a plurality of internal registers that correspond one-to-one to a plurality of rows of the pixel array 20, and the internal registers are connected in series to form a shift register. Is configured.
- the shift register 22 operates under the control of the control circuit 21 and functions to sequentially select the rows of the pixel array 20 by sequentially shifting the register storage data.
- the pixel control signal driver 23 drives the control signal line 24 corresponding to the row specified by the shift register 22, and outputs a pixel signal for one row from the pixel corresponding to the specified row in the pixel array 20. read out.
- the read pixel signal is supplied to the pixel readout circuit 26 via the output signal line 25.
- the pixel readout circuit 26 functions to read out an image signal while reducing noise by, for example, a noise cancellation circuit.
- the image signal for one row read by the pixel reading circuit 26 is supplied to the control circuit 21 via the bus circuit 27 while sequentially selecting pixels in the horizontal direction.
- FIG. 5 is a diagram showing a first example of the layout of the pixel array according to the present invention.
- the pixel array 20 in FIG. 5 includes a light receiving unit 30, a transfer gate 31, a shared circuit 32, a shared connection signal line 33, a control signal line 34, and an output signal line 35.
- the light receiving unit 30 includes a photodiode, and accumulates electric charge having a strength corresponding to input light by photoelectric conversion.
- the light receiving unit 30 is coupled to the shared circuit 32 via the transfer gate 31 and the shared connection signal line 33.
- four continuous light receiving units 30 arranged in a vertical line form one pixel group, and all the light receiving units 30 of one pixel group are coupled to one shared circuit 32.
- the shared circuit 32 includes a read transistor and a reset transistor, and may further include a selection transistor.
- the pixel signal read from the light receiving unit 30 via the transfer gate 31 and the shared connection signal line 33 is amplified by the read transistor of the shared circuit 32, and then output to the outside of the pixel array via the output signal line 35. Read out.
- the control signal line 34 transmits a signal for selecting the transfer gate 31, a signal for selecting the shared circuit 32, a signal for resetting the light receiving unit 30 by the reset transistor of the shared circuit 32, and the like.
- the pixel array 20 in FIG. 5 further includes a light receiving unit 40, a transfer gate 41, a shared circuit 42, and a shared connection signal line 43.
- the light receiving unit 40, the transfer gate 41, the shared circuit 42, and the shared connection signal line 43 are circuit elements equivalent to the light receiving unit 30, the transfer gate 31, the shared circuit 32, and the shared connection signal line 33, respectively.
- There are four receivers 40 One pixel group is formed and coupled to one shared circuit 42.
- the pixel array 20 in FIG. 5 further includes a light receiving unit 50, a transfer gate 51, a shared circuit 52, and a shared connection signal line 53.
- the light receiving unit 50, the transfer gate 51, the shared circuit 52, and the shared connection signal line 53 are circuit elements equivalent to the light receiving unit 30, the transfer gate 31, the shared circuit 32, and the shared connection signal line 33, respectively. .
- Four light receiving portions 50 form one pixel group and are coupled to one shared circuit 52.
- the light receiving units arranged in a predetermined row.
- a predetermined number (4) of (30, 50) are grouped together to form a plurality of pixel groups, and each pixel group is coupled to a corresponding shared circuit (32, 52).
- a predetermined number (4) of light receiving units (40) arranged in other rows are grouped between two adjacent pixel groups (that is, a pixel group including the light receiving unit 30 and a pixel group including the light receiving unit 50).
- a shared circuit (42) coupled to the pixel group formed in this manner is disposed.
- FIG. 6 is a diagram showing the same layout as the pixel array in FIG. 5 together with a cutting line for cross-sectional illustration.
- the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted.
- each circuit element corresponding to an odd-numbered pixel column is shown as a light receiving unit 30, a transfer gate 31, a shared circuit 32, and a shared connection signal line 33, and each circuit element corresponding to an even-numbered pixel column Elements are shown as a light receiving unit 40, a transfer gate 41, a shared circuit 42, and a signal line 43 for shared connection.
- FIG. 7 is a cross-sectional view of the pixel array cut along the cutting line AA ′ in FIG.
- the same elements as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.
- the light receiving unit 30 and the shared circuit 32 are formed in the diffusion layer of the semiconductor substrate 60.
- a transfer gate 31 is formed in the polysilicon layer on the semiconductor substrate 60, and a control signal line 34 is formed in the first metal layer thereon.
- FIG. 6 only shows the approximate position and direction of the control signal line 34; in practice, one transfer gate 31 (one on the drawing is shown) as shown in FIG. In reality, one control signal line is provided for a plurality of transfer gates 31) on the same row.
- a shared connection signal line 33 is formed in the second metal layer on the first metal layer. Common with signal line 33 for shared connection The circuit 32 and the shared connection signal line 33 and the diffusion layer 62 of the transfer gate 31 (the drain end of the transistor constituting the transfer gate) are connected via the contact hole 61, respectively.
- FIG. 8 is a cross-sectional view of the pixel array taken along the cutting line BB ′ of FIG.
- the same components as those in FIGS. 6 and 7 are referred to by the same numerals, and a description thereof will be omitted.
- control signal line 34 and the transfer gate 31 the gate end of the transistor constituting the transfer gate
- control signal line 34 and the shared circuit 32 respectively.
- a shared connection signal line 33 is formed on the second metal layer above the first metal layer.
- FIG. 9 is a cross-sectional view of the pixel array taken along the cutting line CC ′ of FIG. 9, the same components as those in FIGS. 6 to 8 are referred to by the same numerals, and a description thereof will be omitted.
- an output signal line 35 is formed in the second metal layer.
- FIG. 10 is a cross-sectional view of the pixel array cut along the cutting line DD ′ in FIG. In Figure 10
- the light receiving unit 30 and the light receiving unit 40 are formed on the semiconductor substrate 60.
- an output signal line 35 and a shared connection signal line 43 for the light receiving unit 40 are formed.
- FIG. 11 is a cross-sectional view of the pixel array cut along the cutting line EE ′ of FIG.
- the same components as those in FIGS. 6 to 10 are referred to by the same numerals, and a description thereof will be omitted.
- Transfer gates 31 and 41 are formed in the polysilicon layer. In this case, the cut surface and the extending direction of the transfer gates 31 and 41 are the same, and the transfer gates 31 and 41 are continuously provided as one polysilicon electrode from the end to the end of the drawing.
- a control signal line 34 is formed in the first metal layer on the polysilicon layer. The control signal line 34 and the transfer gates 31 and 41 are coupled by a contact hole 65 at the position of each transfer gate.
- FIG. 12 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- the transfer gates 31 are provided in one-to-one correspondence with the light receiving units 30. Control signals TG1 to TG4 are supplied to the gate ends of the four transfer gates 31.
- the shared circuit 32 includes a read transistor 71 and a reset transistor 72.
- the read transistor 71 has a source terminal coupled to the reference potential VR and a drain terminal coupled to the output signal line 35.
- the control signals TG 1 to TG 4 becomes HIGH
- the corresponding transfer gate 31 becomes conductive, and the charge of the corresponding light receiving unit 30 is supplied to the gate terminal of the read transistor 71.
- a voltage depending on the charge amount of the light receiving unit 30 appears on the output signal line 35. In this way, the pixel signal of the selected pixel can be read out.
- the reset transistor 72 is turned on when the reset signal RST becomes HIGH, and resets the selected light receiving unit 30 to the reference voltage VR. By such a reset operation, each pixel of the pixel array 20 can be set to the same initial state.
- FIG. 13 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- the same elements as those of FIG. 12 are referred to by the same numerals, and a description thereof will be omitted.
- the shared circuit 32 further includes a selection transistor 73 in addition to the read transistor 71 and the reset transistor 72.
- the selection transistor 73 is inserted so as to be connected in series to the read transistor 71, and a selection signal SEL is applied to the gate terminal thereof.
- the selection signal SEL becomes HIGH, the read pixel signal of the shared circuit 32 is supplied to the output signal line 35.
- FIG. 14 is a diagram showing a second example of the layout of the pixel array according to the present invention. 14 includes a light receiving unit 130, a transfer gate 131, a shared circuit 132, a control signal line 134, and an output signal line 135.
- the light receiving unit 130 includes a photodiode, and accumulates a charge having a strength corresponding to input light by photoelectric conversion.
- the light receiving unit 130 is coupled to the shared circuit 132 via the transfer gate 131.
- four light receiving units 130 force S are arranged side by side in the vertical direction and two in the horizontal direction.
- One pixel group is formed.
- the shared circuit 132 includes a read transistor and a reset transistor, and may further include a selection transistor.
- the pixel signal read from the light receiving unit 130 via the transfer gate 131 is amplified by the reading transistor of the shared circuit 132 and then read out to the outside of the pixel array via the output signal line 135.
- the control signal line 134 transmits a signal for selecting the transfer gate 131, a signal for selecting the shared circuit 132, a signal for resetting the light receiving unit 130 by the reset transistor of the shared circuit 132, and the like.
- the pixel array in FIG. 14 further includes a light receiving unit 140, a transfer gate 141, and a shared circuit 142.
- the light receiving unit 140, the transfer gate 141, and the shared circuit 142 are circuit elements equivalent to the light receiving unit 130, the transfer gate 131, and the shared circuit 132, respectively.
- Four light receiving portions 140 form one pixel group and are coupled to one shared circuit 142.
- the pixel array in FIG. 14 further includes a light receiving unit 150, a transfer gate 151, and a shared circuit 152.
- the light receiving unit 150, the transfer gate 151, and the shared circuit 152 are circuit elements equivalent to the light receiving unit 130, the transfer gate 131, and the shared circuit 132, respectively.
- Four light receiving portions 150 form one pixel group and are coupled to one shared circuit 152.
- a predetermined number (four) of light receiving sections (130, 150) arranged in a predetermined row (predetermined two rows) are collected.
- a plurality of pixel groups are formed, and each pixel group is coupled to a corresponding shared circuit (132, 152).
- a predetermined number of light receiving units (140) arranged in other columns are provided.
- a shared circuit (142) that is coupled to a pixel group formed by collecting (four) each is arranged.
- FIG. 15 is a diagram illustrating an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array illustrated in FIG.
- four light receiving sections 130 that are photodiodes are coupled to a shared circuit 132 via a transfer gate 131 that is a transistor.
- the transfer gates 131 are provided in one-to-one correspondence with the respective light receiving units 130.
- Four Control signals TGI to TG4 are supplied to the gate end of the transfer gate 131.
- the shared circuit 132 includes a read transistor 171 and a reset transistor 172.
- Read transistor 171 has a source terminal coupled to reference potential VR and a drain terminal coupled to output signal line 135.
- the control signals TG 1 to TG 4 becomes HIGH
- the corresponding transfer gate 131 becomes conductive, and the charge of the corresponding light receiving unit 130 is supplied to the gate terminal of the reading transistor 171.
- a voltage depending on the charge amount of the light receiving unit 130 appears on the output signal line 135. In this way, the pixel signal of the selected pixel can be read out.
- each pixel in the pixel array can be set to the same initial state.
- FIG. 16 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
- the same elements as those of FIG. 15 are referred to by the same numerals, and a description thereof will be omitted.
- the shared circuit 132 further includes a selection transistor 173 in addition to the read transistor 171 and the reset transistor 172.
- the selection transistor 173 is inserted so as to be connected in series with the readout transistor 171 and a selection signal SEL is applied to the gate end thereof.
- the selection signal SEL becomes HIGH, the readout pixel signal of the shared circuit 132 is supplied to the output signal line 135.
- FIG. 17 is a diagram showing a third example of the layout of the pixel array according to the present invention.
- two pixels are combined into one pixel group, and one shared circuit is assigned to each pixel group one-on-one.
- the pixel array in FIG. 17 includes a light receiving unit 230, a transfer gate 231, a shared circuit 232, a control signal line 234, and an output signal line 235.
- the configuration and function of each circuit element are the same as those in the first and second embodiments, and a description thereof will be omitted.
- the shared circuit 2 32 includes a read transistor and a reset transistor, and further includes a selection transistor. May include a transistor.
- the pixel array in FIG. 17 further includes a light receiving unit 240, a transfer gate 241, and a shared circuit 242.
- the light receiving unit 240, the transfer gate 241 and the shared circuit 242 are circuit elements equivalent to the light receiving unit 230, the transfer gate 231 and the shared circuit 232, respectively.
- Two light receiving units 240 form one pixel group and are coupled to one shared circuit 242.
- the pixel array in FIG. 17 further includes a light receiving unit 250, a transfer gate 251, and a shared circuit 252.
- the light receiving unit 250, the transfer gate 251 and the shared circuit 252 are circuit elements equivalent to the light receiving unit 230, the transfer gate 231 and the shared circuit 232, respectively.
- Two light receiving portions 250 form one pixel group and are coupled to one shared circuit 252.
- a plurality of pixel groups are formed by collecting a predetermined number (two) of light receiving portions (230, 250) arranged in a predetermined row. Then, each pixel group is coupled to the corresponding shared circuit (232, 252). In addition, a predetermined number (two) of light receiving units (24 0) arranged in other rows are arranged between two adjacent pixel groups (that is, a pixel group including the light receiving unit 230 and a pixel group including the light receiving unit 250). A shared circuit (242) coupled to the pixel group formed together is arranged.
- FIG. 18A and FIG. 18B are diagrams showing a fourth embodiment of the layout of the pixel array according to the present invention.
- the pixel array layout shown in FIG. 18A and the pixel array layout shown in FIG. 18B are divided into two parts for the sake of illustration. Actually, the pixel array layout is shown in FIG. One pixel array layout is configured.
- eight pixels are grouped into one pixel group, and one shared circuit is assigned to each pixel group on a one-to-one basis.
- the pixel arrays in FIGS. 18A and 18B include a light receiving unit 330, a transfer gate 331, a shared circuit 332, a shared connection signal line 333, a control signal line 334, and an output signal line 335.
- the configuration and function of each circuit element are the same as those in the first to third embodiments, and the description thereof is omitted.
- the shared circuit 332 includes a read transistor and a reset transistor, and further includes a selection transistor. May include a transistor.
- the pixel arrays in FIGS. 18A and 18B further include eight light receiving portions 340, a transfer gate 341, a shared circuit 342, and a shared connection signal line 343 that are continuously arranged in a vertical line.
- the light receiving unit 340, the transfer gate 341, the shared circuit 342, and the shared connection signal line 343 are circuit elements equivalent to the light receiving unit 330, the transfer gate 331, the shared circuit 332, and the shared connection signal line 333, respectively.
- These eight light receiving units 340 form one pixel group and are coupled to one shared circuit 342.
- the pixel arrays in FIGS. 18A and 18B further include a light receiving unit 350, a transfer gate 351, a shared circuit 352, and a shared connection signal line 353 that are continuously arranged in a vertical line.
- the light receiving unit 350, the transfer gate 351, the shared circuit 352, and the shared connection signal line 353 are circuit elements equivalent to the light receiving unit 330, the transfer gate 331, the shared circuit 332, and the shared connection signal line 333, respectively.
- These eight light receiving parts 350 form one pixel group and are coupled to one shared circuit 352.
- a plurality of pixels in which a predetermined number (eight) of light receiving portions (330, 350) arranged in a predetermined row are grouped.
- a group is formed, and each pixel group is coupled to a corresponding shared circuit (332, 352).
- a predetermined number (eight) of light receiving units (340) arranged in other rows are grouped between two adjacent pixel groups (that is, a pixel group including the light receiving unit 330 and a pixel group including the light receiving unit 350).
- a shared circuit (342) coupled to the formed pixel group is disposed.
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Abstract
A solid-state image sensor comprises: a plurality of first light-receptive portions arranged in one or more rows; a plurality of second light-receptive portions arranged in one or more rows different from the aforementioned one or more rows; a first shared circuit which is one-to-one connected to each of pixel groups formed by combining a predetermined number of first light-receptive portions; and a second shared circuit which is one-to-one connected to each of pixel groups formed by combining a predetermined number of second light-receptive portions. The solid-state image sensor is characterized in that the second shared circuit is arranged between the two adjacent pixel groups composed of the first light-receptive portions.
Description
固体撮像素子 Solid-state image sensor
技術分野 Technical field
[0001] 本発明は、一般に固体撮像素子に関し、詳しくは、 CMOS型固体撮像素子のレイ アウトに関する。 TECHNICAL FIELD [0001] The present invention generally relates to a solid-state imaging device, and more particularly to a layout of a CMOS solid-state imaging device.
背景技術 Background art
[0002] CMOS型固体撮像素子においては、フォトダイオードからなる受光素子を縦横に 配置することで画素配列を形成してあり、光電変換で蓄積された電荷を、行及び列 の指定により選択した画素力も読み出すことができる。一般に、各画素には例えばソ 一スフォロワ回路を構成する読み出し用トランジスタ (増幅器)やトランスファーゲート が付随して設けられている。選択信号によりトランスファーゲートを開き、読み出し用ト ランジスタで画素信号を増幅し、列方向に延びる出力信号線を介して増幅後の画素 信号を読み出す。また各画素には、受光素子をリセットするためのリセット用トランジス タが設けられている。 In a CMOS type solid-state imaging device, a pixel array is formed by arranging light receiving elements made of photodiodes vertically and horizontally, and a pixel in which charges accumulated by photoelectric conversion are selected by designating rows and columns Force can also be read. In general, each pixel is provided with, for example, a reading transistor (amplifier) and a transfer gate that constitute a source follower circuit. The transfer gate is opened by the selection signal, the pixel signal is amplified by the readout transistor, and the amplified pixel signal is read out through the output signal line extending in the column direction. Each pixel is provided with a reset transistor for resetting the light receiving element.
[0003] 画素間隔を狭めるとともに回路規模を削減するためには、上記読み出し用トランジ スタ及びリセット用トランジスタ等を各画素に対して一対一に設けるのではなく、複数 の画素力 なる画素群に対して 1セットの増幅器及びリセット用トランジスタ等を設ける ことが好ましい。このように複数の画素で共有される回路部分を、本願では共有回路 と呼ぶ。この場合、各画素に一対一に対応するトランスファーゲートは 1つの画素群 のなかで 1つの画素を選択するために使用し、複数の画素群の中から 1つの画素群 を選択するために、共有回路の一部として選択用トランジスタを設ける構成としてよ ヽ In order to reduce the pixel interval and reduce the circuit scale, the readout transistors and reset transistors are not provided on a one-to-one basis for each pixel, but for a pixel group having a plurality of pixel forces. It is preferable to provide a set of amplifiers and reset transistors. In this application, a circuit portion shared by a plurality of pixels is called a shared circuit. In this case, the transfer gate corresponding to each pixel is used to select one pixel in one pixel group, and shared to select one pixel group from a plurality of pixel groups. A configuration in which a selection transistor is provided as part of the circuit.
[0004] 図 1は、 4つの画素で共有回路を共有する CMOS型固体撮像素子の従来のレイァ ゥトの一例を示す図である。図 1の固体撮像素子は、受光部 10、トランスファーゲート 11、共有回路 12、共有接続用信号線 13、制御信号線 14、及び出力信号線 15を含 む。 FIG. 1 is a diagram showing an example of a conventional layout of a CMOS solid-state imaging device that shares a shared circuit with four pixels. The solid-state imaging device in FIG. 1 includes a light receiving unit 10, a transfer gate 11, a shared circuit 12, a shared connection signal line 13, a control signal line 14, and an output signal line 15.
[0005] 受光部 10は、フォトダイオードからなり、光電変換により入力光に応じた強さの電荷
を蓄積する。受光部 10は、トランスファーゲート 11及び共有接続用信号線 13を介し て、共有回路 12に結合される。図 1の構成では、縦一列に並ぶ 4つの連続する受光 部 10が 1つの画素群を形成し、 1つの画素群の全ての受光部 10が 1つの共有回路 1 2に結合される。共有回路 12は、読み出し用トランジスタ、リセット用トランジスタ、選 択用トランジスタ等を含む。 [0005] The light receiving unit 10 is formed of a photodiode, and has a charge according to input light by photoelectric conversion. Accumulate. The light receiving unit 10 is coupled to the shared circuit 12 via the transfer gate 11 and the shared connection signal line 13. In the configuration of FIG. 1, four continuous light receiving units 10 arranged in a vertical line form one pixel group, and all the light receiving units 10 of one pixel group are coupled to one shared circuit 12. The shared circuit 12 includes a read transistor, a reset transistor, a selection transistor, and the like.
[0006] トランスファーゲート 11及び共有接続用信号線 13を介して受光部 10から読み出さ れた画素信号は、共有回路 12の読み出し用トランジスタにより増幅され、その後出力 信号線 15を介して画素配列外部に読み出される。制御信号線 14は、トランスファー ゲート 11を選択するための信号、共有回路 12を選択するための信号、共有回路 12 のリセット用トランジスタにより受光部 10をリセットするための信号等を伝送する。 [0006] The pixel signal read from the light receiving unit 10 via the transfer gate 11 and the shared connection signal line 13 is amplified by the read transistor of the shared circuit 12, and then output to the outside of the pixel array via the output signal line 15. Read out. The control signal line 14 transmits a signal for selecting the transfer gate 11, a signal for selecting the shared circuit 12, a signal for resetting the light receiving unit 10 by the reset transistor of the shared circuit 12, and the like.
[0007] 図 2は、 4つの画素で共有回路を共有する CMOS型固体撮像素子の従来のレイァ ゥトの別の一例を示す図である。図 2において、図 1と同一の構成要素は同一の番号 で参照し、その説明は省略する。図 2のレイアウトでは、 2つの縦に連続する画素及 び 2つの横に連続する画素を纏めて 1つの画素群を形成し、 1つの画素群の全ての 受光部 10が 1つの共有回路 12に結合される。 FIG. 2 is a diagram showing another example of a conventional layout of a CMOS type solid-state imaging device in which a shared circuit is shared by four pixels. In FIG. 2, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. In the layout of FIG. 2, two vertically continuous pixels and two horizontally continuous pixels are combined to form one pixel group, and all the light receiving units 10 of one pixel group are combined into one shared circuit 12. Combined.
[0008] 図 1及び図 2のレイアウトでは、受光部 10の縦方向の間隔が等間隔でなぐ配置が 空間的に均一でないという問題がある。一般に、画素が等間隔で均一な配置の方が 、入射光を効率的に検出することができる。図 1及び図 2のように画素間隔が等しくな く不均一な配置の場合、入射光を検出する感度が劣化してしまう。 [0008] The layouts of FIGS. 1 and 2 have a problem in that the arrangement in which the intervals in the vertical direction of the light receiving portions 10 are equally spaced is not spatially uniform. In general, incident light can be detected more efficiently when the pixels are uniformly arranged at equal intervals. When the pixel spacing is not equal and non-uniform as shown in FIGS. 1 and 2, the sensitivity for detecting incident light is degraded.
[0009] 図 3は、 4つの画素で共有回路を共有する CMOS型固体撮像素子の従来のレイァ ゥトの更に別の一例を示す図である。図 3において、図 1と同一の構成要素は同一の 番号で参照し、その説明は省略する。 FIG. 3 is a diagram showing still another example of a conventional layout of a CMOS-type solid-state imaging device in which a shared circuit is shared by four pixels. In FIG. 3, the same components as those in FIG. 1 are referred to by the same numerals, and a description thereof will be omitted.
[0010] 図 3の構成では、縦一列に並ぶ 4つの連続する受光部 10が 1つの画素群を形成し 、 1つの画素群の全ての受光部 10がー対の共有回路 12— 1及び 12— 2に結合され る。即ち、図 1の構成における 1つの共有回路 12が、図 3の構成では、 2つの共有回 路 12— 1及び 12— 2に分割されている。このように 2つの共有回路 12—1及び 12— 2に回路を分割して、共有回路に使用するスペースを分散することにより、図 3の構成 では、図 1及び図 2の構成と比較して受光部 10の間隔をより等間隔に近づけている。
[0011] 図 3のレイアウトにより、入射光の検出感度が劣化してしまうという問題はある程度回 避することができる。し力 共有回路を効率的に 2等分できるとは限らず、共有回路に 使用する面積が増大してしまう。また共有回路 12— 2から結合先の受光部までの距 離のばらつき力 図 1及び図 2の場合と比較して、図 3の構成では大きくなつてしまう。 このように受光部力 共有回路までの距離にばらつきがあると、画素毎に電気特性が 異なってしま!/ヽ、撮像画像の画質に悪影響をもたらすことになる。 In the configuration of FIG. 3, four consecutive light receiving units 10 arranged in a vertical row form one pixel group, and all the light receiving units 10 of one pixel group are a pair of shared circuits 12-1 and 12. — Combined with 2. That is, one shared circuit 12 in the configuration of FIG. 1 is divided into two shared circuits 12-1 and 12-2 in the configuration of FIG. In this way, by dividing the circuit into two shared circuits 12-1 and 12-2 and distributing the space used for the shared circuit, the configuration of FIG. 3 is compared with the configuration of FIGS. 1 and 2. The intervals of the light receiving parts 10 are made closer to the same interval. [0011] With the layout of FIG. 3, the problem that the detection sensitivity of incident light is deteriorated can be avoided to some extent. However, it is not always possible to bisect the shared circuit efficiently, and the area used for the shared circuit increases. In addition, the dispersion power of the distance from the shared circuit 12-2 to the light receiving unit at the coupling destination is larger in the configuration of FIG. 3 than in the case of FIGS. If the distance to the light receiving part force sharing circuit varies in this way, the electrical characteristics of each pixel will be different! / ヽ, and the image quality of the captured image will be adversely affected.
[0012] なお関連技術の一例として、特許文献 1には、信号を増幅し転送するトランジスタを 2つの画素で共有する構成が示される。 As an example of related art, Patent Document 1 shows a configuration in which a transistor for amplifying and transferring a signal is shared by two pixels.
(特許文献 1) 特開 2004— 14802号公報 (Patent Document 1) Japanese Unexamined Patent Application Publication No. 2004-14802
発明の開示 Disclosure of the invention
発明が解決しょうとする課題 Problems to be solved by the invention
[0013] 以上を鑑みて本発明では、撮像画像の画質に悪影響をもたらすことになく画素を 均等に配置したレイアウトを有する固体撮像素子を提供することを目的とする。 In view of the above, an object of the present invention is to provide a solid-state imaging device having a layout in which pixels are evenly arranged without adversely affecting the image quality of a captured image.
課題を解決するための手段 Means for solving the problem
[0014] 固体撮像素子は、一又は複数の列に配置された複数の第 1の受光部と、前記一又 は複数の列とは異なる一又は複数の列に配置された複数の第 2の受光部と、複数の 第 1の受光部を所定個数ずつ纏めて複数の画素群を形成し、各画素群に一対一に 結合される第 1の共有回路と、複数の第 2の受光部を所定個数ずつ纏めて複数の画 素群を形成し、各画素群に一対一に結合される第 2の共有回路を含み、第 1の受光 部から構成される 2つの隣接する画素群の間には第 2の共有回路が配置されることを 特徴とする。 [0014] The solid-state imaging device includes a plurality of first light receiving units arranged in one or a plurality of columns, and a plurality of second light receiving units arranged in one or a plurality of columns different from the one or the plurality of columns. A predetermined number of light receiving units and a plurality of first light receiving units are formed to form a plurality of pixel groups, and a first shared circuit coupled to each pixel group in a one-to-one relationship and a plurality of second light receiving units are provided. A predetermined number of pixels are grouped together to form a plurality of pixel groups, and each pixel group includes a second shared circuit that is coupled on a one-to-one basis. Between the two adjacent pixel groups configured by the first light receiving unit. Is characterized in that a second shared circuit is arranged.
発明の効果 The invention's effect
[0015] 本発明による少なくとも 1つの実施例においては、固体撮像素子を上記のような構 成とすることで、画素間隔を略等間隔として均一な配置を実現しながらも、共有回路 力も各受光部までの距離を略一定とすることができる。これにより、撮像画像の画質 に悪影響をもたらすことになく画素を均等に配置したレイアウトを実現し、入射光の検 出に関して高感度な固体撮像素子を提供することができる。
図面の簡単な説明 In at least one embodiment according to the present invention, by configuring the solid-state imaging device as described above, the shared circuit force is also received by each light receiving element while realizing uniform arrangement with pixel intervals approximately equal to each other. The distance to the part can be made substantially constant. As a result, it is possible to realize a layout in which pixels are arranged uniformly without adversely affecting the image quality of a captured image, and to provide a solid-state imaging device that is highly sensitive with respect to detection of incident light. Brief Description of Drawings
[図 1]4つの画素で共有回路を共有する CMOS型固体撮像素子の従来のレイアウト の一例を示す図である。 FIG. 1 is a diagram showing an example of a conventional layout of a CMOS type solid-state imaging device that shares a shared circuit with four pixels.
[図 2]4つの画素で共有回路を共有する CMOS型固体撮像素子の従来のレイアウト の別の一例を示す図である。 FIG. 2 is a diagram showing another example of a conventional layout of a CMOS-type solid-state imaging device that shares a shared circuit with four pixels.
[図 3]4つの画素で共有回路を共有する CMOS型固体撮像素子の従来のレイアウト の更に別の一例を示す図である。 FIG. 3 is a diagram showing still another example of a conventional layout of a CMOS-type solid-state imaging device that shares a shared circuit with four pixels.
[図 4]本発明を適用する固体撮像素子の構成の一例を示す図である。 FIG. 4 is a diagram showing an example of a configuration of a solid-state imaging device to which the present invention is applied.
[図 5]本発明による画素配列のレイアウトの第 1の実施例を示す図である。 FIG. 5 is a diagram showing a first embodiment of a layout of a pixel array according to the present invention.
[図 6]図 5の画素配列と同一のレイアウトを断面図示用の切断線とともに示す図である 6 is a view showing the same layout as the pixel array in FIG. 5 together with a cutting line for cross-sectional illustration.
[図 7]図 6の切断線 A—A'で切断した画素配列の断面図である。 7 is a cross-sectional view of a pixel array cut along a cutting line AA ′ in FIG.
[図 8]図 6の切断線 B— B'で切断した画素配列の断面図である。 FIG. 8 is a cross-sectional view of a pixel array cut along a cutting line BB ′ in FIG.
[図 9]図 6の切断線 C C'で切断した画素配列の断面図である。 FIG. 9 is a cross-sectional view of a pixel array cut along a cutting line CC ′ in FIG.
[図 10]図 6の切断線 D— D'で切断した画素配列の断面図である。 10 is a cross-sectional view of a pixel array cut along a cutting line DD ′ in FIG.
[図 11]図 6の切断線 E—E'で切断した画素配列の断面図である。 FIG. 11 is a cross-sectional view of a pixel array cut along a cutting line EE ′ in FIG.
[図 12]図 5に示す画素配列における 1つの画素群に対応する回路の等価回路の一 例を示す図である。 12 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
[図 13]図 5に示す画素配列における 1つの画素群に対応する回路の等価回路の別 の一例を示す図である。 13 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
[図 14]本発明による画素配列のレイアウトの第 2の実施例を示す図である。 FIG. 14 is a diagram showing a second example of the layout of the pixel array according to the present invention.
[図 15]図 14に示す画素配列における 1つの画素群に対応する回路の等価回路の一 例を示す図である。 15 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
[図 16]図 14に示す画素配列における 1つの画素群に対応する回路の等価回路の別 の一例を示す図である。 FIG. 16 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG.
[図 17]本発明による画素配列のレイアウトの第 3の実施例を示す図である。 FIG. 17 is a diagram showing a third embodiment of the layout of the pixel array according to the present invention.
[図 18A]本発明による画素配列のレイアウトの第 4の実施例を示す図である。 FIG. 18A is a diagram showing a fourth example of the layout of the pixel array according to the present invention.
[図 18B]本発明による画素配列のレイアウトの第 4の実施例を示す図である。
符号の説明 FIG. 18B is a diagram showing a fourth example of the layout of the pixel array according to the present invention. Explanation of symbols
20 画素配列 20 pixel array
21 制御回路 21 Control circuit
22 シフトレジスタ 22 Shift register
23 画素制御信号ドライバ 23 Pixel control signal driver
24 制御信号線 24 Control signal line
25 出力信号線 25 Output signal line
26 画素読出回路 26 Pixel readout circuit
27 バス回路 27 Bus circuit
30, 40, 50 受光部 30, 40, 50 Receiver
31, 41, 51 トランスファーゲート 31, 41, 51 Transfer gate
32, 42, 52 共有回路 32, 42, 52 Shared circuit
33, 43, 53 共有接続用信号線 33, 43, 53 Shared connection signal line
34 制御信号線 34 Control signal line
35 出力信号線 35 Output signal line
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
[0018] 以下に、本発明の実施例を添付の図面を用いて詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0019] 図 4は、本発明を適用する固体撮像素子の構成の一例を示す図である。図 4の固 体撮像素子は、画素配列 20、制御回路 21、シフトレジスタ 22、画素制御信号ドライ ノ 23、制御信号線 24、出力信号線 25、画素読出回路 26、及びバス回路 27を含む FIG. 4 is a diagram showing an example of the configuration of a solid-state imaging device to which the present invention is applied. 4 includes a pixel array 20, a control circuit 21, a shift register 22, a pixel control signal driver 23, a control signal line 24, an output signal line 25, a pixel readout circuit 26, and a bus circuit 27.
[0020] 画素配列 20は、フォトダイオードからなる受光素子を縦横に配置することで画素配 列を形成したものである。画素配列 20には、各画素に一対一に対応したトランスファ 一ゲートが設けられるとともに、複数の画素間で共有される読み出し用トランジスタや リセット用トランジスタ等を含む共有回路が設けられる。 The pixel array 20 is a pixel array formed by arranging light receiving elements made of photodiodes vertically and horizontally. The pixel array 20 is provided with a transfer gate corresponding to each pixel on a one-to-one basis, and with a shared circuit including a readout transistor, a reset transistor, and the like shared among a plurality of pixels.
[0021] 制御回路 21は、固体撮像素子の各部を制御して、画素配列 20から画像データを 読み出すよう機能する。シフトレジスタ 22は、画素配列 20の複数の行に一対一に対 応する複数の内部レジスタを含み、この内部レジスタを直列に接続してシフトレジスタ
を構成したものである。シフトレジスタ 22は、制御回路 21の制御の下で動作してレジ スタ格納データを順次シフトさせることにより、画素配列 20の行を順次選択するよう機 能する。 The control circuit 21 functions to read out image data from the pixel array 20 by controlling each part of the solid-state imaging device. The shift register 22 includes a plurality of internal registers that correspond one-to-one to a plurality of rows of the pixel array 20, and the internal registers are connected in series to form a shift register. Is configured. The shift register 22 operates under the control of the control circuit 21 and functions to sequentially select the rows of the pixel array 20 by sequentially shifting the register storage data.
[0022] 画素制御信号ドライバ 23は、シフトレジスタ 22が指定する行に対応する制御信号 線 24を駆動して、画素配列 20中の指定する行に対応する画素から 1行分の画素信 号を読み出す。読み出された画素信号は、出力信号線 25を介して画素読出回路 26 に供給される。画素読出回路 26は、例えばノイズキャンセル回路等により、ノイズを 軽減しつつ画像信号を読み出すよう機能する。画素読出回路 26により読み出された 1行分の画像信号は、水平方向に順次画素を選択するようにしながら、バス回路 27 を介して制御回路 21に供給される。 The pixel control signal driver 23 drives the control signal line 24 corresponding to the row specified by the shift register 22, and outputs a pixel signal for one row from the pixel corresponding to the specified row in the pixel array 20. read out. The read pixel signal is supplied to the pixel readout circuit 26 via the output signal line 25. The pixel readout circuit 26 functions to read out an image signal while reducing noise by, for example, a noise cancellation circuit. The image signal for one row read by the pixel reading circuit 26 is supplied to the control circuit 21 via the bus circuit 27 while sequentially selecting pixels in the horizontal direction.
[0023] 図 5は、本発明による画素配列のレイアウトの第 1の実施例を示す図である。図 5の 画素配列 20は、受光部 30、トランスファーゲート 31、共有回路 32、共有接続用信号 線 33、制御信号線 34、及び出力信号線 35を含む。 FIG. 5 is a diagram showing a first example of the layout of the pixel array according to the present invention. The pixel array 20 in FIG. 5 includes a light receiving unit 30, a transfer gate 31, a shared circuit 32, a shared connection signal line 33, a control signal line 34, and an output signal line 35.
[0024] 受光部 30は、フォトダイオードからなり、光電変換により入力光に応じた強さの電荷 を蓄積する。受光部 30は、トランスファーゲート 31及び共有接続用信号線 33を介し て、共有回路 32に結合される。図 5の構成では、縦一列に並ぶ 4つの連続する受光 部 30が 1つの画素群を形成し、 1つの画素群の全ての受光部 30が 1つの共有回路 3 2に結合される。共有回路 32は、読み出し用トランジスタ及びリセット用トランジスタを 含み、また更に選択用トランジスタを含んでよい。 [0024] The light receiving unit 30 includes a photodiode, and accumulates electric charge having a strength corresponding to input light by photoelectric conversion. The light receiving unit 30 is coupled to the shared circuit 32 via the transfer gate 31 and the shared connection signal line 33. In the configuration of FIG. 5, four continuous light receiving units 30 arranged in a vertical line form one pixel group, and all the light receiving units 30 of one pixel group are coupled to one shared circuit 32. The shared circuit 32 includes a read transistor and a reset transistor, and may further include a selection transistor.
[0025] トランスファーゲート 31及び共有接続用信号線 33を介して受光部 30から読み出さ れた画素信号は、共有回路 32の読み出し用トランジスタにより増幅され、その後出力 信号線 35を介して画素配列外部に読み出される。制御信号線 34は、トランスファー ゲート 31を選択するための信号、共有回路 32を選択するための信号、共有回路 32 のリセット用トランジスタにより受光部 30をリセットするための信号等を伝送する。 The pixel signal read from the light receiving unit 30 via the transfer gate 31 and the shared connection signal line 33 is amplified by the read transistor of the shared circuit 32, and then output to the outside of the pixel array via the output signal line 35. Read out. The control signal line 34 transmits a signal for selecting the transfer gate 31, a signal for selecting the shared circuit 32, a signal for resetting the light receiving unit 30 by the reset transistor of the shared circuit 32, and the like.
[0026] 図 5の画素配列 20は、また更に受光部 40、トランスファーゲート 41、共有回路 42、 及び共有接続用信号線 43を含む。受光部 40、トランスファーゲート 41、共有回路 4 2、及び共有接続用信号線 43は、それぞれ受光部 30、トランスファーゲート 31、共 有回路 32、及び共有接続用信号線 33と同等の回路素子である。 4つの受光部 40が
1つの画素群を形成し、 1つの共有回路 42に結合される。 The pixel array 20 in FIG. 5 further includes a light receiving unit 40, a transfer gate 41, a shared circuit 42, and a shared connection signal line 43. The light receiving unit 40, the transfer gate 41, the shared circuit 42, and the shared connection signal line 43 are circuit elements equivalent to the light receiving unit 30, the transfer gate 31, the shared circuit 32, and the shared connection signal line 33, respectively. . There are four receivers 40 One pixel group is formed and coupled to one shared circuit 42.
[0027] 図 5の画素配列 20は、また更に受光部 50、トランスファーゲート 51、共有回路 52、 及び共有接続用信号線 53を含む。受光部 50、トランスファーゲート 51、共有回路 5 2、及び共有接続用信号線 53は、それぞれ受光部 30、トランスファーゲート 31、共 有回路 32、及び共有接続用信号線 33と同等の回路素子である。 4つの受光部 50が 1つの画素群を形成し、 1つの共有回路 52に結合される。 The pixel array 20 in FIG. 5 further includes a light receiving unit 50, a transfer gate 51, a shared circuit 52, and a shared connection signal line 53. The light receiving unit 50, the transfer gate 51, the shared circuit 52, and the shared connection signal line 53 are circuit elements equivalent to the light receiving unit 30, the transfer gate 31, the shared circuit 32, and the shared connection signal line 33, respectively. . Four light receiving portions 50 form one pixel group and are coupled to one shared circuit 52.
[0028] 図 5に示されるように、本発明の第 1の実施例においては、所定の列に並ぶ受光部 [0028] As shown in FIG. 5, in the first embodiment of the present invention, the light receiving units arranged in a predetermined row.
(30、 50)を所定個数 (4つ)ずつ纏めて複数の画素群を形成し、各画素群を対応す る共有回路(32、 52)に結合する。また隣り合う 2つの画素群 (即ち受光部 30からなる 画素群と受光部 50からなる画素群)の間には、他の列に並ぶ受光部 (40)を所定個 数 (4つ)ずつ纏めて形成した画素群に結合される共有回路 (42)が配置される。この ような構成とすることで、画素間隔を略等間隔として均一な配置を実現しながらも、共 有回路力 各受光部までの距離を略一定とすることができる。 A predetermined number (4) of (30, 50) are grouped together to form a plurality of pixel groups, and each pixel group is coupled to a corresponding shared circuit (32, 52). In addition, a predetermined number (4) of light receiving units (40) arranged in other rows are grouped between two adjacent pixel groups (that is, a pixel group including the light receiving unit 30 and a pixel group including the light receiving unit 50). A shared circuit (42) coupled to the pixel group formed in this manner is disposed. With such a configuration, it is possible to make the distance to each light receiving portion of the shared circuit force substantially constant while realizing a uniform arrangement with pixel intervals being substantially equal.
[0029] 図 6は、図 5の画素配列と同一のレイアウトを断面図示用の切断線とともに示す図で ある。図 6において、図 5と同一の構成要素は同一の番号で参照し、その説明は省略 する。図 6において、奇数列の画素列に対応する各回路要素は、受光部 30、トランス ファーゲート 31、共有回路 32、及び共有接続用信号線 33として示し、偶数列の画素 列に対応する各回路要素は、受光部 40、トランスファーゲート 41、共有回路 42、及 び共有接続用信号線 43として示してある。 FIG. 6 is a diagram showing the same layout as the pixel array in FIG. 5 together with a cutting line for cross-sectional illustration. In FIG. 6, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. In FIG. 6, each circuit element corresponding to an odd-numbered pixel column is shown as a light receiving unit 30, a transfer gate 31, a shared circuit 32, and a shared connection signal line 33, and each circuit element corresponding to an even-numbered pixel column Elements are shown as a light receiving unit 40, a transfer gate 41, a shared circuit 42, and a signal line 43 for shared connection.
[0030] 図 7は、図 6の切断線 A— A'で切断した画素配列の断面図である。図 7において、 図 6と同一の構成要素は同一の番号で参照し、その説明は省略する。図 7に示され るように、半導体基板 60の拡散層に受光部 30及び共有回路 32が形成される。 FIG. 7 is a cross-sectional view of the pixel array cut along the cutting line AA ′ in FIG. In FIG. 7, the same elements as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted. As shown in FIG. 7, the light receiving unit 30 and the shared circuit 32 are formed in the diffusion layer of the semiconductor substrate 60.
[0031] 半導体基板 60の上のポリシリコン層には、トランスファーゲート 31が形成され、その 上のメタル第 1層に制御信号線 34が形成される。図 6には、制御信号線 34の大まか な位置と方向が示されているだけであり、実際には、図 7に示されるように 1つのトラン スファーゲート 31 (図面上では 1つであるが実際には同一行上にある複数のトランス ファーゲート 31)に対して 1つの制御信号線が設けられる。またメタル第 1層の上のメ タル第 2層には、共有接続用信号線 33が形成される。共有接続用信号線 33と共通
回路 32との間、及び共有接続用信号線 33とトランスファーゲート 31の拡散層 62 (トラ ンスファーゲートを構成するトランジスタのドレイン端)との間は、それぞれコンタクトホ ール 61を介して接続される。 A transfer gate 31 is formed in the polysilicon layer on the semiconductor substrate 60, and a control signal line 34 is formed in the first metal layer thereon. FIG. 6 only shows the approximate position and direction of the control signal line 34; in practice, one transfer gate 31 (one on the drawing is shown) as shown in FIG. In reality, one control signal line is provided for a plurality of transfer gates 31) on the same row. A shared connection signal line 33 is formed in the second metal layer on the first metal layer. Common with signal line 33 for shared connection The circuit 32 and the shared connection signal line 33 and the diffusion layer 62 of the transfer gate 31 (the drain end of the transistor constituting the transfer gate) are connected via the contact hole 61, respectively. The
[0032] 図 8は、図 6の切断線 B— B'で切断した画素配列の断面図である。図 8において、 図 6及び図 7と同一の構成要素は同一の番号で参照し、その説明は省略する。 FIG. 8 is a cross-sectional view of the pixel array taken along the cutting line BB ′ of FIG. In FIG. 8, the same components as those in FIGS. 6 and 7 are referred to by the same numerals, and a description thereof will be omitted.
[0033] 図 8に示されるように、制御信号線 34とトランスファーゲート 31 (トランスファーゲート を構成するトランジスタのゲート端)との間、及び制御信号線 34と共有回路 32との間 は、それぞれコンタクトホール 63を介して接続される。またメタル第 1層の上のメタル 第 2層には、共有接続用信号線 33が形成される。 [0033] As shown in FIG. 8, contact is made between the control signal line 34 and the transfer gate 31 (the gate end of the transistor constituting the transfer gate), and between the control signal line 34 and the shared circuit 32, respectively. Connected through Hall 63. A shared connection signal line 33 is formed on the second metal layer above the first metal layer.
[0034] 図 9は、図 6の切断線 C C'で切断した画素配列の断面図である。図 9において、 図 6乃至図 8と同一の構成要素は同一の番号で参照し、その説明は省略する。 FIG. 9 is a cross-sectional view of the pixel array taken along the cutting line CC ′ of FIG. 9, the same components as those in FIGS. 6 to 8 are referred to by the same numerals, and a description thereof will be omitted.
[0035] 図 9に示されるように、メタル第 2層には、出力信号線 35が形成される。出力信号線As shown in FIG. 9, an output signal line 35 is formed in the second metal layer. Output signal line
35と共有回路 32との間は、コンタクトホール 64を介して接続される。 35 and the shared circuit 32 are connected via a contact hole 64.
[0036] 図 10は、図 6の切断線 D— D'で切断した画素配列の断面図である。図 10においてFIG. 10 is a cross-sectional view of the pixel array cut along the cutting line DD ′ in FIG. In Figure 10
、図 6乃至図 9と同一の構成要素は同一の番号で参照し、その説明は省略する。 6 to 9 are referred to by the same numerals, and a description thereof will be omitted.
[0037] 図 10に示されるように、半導体基板 60には受光部 30及び受光部 40が形成されるAs shown in FIG. 10, the light receiving unit 30 and the light receiving unit 40 are formed on the semiconductor substrate 60.
。メタル第 2層には、出力信号線 35と受光部 40用の共有接続用信号線 43とが形成 されている。 . In the second metal layer, an output signal line 35 and a shared connection signal line 43 for the light receiving unit 40 are formed.
[0038] 図 11は、図 6の切断線 E— E'で切断した画素配列の断面図である。図 11において 、図 6乃至図 10と同一の構成要素は同一の番号で参照し、その説明は省略する。 FIG. 11 is a cross-sectional view of the pixel array cut along the cutting line EE ′ of FIG. In FIG. 11, the same components as those in FIGS. 6 to 10 are referred to by the same numerals, and a description thereof will be omitted.
[0039] ポリシリコン層にはトランスファーゲート 31及び 41が形成される。この場合切断面と トランスファーゲート 31及び 41の延展方向とは同一であり、図面の端から端までトラ ンスファーゲート 31及び 41が連続して一本のポリシリコン電極として設けられている。 ポリシリコン層の上のメタル第 1層には制御信号線 34が形成される。制御信号線 34と トランスファーゲート 31及び 41とは、各トランスファーゲートの位置においてコンタクト ホール 65により結合されている。 [0039] Transfer gates 31 and 41 are formed in the polysilicon layer. In this case, the cut surface and the extending direction of the transfer gates 31 and 41 are the same, and the transfer gates 31 and 41 are continuously provided as one polysilicon electrode from the end to the end of the drawing. A control signal line 34 is formed in the first metal layer on the polysilicon layer. The control signal line 34 and the transfer gates 31 and 41 are coupled by a contact hole 65 at the position of each transfer gate.
[0040] 図 12は、図 5に示す画素配列における 1つの画素群に対応する回路の等価回路 の一例を示す図である。図 12に示すように、フォトダイオードである 4つの受光部 30
力 トランジスタであるトランスファーゲート 31を介して共有回路 32に結合される。こ のトランスファーゲート 31は、各受光部 30に一対一に対応して設けられる。 4つのトラ ンスファーゲート 31のゲート端には、制御信号 TG1乃至 TG4が供給される。 FIG. 12 is a diagram showing an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG. As shown in Figure 12, there are four photo detectors 30 that are photodiodes. It is coupled to the shared circuit 32 via a transfer gate 31 which is a force transistor. The transfer gates 31 are provided in one-to-one correspondence with the light receiving units 30. Control signals TG1 to TG4 are supplied to the gate ends of the four transfer gates 31.
[0041] 共有回路 32は、読み出し用トランジスタ 71とリセット用トランジスタ 72とを含む。読 み出し用トランジスタ 71は、ソース端が参照電位 VRに結合され、ドレイン端が出力信 号線 35に結合される。制御信号 TG 1乃至 TG4のうち 1つが HIGHになると対応する トランスファーゲート 31が導通し、対応する受光部 30の電荷が読み出し用トランジス タ 71のゲート端に供給される。これにより、受光部 30の電荷量に依存した電圧が出 力信号線 35に現れる。このようにして、選択された画素の画素信号を読み出すことが できる。 The shared circuit 32 includes a read transistor 71 and a reset transistor 72. The read transistor 71 has a source terminal coupled to the reference potential VR and a drain terminal coupled to the output signal line 35. When one of the control signals TG 1 to TG 4 becomes HIGH, the corresponding transfer gate 31 becomes conductive, and the charge of the corresponding light receiving unit 30 is supplied to the gate terminal of the read transistor 71. As a result, a voltage depending on the charge amount of the light receiving unit 30 appears on the output signal line 35. In this way, the pixel signal of the selected pixel can be read out.
[0042] なおリセット用トランジスタ 72は、リセット信号 RSTが HIGHになると導通し、選択し た受光部 30を参照電圧 VRにリセットする。このようなリセット動作により、画素配列 20 の各画素を同一の初期状態に設定することができる。 The reset transistor 72 is turned on when the reset signal RST becomes HIGH, and resets the selected light receiving unit 30 to the reference voltage VR. By such a reset operation, each pixel of the pixel array 20 can be set to the same initial state.
[0043] 図 13は、図 5に示す画素配列における 1つの画素群に対応する回路の等価回路 の別の一例を示す図である。図 13において、図 12と同一の構成要素は同一の番号 で参照し、その説明は省略する。 FIG. 13 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG. In FIG. 13, the same elements as those of FIG. 12 are referred to by the same numerals, and a description thereof will be omitted.
[0044] 図 13の構成においては、共有回路 32は、読み出し用トランジスタ 71及びリセット用 トランジスタ 72に加え、更に選択用トランジスタ 73を含む。選択用トランジスタ 73は、 読み出し用トランジスタ 71に直列に接続するように挿入されており、そのゲート端に は選択信号 SELが印加される。選択信号 SELが HIGHになると、共有回路 32の読 出し画素信号が出力信号線 35に供給される。 In the configuration of FIG. 13, the shared circuit 32 further includes a selection transistor 73 in addition to the read transistor 71 and the reset transistor 72. The selection transistor 73 is inserted so as to be connected in series to the read transistor 71, and a selection signal SEL is applied to the gate terminal thereof. When the selection signal SEL becomes HIGH, the read pixel signal of the shared circuit 32 is supplied to the output signal line 35.
[0045] 図 14は、本発明による画素配列のレイアウトの第 2の実施例を示す図である。図 14 の画素配列は、受光部 130、トランスファーゲート 131、共有回路 132、制御信号線 1 34、及び出力信号線 135を含む。 FIG. 14 is a diagram showing a second example of the layout of the pixel array according to the present invention. 14 includes a light receiving unit 130, a transfer gate 131, a shared circuit 132, a control signal line 134, and an output signal line 135.
[0046] 受光部 130は、フォトダイオードからなり、光電変換により入力光に応じた強さの電 荷を蓄積する。受光部 130は、トランスファーゲート 131を介して共有回路 132に結 合される。図 14の構成では、縦に 2つ及び横に 2つ隣接して並ぶ 4つの受光部 130 力 S1つの画素群を形成し、 1つの画素群の全ての受光部 130が 1つの共有回路 132
に結合される。共有回路 132は、読み出し用トランジスタ及びリセット用トランジスタを 含み、また更に選択用トランジスタを含んでよい。 [0046] The light receiving unit 130 includes a photodiode, and accumulates a charge having a strength corresponding to input light by photoelectric conversion. The light receiving unit 130 is coupled to the shared circuit 132 via the transfer gate 131. In the configuration shown in FIG. 14, four light receiving units 130 force S are arranged side by side in the vertical direction and two in the horizontal direction. One pixel group is formed. Combined with The shared circuit 132 includes a read transistor and a reset transistor, and may further include a selection transistor.
[0047] トランスファーゲート 131を介して受光部 130から読み出された画素信号は、共有 回路 132の読み出し用トランジスタにより増幅され、その後出力信号線 135を介して 画素配列外部に読み出される。制御信号線 134は、トランスファーゲート 131を選択 するための信号、共有回路 132を選択するための信号、共有回路 132のリセット用ト ランジスタにより受光部 130をリセットするための信号等を伝送する。 The pixel signal read from the light receiving unit 130 via the transfer gate 131 is amplified by the reading transistor of the shared circuit 132 and then read out to the outside of the pixel array via the output signal line 135. The control signal line 134 transmits a signal for selecting the transfer gate 131, a signal for selecting the shared circuit 132, a signal for resetting the light receiving unit 130 by the reset transistor of the shared circuit 132, and the like.
[0048] 図 14の画素配列は、また更に受光部 140、トランスファーゲート 141、及び共有回 路 142を含む。受光部 140、トランスファーゲート 141、及び共有回路 142は、それぞ れ受光部 130、トランスファーゲート 131、及び共有回路 132と同等の回路素子であ る。 4つの受光部 140が 1つの画素群を形成し、 1つの共有回路 142に結合される。 The pixel array in FIG. 14 further includes a light receiving unit 140, a transfer gate 141, and a shared circuit 142. The light receiving unit 140, the transfer gate 141, and the shared circuit 142 are circuit elements equivalent to the light receiving unit 130, the transfer gate 131, and the shared circuit 132, respectively. Four light receiving portions 140 form one pixel group and are coupled to one shared circuit 142.
[0049] 図 14の画素配列は、また更に受光部 150、トランスファーゲート 151、及び共有回 路 152を含む。受光部 150、トランスファーゲート 151、及び共有回路 152は、それぞ れ受光部 130、トランスファーゲート 131、及び共有回路 132と同等の回路素子であ る。 4つの受光部 150が 1つの画素群を形成し、 1つの共有回路 152に結合される。 The pixel array in FIG. 14 further includes a light receiving unit 150, a transfer gate 151, and a shared circuit 152. The light receiving unit 150, the transfer gate 151, and the shared circuit 152 are circuit elements equivalent to the light receiving unit 130, the transfer gate 131, and the shared circuit 132, respectively. Four light receiving portions 150 form one pixel group and are coupled to one shared circuit 152.
[0050] 図 14に示されるように、本発明の第 2の実施例においては、所定の列(所定の 2列) に並ぶ受光部(130、 150)を所定個数 (4つ)ずつ纏めて複数の画素群を形成し、各 画素群を対応する共有回路(132、 152)に結合する。また隣り合う 2つの画素群 (即 ち受光部 130からなる画素群と受光部 150からなる画素群)の間には、他の列 (他の 2列)に並ぶ受光部(140)を所定個数 (4つ)ずつ纏めて形成した画素群に結合され る共有回路(142)が配置される。このような構成とすることで、画素間隔を略等間隔と して均一な配置を実現しながらも、共有回路力 各受光部までの距離を略一定とす ることができる。なお図 14の第 2の実施例の構成では、共有接続用信号線を削減で きるので、第 1の実施例の構成と比較して、画素間隔を短くすることが可能である。 As shown in FIG. 14, in the second embodiment of the present invention, a predetermined number (four) of light receiving sections (130, 150) arranged in a predetermined row (predetermined two rows) are collected. A plurality of pixel groups are formed, and each pixel group is coupled to a corresponding shared circuit (132, 152). In addition, between two adjacent pixel groups (that is, a pixel group consisting of the light receiving unit 130 and a pixel group consisting of the light receiving unit 150), a predetermined number of light receiving units (140) arranged in other columns (the other two columns) are provided. A shared circuit (142) that is coupled to a pixel group formed by collecting (four) each is arranged. By adopting such a configuration, it is possible to make the distance to each light receiving portion of the shared circuit force substantially constant while realizing uniform arrangement with the pixel intervals being substantially equal. In the configuration of the second embodiment shown in FIG. 14, since the number of shared connection signal lines can be reduced, the pixel interval can be shortened compared to the configuration of the first embodiment.
[0051] 図 15は、図 14に示す画素配列における 1つの画素群に対応する回路の等価回路 の一例を示す図である。図 15に示すように、フォトダイオードである 4つの受光部 130 力 トランジスタであるトランスファーゲート 131を介して共有回路 132に結合される。 このトランスファーゲート 131は、各受光部 130に一対一に対応して設けられる。 4つ
のトランスファーゲート 131のゲート端には、制御信号 TGI乃至 TG4が供給される。 FIG. 15 is a diagram illustrating an example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array illustrated in FIG. As shown in FIG. 15, four light receiving sections 130 that are photodiodes are coupled to a shared circuit 132 via a transfer gate 131 that is a transistor. The transfer gates 131 are provided in one-to-one correspondence with the respective light receiving units 130. Four Control signals TGI to TG4 are supplied to the gate end of the transfer gate 131.
[0052] 共有回路 132は、読み出し用トランジスタ 171とリセット用トランジスタ 172とを含む。 The shared circuit 132 includes a read transistor 171 and a reset transistor 172.
読み出し用トランジスタ 171は、ソース端が参照電位 VRに結合され、ドレイン端が出 力信号線 135に結合される。制御信号 TG 1乃至 TG4のうち 1つが HIGHになると対 応するトランスファーゲート 131が導通し、対応する受光部 130の電荷が読み出し用 トランジスタ 171のゲート端に供給される。これにより、受光部 130の電荷量に依存し た電圧が出力信号線 135に現れる。このようにして、選択された画素の画素信号を読 み出すことができる。 Read transistor 171 has a source terminal coupled to reference potential VR and a drain terminal coupled to output signal line 135. When one of the control signals TG 1 to TG 4 becomes HIGH, the corresponding transfer gate 131 becomes conductive, and the charge of the corresponding light receiving unit 130 is supplied to the gate terminal of the reading transistor 171. As a result, a voltage depending on the charge amount of the light receiving unit 130 appears on the output signal line 135. In this way, the pixel signal of the selected pixel can be read out.
[0053] なおリセット用トランジスタ 172は、リセット信号 RSTが HIGHになると導通し、選択 した受光部 130を参照電圧 VRにリセットする。このようなリセット動作により、画素配 列の各画素を同一の初期状態に設定することができる。 Note that the reset transistor 172 is turned on when the reset signal RST becomes HIGH, and resets the selected light receiving unit 130 to the reference voltage VR. With such a reset operation, each pixel in the pixel array can be set to the same initial state.
[0054] 図 16は、図 14に示す画素配列における 1つの画素群に対応する回路の等価回路 の別の一例を示す図である。図 16において、図 15と同一の構成要素は同一の番号 で参照し、その説明は省略する。 FIG. 16 is a diagram showing another example of an equivalent circuit of a circuit corresponding to one pixel group in the pixel array shown in FIG. In FIG. 16, the same elements as those of FIG. 15 are referred to by the same numerals, and a description thereof will be omitted.
[0055] 図 16の構成においては、共有回路 132は、読み出し用トランジスタ 171及びリセッ ト用トランジスタ 172に加え、更に選択用トランジスタ 173を含む。選択用トランジスタ 173は、読み出し用トランジスタ 171に直列に接続するように挿入されており、そのゲ ート端には選択信号 SELが印加される。選択信号 SELが HIGHになると、共有回路 132の読出し画素信号が出力信号線 135に供給される。 In the configuration of FIG. 16, the shared circuit 132 further includes a selection transistor 173 in addition to the read transistor 171 and the reset transistor 172. The selection transistor 173 is inserted so as to be connected in series with the readout transistor 171 and a selection signal SEL is applied to the gate end thereof. When the selection signal SEL becomes HIGH, the readout pixel signal of the shared circuit 132 is supplied to the output signal line 135.
[0056] 図 17は、本発明による画素配列のレイアウトの第 3の実施例を示す図である。第 3 の実施例においては、 2つの画素を纏めて 1つの画素群とし、各画素群に対して一 対一に 1つの共有回路を割り当てる。 FIG. 17 is a diagram showing a third example of the layout of the pixel array according to the present invention. In the third embodiment, two pixels are combined into one pixel group, and one shared circuit is assigned to each pixel group one-on-one.
[0057] 図 17の画素配列は、受光部 230、トランスファーゲート 231、共有回路 232、制御 信号線 234、及び出力信号線 235を含む。個々の回路要素の構成及び機能は、第 1及び第 2の実施例の場合と同様であり、その説明は省略する。 The pixel array in FIG. 17 includes a light receiving unit 230, a transfer gate 231, a shared circuit 232, a control signal line 234, and an output signal line 235. The configuration and function of each circuit element are the same as those in the first and second embodiments, and a description thereof will be omitted.
[0058] この構成では、縦に 2つ連続して並ぶ 2つの受光部 230が 1つの画素群を形成し、 1つの画素群の全ての受光部 230が 1つの共有回路 232に結合される。共有回路 2 32は、読み出し用トランジスタ及びリセット用トランジスタを含み、また更に選択用トラ
ンジスタを含んでよい。 In this configuration, two light receiving units 230 arranged in succession vertically form one pixel group, and all the light receiving units 230 of one pixel group are coupled to one shared circuit 232. The shared circuit 2 32 includes a read transistor and a reset transistor, and further includes a selection transistor. May include a transistor.
[0059] 図 17の画素配列は、また更に受光部 240、トランスファーゲート 241、及び共有回 路 242を含む。受光部 240、トランスファーゲート 241、及び共有回路 242は、それぞ れ受光部 230、トランスファーゲート 231、及び共有回路 232と同等の回路素子であ る。 2つの受光部 240が 1つの画素群を形成し、 1つの共有回路 242に結合される。 The pixel array in FIG. 17 further includes a light receiving unit 240, a transfer gate 241, and a shared circuit 242. The light receiving unit 240, the transfer gate 241 and the shared circuit 242 are circuit elements equivalent to the light receiving unit 230, the transfer gate 231 and the shared circuit 232, respectively. Two light receiving units 240 form one pixel group and are coupled to one shared circuit 242.
[0060] 図 17の画素配列は、また更に受光部 250、トランスファーゲート 251、及び共有回 路 252を含む。受光部 250、トランスファーゲート 251、及び共有回路 252は、それぞ れ受光部 230、トランスファーゲート 231、及び共有回路 232と同等の回路素子であ る。 2つの受光部 250が 1つの画素群を形成し、 1つの共有回路 252に結合される。 The pixel array in FIG. 17 further includes a light receiving unit 250, a transfer gate 251, and a shared circuit 252. The light receiving unit 250, the transfer gate 251 and the shared circuit 252 are circuit elements equivalent to the light receiving unit 230, the transfer gate 231 and the shared circuit 232, respectively. Two light receiving portions 250 form one pixel group and are coupled to one shared circuit 252.
[0061] 図 17に示されるように、本発明の第 3の実施例においては、所定の列に並ぶ受光 部(230、 250)を所定個数 (2つ)ずつ纏めて複数の画素群を形成し、各画素群を対 応する共有回路(232、 252)に結合する。また隣り合う 2つの画素群 (即ち受光部 23 0からなる画素群と受光部 250からなる画素群)の間には、他の列に並ぶ受光部(24 0)を所定個数 (2つ)ずつ纏めて形成した画素群に結合される共有回路(242)が配 置される。このような構成とすることで、画素間隔を略等間隔として均一な配置を実現 しながらも、共有回路力も各受光部までの距離を略一定とすることができる。 As shown in FIG. 17, in the third embodiment of the present invention, a plurality of pixel groups are formed by collecting a predetermined number (two) of light receiving portions (230, 250) arranged in a predetermined row. Then, each pixel group is coupled to the corresponding shared circuit (232, 252). In addition, a predetermined number (two) of light receiving units (24 0) arranged in other rows are arranged between two adjacent pixel groups (that is, a pixel group including the light receiving unit 230 and a pixel group including the light receiving unit 250). A shared circuit (242) coupled to the pixel group formed together is arranged. By adopting such a configuration, it is possible to make the distance to each light receiving part substantially constant in the shared circuit force while realizing uniform arrangement with the pixel intervals being substantially equal.
[0062] 図 18A及び図 18Bは、本発明による画素配列のレイアウトの第 4の実施例を示す 図である。図 18Aの画素配列レイアウトと図 18Bの画素配列レイアウトとは、図示の都 合上 2つに分割して示すものであり、実際には点線 I にお 、て互 、に接続するこ とで 1つの画素配列レイアウトを構成する。第 4の実施例においては、 8つの画素を纏 めて 1つの画素群とし、各画素群に対して一対一に 1つの共有回路を割り当てる。 FIG. 18A and FIG. 18B are diagrams showing a fourth embodiment of the layout of the pixel array according to the present invention. The pixel array layout shown in FIG. 18A and the pixel array layout shown in FIG. 18B are divided into two parts for the sake of illustration. Actually, the pixel array layout is shown in FIG. One pixel array layout is configured. In the fourth embodiment, eight pixels are grouped into one pixel group, and one shared circuit is assigned to each pixel group on a one-to-one basis.
[0063] 図 18A及び図 18Bの画素配列は、受光部 330、トランスファーゲート 331、共有回 路 332、共有接続用信号線 333、制御信号線 334、及び出力信号線 335を含む。 個々の回路要素の構成及び機能は、第 1乃至第 3の実施例の場合と同様であり、そ の説明は省略する。 The pixel arrays in FIGS. 18A and 18B include a light receiving unit 330, a transfer gate 331, a shared circuit 332, a shared connection signal line 333, a control signal line 334, and an output signal line 335. The configuration and function of each circuit element are the same as those in the first to third embodiments, and the description thereof is omitted.
[0064] この構成では、縦一列に並ぶ 8つの連続する受光部 330が 1つの画素群を形成し、 1つの画素群の全ての受光部 330が 1つの共有回路 332に結合される。共有回路 3 32は、読み出し用トランジスタ及びリセット用トランジスタを含み、また更に選択用トラ
ンジスタを含んでよい。 In this configuration, eight continuous light receiving units 330 arranged in a vertical row form one pixel group, and all the light receiving units 330 of one pixel group are coupled to one shared circuit 332. The shared circuit 332 includes a read transistor and a reset transistor, and further includes a selection transistor. May include a transistor.
[0065] 図 18A及び図 18Bの画素配列は、また更に、縦一列に連続して並ぶ 8つの受光部 340、トランスファーゲート 341、共有回路 342、及び共有接続用信号線 343を含む 。受光部 340、トランスファーゲート 341、共有回路 342、及び共有接続用信号線 34 3は、それぞれ受光部 330、トランスファーゲート 331、共有回路 332、及び共有接続 用信号線 333と同等の回路素子である。これら 8つの受光部 340が 1つの画素群を 形成し、 1つの共有回路 342に結合される。 The pixel arrays in FIGS. 18A and 18B further include eight light receiving portions 340, a transfer gate 341, a shared circuit 342, and a shared connection signal line 343 that are continuously arranged in a vertical line. The light receiving unit 340, the transfer gate 341, the shared circuit 342, and the shared connection signal line 343 are circuit elements equivalent to the light receiving unit 330, the transfer gate 331, the shared circuit 332, and the shared connection signal line 333, respectively. These eight light receiving units 340 form one pixel group and are coupled to one shared circuit 342.
[0066] 図 18A及び図 18Bの画素配列は、また更に、縦一列に連続して並ぶ受光部 350、 トランスファーゲート 351、共有回路 352、及び共有接続用信号線 353を含む。受光 部 350、トランスファーゲート 351、共有回路 352、及び共有接続用信号線 353は、 それぞれ受光部 330、トランスファーゲート 331、共有回路 332、及び共有接続用信 号線 333と同等の回路素子である。これら 8つの受光部 350が 1つの画素群を形成し 、 1つの共有回路 352に結合される。 The pixel arrays in FIGS. 18A and 18B further include a light receiving unit 350, a transfer gate 351, a shared circuit 352, and a shared connection signal line 353 that are continuously arranged in a vertical line. The light receiving unit 350, the transfer gate 351, the shared circuit 352, and the shared connection signal line 353 are circuit elements equivalent to the light receiving unit 330, the transfer gate 331, the shared circuit 332, and the shared connection signal line 333, respectively. These eight light receiving parts 350 form one pixel group and are coupled to one shared circuit 352.
[0067] 図 18A及び図 18Bに示されるように、本発明の第 4の実施例においては、所定の 列に並ぶ受光部(330、 350)を所定個数 (8つ)ずつ纏めて複数の画素群を形成し、 各画素群を対応する共有回路 (332、 352)に結合する。また隣り合う 2つの画素群( 即ち受光部 330からなる画素群と受光部 350からなる画素群)の間には、他の列に 並ぶ受光部(340)を所定個数 (8つ)ずつ纏めて形成した画素群に結合される共有 回路 (342)が配置される。このような構成とすることで、画素間隔を略等間隔として均 一な配置を実現しながらも、共有回路力 各受光部までの距離を略一定とすることが できる。 As shown in FIGS. 18A and 18B, in the fourth embodiment of the present invention, a plurality of pixels in which a predetermined number (eight) of light receiving portions (330, 350) arranged in a predetermined row are grouped. A group is formed, and each pixel group is coupled to a corresponding shared circuit (332, 352). In addition, a predetermined number (eight) of light receiving units (340) arranged in other rows are grouped between two adjacent pixel groups (that is, a pixel group including the light receiving unit 330 and a pixel group including the light receiving unit 350). A shared circuit (342) coupled to the formed pixel group is disposed. By adopting such a configuration, it is possible to make the distance to each light receiving part of the shared circuit force substantially constant while realizing uniform arrangement with the pixel intervals being substantially equal.
[0068] 以上、本発明を実施例に基づいて説明したが、本発明は上記実施例に限定される ものではなぐ特許請求の範囲に記載の範囲内で様々な変形が可能である。
The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims.
Claims
[1] 一又は複数の列に配置された複数の第 1の受光部と、 [1] a plurality of first light receiving units arranged in one or more rows;
該ー又は複数の列とは異なる一又は複数の列に配置された複数の第 2の受光部と 該複数の第 1の受光部を所定個数ずつ纏めて複数の画素群を形成し、各画素群 に一対一に結合される第 1の共有回路と、 A plurality of second light receiving units arranged in one or a plurality of columns different from the plurality of columns, and a plurality of first light receiving units are grouped together by a predetermined number to form a plurality of pixel groups. A first shared circuit coupled one-to-one to the group;
該複数の第 2の受光部を所定個数ずつ纏めて複数の画素群を形成し、各画素群 に一対一に結合される第 2の共有回路 A second shared circuit that forms a plurality of pixel groups by collecting a predetermined number of the plurality of second light receiving sections and is coupled to each pixel group in a one-to-one relationship.
を含み、該第 1の受光部力 構成される 2つの隣接する画素群の間には該第 2の共 有回路が配置されることを特徴とする固体撮像素子。 A solid-state imaging device, wherein the second shared circuit is arranged between two adjacent pixel groups configured by the first light receiving unit force.
[2] 該ー又は複数の列の数は 1であり、該第 1の受光部は 1つの列に直線上に配置さ れ、且つ該第 2の受光部は 1つの列に直線上に配置されることを特徴とする請求項 1 記載の固体撮像素子。 [2] The number of the plurality of rows is one, the first light receiving portions are arranged on a straight line in one row, and the second light receiving portions are arranged on a straight line in one row. The solid-state imaging device according to claim 1, wherein
[3] 出力信号線を更に含み、該第 1及び第 2の共有回路は、対応する該第 1及び第 2の 受光部からの信号に応じた出力信号を該出力信号線に供給する読み出し用トランジ スタを含むことを特徴とする請求項 1記載の固体撮像素子。 [3] An output signal line is further included, and the first and second shared circuits supply the output signal corresponding to the signals from the corresponding first and second light receiving units to the output signal line. 2. The solid-state imaging device according to claim 1, further comprising a transistor.
[4] 該第 1及び第 2の共有回路は、対応する該第 1及び第 2の受光部をリセットするリセ ット用トランジスタを含むことを特徴とする請求項 1記載の固体撮像素子。 4. The solid-state imaging device according to claim 1, wherein the first and second shared circuits include a reset transistor that resets the corresponding first and second light receiving units.
[5] 該第 1及び第 2の共有回路は、当該共有回路を選択するための選択用トランジスタ を含むことを特徴とする請求項 1記載の固体撮像素子。
5. The solid-state imaging device according to claim 1, wherein the first and second shared circuits include a selection transistor for selecting the shared circuit.
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