WO2007104176A1

WO2007104176A1 - Construction and control method of fractional-n pll having fractional frequency divider

Info

Publication number: WO2007104176A1
Application number: PCT/CN2006/000374
Authority: WO
Inventors: Shey-Shi Lu; Shih-An Yu; Yu-Che Yang
Original assignee: Memetics Technology Co., Ltd.
Priority date: 2006-03-13
Filing date: 2006-03-13
Publication date: 2007-09-20

Abstract

A construction and control method of fractional frequency divider are provided. The frequency divider comprises: a divisor controlling unit for producing a divisor selection signal in response to dual-edge triggering of a input signal; a frequency dividing unit coupled to the controlling unit, for frequency dividing the input signal, and dividing the input signal by a integer or a fraction to produce a output of the frequency divider in response to the dual-edge triggering and the selecting signal. A operation of the frequency dividing unit is not retrained when the integer is divided, and when the fracion is divided,the frequency dividing unit is cycling in a way that the frequency dividing unit is retrained by half of a cycle after the operation is done by one cycle of the input signal. A construction and control method of fractional-N PLL having the fractional frequency divider are provided.

Description

具有分数除频器的分数型锁相回路的构形与控制方法 Configuration and control method of fractional phase-locked loop with fractional frequency divider

技术领域 Technical field

本发明为一种分数除频器、一种可编程分数除频器与一种分数型锁相回路 The invention is a fractional frequency divider, a programmable fractional frequency divider and a fractional phase-locked loop

(Fractional - N PLL)的构形与控制方法，尤指一种具有一分数与一整数除数的分数除频器、一种具有可调除频范围的可编程分数除频器以及一种具有可调除频范围的分数型锁相回路。背景技术 (Fractional - N PLL) configuration and control method, especially a fractional divider with a fraction and an integer divisor, a programmable fractional divider with an adjustable frequency division range, and a A fractional phase-locked loop that adjusts the frequency range. Background technique

现有的锁相回路频率合成器的基本架构图如图 1所示。该锁相回路频率合成器 2利用外来的石英震荡器（如温度补偿石英震荡器： TCX0) 21产生一个准确的参考信号，和晶片内的压控震荡器 (VC0) 25经过除频器（Frequency Divider) 26除以 N以后的信号，会通过一个相频检测器（Phase Frequency Detector : PFD) 22 来做比较，然后再借助电荷泵（Charge Pump : CP ) 23及回路滤波器（Loop The basic architecture of the existing phase-locked loop frequency synthesizer is shown in Figure 1. The phase-locked loop frequency synthesizer 2 utilizes an external quartz oscillator (such as a temperature-compensated quartz oscillator: TCX0) 21 to generate an accurate reference signal, and a voltage-controlled oscillator (VC0) 25 in the wafer through the frequency divider (Frequency Divider) 26 divided by the signal after N, will be compared by a Phase Frequency Detector (PFD) 22, and then with the charge pump (Charge Pump: CP) 23 and loop filter (Loop

Filter : LPF) 24来调整压控震荡器 25的震荡频率，而由于整个锁相回路 2的负反馈机制，最后 VC0的信号频率会稳定在参考信号的 N倍上，也就是说 Filter : LPF) 24 to adjust the oscillation frequency of the voltage controlled oscillator 25, and due to the negative feedback mechanism of the entire phase-locked loop 2, the signal frequency of the last VC0 will be stabilized at N times of the reference signal, that is,

Fvco=N F ( 1 ) 经过了该锁相回路频率合成器 2锁定的 VC025 , 它的输出信号的抖动 (Jitter) 会大大的降低，而它在频谱上所表现出来的便是回路频宽内的相位杂讯被压抑下来。' Fvco=NF ( 1 ) After the VC025 locked by the phase-locked loop frequency synthesizer 2, the jitter of its output signal is greatly reduced, and the spectrum is represented by the loop bandwidth. Phase noise is suppressed. '

由于输出频率皆是参考信号源的的整数倍，因此如图 1所示这种架构通称为整数型锁相回路 (Integer- N PLL)。整数型锁相回路在设计上有许多的不便，因为其整数倍频的特性，所以参考信号源的频率必须和频道宽度一样，或者是频道宽度的因数，如此一来便间接影响到频率锁定的时间长短 (为了稳定度的考量，锁相回路的回路频宽必须小于参考信号源频率的 1/10, 而回路频宽会直接影响到锁相回路锁定所需要的时间）。 Since the output frequency is an integer multiple of the reference source, this architecture is commonly referred to as an integer phase-locked loop (Integer-N PLL) as shown in Figure 1. Integer phase-locked loops have many inconveniences in design. Because of their integer multiplier characteristics, the frequency of the reference signal source must be the same as the channel width, or the channel width factor. This indirectly affects the frequency lock. The length of time (for stability considerations, the loop bandwidth of the phase-locked loop must be less than 1/10 of the reference source frequency, and the loop bandwidth directly affects the time required for the phase-locked loop to lock).

为了解决这个问题，于是另一种型态的锁相回路就被发展了出来，便是分数型的锁相回路 (Fractional-N PLL)。一现有的分数型锁相回路的基本架构图如图 2 所示，该分数型锁相回路 3除包含上述图 1中 21至 25各组件外，更包含一可编程除步员器 (Programmable Frequency Divider) 31、一调变器 (Modulator) 32及一力口法器（Adder ) 33。用于将一外加的整数的除数（Integer Modulus ) 与该调变器In order to solve this problem, another type of phase-locked loop has been developed, which is a fractional phase-locked loop (Fractional-N PLL). The basic architecture diagram of an existing fractional phase-locked loop is shown in FIG. 2. The fractional phase-locked loop 3 includes a programmable step-finder (Programmable) in addition to the components 21 to 25 in FIG. Frequency Divider) 31, a Modulator 32 and a force port Adder 33. An integer (Integer Modulus ) used to add an extra integer to the modulator

32的输出信号相加后输入该可编程除频器 32用以产生一除数。这种锁相回路的特点是， VC025的输出频率不再是参考信号源的整数倍，即 The output signals of 32 are summed and input to the programmable frequency divider 32 for generating a divisor. The characteristic of this phase-locked loop is that the output frequency of the VC025 is no longer an integer multiple of the reference source, ie

F_vco二 N. F F (2) 其中 N代表一个整数，而 F是一个小于 1的分数。而这种锁相回路与原本的架构主要不同的地方便在于它多了一个除数的调变器 32，在锁定相位的过程中，会不断的改变除频器 31的除数，使得它的除数平均起来是所设定的一个非整数值。 F _vco II N. FF (2) where N represents an integer and F is a fraction less than one. The phase-locked loop is mainly different from the original architecture in that it has a divisor 32. In the process of locking the phase, the divisor of the frequency divider 31 is constantly changed, so that its divisor average It is a non-integer value set.

举个简单的例子来说，如果今天让除频器 31在四个输出周期中，除数设定为 100, 而在另六个周期里，除数改为 101，这样等效上的除数就变成了 100. 6。 For a simple example, if the frequency divider 31 is set to 100 in four output cycles today, and the divisor is changed to 101 in the other six cycles, the equivalent divisor becomes 100. 6.

. 当然使用这样的架构并非毫无缺点，由上面的说明，不难发现，实际上除频器 31的除数还是一个整数，只是经不断的切换使该除数看起来像是一个分数，因此在每个输出周期中都会产生一些量化误差（quantization error) , 用上面的例子来说，当除数为 100时，量化误差就是 0. 6，除数为 101时，量化误差就是 0. 4，这些误差会使得频率合成器 3产生额外的相位杂讯，和一些突波（spur) , 因此便有人提出较复杂的的调变器 32的架构，例如三角积分调变器，来使得调变讯号的模组乱数化，这样可以将量化误差的能量往较高频的地方移动，降低回路频宽内的相位杂讯。然而，由于除频器 31本质上还是一个整数除频器，这个问题仍然是无法解决。 Of course, using such an architecture is not without drawbacks. From the above description, it is not difficult to find that the divisor of the frequency divider 31 is actually an integer, but the divisor looks like a fraction by constantly switching, so in each In the output cycle, some quantization error is generated. In the above example, when the divisor is 100, the quantization error is 0. 6. When the divisor is 101, the quantization error is 0.4. These errors will make The frequency synthesizer 3 generates additional phase noise, and some spurs, so a more complicated architecture of the modulator 32, such as a delta-sigma modulator, is proposed to make the modulation signal module random. This can move the energy of the quantization error to a higher frequency and reduce the phase noise in the loop bandwidth. However, since the frequency divider 31 is essentially an integer frequency divider, this problem cannot be solved.

前述可编程除频器 31的功能是将压控震荡器 25的输出信号频率降低，借以和参考信号源比较，其原理是主要借助计数压控震荡器的输入信号，来产生它的周期的整数倍信号。 ' The function of the foregoing programmable frequency divider 31 is to reduce the frequency of the output signal of the voltage controlled oscillator 25, thereby comparing with the reference signal source, the principle of which is to generate the integer of its period mainly by counting the input signal of the voltage controlled oscillator. Times signal. '

图 3是一个现有的可编程除频器的架构图，该除频器 31包含了一连串的除数为 2/3的除频器 311， 2/3除频器 311的内部电路则如图 4所示。这个 2/3除频器主要可分成两个部份：除频逻辑 (prescaler logic) 3111和延迟逻辑（end- of- cycle logic) 3112，该除频逻辑 3111包括一第一 "与" 门（AND Gate) 31111、一第一锁存器（latchl) 31112及一第二锁存器 31113，负责处理输入的信号，而该延迟逻辑 3112则包括一第二 "与" 门 31121、一第三锁存器 31122、一第三 "与" 门 31123以及一第四锁存器 31124，且根据 MOD和 FB— CTRL两个控制信号来决定除频器的除数。由图 4可以发现，若 MOD或 FB_CTRL两者中任一者为逻辑 0时，延迟逻辑部分的反馈信号将维持在逻辑 1，因此除频逻辑不会受到其影响，除数为二；而当 MOD和 FB— CTRL均为 1时，延迟逻辑的电路会使除频电路的动作延迟一个周期，而发挥除三的功能。 3 is an architectural diagram of a conventional programmable frequency divider, the frequency divider 31 includes a series of frequency dividers 311 having a divisor of 2/3, and the internal circuit of the 2/3 frequency divider 311 is as shown in FIG. Shown. The 2/3 frequency divider can be divided into two main parts: prescaler logic 3111 and end-of-cycle logic 3112, which includes a first AND gate ( AND Gate) 31111, a first latch (latch1) 31112 and a second latch 31113, which are responsible for processing the input signal, and the delay logic 3112 includes a second AND gate 31121, a third lock The memory 31122, a third AND gate 31123 and a fourth latch 31124, and the divisor of the frequency divider are determined according to two control signals of MOD and FB_CTRL. It can be found from Fig. 4 that if any of MOD or FB_CTRL is logic 0, the feedback of the delay logic part The signal will remain at logic 1, so the divide-by-frequency logic will not be affected by it, and the divisor will be two. When MOD and FB-CTRL are both 1, the delay logic circuit will delay the action of the frequency-dividing circuit by one cycle. In addition to the three features.

请再参看图 3，由 2/3除频器的工作原理来看，只有在 FB一 CTRL和 MOD同时为 1 时， 2/3除频器才会将输入信号除以 3，而把一连串的 2/3除频器串在一起时， FB— CTRL信号是来自于下一级的 CTRL0UT信号，而图 3中最后一级的 2/3除频器，其 FB— CTRL是直接连接到逻辑 1，因此在每次其输出信号为 1时，其反馈控制信号就会由 0变成 1，此时若前一级的 MOD信号是 1的话，除数便会是 3 , 否则便还是除 2，但不管 MOD为何，其反馈控制信号也会变成 1，去控制前一级的除数，如此一来，可以导出整串除频器的除数，如下式： Please refer to FIG. 3 again. According to the working principle of the 2/3 frequency divider, only when FB-CTRL and MOD are 1 at the same time, the 2/3 frequency divider will divide the input signal by 3, and put a series of When the 2/3 dividers are stringed together, the FB_CTRL signal is from the next level of the CTRL0UT signal, and the last stage of the 2/3 divider in Figure 3, its FB_CTRL is directly connected to the logic 1. Therefore, each time its output signal is 1, its feedback control signal will change from 0 to 1. At this time, if the MOD signal of the previous stage is 1, the divisor will be 3, otherwise it will be divided by 2, but Regardless of the MOD, its feedback control signal will also become 1, to control the divisor of the previous stage, so that the divisor of the entire string divider can be derived, as follows:

TOUT = ( 2^{N+ 1} + 2 M0D_N + . . . + 2² . M0D₂ + 2 . MOD i + M0D₀) . T_{I N} TOUT = ( 2 ^{N+ 1} + 2 M0D _N + . . . + 2 ² . M0D ₂ + 2 . MOD i + M0D ₀ ) . T _IN

(3) (3)

其中 T。_UT 是输出信号的周期，而 Τ_ΙΝ是输入信号的周期，由上式可以看出两个主要的缺点：（1)除频范围被限制在 2^Ν+1到 2^Ν+2-1之间，（2)可调的解析度为 1。 Where T. _UT is the period of the output signal, and Τ _ΙΝ is the period of the input signal. Two main disadvantages can be seen from the above equation: (1) The frequency range is limited to 2 ^{Ν +1} to 2 ^{Ν + 2} -1 (2) The adjustable resolution is 1.

发明人鉴于现有技术的缺失，本发明而提出具有分数除频器的分数型锁相回路的构形与控制方法。本发明提出了一个特别的除频器架构，它可以不借助调变器的调变，就达到除分数的功能，是一个崭新的独创电路，由于它本身的除数解析度为 0. 5，因此可将量化误差减少为原来的一半，亦即使相位杂讯降低 6dB的多。发明内容 In view of the deficiencies of the prior art, the inventors have proposed a configuration and control method for a fractional phase-locked loop having a fractional frequency divider. The present invention proposes a special frequency divider architecture, which can achieve the function of dividing the score without the modulation of the modulator, and is a brand-new original circuit, since its own divisor resolution is 0.5. The quantization error can be reduced to half of the original, even if the phase noise is reduced by more than 6dB. Summary of the invention

本发明的主要目的在于提供一种分数除频器（fractional frequency divider ) 、一禾中可编禾呈分数除频器 ( programmable fractional frequency divider ) 、一种分数型锁相回路（fractional-N PLL) 、一种具有可调除频范围的可编程分数除频器与一种具有可调除频范围的分数型锁相回路的构形与控制方法，该等电路具有相对较佳的除数解析度，故可产生相对较低的量化误差以及相对较低的相位杂讯。 The main object of the present invention is to provide a fractional frequency divider, a programmable fractional frequency divider, and a fractional phase-locked loop (fractional-N PLL). a configuration and control method for a programmable fractional frequency divider with an adjustable frequency division range and a fractional phase-locked loop with an adjustable frequency division range, the circuits having relatively good divisor resolution, Therefore, relatively low quantization errors and relatively low phase noise can be generated.

本发明的另一主要目的在于提供一种分数除频器，包含：一除数控制单元，其相应一输入信号的一双缘触发以产生一除数选择信号，以及一除频单元，耦合于该控制单元，用于该输入信号的一除频，且相应该双缘触发及该选择信号将该输入信号除以一整数或一分数除数以产生该除频器的一输出信号。 Another main object of the present invention is to provide a fractional frequency divider, comprising: a divisor control unit, a dual edge trigger of a corresponding input signal to generate a divisor selection signal, and a frequency division unit coupled The control unit is configured to perform a frequency division of the input signal, and the dual edge trigger and the selection signal respectively divide the input signal by an integer or a fractional divisor to generate an output signal of the frequency divider.

根据上述的构想，该双缘触发是指该控制单元及该除频单元皆被该输入信号的一上升边缘及一下降边缘该两者所触发。 According to the above concept, the dual edge triggering means that both the control unit and the frequency dividing unit are triggered by both a rising edge and a falling edge of the input signal.

根据上述的构想，当该除频器是处于一除以该整数除数的模式时，该选择信号为一逻辑低状态，而该除频单元的一运作未被抑制，当该选择信号为一逻辑高状态时，该除频单元的该运作被抑制，且当该除频器是处于一除以该分数除数的模式时，该除频单元是依每当该运作达该输入信号的一周期后即被抑制达半个该周期的一方式循环。 According to the above concept, when the frequency divider is in a mode divided by the integer divisor, the selection signal is in a logic low state, and an operation of the frequency division unit is not suppressed, when the selection signal is a logic In the high state, the operation of the frequency dividing unit is suppressed, and when the frequency divider is in a mode divided by the fractional divisor, the frequency dividing unit is in accordance with a cycle after the operation reaches the input signal. That is, it is suppressed by one way of half of the cycle.

根据上述的构想，该控制单元还接收一除数控制信号及一反馈控制信号，当该除数控制信号或该反馈控制信号为一逻辑低状态时，该选择信号为该逻辑低状态，且当该除数控制信号与该反馈控制信号均为一逻辑高状态时，该选择信号为该逻辑高状态。 According to the above concept, the control unit further receives a divisor control signal and a feedback control signal. When the divisor control signal or the feedback control signal is in a logic low state, the selection signal is in the logic low state, and when the divisor When the control signal and the feedback control signal are both in a logic high state, the selection signal is in the logic high state.

根据上述的构想，该整数除数为 1，且该分数除数为 1. 5。 According to the above concept, the integer divisor is 1, and the fractional divisor is 1. 5.

根据上述的构想，该除频单元还包含：一第一 "非" 门，具有一输入端及一输出端，一第一 "与" 门，具有一第一、一第二及一输出端，其中该第二端耦合于该第一 "非" 门该输出端，一第二 "非" 门，具有一输入端及一输出端，其中该输入端耦合于该除频器该输出端用以接收一第一反馈信号，且该输出端耦合于该第一 "与" 门该第一端，一第一锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第一 "与" 门该输出端，该第二端为一致能输入端（enable input ) ，且该第二端是用于接收该输入信号，一第二锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第一 "与" 门该输出端，且该第二端是用于接收该输入信号，以及一第一多路转接器，具有一第一、一第二、一第三及一输出端，其中该第一端耦合于该第一锁存器该输出端，该第二端耦合于该第二锁存器该输出端，该第三端用于接收该输入信号，且该输出端耦合于该除频器该输出端。 According to the above concept, the frequency dividing unit further comprises: a first "non" gate having an input end and an output end, a first AND gate having a first, a second and an output end, The second end is coupled to the output end of the first "non" gate, and the second "non" gate has an input end and an output end, wherein the input end is coupled to the output end of the frequency divider. Receiving a first feedback signal, and the output end is coupled to the first end of the first AND gate, a first latch having a first, a second, and an output, wherein the first end Coupling to the output end of the first AND gate, the second end is an enable input, and the second end is for receiving the input signal, and the second latch has a first a second and an output, wherein the first end is coupled to the output of the first AND gate, and the second end is for receiving the input signal, and a first multiplexer Having a first, a second, a third, and an output, wherein the first end is coupled to the The output of the first latch is coupled to the output of the second latch, the third terminal is configured to receive the input signal, and the output is coupled to the output of the frequency divider.

根据上述的构想，该控制单元还包含：一第二 "与" 门，具有一第一、一第二及一输出端，其中该第一端耦合于该除频器该输出端用以接收一第二反馈信号，该第二端用于接收该反馈控制信号，一第三锁存器，具有一第一、一第二及 P T/CN2006/000374 一输出端，其中该第一端耦合于该第二 "与" 门该输-出端，该第二端为一致能输入端（enable input ) ，且该第二端用于接收该输入信号，一第四锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第二 "与" 门该输出端，且该第二端用于接收该输入信号，一第二多路转接器，具有一第一、一第二、一第三及一输出端，其中该第一端耦合于该三锁存器该输出端，该第二端耦合于该四锁存器该输出端，且该第三端用于接收该输入信号，以及一第三 "与" 门具有一第一、一第二及一输出端，其中该第一端耦合于该第二多路转接器该输出端，该第二端用于接收该除数控制信号，且该输出端耦合于该第一 "非"门该输入端。 According to the above concept, the control unit further includes: a second AND gate having a first, a second, and an output, wherein the first end is coupled to the output of the frequency divider for receiving a a second feedback signal, the second end is configured to receive the feedback control signal, and a third latch has a first, a second PT/CN2006/000374 an output end, wherein the first end is coupled to the second AND gate of the input-output terminal, the second end is an enable input, and the second end is used for Receiving the input signal, a fourth latch having a first, a second, and an output, wherein the first end is coupled to the output of the second AND gate, and the second end is used Receiving the input signal, a second multiplexer having a first, a second, a third, and an output, wherein the first end is coupled to the output of the three latch, the second An end is coupled to the output of the four latch, and the third end is configured to receive the input signal, and a third AND gate has a first, a second, and an output, wherein the first end The second terminal is configured to receive the divisor control signal, and the output end is coupled to the input terminal of the first "non" gate.

本发明的次一主要目的在于提供一种分数除频器，用于将一输入信号经一除频以产生一输出信号，其中当该除频器处于一第一状态时，该输入信号被除以一整数除数，而该输出信号的产生未被抑制，且当该除频器处于一第二状态时，该输入信号被除以一分数除数，该输出信号的该产生未被抑制达该输入信号的一个周期而后该产生被抑制达半个该周期，并依此一方式循环。 A second main object of the present invention is to provide a fractional frequency divider for dividing an input signal by a frequency to generate an output signal, wherein the input signal is divided when the frequency divider is in a first state. Dividing by an integer, the generation of the output signal is not suppressed, and when the frequency divider is in a second state, the input signal is divided by a fractional divisor, the generation of the output signal is not suppressed to the input One cycle of the signal is then suppressed for half of the cycle and cycled in this manner.

根据上述的构想，该除频器还包含：一除数控制单元，其相应该输入信号的一双缘触发及该第一或该第二状态以产生一除数选择信号，以及一除频单元，耦合于该控制单元，且相应该双缘触发及该选择信号以产生该除频器的该输出信号，其中当该第一状态时，该除数控制信号为一逻辑低状态，且当该第二状态时，该除数控制信号是维持该逻辑低状态达该输入信号的一个该周期而后维持一逻辑高状态达该输入信号的半个该周期，并依该方式循环。 According to the above concept, the frequency divider further includes: a divisor control unit corresponding to a dual edge trigger of the input signal and the first or second state to generate a divisor selection signal, and a frequency dividing unit coupled to The control unit, and correspondingly the dual edge trigger and the selection signal to generate the output signal of the frequency divider, wherein when the first state is, the divisor control signal is in a logic low state, and when the second state is The divisor control signal is to maintain the logic low state for one cycle of the input signal and then maintain a logic high state for half of the cycle of the input signal, and cycle in the manner.

本发明的又一主要目的在于提供一种可编程分数除频器，用于将一输入信号除以复数个具有一分数除数间隔的除数其中之一，以产生一第一输出信号，该除频器包含：一分数除频器，用于接收该输入信号并于一第一及一第二状态时将该输入信号分别除以一第一整数及一分数除数以产生一第二输出信号，以及一除频器长链，具有复数个彼此串连耦合的整数除频器，用于接收该第二输出信号并产生该第一输出信号，其中各该整数除频器于一第三及一第四状态时将该整数除频器的一输入信号分别除以一第二整数及一第三整数除数以产生该整数除法器的一输出信号。 Another main object of the present invention is to provide a programmable fractional divider for dividing an input signal by a plurality of divisors having a fractional divisor interval to generate a first output signal. The device includes: a fractional frequency divider for receiving the input signal and dividing the input signal by a first integer and a fractional divisor to generate a second output signal, respectively, in a first and a second state, and a frequency divider long chain having a plurality of integer frequency dividers coupled in series with each other for receiving the second output signal and generating the first output signal, wherein each of the integer frequency dividers is in a third and a first In the four state, an input signal of the integer frequency divider is divided by a second integer and a third integer divisor to generate an output signal of the integer divider.

根据上述的构想，该分数除频器用于接收复数个除数控制信号其中之一及该长链的一反馈控制信号，且各该整数除频器用于接收该等复数个除数控制信号其中之一与各该整数除频器的一反馈控制信号。 According to the above concept, the fractional frequency divider is configured to receive one of a plurality of divisor control signals and a feedback control signal of the long chain, and each of the integer frequency dividers is configured to receive the plurality of divisor control signals. One of the feedback control signals of one of the integer dividers.

根据上述的构想，当该分数除频器处于该第一状态时，该分数除频器的该除数控制信号或该长链的该反馈控制信号为一逻辑低状态，当该分数除频器是处于该第二状态时，该分数除频器的该除数控制信号与该长链的该反馈控制信号均为一逻辑高状态，当该整数除频器处于该第三状态时，该整数除频器的该除数控制信号或该反馈控制信号为一逻辑低状态，当该整数除频器处于该第四状态时，该整数除频器的该除数控制信号与该反馈控制信号均为一逻辑高状态。 According to the above concept, when the fractional frequency divider is in the first state, the divisor control signal of the fractional frequency divider or the feedback control signal of the long chain is in a logic low state, when the fractional frequency divider is In the second state, the divisor control signal of the fractional frequency divider and the feedback control signal of the long chain are both in a logic high state, and when the integer frequency divider is in the third state, the integer frequency division is performed. The divisor control signal or the feedback control signal of the device is in a logic low state, and when the integer frequency divider is in the fourth state, the divisor control signal of the integer frequency divider and the feedback control signal are both logic high status.

根据上述的构想，该可编程分数除频器的各该除数的一除数值，是借助设定该复数个除数控制信号为该逻辑高或低状态来决定，各该除数的该除数值是处在一自 2的 N次方至 2的 (N+1)次方- 0. 5的范围内，各该除数的该间隔为 0. 5，且该 (N+1) 为该等复数个除数控制信号的一总数。 According to the above concept, a divisor value of each divisor of the programmable fractional divider is determined by setting the complex divisor control signal to the logic high or low state, and the divisor value of each divisor is In the range from the Nth power of 2 to the (N+1)th power of -2. 5, the interval of each divisor is 0.5, and the (N+1) is the plural divisors. A total number of control signals.

根据上述的构想，各该整数除频器为一除数为 2及 3两者之一的整数除频器。根据上述的构想，该分数除频器及该复数个整数除频器的前两级，是采用源极耦合逻辑（SCL)电路，其余的该复数个整数除频器则是采用互补金氧半场效 (CMOS ) 逻辑电路，且在第二级的该整数除频器与第三级的该整数除频器之间还包括一 SCL和 CMOS逻辑转换界面电路。 According to the above concept, each of the integer frequency dividers is an integer frequency divider having a divisor of either 2 and 3. According to the above concept, the fractional frequency divider and the first two stages of the complex integer frequency divider are source coupled logic (SCL) circuits, and the remaining plurality of integer frequency dividers are complementary gold oxide half. Field-effect (CMOS) logic, and an SCL and CMOS logic switching interface circuit between the integer divider of the second stage and the integer divider of the third stage.

根据上述的构想，该 SCL电路还包括：复数个 SCL锁存器以及复数个 SCL多路转接器。 According to the above concept, the SCL circuit further includes: a plurality of SCL latches and a plurality of SCL multiplexers.

本发明的再一主要目的在于提供一种具有可调除频范围的可编程分数除频器，用于接收一输入信号并依据一延伸控制信号以调整复数个具有一分数除数间隔的除数所形成的一除频范围，且据以产生一输出信号，该除频器包含：一可编程分数除频器电路，用于将该输入信号除以该复数个具有一分数除数间隔的除数其中之一，以产生该输出信号，该除频器电路包含复数个彼此串连耦合的整数除频器，以及一除数延伸电路，用以依据该延伸控制信号以切断或不切断包含一特定整数除频器之后的所有各该整数除频器的一反馈控制，以使该可编程分数除频器的该除频范围可被据以调整。 . A further main object of the present invention is to provide a programmable fractional frequency divider having an adjustable frequency division range for receiving an input signal and adjusting a plurality of divisors having a fractional divisor interval according to an extension control signal. a frequency dividing range, and accordingly generating an output signal, the frequency divider comprising: a programmable fractional divider circuit for dividing the input signal by the plurality of divisors having a fractional divisor interval And generating the output signal, the frequency divider circuit includes a plurality of integer frequency dividers coupled in series with each other, and a divisor extension circuit for cutting or not cutting a specific integer divider according to the extension control signal Subsequent feedback control of all of the integer frequency dividers allows the frequency division range of the programmable fractional divider to be adjusted accordingly. .

根据上述的构想，该除数延伸电路还包含：复数个 "或" 门（OR gate) , 其中各该 "或" 门具有一第一、一第二与一输出端，且该第一与该输出端耦合于在任意两个直接相连的该整数除频器之间及在一分数除频器与该复数个整数除频器之间的复数个反馈电路其中的任一，一解码器（decoder) ，具有一输入端及复数个输出端，其中该输入端用于接收该延伸控制信号，该复数个输出端其中的每一耦合于该复数个 "或" 门的该第二端其中的任一，该复数个输出端为输出复数个逻辑低状态与其中的任一是输出一逻辑高状态而其余则输出一逻辑低状态两者其中之一，且输出该逻辑高状态的该输出端以后的该整数除频器是等效于被切断，故对该可编程除频器的该输出信号不产生作用，而可减低该除频范围，以及一多路转接器 (mux) , 具有复数个输入端与一输出端，其中该复数个输入端的每一用于接收该延伸控制信号或耦合于在该任意两个直接相连的该整数除频器之间及在该分数除频器与该复数个整数除频器之间的复数个连接电路其中的任一，该输出端用以输出该可编程分数除频器的该输出信号，且该多路转接器将依据该延伸控制信号以选择该复数个输入端其中之一的一输入信号作为该输出信号。 According to the above concept, the divisor extension circuit further includes: a plurality of OR gates, wherein each of the OR gates has a first, a second, and an output, and the first and the output The end is coupled between any two directly connected integer frequency dividers and a fractional frequency divider and the plurality of integer frequency dividers Any one of a plurality of feedback circuits, a decoder having an input and a plurality of outputs, wherein the input is configured to receive the extension control signal, each of the plurality of outputs Any one of the second ends coupled to the plurality of OR gates, the plurality of outputs are outputting a plurality of logic low states and one of them outputs a logic high state and the remaining outputs a logic low state One of the two, and the integer frequency divider after outputting the output of the logic high state is equivalent to being cut off, so that the output signal of the programmable frequency divider has no effect, and the a frequency division range, and a multiplexer (mux) having a plurality of inputs and an output, wherein each of the plurality of inputs is configured to receive the extension control signal or to be directly coupled to the any two Any one of a plurality of connection circuits between the integer frequency dividers and between the fractional frequency divider and the plurality of integer frequency dividers, the output terminal is configured to output the programmable fractional frequency divider lose Signal, and the multiplexer control signal according to the extension of an input signal to select one of the plurality of input terminals wherein as the output signal.

本发明的下一主要目的在于提供一种分数型锁相回路，包含：一压控震荡器，用于接收一输入信号与产生一输出信号，以及一可编程分数除频器，耦合于该压控震荡器，用于接收该输出信号的一反馈信号，且将该反馈信号经除以复数个具有一分数除数间隔的除数其中之一，以产生一经除频的输出信号。 The next main object of the present invention is to provide a fractional phase-locked loop, comprising: a voltage controlled oscillator for receiving an input signal and generating an output signal, and a programmable fractional frequency divider coupled to the voltage The control oscillator is configured to receive a feedback signal of the output signal, and divide the feedback signal by a plurality of divisors having a fractional divisor interval to generate a frequency-divided output signal.

根据上述的构想，该压控震荡器该输出信号的一频率，最后将稳定于该参考信号源的一频率乘以该除数的一平均值。 According to the above concept, the voltage controlled oscillator outputs a frequency of the output signal, and finally a frequency stabilized by the reference signal source is multiplied by an average of the divisor.

根据上述的构想，该压控震荡器还包括：一第一压控电容，具有一第一端与 —第二端，其中该第一端耦合于该回路滤波器，用于依据该输入信号调整该压控震荡器的一震荡频率，一第二压控电容，具有一第一端与一第二端，其中该第一端耦合于该第一压控电容的该第一端，用于依据该输入信号调整该压控震荡器的该震荡频率，一第一电感，具有一第一端与一第二端，其中该第一端耦合于该第一压控电容的该第二端，该第一电感的该第二端接地，且该第一电感用于与该第一压控电容形成一第一共震腔，一第二电感，具有一第一端与一第二端，其中该第一端耦合于该第二压控电容的该第二端，该第二电感的该第二端接地，且该第二电感用于与该第二压控电容形成一第二共震腔，一第一电容阵列，用于与该第一电感与该第一压控电容形成该第一共震腔，该第一电容阵列包括：复数个第一共震电容，各该第一共震电容均具有一第一端与一第二端，且该第一端均耦合于该第一电感的该第一端，以及复数个第一开关，各该第一开关的每一个均具有一第一端与一第二端，且该第一端耦合于该复数个第一共震电容其中的任一的该第二端，且该复数个第一开关的该第二端接地，一第二电容阵列，用于与该第二电感与该第二压控电容形成该第二共震腔，该第二电容阵列包括：复数个第二共震电容，各该第二共震电容均具有一第一端与一第二端，且该第一端均耦合于该第二电感的该第一端，以及复数个第二开关，各该第二开关均具有一第一端与一第二端，且该第一端耦合于该复数个第二共震电容其中的任一的该第二端，且该复数个第二开关的该第二端接地，以及一核心电路，分别耦合于该第一与该第二电感的该第一端，用于产生该压控震荡器的该输出信号。 According to the above concept, the voltage controlled oscillator further includes: a first voltage control capacitor having a first end and a second end, wherein the first end is coupled to the loop filter for adjusting according to the input signal An oscillating frequency of the voltage-controlled oscillator, a second voltage-controlled capacitor having a first end and a second end, wherein the first end is coupled to the first end of the first voltage-controlled capacitor for The input signal adjusts the oscillation frequency of the voltage controlled oscillator, the first inductor has a first end and a second end, wherein the first end is coupled to the second end of the first voltage control capacitor, The second end of the first inductor is grounded, and the first inductor is configured to form a first common shock cavity with the first voltage control capacitor, and a second inductor has a first end and a second end, wherein the first end The first end is coupled to the second end of the second voltage-controlled capacitor, the second end of the second inductor is grounded, and the second inductor is configured to form a second co-seismic cavity with the second voltage-controlled capacitor, a first capacitor array for forming with the first inductor and the first voltage controlled capacitor a first common shock cavity, the first capacitor array includes: a plurality of first common shock capacitors, each of the first common shock capacitors has a first end and a second end, and the first end is coupled to the first The first end of an inductor, and the plurality of first switches, each of the first switches each having a a first end and a second end, and the first end is coupled to the second end of any one of the plurality of first common shock capacitors, and the second end of the plurality of first switches is grounded a second capacitor array, configured to form the second resonance cavity with the second inductor and the second voltage control capacitor, the second capacitor array comprising: a plurality of second common-shock capacitors, each of the second common-shock capacitors having a first end and a second end, and the first end is coupled to the first end of the second inductor, and the plurality of second switches, each of the second switches having a first end and a second end And the first end is coupled to the second end of any one of the plurality of second common-shock capacitors, and the second end of the plurality of second switches is grounded, and a core circuit is coupled to the first end The first end of the first and the second inductor are configured to generate the output signal of the voltage controlled oscillator.

根据上述的构想，该核心电路还包括：一第一电晶体，具有一第一、一第二与一控制端，其中该第一端耦合于该可编程分数除频器，且该第二端耦合于该控制端，一第二晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该可编程分数除频器，且该控制端耦合于该第一晶体管的该控制端，一第一电阻，具有一第一与一第二端，其中该第一端耦合于该第一晶体管的该第二端，且该第一电阻的该第二端接地，一第三晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该第二晶体管的该第二端，该控制端耦合于该第一电感的该第一端，且该第三晶体管的该第二端耦合于该第二电感的该第一端，以及一第四晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该第三晶体管的该第一端，该第二端耦合于该第一电感的该第一端，且该控制端耦合于该第二电感的该第一端。 According to the above concept, the core circuit further includes: a first transistor having a first, a second, and a control end, wherein the first end is coupled to the programmable fractional frequency divider, and the second end Coupled to the control terminal, a second transistor having a first, a second, and a control terminal, wherein the first terminal is coupled to the programmable fractional frequency divider, and the control terminal is coupled to the first transistor The first resistor has a first end and a second end, wherein the first end is coupled to the second end of the first transistor, and the second end of the first resistor is grounded a third transistor having a first, a second, and a control terminal, wherein the first end is coupled to the second end of the second transistor, the control end is coupled to the first end of the first inductor, and the The second end of the third transistor is coupled to the first end of the second inductor, and the fourth transistor has a first, a second, and a control end, wherein the first end is coupled to the third transistor The first end, the second end is coupled The first end of the first inductor is coupled to the first end of the second inductor.

根据上述的构想，该分数型锁相回路还包含：一石英震荡器，用于产生一参考信号源，一相频检测器，耦合于该石英震荡器与该可编程分数除频器，用于比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号，一电荷泵，耦合于该相频检测器，用于在接收该充电信号时产生一充电动作以提升一输出电流而提升该输出信号的一频率，且在接收该放电信号时产生一放电动作以降低该输出电流而降低该输出信号的该频率，一回路滤波器，耦合于该电荷泵与该压控震荡器，用以滤除该电荷泵该输出电流的一相位杂讯，且据以产生该压控震荡器的该输入信号，一三角积分调变器，用于接收一外加输入信号以产生一调变信号，以及一加法器，耦合于该调变器与该可编程分数除频器，用于接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数 06 000374 除频器以产生该除数。 According to the above concept, the fractional phase-locked loop further comprises: a quartz oscillator for generating a reference signal source, a phase frequency detector coupled to the quartz oscillator and the programmable fractional frequency divider, Comparing a phase and a frequency of the reference signal source and the frequency-divided output signal, and generating a charge or a discharge signal, a charge pump coupled to the phase frequency detector for receiving the charging signal Generating a charging action to boost an output current to increase a frequency of the output signal, and generating a discharging action to reduce the output current and reduce the frequency of the output signal when receiving the discharging signal, the primary loop filter, coupling And the voltage-controlled oscillator and the voltage-controlled oscillator for filtering a phase noise of the output current of the charge pump, and generating the input signal of the voltage-controlled oscillator, a triangular integral modulator, for Receiving an applied input signal to generate a modulated signal, and an adder coupled to the modulator and the programmable fractional divider for receiving an added integer Modulated signal, and inputs the programmable score after the two together 06 000374 Frequency divider to generate the divisor.

根据上述的构想，该石英震荡器为一温度补偿石英震荡器 (TCX0)。 According to the above concept, the quartz oscillator is a temperature compensated quartz oscillator (TCX0).

根据上述的构想，该相频检测器更用于接收一极性控制信号 (POL)，当 P0L=1 及该参考信号源领先该输出信号时，该相频检测器输出该充电信号，而当 POL=0及该输出信号领先该参考信号源时，该相频检测器则输出该放电信号。 According to the above concept, the phase frequency detector is further configured to receive a polarity control signal (POL). When P0L=1 and the reference signal source leads the output signal, the phase frequency detector outputs the charging signal, and when When POL=0 and the output signal leads the reference signal source, the phase frequency detector outputs the discharge signal.

根据上述的构想，该电荷泵还包括：一偏压电流源，用于提供一电流偏压，一偏压电路，耦合于该偏压电流源，用于提供一偏压，一第一输出电流源，耦合于该偏压电路，用于提供一第一输出电流，一充电开关，耦合于该相频检测器与该第一输出电流源，用于当接收该充电信号时，产生该充电动作，一放电开关，耦合于该相频检测器与该输出电流源，用于当接收该放电信号时，产生该放电动作，一第一控制开关，耦合于该输出电流源，用以控制该泵的一输出电流的大小，一第二输出电流源，耦合于该第一控制开关，用于提供一第二输出电流，一第二控制开关，耦合于该第二输出电流源，用以控制该泵的该输出电流的大小，一第三输出电流源，耦合于该第二控制开关，用于提供一第三输出电流。 According to the above concept, the charge pump further includes: a bias current source for providing a current bias, a bias circuit coupled to the bias current source for providing a bias voltage, a first output current a source coupled to the bias circuit for providing a first output current, a charging switch coupled to the phase frequency detector and the first output current source, configured to generate the charging action when receiving the charging signal a discharge switch coupled to the phase frequency detector and the output current source for generating the discharge action when receiving the discharge signal, a first control switch coupled to the output current source for controlling the pump An output current source, a second output current source coupled to the first control switch for providing a second output current, and a second control switch coupled to the second output current source for controlling the The magnitude of the output current of the pump, a third output current source coupled to the second control switch for providing a third output current.

根据上述的构想，该偏压电路为一标准的低电压偏压电路，当该第一与该第二控制开关均关断时，该输出电流为该第一输出电流，当该第一控制开关导通及该第二控制开关关断时，该输出电流为该第一输出电流与该第二输出电流的和，且当该第一与该第二控制开关均导通时，该输出电流为该第一、该第二与该第三输出电流的和。 According to the above concept, the bias circuit is a standard low voltage bias circuit. When the first control switch and the second control switch are both turned off, the output current is the first output current, when the first control switch When the conduction and the second control switch are turned off, the output current is a sum of the first output current and the second output current, and when both the first control switch and the second control switch are turned on, the output current is a sum of the first, the second, and the third output current.

根据上述的构想，该回路滤波器为一三阶滤波器。 According to the above concept, the loop filter is a third-order filter.

根据上述的构想，该回路滤波器还包括：一第一电容，具有一第一端与一第二端，其中该第一端耦合于该电荷泵，且该第二端接地，一第二电阻，具有一第一端与一第二端，其中该第一端耦合于该第一电容的该第一端，一第二电容，具有一第一端与一第二端，其中该第一端耦合于该第二电阻的该第二端，且该第二电容的该第二端接地，一第三电阻，具有一第一端与一第二端，其中该第一端耦合于该第二电阻的该第一端，以及一第三电容，具有一第一端与一第二端，其中该第一端耦合于该第三电阻的该第二端与该压控震荡器，且该第三电容的该第二端接地。 According to the above concept, the loop filter further includes: a first capacitor having a first end and a second end, wherein the first end is coupled to the charge pump, and the second end is grounded, and a second resistor Having a first end and a second end, wherein the first end is coupled to the first end of the first capacitor, and a second capacitor has a first end and a second end, wherein the first end The second end of the second resistor is coupled to the second end, and the second end of the second capacitor is grounded. The third resistor has a first end and a second end, wherein the first end is coupled to the second end The first end of the resistor, and a third capacitor having a first end and a second end, wherein the first end is coupled to the second end of the third resistor and the voltage controlled oscillator, and the The second end of the three capacitors is grounded.

根据上述的构想，该三角积分器为一三阶三角积分器。根据上述的构想，该三角积分器包括：一第一一阶三角积分器，用于接收该外加的输入信号以产生一第一量化杂讯与一第一输出信号，一第二一阶三角积分器，耦合于该第一一阶三角积分器，用于接收该第一量化杂讯以产生一第二量化杂讯与一第二输出信号，一第三一阶三角积分器，耦合于该第二一阶三角积分器，用于接收该第二量化杂讯以产生一第三输出信号，以及一位操控节点，耦合于该第一、该第二与该第三一阶三角积分器，用于接收该第一、该第二与该第三输出信号以产生该调变信号。 According to the above concept, the triangular integrator is a third-order triangular integrator. According to the above concept, the triangular integrator includes: a first first-order triangular integrator, configured to receive the applied input signal to generate a first quantization noise and a first output signal, and a second first-order triangular integral And coupled to the first first-order triangular integrator, configured to receive the first quantization noise to generate a second quantization noise and a second output signal, and a third first-order triangular integrator coupled to the first a second-order triangular integrator for receiving the second quantization noise to generate a third output signal, and a steering node coupled to the first, the second, and the third first-order triangular integrator Receiving the first, second, and third output signals to generate the modulated signal.

根据上述的构想，该第一、该第二与该第三一阶三角积分器皆为一 24位的累加器。 According to the above concept, the first, second and third first-order triangular integrators are all a 24-bit accumulator.

根据上述的构想，该第一一阶三角积分器为一 24位的累加器，该第二一阶三角积分器为一 16位的累加器，且该第三一阶三角积分器为一 8位的累加器。 According to the above concept, the first first-order triangular integrator is a 24-bit accumulator, the second first-order triangular integrator is a 16-bit accumulator, and the third first-order triangular integrator is an 8-bit accumulator. Accumulator.

本发明的另一主要目的在于提供一种具有可调除频范围的分数型锁相回路，包含：一分数型锁相回路电路，用于接收一输入信号与产生一输出信号，包含一可编程分数除频器，用于接收该输出信号的一反馈信号，且将该反馈信号经除以复数个具有一分数除数间隔的除数其中之一，以产生一经除频的输出信号，以及一除数延伸电路，用以依据一延伸控制信号，俾使该可编程分数除频器的该复数个除数所形成的一除频范围可被据以调整。 Another main object of the present invention is to provide a fractional phase-locked loop having an adjustable frequency division range, comprising: a fractional phase-locked loop circuit for receiving an input signal and generating an output signal, including a programmable a fractional frequency divider, configured to receive a feedback signal of the output signal, and divide the feedback signal by a plurality of divisors having a fractional divisor interval to generate a divided output signal, and a divisor extension The circuit is configured to adjust a frequency division range formed by the plurality of divisors of the programmable fractional divider according to an extended control signal.

根据上述的构想，该分数型锁相回路还包含：一石英震荡器，用于产生一参考信号源，一相频检测器，耦合于该石英震荡器与该具有可调除频范围的可编程分数除频器，用于比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电信号或一放电信号，一电荷泵，耦合于该相频检测器，用于在接收该充电信号时产生一充电动作以提升一输出电流俾提升该输出信号的一频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该输出信号的该频率，一回路滤波器，耦合于该电荷泵与该压控震荡器，用以滤除该电荷泵该输出电流的一相位杂讯，且据以产生该压控震荡器的该输入信号，一三阶三角积分调变器，用于接收一外加输入信号以产生一调变信号，以及一加法器，耦合于该调变器与该可编程分数除频器，用于接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器以产生该除数。 According to the above concept, the fractional phase-locked loop further comprises: a quartz oscillator for generating a reference signal source, a phase frequency detector coupled to the quartz oscillator and the programmable programmable frequency range a fractional frequency divider for comparing a phase and a frequency of the reference signal source with the frequency-divided output signal, and generating a charging signal or a discharging signal, a charge pump coupled to the phase frequency detector And generating a charging action to receive an output current to increase a frequency of the output signal when receiving the charging signal, and generating a discharging action to reduce the output current when the discharging signal is received to reduce the output signal a first loop filter coupled to the charge pump and the voltage controlled oscillator for filtering a phase noise of the output current of the charge pump, and generating the input signal of the voltage controlled oscillator, a third-order delta-sigma modulator for receiving an applied input signal to generate a modulated signal, and an adder coupled to the modulator and the programmable fraction Frequency divider for receiving an integer applied to the modulation signal, and inputs the programmable fractional divider to generate the divisor after the addition of both.

本发明的次一主要目的在于提供一种分数除频器的控制方法，该方法包含下列步骤：（a)当一分数除频器用于将一输入信号除以一整数除数以产生一输出信号时，使一除数控制信号或一反馈控制信号为一逻辑低状态，且使该除频器相应一输入信号的一双缘触发而产生一具有逻辑低状态的除数选择信号以使该除频器的一输出信号的产生不被抑制；（b)当该除数控制信号及该反馈控制信号均为一逻辑高状态时，使该除频器相应该双缘触发而产生一具有逻辑高状态的除数选择信号以使该输出信号的产生被抑制；以及 (c)当该除频器用于将该输入信号除以一分数除数以产生该输出信号时，该除频器产生该具有逻辑低状态的除数选择信号以使该输出信号持续产生达该输入信号的一个周期，而后该除频器产生该具有逻辑高状态的除数选择信号以使该输出信号的产生被抑制达半个该周期，并依此一方式循环。 A second main objective of the present invention is to provide a method for controlling a fractional frequency divider, the method comprising the following Column step: (a) when a fractional frequency divider is used to divide an input signal by an integer divisor to generate an output signal, causing a divisor control signal or a feedback control signal to be in a logic low state, and causing the frequency division a pair of edge triggers corresponding to an input signal to generate a divisor selection signal having a logic low state to prevent generation of an output signal of the frequency divider; (b) when the divisor control signal and the feedback control signal are both a logic high state, causing the frequency divider to generate a divisor selection signal having a logic high state corresponding to the double edge triggering to cause generation of the output signal to be suppressed; and (c) when the frequency divider is used to When the input signal is divided by a fractional divisor to generate the output signal, the frequency divider generates the divisor selection signal having a logic low state to continuously generate the output signal for one cycle of the input signal, and then the frequency divider generates the signal A divisor selection signal having a logic high state causes the generation of the output signal to be suppressed for half of the period, and cycles in this manner.

本发明的又一主要目的在于提供一种可编程分数除频器的控制方法，其中该除频器用于将一输入信号除以复数个具有一分数除数间隔的除数其中之一以产生一第一输出信号，该除频器包括一分数除频器，用于产生一第二输出信号，及一除频器长链，包含复数个彼此串连耦合的整数除频器，耦合于该分数除频器，用于产生该第一输出信号，该方法包含下列步骤：（a)使该分数除频器接收该输入信号、复数个除数控制信号其中之一及该长链的一反馈控制信号，且使各该整数除频器均接收该复数个除数控制信号其中之一及各该整数除频器的一反馈控制信号；（b)当该分数除频器的该除数控制信号或该长链的该反馈控制信号为一逻辑低状态时，将该输入信号除以一第一整数除数以产生该第二输出信号，当该分数除频器的该除数控制信号或该长链的该反馈控制信号保持一逻辑低状态达该输入信号的一个周期，而后该分数除频器的该除数控制信号及该长链的该反馈控制信号保持一逻辑高状态达半个该周期，并依此一方式循环时，将该输入信号除以一分数除数以产生该第二输出信号；（c)当该整数除频器的该除数控制信号或该反馈控制信号为一逻辑低状态时，将该整数除频器的一输入信号除以一第二整数除数以产生该整数除频器的一输出信号，当该整数除频器的该除数控制信号及该反馈控制信号均保持一逻辑高状态时，将该整数除频器的该输入信号除以一第三整数除数以产生该整数除频器的该输出信号；以及 (d)使该可编程分数除频器依据该输入信号及各该除数以产生该第一输出信号。 Another main object of the present invention is to provide a control method of a programmable fractional frequency divider, wherein the frequency divider is configured to divide an input signal by a plurality of divisors having a fractional divisor interval to generate a first An output signal, the frequency divider comprising a fractional frequency divider for generating a second output signal, and a long divider of the frequency divider, comprising a plurality of integer frequency dividers coupled in series with each other, coupled to the fractional frequency division For generating the first output signal, the method includes the following steps: (a) causing the fractional frequency divider to receive the input signal, one of the plurality of divisor control signals, and a feedback control signal of the long chain, and Having each of the integer frequency dividers receive one of the plurality of divisor control signals and a feedback control signal of each of the integer frequency dividers; (b) when the divisor control signal of the fractional divider or the long chain When the feedback control signal is in a logic low state, the input signal is divided by a first integer divisor to generate the second output signal, when the divisor control signal of the fractional divider or the The feedback control signal of the chain maintains a logic low state for one cycle of the input signal, and then the divisor control signal of the fractional frequency divider and the feedback control signal of the long chain maintain a logic high state for half of the period, And cyclically dividing the input signal by a fractional divisor to generate the second output signal; (c) when the divisor control signal of the integer frequency divider or the feedback control signal is in a logic low state Dividing an input signal of the integer frequency divider by a second integer divisor to generate an output signal of the integer frequency divider, and maintaining the logic of the divisor control signal and the feedback control signal of the integer frequency divider In the high state, dividing the input signal of the integer frequency divider by a third integer divisor to generate the output signal of the integer frequency divider; and (d) causing the programmable fractional divider to be based on the input signal and Each of the divisors produces the first output signal.

本发明的再一主要目的在于提供一种具有可调除频范围的可编程分数除频器的控制方法，其中该除频器用于将一输入信号除以复数个具有一分数除数间隔的除数其中之一以产生一第一输出信号，该除频器包括一分数除频器，用于产生一第二输出信号，一除频器长链，包含复数个彼此串连耦合的整数除频器，耦合于该分数除频器，用于产生该第一输出信号，及一除数延伸电路，用以调整该复数个除数所形成的一除数范围，该方法包含下列步骤：（a)使该除数延伸电路产生一控制信号以切断或不切断包含一特定整数除频器之后的所有各该整数除频器的一反馈控制，俾使该除数范围可被调整；（b)使该分数除频器接收该输入信号、复数个除数控制信号其中之一及该长链的一反馈控制信号，且使各该整数除频器均接收该复数个除数控制信号其中之一及各该整数除频器的一反馈控制信号；（c)当该分数除频器的该除数控制信号或该长链的该反馈控制信号为一逻辑低状态时，将该输入信号除以一第一整数除数以产生该第二输出信号，当该分数除频器的该除数控制信号或该长链的该反馈控制信号保持一逻辑低状态达该输入信号的一个周期，而后该分数除频器的该除数控制信号及该长链的该反馈控制信号保持一逻辑高状态达半个该周期，并依此一方式循环时，将该输入信号除以一分数除数以产生该第二输出信号；（d)当该整数除频器的该除数控制信号或该反馈控制信号为一逻辑低状态时，将该整数除频器的一输入信号除以一第二整数除数以产生该整数除频器的一输出信号，当该整数除频器的该除数控制信号及该反馈控制信号均保持一逻辑高状态时，将该整数除频器的该输入信号除以一第三整数除数以产生该整数除频器的该输出信号；以及 (e)使该可编程分数除频器依据该输入信号及各该除数以产生该第一输出信号。 Still another main object of the present invention is to provide a programmable fractional frequency divider having an adjustable frequency division range Control method, wherein the frequency divider is configured to divide an input signal by a plurality of divisors having a fractional divisor interval to generate a first output signal, the frequency divider comprising a fractional frequency divider for generating a second output signal, a long divider of the frequency divider, comprising a plurality of integer frequency dividers coupled in series with each other, coupled to the fractional frequency divider for generating the first output signal, and a divisor extension circuit To adjust a divisor range formed by the plurality of divisors, the method includes the steps of: (a) causing the divisor extension circuit to generate a control signal to cut or not cut all of the integers including a particular integer divider; a feedback control of the frequency converter to enable the divisor range to be adjusted; (b) causing the fractional frequency divider to receive the input signal, one of the plurality of divisor control signals, and a feedback control signal of the long chain, and Each of the integer frequency dividers receives one of the plurality of divisor control signals and a feedback control signal of each of the integer frequency dividers; (c) the divisor control of the fractional frequency divider When the signal or the long chain of the feedback control signal is in a logic low state, dividing the input signal by a first integer divisor to generate the second output signal, when the divisor control signal of the fractional divider or the length The feedback control signal of the chain maintains a logic low state for one cycle of the input signal, and then the divisor control signal of the fractional frequency divider and the feedback control signal of the long chain maintain a logic high state for half of the period, And in the same manner, the input signal is divided by a fractional divisor to generate the second output signal; (d) when the divisor control signal of the integer frequency divider or the feedback control signal is in a logic low state Dividing an input signal of the integer frequency divider by a second integer divisor to generate an output signal of the integer frequency divider, and maintaining the logic of the divisor control signal and the feedback control signal of the integer frequency divider In the high state, dividing the input signal of the integer frequency divider by a third integer divisor to generate the output signal of the integer frequency divider; and (e) causing the programmable fractional frequency divider According to the input signal and each of the divisor to generate the first output signal.

本发明的下一主要目的在于提供一种分数型锁相回路的控制方法，该方法包含下列步骤：（a)使一压控震荡器接收一输入信号与产生一输出信号；以及 (b)使一可编程分数除频器接收该输出信号的一反馈信号，且将该反馈信号经复数个具有一分数除数间隔的除数其中之一的除频后，产生一经除频的输出信号。 The next main object of the present invention is to provide a method for controlling a fractional phase-locked loop, the method comprising the steps of: (a) causing a voltage controlled oscillator to receive an input signal and generate an output signal; and (b) A programmable fractional frequency divider receives a feedback signal of the output signal, and divides the feedback signal by a plurality of divisors having a fractional divisor interval to generate a frequency-divided output signal.

根据上述的构想，该控制方法还包含下列步骤：（c)使一石英震荡器产生一参考信号源；（d)由一相频检测器比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号；（e)使一电荷泵于接收该充电信号时产生一充电动作以提升一输出电流俾提升该经除频的输出信号的该频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该经除频的输出信号的该频率；（f)由一回路滤波器滤除该电荷泵该输出电流的一相位杂讯，且据以产生该压控震荡器的该输入信号；（g)使一三角积分调变器接收一外加的输入信号以产生一调变信号；（h)使一加法器接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器，以产生该除数；以及（i)经该分数型锁相回路的复数个运作后，使该压控震荡器该输出信号的一频率，稳定于该参考信号源的一频率乘以该除数的一平均值。 According to the above concept, the control method further comprises the following steps: (c) causing a quartz oscillator to generate a reference signal source; (d) comparing the reference signal source and the frequency-divided output signal by a phase frequency detector; a phase and a frequency, and accordingly generating a charge or a discharge signal; (e) causing a charge pump to generate a charging action upon receiving the charge signal to boost an output current and boost the frequency-divided output signal Frequency, and generating a discharge action to reduce the output current when receiving the discharge signal, reducing the frequency-divided output signal (f) filtering a phase noise of the output current of the charge pump by a loop filter, and generating the input signal of the voltage controlled oscillator; (g) causing a triangular integral modulator Receiving an additional input signal to generate a modulated signal; (h) causing an adder to receive an applied integer and the modulated signal, and adding the two to the programmable fractional divider to generate And (i) after the plurality of operations of the fractional phase-locked loop, causing a frequency of the output signal of the voltage controlled oscillator to be stabilized at a frequency of the reference signal source multiplied by an average of the divisor .

本发明的另一主要目的在于提供一种具有可调除频范围的分数型锁相回路的控制方法，该方法包含下列步骤：（a)使一压控震荡器接收一输入信号与产生一输出信号；以及 (b)使一具有可调除频范围的可编程分数除频器接收该输出信号的一反馈信号，且将该反馈信号经复数个具有一分数除数间隔的除数其中之一的除频后，产生一经除频的输出信号，且该除频器的一除数范围是相应该除频器所接收的一延伸控制信号而可被据以调整。 Another main object of the present invention is to provide a control method for a fractional phase-locked loop having an adjustable frequency division range, the method comprising the steps of: (a) causing a voltage controlled oscillator to receive an input signal and generate an output And (b) causing a programmable fractional divider having an adjustable frequency division range to receive a feedback signal of the output signal, and dividing the feedback signal by a plurality of divisors having a fractional divisor interval After the frequency, a frequency-divided output signal is generated, and a divisor range of the frequency divider is adjusted according to an extended control signal received by the frequency divider.

根据上述的构想，该控制方法还包含下列步骤：（c)使一石英震荡器产生一参考信号源；（d)由一相频捡测器比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号；（e)使一电荷泵于接收该充电信号时产生一充电动作以提升一输出电流俾提升该经除频的输出信号的该频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该经除频的输出信号的该频率；（f)由一回路滤波器滤除该电荷泵该输出电流的一相位杂讯，且据以产生该压控震荡器的该输入信号；（g)使一三角积分调变器接收一外加的输入信号以产生一调变信号；（h)使一加法器接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器，以产生该除数；以及（i)经该分数型锁相回路的复数个运作后，使该压控震荡器该输出信号的一频率，稳定于该参考信号源的一频率乘以该除数的一平均值。附图概述 According to the above concept, the control method further comprises the following steps: (c) causing a quartz oscillator to generate a reference signal source; (d) comparing the reference signal source and the frequency-divided output signal by a phase frequency detector. a phase and a frequency, and accordingly generating a charge or a discharge signal; (e) causing a charge pump to generate a charging action upon receiving the charge signal to boost an output current and boost the frequency-divided output signal The frequency, and receiving a discharge signal to generate a discharge action to reduce the output current, reduce the frequency of the frequency-divided output signal; (f) filtering the output current of the charge pump by a loop filter Phase noise, and accordingly generating the input signal of the voltage controlled oscillator; (g) causing a triangular integral modulator to receive an applied input signal to generate a modulated signal; (h) causing an adder to receive a An additional integer and the modulated signal, and adding the two to the programmable fractional divider to generate the divisor; and (i) after the plurality of operations of the fractional phase-locked loop, Pressure A frequency at which the output signal of the oscillator is stabilized at a frequency of the reference source multiplied by an average of the divisor. BRIEF abstract

图 1 : 其显示一现有的锁相回路频率合成器的基本架构图; Figure 1: shows the basic architecture of an existing phase-locked loop frequency synthesizer;

图 2: 其显示一现有的分数型锁相回路的基本架构图； Figure 2: shows the basic architecture of an existing fractional phase-locked loop;

图 3 : 其显示一现有的可编程除频器的架构图； Figure 3: shows an architectural diagram of an existing programmable frequency divider;

图 4: 其显示一现有的除数为 2/3的除频器的架构图；图 5: 其显示一依据本发明构想的除数为 1/1. 5的除频器的架构图；图 6: 其显示一依据本发明构想的除数为 1/1. 5的除频器的操作图； Figure 4: It shows an architectural diagram of a conventional divider with a divide by 2/3; Figure 5: shows an architectural diagram of a frequency divider with a divisor of 1/1.5 in accordance with the teachings of the present invention; Figure 6: shows an operation of a frequency divider having a divisor of 1/1.5 according to the present invention. Figure

图 7: 其显示一依据本发明构想的解析度为 0. 5的可编程除频器的架构图；图 8: 其显示本发明的具有 50%责任周期输出波形的除以 3电路的较佳实施例于输入 2. 6 GHz时，所量的的 871 丽 z输出波形； Figure 7: shows an architectural diagram of a programmable frequency divider having a resolution of 0.5 in accordance with the teachings of the present invention; Figure 8: FIG. 8 shows a preferred embodiment of the present invention having a 50% duty cycle output waveform divided by 3 circuits. In the embodiment, when the input is 2. 6 GHz, the amount of the 871 丽 z output waveform;

图 9: 其显示本发明的可程式除法器的较佳实施例于除数为 255. 5及输入频率为 2. 56 GHz时，所量得的输出波形 ( 10. 02 MHz ) ； Figure 9: shows a preferred embodiment of the programmable divider of the present invention with a divisor of 255.5 and an input frequency of 2.56 GHz, the measured output waveform ( 10. 02 MHz);

图 10: 其显示本发明的可程式除法器的较佳实施例于除数为 511及输入频率为 1. 28 GHz时，所量得的输出波形（2. 504 腿 z) ； Figure 10: shows a preferred embodiment of the programmable divider of the present invention with an output waveform (2. 504 legs z) measured at a divisor of 511 and an input frequency of 1.28 GHz;

图 11 : 其显示一依据本发明构想的加上除数延伸电路的可编程除频器的架构图； Figure 11 is a block diagram showing a programmable frequency divider incorporating a divisor extension circuit in accordance with the teachings of the present invention;

图 12 (a)至 (c)：其分别显示一依据本发明构想的锁相回路频率合成器的第一较佳实施例的***方块图、该第一较佳实施例的主要电路的方块图与一第二较佳实施例的主要电路的方块图； 12 (a) to (c): respectively showing a system block diagram of a first preferred embodiment of a phase locked loop frequency synthesizer in accordance with the teachings of the present invention, and a block diagram of the main circuit of the first preferred embodiment a block diagram of a main circuit of a second preferred embodiment;

图 13 : 其显示一依据本发明构想的具有除数联结器的可编程除频器的架构图； Figure 13: shows an architectural diagram of a programmable frequency divider with a divisor coupler in accordance with the teachings of the present invention;

图 14: 其显示一依据本发明构想的测量装置图； Figure 14: shows a diagram of a measuring device contemplated in accordance with the present invention;

图 15 : 其显示当参考信号源频率为 33MHz，且载波频率为2813丽2以及1/1. 5 除频器 411被开启与关闭时所分别测量的相位杂讯的波形图；以及 Figure 15: shows the waveform of the phase noise measured when the reference signal source frequency is 33MHz and the carrier frequency is 2813 丽2 and 1/1. 5 when the frequency divider 411 is turned on and off;

图 16: 其显示所测量的具有相同载波频率的除数联结器移动调变位： 0位、 1 位、 2位与 3位等该四个模式的相位杂讯的波形图。本发明的最佳实施方式 Figure 16: It shows the divisor coupler shifting bits with the same carrier frequency measured: waveforms of the phase noise of the four modes, such as 0 bit, 1 bit, 2 bits and 3 bits. BEST MODE FOR CARRYING OUT THE INVENTION

为了解决前述的两个问题，本发明提出几个新的除频器架构，首先，是一个除数为 1/1. 5的除频器 411，其架构图如图 5所示。这个电路应用的是双缘触发的原理，将原本的 2/3除频器里面的串联鎖存器，即图 4中的第一锁存器 31112与第二锁存器 31113和第三锁存器 31122与第四锁存器 31124，用并联的鎖存器和一个多路转接器来取代（即分别被第一锁存器 41114、第二锁存器 41115与第一多路转接器 41116 和第三锁存器 41122、第四锁存器 41123与第二多路转接器 41124所取代）。其中的第一锁存器 41114和第三锁存器 41122是负缘触发的鎖存器，而第二锁存器 41115和第四锁存器 41123则是正缘触发，再加上一个多路转接器（第一多路转接器 41116或第二多路转接器 41124 ) ，便可以达到适当双缘触发效果。该除数为 1/1. 5的除频器 411包含一除频单元 4111以及一除数控制单元 4112。其中该除频单元 4111，除上述的第一锁存器 41114、第二锁存器 41115与第一多路转接器 41116 外，还包括：一第一 "非" 门 41111、一第一 "与" 门 41112与一第二 "非" 门 41113。而该除数控制单元 4112，除上述的第三锁存器 41122、第四锁存器 41123与第二多路转接器 41124外，还包括：一第二 "与" 门 41121及一第三 "与" 门 41125。其中该除数控制单元 4112是用以产生一除数控制信号以抑制（逻辑 1时）或不抑制（逻辑 0时）该除频单元 4111的运作与输出信号的产生。至该除频单元 4111是用以依据一输入信号的双缘触发与该除数控制信号以将该输入信号除以一整数除数（1 ) 或一分数除数（1. 5 ) 。和除数为 2/3的除频器一样，在 MOD和 FB_CTRL均为逻辑 1的情况下，其便可以发挥除以 1. 5的功能，图 6清楚的说明当除数为 1. 5时，该除频器 411的操作波形，反之则让输出信号简单的跟随输入信号，换言之，就是除以 1。 In order to solve the above two problems, the present invention proposes several new frequency divider architectures. First, a frequency divider 411 having a divisor of 1/1.5 is shown in FIG. This circuit applies the principle of double-edge triggering. The serial latch in the original 2/3 frequency divider, that is, the first latch 31112 and the second latch 31113 and the third latch in FIG. The device 31122 and the fourth latch 31124 are replaced by a parallel latch and a multiplexer (ie, by the first latch 41114, the second latch 41115, and the first multiplexer, respectively). 41116 and third latch 41122, fourth latch 41123 and second multiplexer 41124 are replaced). The first latch 41114 and the third latch 41122 are negative-triggered latches, and the second latch 41115 and the fourth latch 41123 are positive-edge triggers, plus a multi-turn The adapter (the first multiplexer 41116 or the second multiplexer 41124) can achieve the appropriate double edge triggering effect. The frequency divider 411 having a divisor of 1/1.5 includes a frequency dividing unit 4111 and a divisor control unit 4112. The frequency dividing unit 4111 includes, in addition to the first latch 41114, the second latch 41115 and the first multiplexer 41116, a first "non" gate 41111, a first" And "door 41112 and a second "non" gate 41113. The divisor control unit 4112, in addition to the third latch 41122, the fourth latch 41123 and the second multiplexer 41124, further includes: a second AND gate 41121 and a third" With "door 41125. The divisor control unit 4112 is configured to generate a divisor control signal to suppress (when logic 1) or not (when logic 0) the operation of the frequency division unit 4111 and the generation of an output signal. The frequency dividing unit 4111 is configured to divide the input signal by an integer divisor (1) or a fractional divisor (1.5) according to the double edge trigger of an input signal and the divisor control signal. And the div and the FB_CTRL are both logic 1 and can be used to divide by the function of 1.5. Figure 6 clearly shows that when the divisor is 1.5, The operating waveform of the frequency divider 411, on the other hand, causes the output signal to simply follow the input signal, in other words, is divided by one.

有了这个除数为 1/1. 5的除频器 411之后，也可以实现双模可程式分数除频器。此除频器的一种模式是除以分数模式，而另一种模式是在整数除数情况下，产生 50%责任周期的输出讯号。根据本发明的构想将该除数为 1/1. 5的除频器 411串在包含复数个除数为 2/3的除频器 311的可编程除频器 31的最前端，即构成一除数间隔（解析度）为 0. 5的（双模）可编程分数除频器（的核心电路） 41如图 7所示。而跟之前的除频器一样，其除数也可以由下式导出： With this divider 411 with a divisor of 1/1. 5, a dual-mode programmable fractional divider can also be implemented. One mode of this frequency divider is divided by the fractional mode, and the other mode is the output signal of 50% duty cycle in the case of integer divisor. According to the concept of the present invention, the frequency divider 411 having the divisor of 1/1.5 is at the forefront of the programmable frequency divider 31 including the plurality of dividers 311 having a divisor of 2/3, that is, forming a divisor interval. (Resolution) The (double-mode) programmable fractional divider (core circuit) 41 of 0.5 is shown in FIG. As with the previous frequency divider, its divisor can also be derived from:

TOUT 二 ( 2^N + 2 · M0D_N + . . . + 2 . M0D₂ +M0D ! +0. 5 . M0D₀) . T_{I N} TOUT II ( 2 ^N + 2 · M0D _N + . . . + 2 . M0D ₂ +M0D ! +0. 5 . M0D ₀ ) . T _IN

(4) (4)

同样的， T。_UT 是输出信号的周期，而 T_IN是输入信号的周期，其复数个除数所形成的除频范围（除数范围）在 2N到 2N+1-0. 5之间。每个除数的间隔（即解析度）为 0. 5故其可调的解析度已经缩小到原来的一半，也就是 0. 5了。对一个使用三角调变积分器的锁相回路而言，由这个调变器贡献的相位杂讯 S 可以写成：

其中 M是平均的除数， f。_ut是平均的输出频率， F {}代表傅利叶转换，而 b (t)是调变器产生的调变信号， k是设定的除数的分数部份。由于本发明的除数解析度已经到 0. 5，和现有的除频器比较起来小了一半，因此带入上式中，可以导出5 将会比使用一般的除频器来得小 6dB。 The same, T. _UT is the period of the output signal, and T _IN is the period of the input signal, and the division range (divisor range) formed by the plurality of divisors is between 2N and 2N+1-0. The interval of each divisor (ie, the resolution) is 0.5, so its adjustable resolution has been reduced to half of the original, that is, 0.5. For a phase-locked loop using a triangular modulation integrator, the phase noise S contributed by this modulator can be written as:

Where M is the average divisor, f. _Ut is the average output frequency, F {} represents the Fourier transform, and b (t) is the modulation signal produced by the modulator, and k is the fractional part of the set divisor. Since the divisor resolution of the present invention has reached 0.5, which is half the size of the existing frequency divider, it can be derived from the above equation, and the output of 5 will be 6 dB smaller than that of the conventional frequency divider.

为验证上述除数为 1/1. 5的除频器 411的功能，一依据图 7所示可编程分数除频器 41的具有 50%责任周期的除以 3电路和一双模可编程分数除法器，均已实现。当输入讯号为 2. 6G¾时，该除以 3电路所量得的输出讯号示于图 9。由图 9可看到有输入讯号频率三分之一（871M ) 的输出讯号，而且责任周期为 50%。 To verify the function of the frequency divider 411 having the above divisor of 1/1.5, a divide by 3 circuit and a dual mode programmable fractional division with a 50% duty cycle of the programmable fractional frequency divider 41 shown in FIG. , have been implemented. When the input signal is 2. 6G3⁄4, the output signal divided by the 3 circuit is shown in Figure 9. Figure 9 shows the output signal with one-third (871M) of the input signal frequency, and the duty cycle is 50%.

至于该双模可编程除法器是以 8位实现，包括了 1个 1/1. 5除法器及 7个 2/3除法器。根据 (4)，于分数模式时，除数范围为 128至 255. 5，间隔为 0. 5 _; 而于整数模式时，除数范围为 256至 511，间隔为 1。在图 10中显示，当除数设定为 255. 5且输入 2. 56GH_Z讯号时，此可编程除法器的输出波形。由图 10可知，输出频率为 10. 02MH_Z, 对应于正确的除数。图 11是当除数设为 511且输入讯号为 1. 28GHz时，该可编程除法器所输出的波形。输出频率为 2. 504MH_Z，亦即输入频率的 511分之 1。请注意图 10的该输出波形具有 50%的责任周期。 The dual-mode programmable divider is implemented in 8-bit, including one 1/1.5 divider and seven 2/3 dividers. According to (4), in the fractional mode, the divisor range is 128 to 255.5, and the interval is 0.5 _. In the integer mode, the divisor range is 256 to 511 with an interval of 1. Shown in FIG. 10, when the divisor is set to 255.5 2. 56GH _Z and the input signal, the output waveform of this programmable divider. As can be seen from Fig. 10, the output frequency is 10.02 MH _Z , which corresponds to the correct divisor. Figure 11 is a waveform output by the programmable divider when the divisor is set to 511 and the input signal is 1.28 GHz. The output frequency is 2. 504MH _Z , which is 511 of the input frequency. Please note that the output waveform of Figure 10 has a 50% duty cycle.

另外，为了增加除频器的除数范围，本发明发展出如图 11所示的加上除数延伸电路 511的可编程分数除频器 51的架构图。在图 11中，该除数延伸电路 511包含复数个或（OR) 门 5111、一解码器（DECODER) 5112与一四对一多路转接器 5113，用于打断后面几级的反馈控制信号，并***一个或门 5111，将反馈信号和另一个控制信号做 OR的运算之后，再反馈给前一级，而这些控制信号是由 DEC0DER5112根据输入的延伸控制信号 (MOD— EXT)所产生的，整个电路的运作方式如下：当输入 Further, in order to increase the divisor range of the frequency divider, the present invention develops an architectural diagram of the programmable fractional frequency divider 51 with the divisor extension circuit 511 shown in FIG. In FIG. 11, the divisor extension circuit 511 includes a plurality of OR gates 5111, a decoder (DECODER) 5112 and a four-to-one multiplexer 5113 for interrupting the feedback control signals of the subsequent stages. And inserting an OR gate 5111, ORing the feedback signal and another control signal, and then feeding back to the previous stage, and these control signals are generated by the DEC0DER5112 according to the input extended control signal (MOD_EXT). , the whole circuit works as follows: when input

MOD— EXT=00时， DEC0DER5112的输出信号 DEC [2 : 0] =000，且多路转接器 ( MUX )When MOD_ EXT=00, the output signal of DEC0DER5112 is DEC [2 : 0] =000, and the multiplexer ( MUX )

5113会选择 F_DUTg为输出信号，故此时的除频范围 (Modulus Range ) 是 2⁸到 2⁹ - 0· 5，当输入 MOD_EXT=01时， DEC0DER5112的输出信号则是 DEC [2 : 0] =001，因为5113 will select F _DUTg as the output signal, so the frequency range (Modulus Range) is 2 ⁸ to 2 ⁹ - 0· 5. When MOD_EXT=01 is input, the output signal of DEC0DER5112 is DEC [2 : 0] = 001, because

DEC [0] =1 , 因此 FB_CTRL8会维持在逻辑 1的状态，此时 2/3 除频器 8 ( 311 ) 便不会受到下一级 2/3除频器的反馈控制，接着选取 F0UT8为输出信号，等效上便如同把最后一级的 2/3除频器拿掉一样，因此除频范围就变成了 2⁷到 2⁸- 0. 5，依此类推，图 11中的加上除数延伸电路 511的可编程分数除频器 51，其除频范围便可以从DEC [0] =1, so FB_CTRL8 will remain in the logic 1 state, then 2/3 divider 8 ( 311 ) will not be subjected to the feedback control of the next stage 2/3 divider, then select F0UT8 as The output signal is equivalent to removing the 2/3 prescaler of the last stage, so the frequency range becomes 2 ⁷ to 2 ⁸ - 0. 5, and so on, the addition in Figure 11 The programmable fractional frequency divider 51 of the upper divisor extension circuit 511 can be selected from the frequency range

2⁵到 2⁹- 0. 5，控制信号和对应的除数范围如表一所示。 2 ⁵ to 2 ⁹ - 0. 5, the control signal and the corresponding divisor range are shown in Table 1.

表一控制信号和对应的除频范围

实验结果 Table 1 control signal and corresponding frequency range

Experimental result

1.***架构总览 1. System Architecture Overview

图 12 (a)是根据本发明构想所提出的锁相回路频率合成器的第一较佳实施例完整的***方块图，除了解析度为 0. 5的分数型锁相回路 4的主要的电路（如图 Figure 12 (a) is a complete system block diagram of a first preferred embodiment of a phase-locked loop frequency synthesizer according to the present invention, except for the main circuit of the fractional phase-locked loop 4 having a resolution of 0.5. (as shown

12 (b)所示），包含：一相频检测器 22、一电荷泵 23、一回路滤波器 24、一压控震荡器 25 (包括：一核心电路 250—电容阵列 251、二个共震电感 252以及两个压控电容 253) 、一三阶 DSM32、一加法器 33以及一解析度为 0. 5的可编程分数除频器 41之外，其余的界面电路在这张图中也清楚的画了出来，包含有：（1)参考信号源的缓冲电路 43，其可将外部参考信号源放大，并调整振幅到和 PFD所需要的 CMOS逻辑准位一样，（2) VC0的输出级 254还有和除频器间的界面电路 44，为了测量上的方便，12 (b) shows), comprising: a phase frequency detector 22, a charge pump 23, a loop filter 24, and a voltage controlled oscillator 25 (including: a core circuit 250 - a capacitor array 251, two resonances) Inductor 252 and two voltage-controlled capacitors 253), a third-order DSM32, an adder 33, and a programmable fractional divider 41 with a resolution of 0.5, the remaining interface circuits are also clearly drawn in this picture. Out, including: (1) a reference signal source buffer circuit 43, which can amplify the external reference signal source and adjust the amplitude to the same CMOS logic level as the PFD, (2) VC0 output stage 254 There is an interface circuit 44 between the frequency divider and the frequency divider, for the convenience of measurement,

VC0的输出级 254必须有足够的驱动能力来驱动 50欧姆的负载，（3)除频器的输出多路转接器 42，为了某些极性上的考量，本发明的除频器的输出有两种，一种是经过反向器的，而另一种没有。此外，由于本发明的除频器解析度达到 0. 5，若将其再经过一个除二电路，便可以产生 50% duty cycle的输出，加上这个部分总共会有四种输出产生，因此需要一个四对一的多路转接器 42。（4)除数寄存器 45和The output stage 254 of VC0 must have sufficient drive capability to drive a 50 ohm load, and (3) the output multiplexer 42 of the frequency divider, for certain polarity considerations, the output of the frequency divider of the present invention. There are two kinds, one is through the reverser, and the other is not. In addition, since the resolution of the frequency divider of the present invention reaches 0.5, if it is passed through a divide-by-2 circuit, a 50% duty cycle output can be generated, and a total of four outputs are generated in this portion, so A four-to-one multiplexer 42. (4) Divisor register 45 and

DSM32的时脉信号的多路转接器 42，由于 PFD22是正缘触发的电路，如果除数也是在时脉信号的正缘改变，也许会造成不可预知的错误，因此在寄存器 45和 DSM32前面加上一个多路转接器 42，实验时可以改变触发极性来观察其所带来的影响。另外，根据本发明构想所提出的锁相回路频率合成器的第二较佳实施例的主要的电路如图 12 (c)所示，该解析度为 0. 5的具有可调除频范围的分数型锁相回路 5与前述第一较佳实施例解析度为 0. 5的分数型锁相回路 4的区别在于该解析度为 0. 5的可编程分数除频器 41被一解析度为 0. 5的具有可调除频范围的可编程分数除频器 51所取代。 DSM32 clock signal multiplexer 42, since PFD22 is a positive edge triggered circuit, if the divisor is also A positive edge change in the clock signal may cause an unpredictable error. Therefore, a multiplexer 42 is added in front of the register 45 and the DSM 32. During the experiment, the trigger polarity can be changed to observe the effect. The singularity of the second embodiment of the present invention is as shown in Figure 12 (c), the resolution is 0.5 with an adjustable frequency division range. The fractional phase-locked loop 5 differs from the first preferred embodiment in that the resolution of the fractional phase-locked loop 4 is 0.5. The programmable fractional divider 41 having a resolution of 0.5 is resolved by a resolution of A programmable fractional frequency divider 51 with an adjustable divide range is replaced by 0.5.

而根据图 12 (a)所建构的这整个晶片里面的控制信号繁多，因此本发明利用商用晶片常见的串联转并联控制界面： 3 wire serial interface (TWIF) , 将控制信号用序列的方式输入，再经过寄存器送到指定的锁存器中，来节省工 /0 PAD的数目。 However, according to FIG. 12 (a), the entire control chip has a large number of control signals, so the present invention utilizes a common serial-parallel control interface of a commercial chip: 3 wire serial interface (TWIF), which inputs a control signal in a sequence. It is then sent to the specified latch through the register to save the number of workers / 0 PAD.

为验证本发明所提议的 1/1. 5除频器 411确能压抑量化杂讯，一除数联结器 (modulus combiner) 412被设计与提供（如图 13所示），其用于联结整数除数与分数除数，具有移动本发明所提议的解析度为 0. 5的可编程分数除频器 41的调变位 (modulation bits)的功能。亦即头三个最低有效位（Least Significant Bits : LSBs) 的联结组件 4121，是分别输入第 1个除频器（1/1. 5除频器 411)，第 2个除频器 (2/3除频器 311)与第 3个除频器 (2/3除频器 311)，其量化杂讯的修订量化水准 (modified quantization level)为 0. 5者，抑或次三个最低有效位（LSBs) 的联结组件 4122，是分别输入第 2个除频器 (2/3除频器 311)，第 3个除频器 (2/3除频器 311) 与第 4个除频器（2/3除频器 311) ，其量化杂讯的原有量化水准（original quantization level)为 1. 0者，两者其中之一可被选择，并被三角调变器所调变 (如图 13所示）。因此，在频率合成器的中具有或不具有本发明所提议的 1/1. 5除频器 411的相位杂讯的性能，可在同样的合成频率下做一比较。 To verify that the proposed 1/1.5 demodulator 411 of the present invention can suppress quantization noise, a diplex combiner 412 is designed and provided (as shown in Figure 13) for coupling integer divisors. And the fractional divisor having the function of shifting the modulation bits of the programmable fractional divider 41 proposed by the present invention with a resolution of 0.5. That is, the first three least significant bits (Least Significant Bits: LSBs) of the coupling component 4121 are input to the first frequency divider (1/1.5 demultiplexer 411), and the second demultiplexer (2/). 3, the frequency divider 311) and the third frequency divider (2/3 frequency divider 311), the modified quantization level of the quantized noise is 0.5, or the third least significant bits ( The LSBs) coupling component 4122 inputs the second frequency divider (2/3 frequency divider 311), the third frequency divider (2/3 frequency divider 311) and the fourth frequency divider (2). /3 frequency divider 311), the original quantization level of the quantized noise is 1.0, one of which can be selected and modulated by the triangular modulator (Fig. 13) Shown). Therefore, the performance of the phase noise in the frequency synthesizer with or without the 1/1.5 demultiplexer 411 proposed by the present invention can be compared at the same synthesizing frequency.

2.测量结果 2. Measurement results

图 14为本发明上述晶片 4的一测量装置图。该晶片 4是使用印刷电路板来测量，而该测量装置 6包括一电源供应器 (power supply) 61以提供电压源，经过稳压器 (_reg_Ulat_or) 62以稳定直流电压，再供给待测晶片 4使用，而控制信号则是利用个人电脑 63，通过可编程数据产生器 (PG) 64，产生所需要的信号模块来控制锁相回路 4以及一信号源分析仪 ( signal source analyzer : Agilent E5052A SSA ) 65。而所有的测量结果，除另有说明外，皆是用上述安捷伦的信号源分析仪 E5052A (65 )所测量的。 Figure 14 is a view showing a measuring apparatus of the above wafer 4 of the present invention. The wafer 4 is measured using a printed circuit board, and the measuring device 6 includes a power supply 61 to supply a voltage source, and is stabilized by a voltage regulator ( _reg _U lat _or ) 62 for supply. The test chip 4 is used, and the control signal is controlled by the personal computer 63, through the programmable data generator (PG) 64, to generate the required signal module to control the phase locked loop 4 and a signal source analyzer (signal source analyzer: Agilent E5052A SSA) 65. All measurements, unless otherwise stated, were measured using the Agilent signal source analyzer E5052A (65).

当参考信号源频率为 33MHz、载波频率（carrier frequency)为 2813MHz以及 1/1. 5除频器 411被开启与关闭（各自对应于前述第 1/2/3个除频器与第 2/3/4个除频器被三角积分调变器所调变的条件）时，所测量的的相位杂讯如图 15所示。很清楚地，借助所提供的 1/1. 5除频器 411，在频段外的由三角积分调变器所贡献的相位杂讯确实减低了 6dB (在偏移频率： " offset " 为 4MHz时，由- 129降至- 135dBc/Hz ) ，其与理论的预测值一致。 When the reference signal source frequency is 33 MHz, the carrier frequency (carrier frequency) is 2813 MHz, and the 1/1. 5 frequency divider 411 is turned on and off (each corresponding to the aforementioned 1/2/3 frequency divider and the second/third) When the /4 frequency dividers are modulated by the delta-sigma modulator, the measured phase noise is shown in Figure 15. Clearly, with the 1/1.5 demultiplexer 411 provided, the phase noise contributed by the delta-sigma modulator outside the band is indeed reduced by 6 dB (at offset frequency: "offset" is 4 MHz) , from -129 to -135dBc/Hz), which is consistent with the theoretical prediction.

事实上，前述的调变联结器 412可在四个不同的模式中移动调变位。模式 -: 调变的位输入该第 1/2/3个除频器（三角积分调变器移动 0位）；模式二：调变的位输入该第 2/3/4个除频器（三角积分调变器移动 1位）；模式三：调变的位输入该第 3/4/5个除频器（三角积分调变器移动 2位）；模式四：调变的位输入该第 4/5/6个除频器（三角积分调变器移动 3位）。因为这四个模式的除频器的解析度分别为 0. 5、 1、 2及 4，故可比较由解析度分别为 0. 5、 1、 2及 4的三角积分调变器所供献的相位杂讯；而所测量的具有相同载波频率的该四个模式的相位杂讯的波形图如图 16所示。可清楚看出，在该回路频宽以外的频率，相位杂讯被三角积分调变器所支配，具有一位的移位，亦即在具有较大的解析度（step size)时，相位杂讯确实增加了，且其差距如公式 (5)所预测的一样，正好是 6dB。因此本发明所提议的方法确实可以超越现有的频率合成器，使得来自于三角积分调变器的量化杂讯降低达 6dB。 In fact, the aforementioned modulation coupler 412 can shift the modulation bits in four different modes. Mode -: The modulated bit is input to the 1/2/3th frequency divider (the delta-sigma modulator shifts 0 bits); Mode 2: The modulated bit is input to the 2/3/4th frequency divider ( The triangular integral modulator moves 1 bit); mode 3: The modulated bit is input to the 3/4/5 frequency divider (the delta-sigma modulator shifts 2 bits); mode 4: the modulated bit input is the first 4/5/6 frequency dividers (triangular integral modulator moves 3 bits). Since the resolutions of the four modes of the frequency divider are 0.5, 1, 2, and 4, respectively, the triangle integral modulators with resolutions of 0.5, 1, 2, and 4 can be compared. Phase noise of the four modes of phase noise detected by the same carrier frequency is shown in FIG. It can be clearly seen that at frequencies other than the loop bandwidth, the phase noise is dominated by the delta-sigma modulator and has a one-bit shift, that is, when there is a large step size, the phase is miscellaneous. The news has indeed increased, and the gap is exactly the same as predicted by equation (5), which is exactly 6dB. Therefore, the proposed method of the present invention can indeed surpass the existing frequency synthesizer, so that the quantized noise from the delta-sigma modulator is reduced by 6 dB.

前述本发明所提出的分数除频器、可编程分数除频器、具有可调除频围的可编程分数除频器与分数型锁相回路等装置的控制方法，兹按其运作原理与步骤分别叙述如下： The control method of the fractional frequency divider, the programmable fractional frequency divider, the programmable fractional frequency divider with adjustable frequency division, and the fractional phase-locked loop proposed by the present invention is based on the operation principle and steps thereof. Described separately as follows:

其中有关本发明所提议的分数除频器 411 (如图 5所示）的控制方法，包含下列步骤：（a)当一分数除频器 411用于将一输入信号除以一整数除数以产生一输出信号时，使一除数控制信号或一反馈控制信号为一逻辑低状态，且使该除频器 411相应一输入信号的一双缘触发而产生一具有逻辑低状态的除数选择信号以使该除频器的一输出信号的产生不被抑制；（b)当该除数控制信号及该反馈控制信号均为一逻辑高状态时，使该除频器 411相应该双缘触发而产生一具有逻辑高状态的除数选择信号以使该输出信号的产生被抑制；以及 (c)当该除频器 411用于将该输入信号除以一分数除数以产生该输出信号时，该除频器 411产生该具有逻辑低状态的除数选择信号以使该输出信号持续产生达该输入信号的一个周期，而后该除频器 411产生该具有逻辑高状态的除数选择信号以使该输出信号的产生被抑制达半个该周期，并依此一方式循环。 The method for controlling the fractional frequency divider 411 (shown in FIG. 5) proposed by the present invention comprises the following steps: (a) when a fractional frequency divider 411 is used to divide an input signal by an integer divisor to generate When a signal is output, a divisor control signal or a feedback control signal is set to a logic low state, and the frequency divider 411 is triggered by a double edge of an input signal to generate a divisor selection signal having a logic low state to enable the signal The generation of an output signal of the frequency divider is not suppressed; (b) when the divisor control signal and the feedback control signal are both in a logic high state, causing the frequency divider 411 to generate a logic corresponding to the double edge trigger High state divisor Selecting a signal to suppress generation of the output signal; and (c) when the frequency divider 411 is configured to divide the input signal by a fractional divisor to generate the output signal, the frequency divider 411 generates the logic low a divisor selection signal of the state to continuously generate the output signal for one cycle of the input signal, and then the frequency divider 411 generates the divisor selection signal having a logic high state to suppress the generation of the output signal for half of the cycle , and cycle in this way.

至于本发明所提议的可编程分数除频器 41 (如图 7所示）的控制方法，其中该可编程分数除频器 41用于将一输入信号（FIN) 除以复数个具有一分数除数间隔 As for the control method of the programmable fractional frequency divider 41 (shown in FIG. 7) proposed by the present invention, the programmable fractional frequency divider 41 is configured to divide an input signal (FIN) by a plurality of fractional divisors. interval

(0. 5) 的除数其中之一以产生一第一输出信号（F0UT) ，该可编程分数除频器 41 包括一分数除频器 411，用于产生一第二输出信号（F0UT1 ) ，及一除频器长链One of the divisors of (0.5) to generate a first output signal (F0UT), the programmable fractional frequency divider 41 includes a fractional frequency divider 411 for generating a second output signal (F0UT1), and a frequency divider long chain

(即一现有的可编程除频器） 31，包含复数个彼此串连耦合的整数除频器 311，耦合于该分数除频器 411，用于产生该第一输出信号（F0UT ) ，该方法包含下列步骤：（a)使该分数除频器 411接收该输入信号（FIN) 、复数个除数控制信号（M0D0 至 M0DN) 其中之一（M0D0) 及该长链 31的一反馈控制信号（FB一 CTRL1 ) ，且使各该整数除频器 311均接收该复数个除数控制信号（MODI至 M0DN) 其中之一及各该整数除频器 311的一反馈控制信号（FB— CTRL2至 FB— CTRLN+ 1其中之一）；（b)当该分数除频器 411的该除数控制信号（M0D0 ) 或该长链 31的该反馈控制信号（FB— CTRL1 ) 为一逻辑低状态时，将该输入信号除以一第一整数除数以产生该第二输出信号，当该分数除频器 411的该除数控制信号（MOD0) 或该长链的该反馈控制信号(ie, an existing programmable frequency divider) 31, comprising a plurality of integer frequency dividers 311 coupled in series with each other, coupled to the fractional frequency divider 411, for generating the first output signal (F0UT), The method comprises the following steps: (a) causing the fractional frequency divider 411 to receive the input signal (FIN), one of the plurality of divisor control signals (M0D0 to M0DN) (M0D0) and a feedback control signal of the long chain 31 ( FB_CTRL1), and each of the integer frequency dividers 311 receives one of the plurality of divisor control signals (MODI to M0DN) and a feedback control signal of each of the integer frequency dividers 311 (FB_CTRL2 to FB- (b) when the divisor control signal (M0D0) of the fractional frequency divider 411 or the feedback control signal (FB_CTRL1) of the long chain 31 is in a logic low state, the input is Dividing the signal by a first integer divisor to generate the second output signal, the divisor control signal (MOD0) of the fractional frequency divider 411 or the feedback control signal of the long chain

(FB—CTRL1 ) 保持一逻辑低状态达该输入信号 FIN的一个周期，而后该分数除频器 411的该除数控制信号（M0D0) 及该长链 31的该反馈控制信号（FB一 CTRL1 ) 保持一逻辑高状态达半个该周期，并依此一方式循环时，将该输入信号（FIN) 除以一分数除数以产生该第二输出信号（F0UT1 ) ； (c)当该整数除频器 311的该除数控制信号（MODI至 M0DN其中之一）或该反馈控制信号（FB一 CTRL2至 FB— CTRLN+ 1其中之一）为一逻辑低状态时，将该整数除频器 311的一输入信号（F0UT1至 F0UTN其中之一）除以一第二整数除数以产生该整数除频器 311的一输出信号（F0UT2至 F0UTN以及 F0UT其中之一），当该整数除频器 311的该除数控制信号（MODI至 M0DN 其中之一）及该反馈控制信号（FB— CTRL2至 FB_CTRLN+1其中之一）均保持一逻辑高状态时，将该整数除频器 311的该输入信号（FIN) 除以一第三整数除数以产生该整数除频器 311的该输出信号（F0UT2至 F0UTN以及 F0UT其中之一）；以及（d) 使该可编程分数除频器 41依据该输入信号（FIN) 及各该除数以产生该第一输出信号（F0UT) 。 (FB_CTRL1) maintaining a logic low state for one cycle of the input signal FIN, and then the divisor control signal (M0D0) of the fractional frequency divider 411 and the feedback control signal (FB_CTRL1) of the long chain 31 are maintained a logic high state for half of the period, and in this manner, the input signal (FIN) is divided by a fractional divisor to generate the second output signal (F0UT1); (c) when the integer divider When the divisor control signal (one of MODI to MODN) of the 311 or the feedback control signal (one of FB_CTRL2 to FB_CTRLN+1) is a logic low state, an input signal of the integer frequency divider 311 is input. (one of F0UT1 to FOUTT) divided by a second integer divisor to generate an output signal (one of FUTU2 to FOUTIN and F0UT) of the integer frequency divider 311, when the divisor control signal of the integer frequency divider 311 Dividing the input signal (FIN) of the integer frequency divider 311 by one (the one of MODI to M0DN) and the feedback control signal (one of FB_CTRL2 to FB_CTRLN+1) are maintained at a logic high state Third integer divisor The integer divide the frequency of the output signal 311 (and one F0UT2 F0UT to F0UTN); and (d) The programmable fractional frequency divider 41 is caused to generate the first output signal (FOUT) according to the input signal (FIN) and each of the divisors.

有关本发明所提议的具有可调除频范围的可编程分数除频器 51 (如图 11所示）的控制方法，其中该具有可调除频范围的可编程分数除频器 51用于将一输入信号（F;TN) 除以复数个具有一分数除数间隔（0. 5 ) 的除数其中之一以产生一第一输出信号（F0UT) ，该具有可调除频范围的可编程分数除频器 51包括一分数除频器 411，用于产生一第二输出信号（F0UT1 ) , 一除频器长链 31，包含复数个彼此串连耦合的整数除频器 311，耦合于该分数除频器 411，用于产生该第一输出信号（F0UT) ，及一除数延伸电路 511 (包含复数个 "或" 门 5111、一解码器 5112与一多路转接器 5113 ) ，用以调整该复数个除数所形成的一除数范围，该方法包含下列步骤：（a)使该除数延伸电路 511产生一控制信号（DEC[0 : 2]，其是相应一外加的延伸控制信号 MOD— EXT而产生）以切断或不切断包含一特定整数除频器 311之后的所有各该整数除频器 311的一反馈控制（切断或不切断 FB— CTRL1至 FB— CTRLN 其中之一），俾使该除数范围可被调整；（b)使该分 ft除频器 411接收该输入信号 A control method for a programmable fractional frequency divider 51 (shown in FIG. 11) having an adjustable frequency division range as proposed by the present invention, wherein the programmable fractional frequency divider 51 having an adjustable frequency division range is used for An input signal (F; TN) divided by a plurality of divisors having a fractional divisor interval (0.5) to generate a first output signal (F0UT), the programmable fractional division with an adjustable frequency division range The frequency converter 51 includes a fractional frequency divider 411 for generating a second output signal (F0UT1), a frequency divider long chain 31, and a plurality of integer frequency dividers 311 coupled in series with each other, coupled to the fractional division The frequency converter 411 is configured to generate the first output signal (FOUT), and a divisor extension circuit 511 (including a plurality of OR gates 5111, a decoder 5112 and a multiplexer 5113) for adjusting the A divisor range formed by a plurality of divisors, the method comprising the steps of: (a) causing the divisor extension circuit 511 to generate a control signal (DEC[0:2] which is a corresponding extended extension control signal MOD_EXT Generated) Or does not cut off a feedback control of all of the integer frequency dividers 311 after a specific integer frequency divider 311 (cut or not cut one of FB_CTRL1 to FB_CTRLN), so that the divisor range can be adjusted (b) causing the sub-ft frequency divider 411 to receive the input signal

(FIN) 、复数个除数控制信号（M0D0至 M0DN) 其中之一（M0D0) 及该长链 31的一反馈控制信号（FB— CTRL1 ) ，且使各该整数除频器 311均接收该复数个除数控制信号（MODI至 M0DN ) 其中之一及各该整数除频器 311的一反馈控制信号（FB_ CTRL2至 FB— CTRLN + 1其中之一) ； (c)当该分数除频器 411的该除数控制信号(FIN), one of a plurality of divisor control signals (M0D0 to M0DN) (M0D0) and a feedback control signal (FB_CTRL1) of the long chain 31, and each of the integer frequency dividers 311 receives the plurality of One of the divisor control signals (MODI to M0DN) and a feedback control signal (one of FB_CTRL2 to FB_CTRLN+1) of each of the integer frequency dividers 311; (c) when the fractional frequency divider 411 Divisor control signal

(M0D0) 或该长链 31的该反馈控制信号（FB— CTRL1 ) 为一逻辑低状态时，将该输入信号除以一第一整数除数以产生该第二输出信号，当该分数除频器 411的该除数控制信号（M0D0) 或该长链的该反馈控制信号（FB— CTRL1 ) 保持一逻辑低状态达该输入信号（FIN ) 的一个周期，而后该分数除频器 411的该除数控制信号(M0D0) or when the feedback control signal (FB_CTRL1) of the long chain 31 is in a logic low state, dividing the input signal by a first integer divisor to generate the second output signal, when the fractional frequency divider The divisor control signal (M0D0) of the 411 or the feedback control signal (FB_CTRL1) of the long chain maintains a logic low state for one period of the input signal (FIN), and then the divisor control of the fractional frequency divider 411 signal

(MOD0) 及该长链 31的该反馈控制信号（FB— CTRL1 ) 保持一逻辑高状态达半个该周期，并依此一方式循环时，将该输入信号（FIN) 除以一分数除数以产生该第二输出信号（F0UT1 ) ； (d)当该整数除频器 311的该除数控制信号（MODI至 M0DN其中之一）或该反馈控制信号（FB— CTRL2至 FB— CTRLN+1其中之一）为一逻辑低状态时，将该整数除频器 311的一输入信号（F0UT1至 F0UTN其中之一）除以一第二整数除数以产生该整数除频器 311的一输出信号（F0UT2至 F0UTN以及 F0UT其中之一），当该整数除频器 311的该除数控制信号（MODI至 M0DN其中之一）及该反馈控制信号 (FB— CTRL2至 FB__CTRLN+1其中之一）均保持一逻辑高状态时，将该整数除频器 311的该输入信号（F0UT1至 F0UTN其中之一）除以一第三整数除数以产生该整数除频器 311的该输出信号（F0UT2至 F0UTN以及 F0UT其中之一）；以及（e)使该可编程分数除频器 51依据该输入信号（FIN ) 及各该除数以产生该第一输出信号(MOD0) and the feedback control signal (FB_CTRL1) of the long chain 31 remain in a logic high state for half of the period, and when the loop is performed in this manner, the input signal (FIN) is divided by a fractional divisor. Generating the second output signal (F0UT1); (d) when the divisor control signal (one of MODI to MODN) of the integer frequency divider 311 or the feedback control signal (FB_CTRL2 to FB_CTRLN+1) a) when a logic low state, an input signal (one of F0UT1 to FOUTN) of the integer frequency divider 311 is divided by a second integer divisor to generate an output signal of the integer frequency divider 311 (F0UT2 to One of F0UTN and F0UT), the divisor control signal (one of MODI to MODN) of the integer frequency divider 311 and the feedback control signal When one of FB_CTRL2 to FB__CTRLN+1 is maintained at a logic high state, the input signal (one of F0UT1 to FOUTN) of the integer frequency divider 311 is divided by a third integer divisor to generate the integer. The output signal of the frequency divider 311 (one of F0UT2 to FOUTIN and F0UT); and (e) causing the programmable fractional frequency divider 51 to generate the first output signal according to the input signal (FIN) and each of the divisors

(F0UT) 。 (F0UT).

另有关本发明所提议的分数型锁相回路 4 (其完整的***方块图如图 12 (a)所示，而其主要电路如图 12 (b)所示，包含：一相频检测器 22、一电荷泵 23、一回路滤波器 24、一压控震荡器 25、一三阶 DSM32、一加法器 33以及一可编程分数除频器 41 ) 的控制方法，该方法包含下列步骤：（a)使一压控震荡器 25接收一输入信号与产生一输出信号；以及 (b)使一可编程分数除频器 41接收该输出信号的一反馈信号，且将该反馈信号经复数个具有一分数除数间隔（0. 5) 的除数其中之一的除频后，产生一经除频的输出信号。上述有关本发明所提议的分数型锁相回路 4的控制方法，该方法还包含下列步骤：（c)使一石英震荡器 25产生一参考信号源 REF; (d) 由一相频检测器 22比较该参考信号源 REF与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号；（e)使一电荷泵 23于接收该充电信号时产生一充电动作以提升一输出电流而提升该经除频的输出信号的该频率，且在接收该放电信号时产生一放电动作以降低该输出电流而降低该经除频的输出信号的该频率；（f)由一回路滤波器 24滤除该电荷泵 23该输出电流的一相位杂讯，且据以产生该压控震荡器 25的该输入信号；（g)使一三角积分调变器 32接收一外加的输入信号以产生一调变信号；（h)使一加法器 33接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器 41，以产生该除数；以及 (i)经该分数型锁相回路 4的复数个运作后，使该压控震荡器 25该输出信号的一频率，稳定于该参考信号源 REF的一频率乘以该除数的一平均值。 Further, the fractional phase-locked loop 4 proposed by the present invention has a complete system block diagram as shown in FIG. 12(a), and its main circuit is as shown in FIG. 12(b), including: a phase-frequency detector 22 , a charge pump 23, a loop filter 24, a voltage controlled oscillator 25, a third order DSM32, an adder 33, and a programmable fractional frequency divider 41), the method comprising the following steps: ???a voltage controlled oscillator 25 receives an input signal and generates an output signal; and (b) causes a programmable fractional frequency divider 41 to receive a feedback signal of the output signal, and the feedback signal has a plurality of After dividing by one of the divisors of the fractional divisor interval (0.5), a de-frequency output signal is generated. The above control method for the fractional phase-locked loop 4 proposed by the present invention further comprises the following steps: (c) causing a quartz oscillator 25 to generate a reference signal source REF; (d) by a phase frequency detector 22 Comparing a phase and a frequency of the reference signal source REF and the frequency-divided output signal, and generating a charging or a discharging signal; (e) causing a charge pump 23 to generate a charging action when receiving the charging signal Raising the frequency of the frequency-divided output signal by boosting an output current, and generating a discharge action to reduce the output current to reduce the frequency of the divided output signal when receiving the discharge signal; (f) A phase noise of the output current of the charge pump 23 is filtered by the primary loop filter 24, and the input signal of the voltage controlled oscillator 25 is generated accordingly; (g) a triangular integral modulator 32 is received. Input signal to generate a modulated signal; (h) causing an adder 33 to receive an applied integer and the modulated signal, and adding the two to the programmable fractional divider 41 to generate the divisor And (i) after the plurality of operations of the fractional phase locked loop 4, causing the frequency of the output signal of the voltage controlled oscillator 25 to be stabilized at a frequency of the reference signal source REF multiplied by an average of the divisor .

另有关本发明所提议的具有可调除频范围的分数型锁相回路 5 (参看图 12 (c) , 其主要电路包含：一相频检测器 22、一电荷泵 23、一回路滤波器 24、一压控震荡器 25、一三阶 DSM32、一加法器 33以及一具有可调除频范围的可编程分数除频器 51 ) 的控制方法，该方法包含下列步骤：（a)使一压控震荡器 25接收一输入信号与产生一输出信号；以及 (b)使一具有可调除频范围的可编程分数除频器 51接收该输出信号的一反馈信号，且将该反馈信号经复数个具有一分数除数间隔的除数其中之一的除频后，产生一经除频的输出信号，且该除频器 51的一除数范围是相应该除频器所接收的一延伸控制信号而可被据以调整。 Further, in relation to the fractional phase-locked loop 5 having the adjustable frequency division range proposed by the present invention (see FIG. 12(c), the main circuit thereof includes: a phase frequency detector 22, a charge pump 23, and a loop filter 24. a control method of a voltage controlled oscillator 25, a third order DSM32, an adder 33, and a programmable fractional frequency divider 51 having an adjustable frequency division range, the method comprising the following steps: (a) making a pressure The control oscillator 25 receives an input signal and generates an output signal; and (b) causes a programmable fractional frequency divider 51 having an adjustable frequency division range to receive a feedback signal of the output signal, and the feedback signal is subjected to a plurality of signals Divisors with a fractional divisor interval After one of the frequency divisions, a frequency-divided output signal is generated, and a divisor range of the frequency divider 51 is adjusted according to an extension control signal received by the frequency divider.

当然，有关本发明所提议的分数型锁相回路 5的控制方法，其还包含前述本发明所提议的分数型锁相回路 4的控制方法中的步骤 (c)至步骤 (i)等各步骤。 Of course, the control method of the fractional phase-locked loop 5 proposed by the present invention further includes steps (c) to (i) and the like in the control method of the fractional phase-locked loop 4 proposed by the present invention. .

由上述的说明可知，本发明在于提供一种分数除频器、一种可编程分数除频器与一种分数型锁相回路、一种具有可调除频范围的可编程分数除频器与一种具有可调除频范围的分数型锁相回路的构形与控制方法，该电路具有相对较佳的除数解析度，故可产生相对较低的量化误差以及相对较低的相位杂讯。 As can be seen from the above description, the present invention provides a fractional frequency divider, a programmable fractional frequency divider and a fractional phase-locked loop, a programmable fractional frequency divider with an adjustable frequency division range and A configuration and control method for a fractional phase-locked loop with an adjustable frequency division range. The circuit has a relatively good resolution of the divisor, so that relatively low quantization error and relatively low phase noise can be generated.

以上仅是本发明的较佳实施例的详细说明，这些较佳实施例并不是对本发明的限制，熟悉本领域的技术人员根据本发明的精神还可作出种种的等效的改变或替换，这些等效的改变或替换均应包括在本发明的范围内，因此本发明的范围应由所附的本申请权利要求范围所限定。 The above is only a detailed description of the preferred embodiments of the present invention. These preferred embodiments are not intended to limit the invention, and those skilled in the art can make various equivalent changes or substitutions in accordance with the spirit of the invention. Equivalent changes or substitutions are intended to be included within the scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

Claims

权利要求 Rights request

1. 一种分数除频器，包含： 1. A fractional frequency divider comprising:

一除数控制单元，其相应一输入信号的一双缘触发以产生一除数选择信号；以及 a divisor control unit that triggers a double edge of a corresponding input signal to generate a divisor selection signal;

一除频单元，耦合于该控制单元，用于该输入信号的一除频，且相应该双缘触发及该选择信号将该输入信号除以一整数或一分数除数以产生该除频器的一输出信号。 a frequency dividing unit coupled to the control unit for dividing a frequency of the input signal, and corresponding to the double edge trigger and the selection signal dividing the input signal by an integer or a fractional divisor to generate the frequency divider An output signal.

2.如权利要求 1所述的除频器，其特征在于： 2. A frequency divider according to claim 1 wherein:

该双缘触发是指该控制单元及该除频单元皆被该输入信号的一上升边缘及一下降边缘该两者所触发；及 /或 The dual edge triggering means that both the control unit and the frequency dividing unit are triggered by a rising edge and a falling edge of the input signal; and/or

当该除频器处于一除以该整数除数的模式时，该选择信号为一逻辑低状态，而该除频单元的一运作未被抑制，当该选择信号为一逻辑高状态时，该除频单元的该运作被抑制，且当该除频器处于一除以该分数除数的模式时，该除频单元是依每当该运作达该输入信号的一周期后即被抑制达半个该周期的一方式循环。 When the frequency divider is in a mode divided by the integer divisor, the selection signal is in a logic low state, and an operation of the frequency dividing unit is not suppressed. When the selection signal is in a logic high state, the dividing is performed. The operation of the frequency unit is suppressed, and when the frequency divider is in a mode divided by the fractional divisor, the frequency division unit is suppressed by half each time the operation reaches the input signal. One way cycle of the cycle.

3.如权利要求 1所述的除频器，其特征在于- 该控制单元还接收一除数控制信号及一反馈控制信号，当该除数控制信号或该反馈控制信号为一逻辑低状态时，该选择信号为该逻辑低状态，且当该除数控制信号与该反馈控制信号均为一逻辑高状态时，该选择信号为该逻辑高状态；及 / 或 The frequency divider according to claim 1, wherein the control unit further receives a divisor control signal and a feedback control signal, when the divisor control signal or the feedback control signal is in a logic low state, The selection signal is in the logic low state, and when the divisor control signal and the feedback control signal are both in a logic high state, the selection signal is in the logic high state; and/or

该整数除数为 1，且该分数除数为 1.5 The integer divisor is 1, and the fractional divisor is 1.5.

4.如权利要求 1至 3之任一所述的除频器，其特征在于该除频单元还包含：一第一 "非"门，具有一输入端及一输出端； The frequency divider according to any one of claims 1 to 3, wherein the frequency dividing unit further comprises: a first "non" gate having an input end and an output end;

一第一 "与"门，具有一第一、一第二及一输出端，其中该第二端耦合于该第一 "非" 门该输出端； a first AND gate having a first, a second, and an output, wherein the second end is coupled to the output of the first "non" gate;

一第二 "非"门，具有一输入端及一输出端，其中该输入端耦合于该除频器该输出端用以接收一第一反馈信号，且该输出端耦合于该第一 "与" 门该第一顺； a second "non" gate having an input end and an output end, wherein the input end is coupled to the frequency divider, the output end is configured to receive a first feedback signal, and the output end is coupled to the first " "The door should be the first;

一第一锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第一 "与" 门该输出端，该第二端为一致能输入端，且该第二端用于接收该输入信号； a first latch having a first, a second, and an output, wherein the first end is coupled to the output of the first AND gate, and the second end is a uniform input, and the The second end is for receiving the input letter number;

一第二锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第一 "与" 门该输出端，且该第二端是用于接收该输入信号；以及 a second latch having a first, a second, and an output, wherein the first end is coupled to the output of the first AND gate, and the second end is configured to receive the input signal ; as well as

一第一多路转接器，具有一第一、一第二、一第三及一输出端，其中该第一端耦合于该第一锁存器该输出端，该第二端耦合于该第二锁存器该输出端，该第三端用于接收该输入信号，且该输出端耦合于该除频器该输出端，其中该控制单元还包含： a first multiplexer having a first, a second, a third, and an output, wherein the first end is coupled to the output of the first latch, and the second end is coupled to the The second latch is configured to receive the input signal, and the output is coupled to the output of the frequency divider, wherein the control unit further comprises:

一第二 "与" 门，具有一第一、一第二及一输出端，其中该第一端耦合于该除频器该输出端用以接收一第二反馈信号，该第二端用于接收该反馈控制信号；一第三锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第二 "与" 门该输出端，该第二端为一致能输入端，且该第二端是用于接收该输入信号； a second AND gate having a first, a second, and an output, wherein the first end is coupled to the frequency divider and the output is configured to receive a second feedback signal, the second end is for Receiving the feedback control signal; a third latch having a first, a second, and an output, wherein the first end is coupled to the output of the second AND gate, and the second end is identical An input terminal, and the second end is for receiving the input signal;

一第四锁存器，具有一第一、一第二及一输出端，其中该第一端耦合于该第二 "与" 门该输出端，且该第二端用于接收该输入信号； a fourth latch having a first, a second, and an output, wherein the first end is coupled to the output of the second AND gate, and the second end is configured to receive the input signal;

一第二多路转接器，具有一第一、一第二、一第三及一输出端，其中该第一端耦合于该三锁存器该输出端，该第二端耦合于该四锁存器该输出端，且该第三端是用于接收该输入信号；以及 a second multiplexer having a first, a second, a third, and an output, wherein the first end is coupled to the output of the three latch, and the second end is coupled to the fourth The output of the latch, and the third end is for receiving the input signal;

一第三 "与" 门具有一第一、一第二及一输出端，其中该第一端耦合于该第二多路转接器该输出端，该第二端用于接收该除数控制信号，且该输出端耦合于该第一 "非" 门该输入端。 a third AND gate has a first, a second, and an output, wherein the first end is coupled to the output of the second multiplexer, and the second end is configured to receive the divisor control signal And the output is coupled to the first "non" gate of the input.

5.一种分数除频器，用于将一输入信号经一除频以产生一输出信号，其中当该除频器是处于一第一状态时，该输入信号被除以一整数除数，而该输出信号的产生未被抑制，且当该除频器是处于一第二状态时，该输入信号被除以一分数除数，该输出信号的该产生未被抑制达该输入信号的一个周期而后该产生被抑制达半个该周期，并依此一方式循环。 5. A fractional frequency divider for dividing an input signal by a frequency to generate an output signal, wherein when the frequency divider is in a first state, the input signal is divided by an integer divisor The generation of the output signal is not suppressed, and when the frequency divider is in a second state, the input signal is divided by a fractional divisor, the generation of the output signal is not suppressed for one cycle of the input signal This generation is suppressed for half of this cycle and is cycled in this manner.

6.如权利要求 5所述的除频器，其特征在于该除频器还包含： 6. The frequency divider of claim 5, wherein the frequency divider further comprises:

一除数控制单元，其相应该输入信号的一双缘触发及该第一或该第二状态以产生一除数选择信号；以及 a divisor control unit that triggers a dual edge of the input signal and the first or second state to generate a divisor selection signal;

一除频单元，耦合于该控制单元，且相应该双缘触发及该选择信号以产生该除频器的该输出信号， a frequency dividing unit coupled to the control unit, and corresponding to the double edge trigger and the selection signal to generate the The output signal of the frequency divider,

其中当该第一状态时，该除数控制信号为一逻辑低状态，且当该第二状态时，该除数控制信号维持该逻辑低状态达该输入信号的一个该周期而后维持一逻辑高状态达该输入信号的半个该周期，并依该方式循环。 Wherein, in the first state, the divisor control signal is in a logic low state, and when in the second state, the divisor control signal maintains the logic low state for a period of the input signal and then maintains a logic high state Half of the cycle of the input signal, and cycle in this manner.

7.一种可编程分数除频器，用于将一输入信号除以复数个具有一分数除数间隔的除数其中之一，以产生一第一输出信号，该除频器包含： 7. A programmable fractional divider for dividing an input signal by a plurality of divisors having a fractional divisor interval to produce a first output signal, the frequency divider comprising:

一分数除频器，用于接收该输入信号并于一第一及一第二状态时将该输入信号分别除以一第一整数及一分数除数以产生一第二输出信号；以及 a fractional frequency divider for receiving the input signal and dividing the input signal by a first integer and a fractional divisor respectively to generate a second output signal in a first and a second state;

一除频器长链，具有复数个彼此串连耦合的整数除频器，用于接收该第二输出信号并产生该第一输出信号， a frequency divider long chain having a plurality of integer frequency dividers coupled in series with each other for receiving the second output signal and generating the first output signal,

其中各该整数除频器于一第三及一第四状态时将该整数除频器的一输入信号分别除以一第二整数及一第三整数除数以产生该整数除法器的一输出信号。 The integer frequency divider divides an input signal of the integer frequency divider by a second integer and a third integer divisor respectively to generate an output signal of the integer divider in a third state and a fourth state. .

8.如权利要求 7所述的可编程分数除频器，其特征在于该分数除频器用于接收复数个除数控制信号其中之一及该长链的一反馈控制信号，且各该整数除频器用于接收该复数个除数控制信号其中之一与各该整数除频器的一反馈控制信号，其中- 当该分数除频器处于该第一状态时，该分数除频器的该除数控制信号或该长链的该反馈控制信号为一逻辑低状态，当该分数除频器处于该第二状态时，该分数除频器的该除数控制信号与该长链的该反馈控制信号均为一逻辑高状态，当该整数除频器处于该第三状态时，该整数除频器的该除数控制信号或该反馈控制信号为一逻辑低状态，当该整数除频器处于该第四状态时，该整数除频器的该除数控制信号与该反馈控制信号均为一逻辑高状态；及 /或 The programmable fractional frequency divider according to claim 7, wherein the fractional frequency divider is configured to receive one of a plurality of divisor control signals and a feedback control signal of the long chain, and each of the integer frequency divisions The device is configured to receive one of the plurality of divisor control signals and a feedback control signal of each of the integer frequency dividers, wherein - when the fractional frequency divider is in the first state, the divisor control signal of the fractional frequency divider Or the feedback control signal of the long chain is in a logic low state, and when the fractional frequency divider is in the second state, the divisor control signal of the fractional frequency divider and the feedback control signal of the long chain are both a logic high state, when the integer frequency divider is in the third state, the divisor control signal or the feedback control signal of the integer frequency divider is in a logic low state, when the integer frequency divider is in the fourth state The divisor control signal of the integer frequency divider and the feedback control signal are both in a logic high state; and/or

该可编程分数除频器的各该除数的一除数值，是借助设定该复数个除数控制信号为该逻辑高或低状态来决定，各该除数的该除数值是处在一自 2的 N次方至 2 的 (N+1)次方 -0.5的范围内，各该除数的该间隔为 0.5，且该 (N+1)为该复数个除数控制信号的一总数。 A divisor value of each of the divisors of the programmable fractional divider is determined by setting the complex divisor control signal to the logic high or low state, and the divisor value of each divisor is at a self-zero In the range of N to 2 (N+1)th power -0.5, the interval of each divisor is 0.5, and the (N+1) is a total number of the plurality of divisor control signals.

9.如权利要求 7所述的可编程分数除频器，其特征在于： 9. The programmable fractional frequency divider of claim 7 wherein:

该分数除频器为一如权利要求 1或 5所述的除频器； The fractional frequency divider is the frequency divider according to claim 1 or 5;

各该整数除频器为一除数为 2及 3两者之一的整数除频器；及 /或该分数除频器及该复数个整数除频器的前两级，是采用源极耦合逻辑 (SCL) 电路，其余的该复数个整数除频器则是采用互补金氧半场效（CMOS ) 逻辑电路，且在第二级的该整数除频器与第三级的该整数除频器之间还包括一 SCL和 CMOS逻辑转换界面电路，其中该 SCL电路可还包括：复数个 SCL锁存器以及复数个 SCL多路转接器。 Each of the integer frequency dividers is an integer frequency divider having a divisor of two and three; and/or The fractional frequency divider and the first two stages of the complex integer frequency divider are source coupled logic (SCL) circuits, and the remaining plurality of integer frequency dividers are complementary metal oxide half field effects (CMOS). a logic circuit, and further comprising an SCL and CMOS logic conversion interface circuit between the integer frequency divider of the second stage and the integer frequency divider of the third stage, wherein the SCL circuit further comprises: a plurality of SCL latches And a number of SCL multiplexers.

10. 一种具有可调除频范围的可编程分数除频器，用于接收一输入信号并依据一延伸控制信号以调整复数个具有一分数除数间隔的除数所形成的一除频范围，且据以产生一输出信号，该除频器包含： 10. A programmable fractional frequency divider having an adjustable frequency division range for receiving an input signal and adjusting a division range formed by a plurality of divisors having a fractional divisor interval according to an extension control signal, and According to an output signal, the frequency divider comprises:

一可编程分数除频器电路，用于将该输入信号除以该复数个具有一分数除数间隔的除数其中之一，以产生该输出信号，该除频器电路包含复数个彼此串连耦合的整数除频器；以及 a programmable fractional divider circuit for dividing the input signal by one of the plurality of divisors having a fractional divisor interval to generate the output signal, the demultiplexer circuit comprising a plurality of serially coupled to each other Integer frequency divider;

一除数延伸电路，用以依据该延伸控制信号以切断或不切断包含一特定整数除频器之后的所有各该整数除频器的一反馈控制，以使该可编程分数除频器的该除频范围可被据以调整。 a divisor extension circuit for switching off or not cutting a feedback control of all of the integer frequency dividers including a specific integer frequency divider according to the extension control signal to cause the division of the programmable fractional divider The frequency range can be adjusted accordingly.

11. 如权利要求 10所述的可编程分数除频器，其特征在于该除频器电路为一如权利要求 7所述的可编程分数除频器，且该除数延伸电路还包含： 11. The programmable fractional frequency divider according to claim 10, wherein the frequency divider circuit is the programmable fractional frequency divider of claim 7, and the divisor extension circuit further comprises:

复数个 "或" 门； a plurality of "or" doors;

其中各该 "或" 门具有一第一、一第二与一输出端，且该第一与该输出端耦合于在任意两个直接相连的该整数除频器之间及在该分数除频器与该复数个整数除频器之间的复数个反馈电路其中的任一； Each of the OR gates has a first, a second and an output, and the first and the output are coupled between any two directly connected integer frequency dividers and at the fractional frequency division Any of a plurality of feedback circuits between the plurality of integer frequency dividers;

一解码器，具有一输入端及复数个输出端； a decoder having an input and a plurality of outputs;

其中该输入端用于接收该延伸控制信号，该复数个输出端其中的每一耦合于该复数个 "或" 门的该第二端其中的任一，该复数个输出端为输出复数个逻辑低状态与其中的任一输出一逻辑高状态而其余则输出一逻辑低状态两者其中之一，且输出该逻辑高状态的该输出端以后的该整数除频器是等效于被切断，故对该可编程除频器的该输出信号不产生作用，而可减低该除频范围；以及 Wherein the input is configured to receive the extension control signal, each of the plurality of outputs being coupled to any one of the second ends of the plurality of OR gates, the plurality of outputs being outputting a plurality of logic The low state and one of the outputs outputs a logic high state and the rest outputs one of a logic low state, and the integer frequency divider after outputting the output of the logic high state is equivalent to being cut off, Therefore, the output signal of the programmable frequency divider has no effect, and the frequency division range can be reduced;

一多路转接器，具有复数个输入端与一输出端， a multiplexer having a plurality of inputs and an output

其中该复数个输入端的每一用于接收该延伸控制信号或耦合于在该任意两个直接相连的该整数除频器之间及在该分数除频器与该复数个整数除频器之间的复数个连接电路其中的任一，该输出端用以输出该可编程分数除频器的该输出信号，且该多路转接器将依据该延伸控制信号以选择该复数个输入端其中之一的一输入信号作为该输出信号。 Wherein each of the plurality of inputs is for receiving the extension control signal or for coupling between the two directly connected integer frequency dividers and between the fractional divider and the plurality of integer frequency dividers Complex Any one of a plurality of connection circuits for outputting the output signal of the programmable fractional divider, and the multiplexer is to select one of the plurality of inputs according to the extension control signal An input signal is used as the output signal.

12. 一种分数型锁相回路，包含： 12. A fractional phase-locked loop, comprising:

一压控震荡器，用于接收一输入信号与产生一输出信号；以及 a voltage controlled oscillator for receiving an input signal and generating an output signal;

一可编程分数除频器，耦合于该压控震荡器，用于接收该输出信号的一反馈信号，且将该反馈信号经除以复数个具有一分数除数间隔的除数其中之一，以产生一经除频的输出信号。 a programmable fractional frequency divider coupled to the voltage controlled oscillator for receiving a feedback signal of the output signal, and dividing the feedback signal by a plurality of divisors having a fractional divisor interval to generate A frequency-divided output signal.

13. 如权利要求 12所述的分数型锁相回路，其特征在于： 13. The fractional phase locked loop of claim 12, wherein:

该压控震荡器该输出信号的一频率，最后将稳定于该参考信号源的一频率乘以该除数的一平均值；及 /或 The voltage controlled oscillator outputs a frequency of the output signal, and finally a frequency stabilized by the reference signal source is multiplied by an average of the divisor; and/or

该可编程分数除频器为一如权利要求 7所述的可编程分数除频器。 The programmable fractional divider is a programmable fractional divider as claimed in claim 7.

14. 如权利要求 12所述的分数型锁相回路，其特征在于该压控震荡器还包括： 14. The fractional phase locked loop of claim 12, wherein the voltage controlled oscillator further comprises:

一第一压控电容，具有一第一端与一第二端，其中该第一端耦合于该回路滤波器，用于依据该输入信号调整该压控震荡器的一震荡频率； a first voltage-controlled capacitor having a first end and a second end, wherein the first end is coupled to the loop filter for adjusting an oscillation frequency of the voltage controlled oscillator according to the input signal;

一第二压控电容，具有一第一端与一第二端，其中该第一端耦合于该第一压控电容的该第一端，用于依据该输入信号调整该压控震荡器的该震荡频率； a second voltage-controlled capacitor having a first end and a second end, wherein the first end is coupled to the first end of the first voltage-controlled capacitor, and is configured to adjust the voltage-controlled oscillator according to the input signal The oscillation frequency;

一第一电感，具有一第一端与一第二端，其中该第一端耦合于该第一压控电容的该第二端，该第一电感的该第二端接地，且该第一电感用于与该第一压控电容形成一第一共震腔； a first inductor having a first end and a second end, wherein the first end is coupled to the second end of the first voltage controlled capacitor, the second end of the first inductor is grounded, and the first The inductor is configured to form a first resonance chamber with the first voltage control capacitor;

一第二电感，具有一第一端与一第二端，其中该第一端耦合于该第二压控电容的该第二端，该第二电感的该第二端接地，且该第二电感用于与该第二压控电容形成一第二共震腔； a second inductor having a first end and a second end, wherein the first end is coupled to the second end of the second voltage controlled capacitor, the second end of the second inductor is grounded, and the second The inductor is configured to form a second resonance chamber with the second voltage controlled capacitor;

一第一电容阵列，用于与该第一电感与该第一压控电容形成该第一共震腔，该第一电容阵列包括： a first capacitor array, configured to form the first resonance cavity with the first inductor and the first voltage control capacitor, the first capacitor array comprising:

复数个第一共震电容，各该第一共震电容均具有一第一端与一第二端，且该第一端均耦合于该第一电感的该第一端，以及 a plurality of first common-shock capacitors, each of the first common-shock capacitors having a first end and a second end, and the first end is coupled to the first end of the first inductor, and

复数个第一开关，各该第一开关均具有一第一端与一第二端，且该第一端耦合于该复数个第一共震电容其中的任一的该第二端，且该复数个第一开关的该第二端接地； a plurality of first switches, each of the first switches having a first end and a second end, and the first end is coupled And the second end of any one of the plurality of first common shock capacitors, and the second end of the plurality of first switches is grounded;

一第二电容阵列，用于与该第二电感与该第二压控电容形成该第二共震腔，该第二电容阵列包括： a second capacitor array for forming the second resonance cavity with the second inductor and the second voltage control capacitor, the second capacitor array comprising:

复数个第二共震电容，各该第二共震电容均具有一第一端与一第二端，且该第一端均耦合于该第二电感的该第一端，以及 a plurality of second common-shock capacitors, each of the second common-shock capacitors having a first end and a second end, and the first end is coupled to the first end of the second inductor, and

复数个第二开关，各该第二开关均具有一第一端与一第二端，且该第一端耦合于该复数个第二共震电容其中的任一的该第二端，且该复数个第二开关的该第二端接地；以及 a plurality of second switches, each of the second switches having a first end and a second end, and the first end is coupled to the second end of any one of the plurality of second common shock capacitors, and the second end The second end of the plurality of second switches is grounded;

一核心电路，分别耦合于该第一与该第二电感的该第一端，用于产生该压控震荡器的该输出信号，其中该核心电路还包括： A core circuit is coupled to the first ends of the first and second inductors for generating the output signal of the voltage controlled oscillator, wherein the core circuit further includes:

一第一晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该可编程分数除频器，且该第二端耦合于该控制端； a first transistor having a first, a second, and a control terminal, wherein the first terminal is coupled to the programmable fractional frequency divider, and the second terminal is coupled to the control terminal;

一第二晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该可编程分数除频器，且该控制端耦合于该第一晶体管的该控制端； a second transistor having a first, a second, and a control terminal, wherein the first terminal is coupled to the programmable fractional frequency divider, and the control terminal is coupled to the control terminal of the first transistor;

一第一电阻，具有一第一与一第二端，其中该第一端耦合于该第一晶体管的该第二端，且该第一电阻的该第二端接地； a first resistor having a first end and a second end, wherein the first end is coupled to the second end of the first transistor, and the second end of the first resistor is grounded;

一第三晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该第二晶体管的该第二端，该控制端耦合于该第一电感的该第一端，且该第三晶体管的该第二端耦合于该第二电感的该第一端；以及 a third transistor having a first, a second, and a control terminal, wherein the first terminal is coupled to the second end of the second transistor, the control terminal is coupled to the first end of the first inductor, And the second end of the third transistor is coupled to the first end of the second inductor;

一第四晶体管，具有一第一、一第二与一控制端，其中该第一端耦合于该第三晶体管的该第一端，该第二端耦合于该第一电感的该第一端，且该控制端耦合于该第二电感的该第一端。 a fourth transistor having a first, a second, and a control terminal, wherein the first end is coupled to the first end of the third transistor, and the second end is coupled to the first end of the first inductor And the control end is coupled to the first end of the second inductor.

15. 如权利要求 12所述的分数型锁相回路，其特征在于还包含： 15. The fractional phase-locked loop of claim 12, further comprising:

一石英震荡器，用于产生一参考信号源； a quartz oscillator for generating a reference signal source;

一相频检测器，耦合于该石英震荡器与该可编程分数除频器，用于比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号； a phase frequency detector coupled to the quartz oscillator and the programmable fractional frequency divider for comparing a phase and a frequency of the reference signal source and the frequency-divided output signal, and thereby generating a charge or a discharge signal;

一电荷泵，耦合于该相频检测器，用于在接收该充电信号时产生一充电动作以提升一输出电流俾提升该输出信号的一频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该输出信号的该频率； a charge pump coupled to the phase frequency detector for generating a charging action when receiving the charging signal Elevating an output current, raising a frequency of the output signal, and generating a discharge action to reduce the output current when the discharge signal is received, and decreasing the frequency of the output signal;

一回路滤波器，耦合于该电荷泵与该压控震荡器，用以滤除该电荷泵该输出电流的一相位杂讯，且据以产生该压控震荡器的该输入信号； a first loop filter coupled to the charge pump and the voltage controlled oscillator for filtering a phase noise of the output current of the charge pump, and thereby generating the input signal of the voltage controlled oscillator;

一三角积分调变器，用于接收一外加输入信号以产生一调变信号；以及一加法器，耦合于该调变器与该可编程分数除频器，用于接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器以产生该除数，其中- 该石英震荡器为一温度补偿石英震荡器 (TCXO); a triangular integral modulator for receiving an external input signal to generate a modulated signal; and an adder coupled to the modulator and the programmable fractional divider for receiving an added integer and the Modulating the signal, adding the two and inputting the programmable fractional divider to generate the divisor, wherein - the quartz oscillator is a temperature compensated quartz oscillator (TCXO);

该相频检测器还用于接收一极性控制信号 (POL)，当： POL=l及该参考信号源领先该输出信号时，该相频检测器输出该充电信号，而当 POLM3及该输出信号领先该参考信号源时，该相频检测器则输出该放电信号； The phase frequency detector is further configured to receive a polarity control signal (POL), when: POL=l and the reference signal source leads the output signal, the phase frequency detector outputs the charging signal, and when the POLM3 and the output When the signal leads the reference signal source, the phase frequency detector outputs the discharge signal;

该电荷泵还包括： The charge pump also includes:

一偏压电流源，用于提供一电流偏压； a bias current source for providing a current bias;

一偏压电路，耦合于该偏压电流源，用于提供一偏压； a bias circuit coupled to the bias current source for providing a bias voltage;

一第一输出电流源，耦合于该偏压电路，用于提供一第一输出电流；一充电开关，耦合于该相频检测器与该第一输出电流源，用于当接收该充电信号时，产生该充电动作； a first output current source coupled to the bias circuit for providing a first output current; a charging switch coupled to the phase frequency detector and the first output current source for receiving the charging signal , generating the charging action;

一放电开关，耦合于该相频检测器与该输出电流源，用于当接收该放电信号时，产生该放电动作； a discharge switch coupled to the phase frequency detector and the output current source for generating the discharge action when receiving the discharge signal;

一第一控制开关，耦合于该输出电流源，用以控制该泵的一输出电流的大小； a first control switch coupled to the output current source for controlling an output current of the pump;

一第二输出电流源，耦合于该第一控制开关，用于提供一第二输出电流；一第二控制开关，耦合于该第二输出电流源，用以控制该泵的该输出电流的大小； a second output current source coupled to the first control switch for providing a second output current; a second control switch coupled to the second output current source for controlling the magnitude of the output current of the pump ;

一第三输出电流源，耦合于该第二控制开关，用于提供一第三输出电流，其中该偏压电路可为一标准的低电压偏压电路，当该第一与该第二控制开关均关断时，该输出电流为该第一输出电流，当该第一控制开关导通及该第二控制开关关断时，该输出电流为该第一输出电流与该第二输出电流之和，且当该第一与该第二控制开关均导通时，该输出电流为该第一、该第二与该第三输出电流之和；该回路滤波器为一三阶滤波器，其中该回路滤波器可还包括： a third output current source coupled to the second control switch for providing a third output current, wherein the bias circuit can be a standard low voltage bias circuit, when the first and the second control switch When both are turned off, the output current is the first output current. When the first control switch is turned on and the second control switch is turned off, the output current is the sum of the first output current and the second output current. And when the first and the first When the two control switches are both turned on, the output current is the sum of the first, the second, and the third output current; the loop filter is a third-order filter, wherein the loop filter may further include:

一第一电容，具有一第一端与一第二端，其中该第一端耦合于该电荷泵，且该第二端接地； a first capacitor having a first end and a second end, wherein the first end is coupled to the charge pump, and the second end is grounded;

一第二电阻，具有一第一端与一第二端，其中该第一端耦合于该第一电容的该第一端； a second resistor having a first end and a second end, wherein the first end is coupled to the first end of the first capacitor;

一第二电容，具有一第一端与一第二端，其中该第一端耦合于该第二电阻的该第二端，且该第二电容的该第二端接地； a second capacitor having a first end and a second end, wherein the first end is coupled to the second end of the second resistor, and the second end of the second capacitor is grounded;

一第三电阻，具有一第一端与一第二端，其中该第一端耦合于该第二电阻的该第一端；以及 a third resistor having a first end and a second end, wherein the first end is coupled to the first end of the second resistor;

一第三电容，具有一第一端与一第二端，其中该第一端耦合于该第三电阻的该第二端与该压控震荡器，且该第三电容的该第二端接地；及 /或 a third capacitor having a first end and a second end, wherein the first end is coupled to the second end of the third resistor and the voltage controlled oscillator, and the second end of the third capacitor is grounded ; and / or

该三角积分器为一三阶三角积分器，而该三角积分器包括： The triangular integrator is a third-order triangular integrator, and the triangular integrator includes:

一第一一阶三角积分器，用于接收该外加的输入信号以产生一第一量化杂讯与一第一输出信号； a first first-order triangular integrator for receiving the applied input signal to generate a first quantization noise and a first output signal;

一第二一阶三角积分器，耦合于该第一一阶三角积分器，用于接收该第一量化杂讯以产生一第二量化杂讯与一第二输出信号； a second first-order triangular integrator coupled to the first first-order triangular integrator for receiving the first quantized noise to generate a second quantized noise and a second output signal;

一第三一阶三角积分器，耦合于该第二一阶三角积分器，用于接收该第二量化杂讯以产生一第三输出信号；以及 a third-order triangular integrator coupled to the second first-order triangular integrator for receiving the second quantized noise to generate a third output signal;

一位操控节点，耦合于该第一、该第二与该第三一阶三角积分器，用于接收该第一、该第二与该第三输出信号以产生该调变信号，其中该第一、该第二与该第三一阶三角积分器皆为一 24位的累加器；或 a steering node coupled to the first, second, and third first-order triangular integrators for receiving the first, second, and third output signals to generate the modulated signal, wherein the 1. The second and the third first-order triangular integrator are both a 24-bit accumulator; or

该第一一阶三角积分器为一 24位的累加器，该第二一阶三角积分器为一 16位的累加器，且该第三一阶三角积分器为一 8位的累加器。 The first first-order triangular integrator is a 24-bit accumulator, the second first-order triangular integrator is a 16-bit accumulator, and the third-order triangular integrator is an 8-bit accumulator.

16. 一种具有可调除频范围的分数型锁相回路，包含： 16. A fractional phase-locked loop with an adjustable frequency division range, comprising:

一分数型锁相回路电路，用于接收一输入信号与产生一输出信号，包含一可编程分数除频器，用于接收该输出信号的一反馈信号，且将该反馈信号经除以复数个具有一分数除数间隔的除数其中之一，以产生一经除频的输出信号；以及一除数延伸电路，用以依据一延伸控制信号，以使该可编程分数除频器的该复数个除数所形成的一除频范围可被据以调整。 a fractional phase-locked loop circuit for receiving an input signal and generating an output signal, comprising a programmable fractional divider for receiving a feedback signal of the output signal, and dividing the feedback signal by a plurality of One of a divisor having a fractional divisor interval to generate a demultiplexed output signal; and a divisor extension circuit for utilizing an extension control signal to cause the programmable fractional divider to A range of divisions formed by a plurality of divisors can be adjusted accordingly.

17. 如权利要求 16所述的分数型锁相回路，其特征在于该锁相回路电路为一如权利要求 12所述的分数型锁相回路，且该分数型锁相回路还包含： 17. The fractional phase locked loop of claim 16, wherein the phase locked loop circuit is a fractional phase locked loop according to claim 12, and the fractional phase locked loop further comprises:

一相频检测器，耦合于该石英震荡器与该具有可调除频范围的可编程分数除频器，用于比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电信号或一放电信号； a phase frequency detector coupled to the quartz oscillator and the programmable fractional frequency divider having an adjustable frequency division range for comparing a phase and a frequency of the reference signal source and the frequency-divided output signal, And generating a charging signal or a discharging signal accordingly;

一电荷泵，耦合于该相频检测器，用于在接收该充电信号时产生一充电动作以提升一输出电流俾提升该输出信号的一频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该输出信号的该频率； a charge pump coupled to the phase frequency detector for generating a charging action when receiving the charging signal to boost an output current, boosting a frequency of the output signal, and generating a discharging action when receiving the discharging signal Decreasing the output current 俾 lowering the frequency of the output signal;

一三阶三角积分调变器，用于接收一外加输入信号以产生一调变信号；以及一加法器，耦合于该调变器与该可编程分数除频器，用于接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器以产生该除数。 a third-order delta-sigma modulator for receiving an applied input signal to generate a modulated signal; and an adder coupled to the modulator and the programmable fractional divider for receiving an additional integer And the modulated signal is added, and the two are added together and input to the programmable fractional divider to generate the divisor.

18. 一种分数除频器的控制方法，该方法包含下列步骤： 18. A method of controlling a fractional frequency divider, the method comprising the steps of:

0)当一分数除频器用于将一输入信号除以一整数除数以产生一输出信号时，使一除数控制信号或一反馈控制信号为一逻辑低状态，且使该除频器相应一输入信号的一双缘触发而产生一具有逻辑低状态的除数选择信号以使该除频器的一输出信号的产生不被抑制； 0) when a fractional frequency divider is used to divide an input signal by an integer divisor to generate an output signal, causing a divisor control signal or a feedback control signal to be in a logic low state, and causing the frequency divider to correspond to an input A double edge of the signal is triggered to generate a divisor selection signal having a logic low state such that generation of an output signal of the frequency divider is not suppressed;

(b)当该除数控制信号及该反馈控制信号均为一逻辑高状态时，使该除频器相应该双缘触发而产生一具有逻辑高状态的除数选择信号以使该输出信号的产生被抑制；以及 (b) when the divisor control signal and the feedback control signal are both in a logic high state, causing the frequency divider to generate a divisor selection signal having a logic high state corresponding to the double edge triggering to cause the output signal to be generated. Suppression;

(c)当该除频器用于将该输入信号除以一分数除数以产生该输出信号时，该除频器产生该具有逻辑低状态的除数选择信号以使该输出信号持续产生达该输入信号的一个周期，而后该除频器产生该具有逻辑高状态的除数选择信号以使该输出信号的产生被抑制达半个该周期，并依此一方式循环。 (c) when the frequency divider is configured to divide the input signal by a fractional divisor to generate the output signal, the frequency divider generates the divisor selection signal having a logic low state to cause the output signal to continue to generate the input signal One cycle, then the frequency divider generates the divisor selection signal having a logic high state to suppress the generation of the output signal for half of the cycle, and cycle in this manner.

19. 如权利要求 18所述的控制方法，其特征在于该分数除频器为一如权利要求 1或 5所述的除频器。 19. The control method according to claim 18, wherein the fractional frequency divider is the frequency divider according to claim 1 or 5.

20. 一种可编程分数除频器的控制方法，其特征在于该除频器用于将一输入信号除以复数个具有一分数除数间隔的除数其中之一以产生一第一输出信号，该除频器包括一分数除频器，用于产生一第二输出信号，及一除频器长链，包含复数个彼此串连耦合的整数除频器，耦合于该分数除频器，用于产生该第一输出信号，该方法包含下列步骤： 20. A control method for a programmable fractional frequency divider, characterized in that the frequency divider is configured to divide an input signal by a plurality of divisors having a fractional divisor interval to generate a first output signal, the division The frequency converter includes a fractional frequency divider for generating a second output signal, and a long chain of the frequency divider, comprising a plurality of integer frequency dividers coupled in series with each other, coupled to the fractional frequency divider for generating The first output signal, the method comprises the following steps:

(aM吏该分数除频器接收该输入信号、复数个除数控制信号其中之一及该长链的一反馈控制信号，且使各该整数除频器均接收该复数个除数控制信号其中之一及各该整数除频器的一反馈控制信号； (aM) the fractional frequency divider receives the input signal, one of the plurality of divisor control signals, and a feedback control signal of the long chain, and causes each of the integer frequency dividers to receive one of the plurality of divisor control signals And a feedback control signal of each of the integer frequency dividers;

(b)当该分数除频器的该除数控制信号或该长链的该反馈控制信号为一逻辑低状态时，将该输入信号除以一第一整数除数以产生该第二输出信号，当该分数除频器的该除数控制信号或该长链的该反馈控制信号保持一逻辑低状态达该输入信号的一个周期，而后该分数除频器的该除数控制信号及该长链的该反馈控制信号保持一逻辑高状态达半个该周期，并依此一方式循环时，将该输入信号除以一分数除数以产生该第二输出信号； (b) when the divisor control signal of the fractional divider or the feedback control signal of the long chain is in a logic low state, dividing the input signal by a first integer divisor to generate the second output signal, when The divisor control signal of the fractional frequency divider or the feedback control signal of the long chain maintains a logic low state for one period of the input signal, and then the divisor control signal of the fractional divider and the feedback of the long chain The control signal maintains a logic high state for half of the period, and when cycled in this manner, dividing the input signal by a fractional divisor to generate the second output signal;

(c)当该整数除频器的该除数控制信号或该反馈控制信号为一逻辑低状态时，将该整数除频器的一输入信号除以一第二整数除数以产生该整数除频器的一输出信号，当该整数除频器的该除数控制信号及该反馈控制信号均保持一逻辑高状态时，将该整数除频器的该输入信号除以一第三整数除数以产生该整数除频器的该输出信号；以及 (c) when the divisor control signal or the feedback control signal of the integer frequency divider is in a logic low state, dividing an input signal of the integer frequency divider by a second integer divisor to generate the integer frequency divider An output signal, when the divisor control signal of the integer frequency divider and the feedback control signal are both maintained at a logic high state, dividing the input signal of the integer frequency divider by a third integer divisor to generate the integer The output signal of the frequency divider;

(d)使该可编程分数除频器依据该输入信号及各该除数以产生该第一输出信号。 (d) causing the programmable fractional divider to generate the first output signal based on the input signal and each of the divisors.

21. 如权利要求 20所述的控制方法，其特征在于该可编程分数除频器为一如权利要求 7所述的可编程分数除频器。 21. The control method of claim 20, wherein the programmable fractional divider is the programmable fractional divider of claim 7.

22. 一种具有可调除频范围的可编程分数除频器的控制方法，其中该除频器用于将一输入信号除以复数个具有一分数除数间隔的除数其中之一以产生一第一输出信号，该除频器包括一分数除频器，用于产生一第二输出信号，一除频器长链，包含复数个彼此串连耦合的整数除频器，耦合于该分数除频器，用于产生该第一输出信号，及一除数延伸电路，用以调整该复数个除数所形成的一除数范围，该方法包含下列步骤： (a)使该除数延伸电路产生一控制信号以切断或不切断包含一特定整数除频器之后的所有各该整数除频器的一反馈控制，俾使该除数范围可被调整； 22. A control method for a programmable fractional frequency divider having an adjustable frequency division range, wherein the frequency divider is configured to divide an input signal by a plurality of divisors having a fractional divisor interval to generate a first An output signal, the frequency divider comprising a fractional frequency divider for generating a second output signal, a long divider of the frequency divider, comprising a plurality of integer frequency dividers coupled in series with each other, coupled to the fractional frequency divider And for generating the first output signal, and a divisor extension circuit for adjusting a divisor range formed by the plurality of divisors, the method comprising the following steps: (a) causing the divisor extension circuit to generate a control signal to cut or not cut off a feedback control of all of the integer frequency dividers including a particular integer frequency divider, such that the divisor range can be adjusted;

(b)使该分数除频器接收该输入信号、复数个除数控制信号其中之一及该长链的一反馈控制信号，且使各该整数除频器均接收该复数个除数控制信号其中之一及各该整数除频器的一反馈控制信号； (b) causing the fractional frequency divider to receive the input signal, one of the plurality of divisor control signals, and a feedback control signal of the long chain, and causing each of the integer frequency dividers to receive the plurality of divisor control signals And a feedback control signal of each of the integer frequency dividers;

(c)当该分数除频器的该除数控制信号或该长链的该反馈控制信号为一逻辑低状态时，将该输入信号除以一第一整数除数以产生该第二输出信号，当该分数除频器的该除数控制信号或该长链的该反馈控制信号保持一逻辑低状态达该输入信号的一个周期，而后该分数除频器的该除数控制信号及该长链的该反馈控制信号保持一逻辑高状态达半个该周期，并依此一方式循环时，将该输入信号除以一分数除数以产生该第二输出信号； (c) when the divisor control signal of the fractional divider or the feedback control signal of the long chain is in a logic low state, dividing the input signal by a first integer divisor to generate the second output signal, when The divisor control signal of the fractional frequency divider or the feedback control signal of the long chain maintains a logic low state for one period of the input signal, and then the divisor control signal of the fractional divider and the feedback of the long chain The control signal maintains a logic high state for half of the period, and when cycled in this manner, dividing the input signal by a fractional divisor to generate the second output signal;

(d)当该整数除频器的该除数控制信号或该反馈控制信号为一逻辑低状态时，将该整数除频器的一输入信号除以一第二整数除数以产生该整数除频器的一输出信号，当该整数除频器的该除数控制信号及该反馈控制信号均保持一逻辑高状态时，将该整数除频器的该输入信号除以一第三整数除数以产生该整数除频器的该输出信号；以及 (d) when the divisor control signal or the feedback control signal of the integer frequency divider is in a logic low state, dividing an input signal of the integer frequency divider by a second integer divisor to generate the integer frequency divider An output signal, when the divisor control signal of the integer frequency divider and the feedback control signal are both maintained at a logic high state, dividing the input signal of the integer frequency divider by a third integer divisor to generate the integer The output signal of the frequency divider;

(e)使该可编程分数除频器依据该输入信号及各该除数以产生该第一输出信号。 (e) causing the programmable fractional divider to generate the first output signal based on the input signal and each of the divisors.

23. 如权利要求 22所述的控制方法，其特征在于该具有可调除频范围的可编程分数除频器为一如权利要求 10所述的可编程分数除频器。 23. The control method according to claim 22, wherein the programmable fractional divider having the adjustable frequency division range is the programmable fractional divider of claim 10.

24. 一种分数型锁相回路的控制方法，该方法包含下列步骤： 24. A method of controlling a fractional phase-locked loop, the method comprising the steps of:

(aM吏一压控震荡器接收一输入信号与产生一输出信号；以及 (aM吏 a voltage controlled oscillator receives an input signal and generates an output signal;

(bM吏一可编程分数除频器接收该输出信号的一反馈信号，且将该反馈信号经复数个具有一分数除数间隔的除数其中之一的除频后，产生一经除频的输出信号。 (bM) A programmable fractional frequency divider receives a feedback signal of the output signal, and divides the feedback signal by a plurality of divisors having a fractional divisor interval to generate a frequency-divided output signal.

25. 如权利要求 24所述的控制方法，其特征在于还包含下列步骤： 25. The control method according to claim 24, further comprising the following steps:

(c)使一石英震荡器产生一参考信号源； (c) causing a quartz oscillator to generate a reference signal source;

(d)由一相频检测器比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号； (e)使一电荷泵于接收该充电信号时产生一充电动作以提升一输出电流而提升该经除频的输出信号的该频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该经除频的输出信号的该频率； (d) comparing, by a phase frequency detector, a phase and a frequency of the reference signal source and the frequency-divided output signal, and generating a charge or a discharge signal accordingly; (e) causing a charge pump to generate a charging action upon receiving the charging signal to boost an output current to increase the frequency of the frequency-divided output signal, and generating a discharging action to reduce the output upon receiving the discharging signal Current 俾 reduces the frequency of the frequency-divided output signal;

(f)由一回路滤波器滤除该电荷泵该输出电流的一相位杂讯，且据以产生该压控震荡器的该输入信号； (f) filtering, by a primary loop filter, a phase noise of the output current of the charge pump, and thereby generating the input signal of the voltage controlled oscillator;

(gM吏一三角积分调变器接收一外加的输入信号以产生一调变信号； (The gM吏-delta integral adjuster receives an applied input signal to generate a modulated signal;

(h)使一加法器接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器，以产生该除数；以及 (h) causing an adder to receive an additional integer and the modulated signal, and adding the two to the programmable fractional divider to generate the divisor;

(i)经该分数型锁相回路的复数个运作后，使该压控震荡器该输出信号的一频率，稳定于该参考信号源的一频率乘以该除数的一平均值，其中该分数型锁相回路可为一如权利要求 12所述的分数型锁相回路。 (i) after a plurality of operations of the fractional phase-locked loop, causing a frequency of the output signal of the voltage controlled oscillator to be stabilized at a frequency of the reference signal source multiplied by an average of the divisor, wherein the fraction The type phase locked loop can be a fractional phase locked loop as claimed in claim 12.

26. 一种具有可调除频范围的分数型锁相回路的控制方法，该方法包含下列步骤： 26. A method of controlling a fractional phase-locked loop having an adjustable frequency division range, the method comprising the following steps:

(a)使一压控震荡器接收一输入信号与产生一输出信号；以及 (a) causing a voltage controlled oscillator to receive an input signal and generate an output signal;

(b)使一具有可调除频范围的可编程分数除频器接收该输出信号的一反馈信号，且将该反馈信号经复数个具有一分数除数间隔的除数其中之一的除频后，产生一经除频的输出信号，且该除频器的一除数范围是相应该除频器所接收的一延伸控制信号而可被据以调整。 (b) causing a programmable fractional divider having an adjustable frequency division range to receive a feedback signal of the output signal, and subjecting the feedback signal to a division of the plurality of divisors having a fractional divisor interval, A frequency-divided output signal is generated, and a divisor range of the frequency divider is adjusted according to an extended control signal received by the frequency divider.

27. 如权利要求 26所述的控制方法，其特征在于还包含下列步骤： 27. The control method according to claim 26, further comprising the steps of:

(d)由一相频检测器比较该参考信号源与该经除频的输出信号的一相位与一频率，且据以产生一充电或一放电信号； (d) comparing, by a phase frequency detector, a phase and a frequency of the reference signal source and the frequency-divided output signal, and thereby generating a charge or a discharge signal;

(e)使一电荷泵于接收该充电信号时产生一充电动作以提升一输出电流俾提升该经除频的输出信号的该频率，且在接收该放电信号时产生一放电动作以降低该输出电流俾降低该经除频的输出信号的该频率； (e) causing a charge pump to generate a charging action upon receiving the charging signal to boost an output current, boosting the frequency of the frequency-divided output signal, and generating a discharging action to reduce the output upon receiving the discharging signal Current 俾 reduces the frequency of the frequency-divided output signal;

(g)使一三角积分调变器接收一外加的输入信号以产生一调变信号； (g) causing a triangular integral modulator to receive an applied input signal to generate a modulated signal;

(h)使一加法器接收一外加的整数与该调变信号，并将该两者相加后输入该可编程分数除频器，以产生该除数；以及 (h) causing an adder to receive an additional integer and the modulated signal, and adding the two to input the Programming a fractional divider to generate the divisor;

(i)经该分数型锁相回路的复数个运作后，使该压控震荡器该输出信号的一频率，稳定于该参考信号源的一频率乘以该除数的一平均值，其中该具有可调除频范围的分数型锁相回路可为一如申请专利范围第 16项所述的分数型锁相回路。 (i) after a plurality of operations of the fractional phase-locked loop, causing a frequency of the output signal of the voltage controlled oscillator to be stabilized at a frequency of the reference signal source multiplied by an average of the divisor, wherein The fractional phase-locked loop of the adjustable frequency division range can be a fractional phase-locked loop as described in claim 16 of the patent application.