WO2007088494A1 - Semiconductor device and method of manufacturing such a device - Google Patents

Semiconductor device and method of manufacturing such a device Download PDF

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Publication number
WO2007088494A1
WO2007088494A1 PCT/IB2007/050210 IB2007050210W WO2007088494A1 WO 2007088494 A1 WO2007088494 A1 WO 2007088494A1 IB 2007050210 W IB2007050210 W IB 2007050210W WO 2007088494 A1 WO2007088494 A1 WO 2007088494A1
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Prior art keywords
region
transistor
semiconductor
epitaxially
epitaxially thickened
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PCT/IB2007/050210
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French (fr)
Inventor
Johannes J. T. M. Donkers
Philippe Meunier-Beillard
Erwin Hijzen
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Nxp B.V.
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Publication of WO2007088494A1 publication Critical patent/WO2007088494A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Definitions

  • the invention relates to a semiconductor device with a substrate and a semiconductor body of silicon that is provided at one location with a field effect or bipolar transistor with a semiconductor region which forms part of the transistor and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is adjacent to the surface of the semiconductor body, which semiconductor region is provided with an epitaxially thickened region.
  • the invention also relates to a method of manufacturing such a device.
  • the extrinsic part of the base region which in principle has approximately the same thickness as the functional part thereof, may exhibit this problem that the - lateral - resistance thereof is too high.
  • the semiconductor region in this case the extrinsic base region, has been provided with a thickened region by means of local/selective epitaxy. This makes it possible to realize a good, i.e. a low-ohmic, electrical connection of the base region of a very fast bipolar transistor.
  • the extrinsic base region provided with the epitaxially thickened region is called a "raised" region in that case.
  • the semiconductor region may also form a source and/or drain region of a field effect transistor.
  • a so- termed "raised" configuration of the source and/or drain region makes it possible to provide a very small transistor with a relatively low-ohmic connection of the source and drain region.
  • Such a field effect transistor is known from US patents US 5,827,768; US 6,523,378 and US 2005/0,095,796.
  • MOS Metal Oxide Semiconductor
  • Bi(C)MOS Bipolar(Complementary) MOS
  • existing preparation processes such as the aforementioned process, comprise a large number of steps and/or are laborious in the case of the aforesaid integration. This stands in the way of realizing a high output and/or a low cost price.
  • the object of the present invention is therefore to provide a device which lends itself very well for integrating other semiconductor components therein, which device can be manufactured by means of a manufacturing methods that is simple and/or comprises relatively few steps.
  • a device of the kind referred to in the introduction is according to the invention characterized in that the surface of the semiconductor body is provided with another epitaxially thickened region at a location other than the location where the transistor is present, and in that said other epitaxially thickened region is provided with at least one pn-junction.
  • the invention is in the first place based on the perception that an epitaxially thickened region provides excellent possibilities of forming one or more pn-junctions therein. The fact is that this can be realized in a simple manner during the epitaxial growth by supplying doping elements at the right moment, for example by suitably opening and closing gas lines carrying doping elements.
  • the invention is furthermore based on the perception that the presence of such (a) pn-junction(s) above the base region or source/drain region of a transistor is not desirable, but that such a junction can be removed or prevented from being formed in a simple manner, for example by means of an overdoping ion implantation.
  • the invention is furthermore based on the perception that a further epitaxially thickened region provided with two pn-junctions can form a bipolar transistor in a simple manner.
  • said other epitaxially thickened region is therefore provided with two pn-junctions, which form part of another transistor, which other transistor comprises a bipolar transistor.
  • the transistor comprises a MOSFET, this makes it possible to realize a Bi(C)MOS circuit, which is sufficiently easy to manufacture and which nevertheless offers sufficient possibilities of realizing an added bipolar transistor with a quality that is adequate for many applications.
  • the epitaxially thickened region and the other epitaxially thickened region have been formed simultaneously.
  • the manufacture is relatively simple in that case and, as already noted above, a local implantation provides a simple possibility of eliminating the pn-junctions at locations where they are not desirable.
  • the invention offers advantages also if said other epitaxially thickened region and the epitaxially thickened region have been formed in two different epitaxy steps.
  • the device may exhibit the same (surface) geometry at the location of the transistor and at the location of the other transistor in that case.
  • the epitaxially thickened region may in that case be screened by means of a mask during the formation of the other epitaxially thickened region provided with said at least one pn- junction.
  • the epitaxially thickened region need not comprise (a) pn-junction(s) in that case, and consequently no pn-junctions need to be removed therefrom.
  • the pn-junction(s) has (have) been removed from the epitaxially thickened region by overdoping.
  • both the epitaxially thickened region and the other epitaxially thickened region furthermore comprise an implanted region which overdopes said at least one pn-junction at least locally.
  • an advantage for the other epitaxially thickened region is the fact that in this variant the other (bipolar) transistor can be structured more adequately and/or more easily.
  • the other epitaxially thickened region is preferably positioned beside or on either side of another gate region that has been formed simultaneously with the gate region of the transistor.
  • Such an other gate region may have been formed in the device in a MOS process without any difficulty, as this can take place simultaneously with the formation of the real MOS transistors.
  • the isolating distance pieces (so-termed spacers) of such an other gate region may contribute to the configuration/structuring of the other (bipolar) transistor.
  • the other gate region may function as a connecting region or as a control region for said at least one pn-junction in the other epitaxially thickened region.
  • the other thickened region comprises only one pn-junction, but also if said at least one bipolar transistor comprises two pn-junctions.
  • said at least one pn-junction extends approximately parallel to the surface of the semiconductor body.
  • Such (a) pn-junction(s) is easy to form during an epitaxy process, and it can be also used very well in the formation of a bipolar transistor.
  • MOS transistors are very inexpensive, essential components for very many functions, such as a logic function.
  • a bipolar transistor integrated in said other thickened region has a quality that suffices for many functions for which the presence of a bipolar transistor is indispensable, whilst in addition it can still be manufactured in a relatively simple and inexpensive manner.
  • a method of manufacturing a semiconductor device with a substrate and a semiconductor body of silicon that is provided at one location with a field effect or bipolar transistor comprising a semiconductor region which forms part of the transistor and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is formed adjacent to the surface of the semiconductor body, which semiconductor region is provided with an epitaxially thickened region, is according to the invention characterized in that the surface of the semiconductor body is provided with another epitaxially thickened region at a location other than the location where the transistor is formed and in that said other epitaxially thickened region is provided with at least one pn- junction. In this way a device according to the invention is obtained in a simple manner.
  • said at least one pn-junction is formed in situ during the epitaxial process by means of which said other epitaxially thickened region is formed.
  • Fig. 1 is a schematic, cross-sectional view perpendicular to the thickness direction of an embodiment of a device according to the invention.
  • Figs. 2-7 are schematic, cross-sectional views perpendicular to the thickness direction of the device of Fig. 1, showing successive stages of the manufacture of the device by means of an embodiment of the method according to the invention.
  • the Figures are not drawn to scale, and some dimensions are exaggerated for the sake of clarity. Corresponding regions or parts are indicated by the same numerals as much as possible.
  • Fig. 1 is a schematic, cross-sectional view perpendicular to the thickness direction of an embodiment of a semiconductor device 10 according to the invention.
  • the semiconductor device 10 comprises a substrate 12, of p-type silicon in this embodiment, and a semiconductor body 11 of silicon provided with an n-type epitaxial layer 16, two n-type epitaxial layers 16,17 in this embodiment.
  • a gate dielectric layer 18, of a thermally formed silicon dioxide in this case, has been formed thereon.
  • the semiconductor body 11 is provided with a field effect transistor or bipolar transistor Tl at a location A.
  • the transistor Tl is not shown in the Figure, but it is provided with p-type (in this case) source and drain regions adjacent to the surface, which are separated from each other by an n-type (in this case) channel region, above which a silicon dioxide (in this case) gate dielectric is located.
  • a gate dielectric Present above the gate dielectric is a gate region comprising a p-type (in this case) polycrystalline silicon region surrounded by distance pieces or spacers.
  • Present below the distance pieces or spacers are extension regions of the source and drain regions.
  • the source and drain regions of the MOS transistor Tl are provided with an epitaxially thickened region, i.e. a p-type (in this case) doped epitaxial silicon region which is present on the p-type source and drain regions of silicon and which contributes to a low connection resistance of the source and drain regions.
  • the surface of the semiconductor body 11 is provided with another epitaxially thickened region 1 , which other epitaxially thickened region 1 comprises at least one pn-junction, two pn-junctions 2,3 in this case.
  • the semiconductor body 11 of this example comprises a group of silicon semiconductor regions 13,14,15,16, in this case of the n-conductivity type.
  • a p-type silicon semiconductor region 20 is positioned between the pn- junctions 2,3.
  • Said other thickened region 1 thus comprises a bipolar transistor T2, which is defined in part by the connecting diagram of the various semiconductor regions 13,14,15,16 and 20 via the connecting conductors 30,31,32,33,34 that are located in an electrically insulating layer 40, of silicon dioxide in this case.
  • said other epitaxially thickened region 1 and said epitaxially thickened region have been formed simultaneously in a single epitaxial deposition process.
  • the pn-junction(s) has (have) Ben (locally) removed by overdoping, in this case by means of an ion implantation with doping ions of the p- conductivity type, such as boron ions.
  • a similar ion implantation has formed a p-type region 4 in this case, which is present in said other epitaxially thickened region 1 and which connects the p-type silicon semiconductor region 20 to the connecting conductors 31,33.
  • the other epitaxially thickened region 1 is positioned beside or, as in this case, on either side of another gate region 5, which has been formed simultaneously with the gate region of the transistor Tl .
  • the position of the other, bipolar transistor T2 depends in part on the way in which the connecting conductors have been driven.
  • a first possibility in this connection is that if the connecting conductors 30,34 function as a double connection for a double emitter region 13,14,13A,14A, the connections 31,33 will function as a double connection for a double base region 20,2OA via the p-type region 4.
  • the collector of the npn-transistor T2 is in that case made up of the semiconductor regions 15, 16, which are provided with a connecting conductor (not shown). Said connecting conductor may be connected to the collector regions via a sunken n-type (in this case) semiconductor region.
  • Another connecting possibility for the transistor T2 is provided if the connecting conductor 31 functions as an emitter connection and the connecting conductor 33 functions as a collector connection for the p-type semiconductor regions 20 and 2OA, respectively.
  • the semiconductor regions 15,16 form the base region of the lateral pnp (in this case) transistor T2.
  • the other gate region 5 may not be in use in the semiconductor device 10 of this example, but it may also advantageously function as a connecting region or as a control region (gate region) for the at least one pn-junction 2,3 in the other epitaxially thickened region 1.
  • RESURF REduced SURface Field
  • the gate region 5 may have been used for influencing the base region or the emitter and collector regions. In this way the other bipolar transistor T2 actually forms a semiconductor component provided with four connections.
  • An important advantage of the semiconductor device 10 of this example is the fact that it may have been formed in a standard CMOS process (see Tl), in which only relatively few adaptations are needed in order to obtain bipolar transistors (see T2) that have relatively good characteristics.
  • the latter means that said bipolar transistors are not as good as those obtained by using a genuine bipolar process or a bipolar (C)MOS process, to be true, but considerably better than those obtained with parasitic (bipolar) transistors that are normally present.
  • the semiconductor device 10 of this example can be manufactured as follows by means of a method according to the invention.
  • Figs. 2-7 are schematic, cross-sectional views perpendicular to the thickness direction of the device of Fig. 1, showing successive stages of the manufacture of the device by means of an embodiment of the method according to the invention.
  • the starting point (see Fig. 2) is a p-type silicon substrate 12, on which an n- type epitaxial layer 16, in this case two n-type silicon layers 16,17, is deposited.
  • a gate dielectric layer 18 is formed thereon, in this case by means of a thermally formed silicon dioxide.
  • a gate region (not shown) for a MOS transistor Tl is formed at the location of part A of the semiconductor body 11, which gate region has the same structure and which is formed simultaneously with another gate region 5 that is formed at the location B on the semiconductor body 11.
  • the other gate region 5 is in this case formed by means of photolithography and etching from a p-type polycrystalline silicon layer 5 A with a hard masking layer 50 of silicon dioxide present thereon, with spacers 19 being formed on either side thereof, in this case comprising an L-shaped silicon nitride region, on which an approximately rectangular silicon dioxide region is present.
  • the source and drain regions of the MOS transistor Tl are formed by means of an ion implantation on either side of the gate region, which is identical to the other gate region 5.
  • the other gate region 5 at location B of the semiconductor body 11 is screened by means of a masking layer (not shown) of a photoresist, for example.
  • another epitaxially thickened region 1 provided with two pn-junctions 2,3 on either side of the other gate region 5 and on either side of the gate region Tl is formed at location B simultaneously with the formation of an epitaxially thickened region at location A.
  • the pn-junctions 2,3 extend (substantially) parallel to the surface of the semiconductor body 11 and are formed not only of a silicon compound used in the epitaxial deposition process but also of gaseous compounds of n-type or p-type contamination atoms such as phosphine or boron, which are supplied at the appropriate moments.
  • the I-shaped part of the spacers 19 is removed by selective etching.
  • the hard mask 50 is removed at the same time.
  • TEOS Tetra Ethyl Ortho Silicate
  • part of the silicon nitride layer 6OB is selectively removed by etching, and subsequently an ion implantation of boron ions is carried out, forming a p-type region 4 that overdopes part of the n-type semiconductor regions 14,15,16 into p-type regions, forming as a p-type semiconductor region 10 located between the pn-junctions 2,3.
  • the p-type region 4 extends in the form of extensions under the L-shaped silicon nitride parts of the spacers 19.
  • an npn- version of Tl can be structure in this manner whilst on the other hand this structure can readily make use of the other gate region 5 that can function in particular as a control region in the 4-terminal device.
  • the masking layer 70 is removed and a new masking layer 80 of a photoresist is patterned on the semiconductor body 11.
  • a new masking layer 80 of a photoresist is patterned on the semiconductor body 11.
  • another part of the silicon nitride layer 6OB is removed by selective etching, for example by means of hot phosphoric acid.
  • the higher doped n-type region 13 is formed by means of an ion implantation. Also with regard to this step it applies that in a possible modification an implantation that is commonly used in CMOS processes might be used for this purpose.
  • a structure is obtained (see Fig. 7) in which the action of the remaining parts 6OB of the silicon nitride layer has resulted in part of the less highly doped n-type semiconductor region 14 still being present at the surface between the highly doped n-type semiconductor region 13 and the p-type semiconductor region 20. Among other things this prevents the occurrence of a breakdown at an edge of the p-type region 20 during operation of the device 10.
  • the various semiconductor regions are then provided in a self-aligning manner with contact regions that comprise a metal suicide. Such a suicide process is also used, simultaneously therewith, in the formation of the contact regions of the source, drain and gate regions of the MOS transistor Tl.
  • a silicon dioxide layer 40 is applied, which is provided with openings by photolithography and etching.
  • connecting conductors 30-34 can readily be formed, for example in the form of tungsten plugs. Said plugs are connected to the various semiconductor regions 13,20,5 A via metal suicide contact regions.
  • individual devices 10 according to the invention can be obtained.
  • the invention is not limited to the embodiment is that are shown herein, as many variations and modifications can be realized by those skilled in the art within the scope of the invention.
  • the structure and the manufacture of the transistor as described in the examples are quite suitable for use in an IC.
  • STI Shallow hole Trench Isolation
  • LOCOS Low Oxidation Of Silicon
  • germanium may be advantageously added to the silicon of the various semiconductor regions for improving the characteristics of the various transistors.

Abstract

The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon that is provided at one location (A) with a field effect or bipolar transistor (Tl) with a semiconductor region which forms part of the transistor (Tl) and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is adjacent to the surface of the semiconductor body (11), which semiconductor region is provided with an epitaxially thickened region. According to the invention the surface of the semiconductor body (11) is provided with another epitaxially thickened region (1) at a location (B) other than the location where the transistor is present, and said other epitaxially thickened region is provided with at least one pn-junction (2,3). If the device is provided with two pn-junctions (2,3) it allows advantageously the integration of a bipolar transistor (T2) into a device with a MOSFET (Tl). The pn-junctions in the epitaxially thickened region of the latter can be removed without difficulty, e.g. by overdoping. The invention also relates to a method of manufacturing such a device (10).

Description

Semiconductor device and method of manufacturing such a device
The invention relates to a semiconductor device with a substrate and a semiconductor body of silicon that is provided at one location with a field effect or bipolar transistor with a semiconductor region which forms part of the transistor and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is adjacent to the surface of the semiconductor body, which semiconductor region is provided with an epitaxially thickened region. The invention also relates to a method of manufacturing such a device.
Such a device and method are known from US patent US 6,911,681. Said document discusses a bipolar transistor with a so-termed "raised extrinsic base", i.e. the base region of the bipolar transistor that is shown therein, a functional part of which is located under the emitter region and above the collector region, also comprises a further part that extends laterally beside said functional part at the surface of the semiconductor body. Said part forms a semiconductor region, the so-termed "extrinsic base", which functions inter alia as a connecting region for a required electrical connection of the base region. As it is desirable with a view to obtaining an optimum, i.e. in particular a very fast, operation of the transistor that the functional part of the base region be very thin, the extrinsic part of the base region, which in principle has approximately the same thickness as the functional part thereof, may exhibit this problem that the - lateral - resistance thereof is too high. To obviate this problem, the semiconductor region, in this case the extrinsic base region, has been provided with a thickened region by means of local/selective epitaxy. This makes it possible to realize a good, i.e. a low-ohmic, electrical connection of the base region of a very fast bipolar transistor. The extrinsic base region provided with the epitaxially thickened region is called a "raised" region in that case.
In a similar manner, and for similar reasons, the semiconductor region may also form a source and/or drain region of a field effect transistor. In this case, too, a so- termed "raised" configuration of the source and/or drain region makes it possible to provide a very small transistor with a relatively low-ohmic connection of the source and drain region. Such a field effect transistor is known from US patents US 5,827,768; US 6,523,378 and US 2005/0,095,796.
A drawback of the known device is that it is not suitable, or at least not very, for processes in which other semiconductor elements are integrated in the device, such as pn- junction functioning as a (variable) capacitor or another, in particular a bipolar, transistor besides MOS (=Metal Oxide Semiconductor) transistor such as in Bi(C)MOS (=Bipolar(Complementary) MOS) processes. More in particular, existing preparation processes, such as the aforementioned process, comprise a large number of steps and/or are laborious in the case of the aforesaid integration. This stands in the way of realizing a high output and/or a low cost price.
The object of the present invention is therefore to provide a device which lends itself very well for integrating other semiconductor components therein, which device can be manufactured by means of a manufacturing methods that is simple and/or comprises relatively few steps.
In order to achieve that object, a device of the kind referred to in the introduction is according to the invention characterized in that the surface of the semiconductor body is provided with another epitaxially thickened region at a location other than the location where the transistor is present, and in that said other epitaxially thickened region is provided with at least one pn-junction. The invention is in the first place based on the perception that an epitaxially thickened region provides excellent possibilities of forming one or more pn-junctions therein. The fact is that this can be realized in a simple manner during the epitaxial growth by supplying doping elements at the right moment, for example by suitably opening and closing gas lines carrying doping elements. The invention is furthermore based on the perception that the presence of such (a) pn-junction(s) above the base region or source/drain region of a transistor is not desirable, but that such a junction can be removed or prevented from being formed in a simple manner, for example by means of an overdoping ion implantation. The invention is furthermore based on the perception that a further epitaxially thickened region provided with two pn-junctions can form a bipolar transistor in a simple manner.
In a preferred embodiment of a device according to the invention, said other epitaxially thickened region is therefore provided with two pn-junctions, which form part of another transistor, which other transistor comprises a bipolar transistor. Especially if the transistor comprises a MOSFET, this makes it possible to realize a Bi(C)MOS circuit, which is sufficiently easy to manufacture and which nevertheless offers sufficient possibilities of realizing an added bipolar transistor with a quality that is adequate for many applications.
Preferably, the epitaxially thickened region and the other epitaxially thickened region have been formed simultaneously. The manufacture is relatively simple in that case and, as already noted above, a local implantation provides a simple possibility of eliminating the pn-junctions at locations where they are not desirable.
It is noted in that connection that the invention offers advantages also if said other epitaxially thickened region and the epitaxially thickened region have been formed in two different epitaxy steps. After all, the device may exhibit the same (surface) geometry at the location of the transistor and at the location of the other transistor in that case. The epitaxially thickened region may in that case be screened by means of a mask during the formation of the other epitaxially thickened region provided with said at least one pn- junction. The epitaxially thickened region need not comprise (a) pn-junction(s) in that case, and consequently no pn-junctions need to be removed therefrom.
In another advantageous embodiment, the pn-junction(s) has (have) been removed from the epitaxially thickened region by overdoping. The advantage of this has already been discussed in the foregoing.
Preferably, both the epitaxially thickened region and the other epitaxially thickened region furthermore comprise an implanted region which overdopes said at least one pn-junction at least locally. The advantage of this for the epitaxially thickened region will be apparent from the foregoing, whilst an advantage for the other epitaxially thickened region is the fact that in this variant the other (bipolar) transistor can be structured more adequately and/or more easily.
In a device in which the transistor is a field effect transistor provided with a gate region, the other epitaxially thickened region is preferably positioned beside or on either side of another gate region that has been formed simultaneously with the gate region of the transistor. Such an other gate region may have been formed in the device in a MOS process without any difficulty, as this can take place simultaneously with the formation of the real MOS transistors. The isolating distance pieces (so-termed spacers) of such an other gate region may contribute to the configuration/structuring of the other (bipolar) transistor. In addition to that, the other gate region may function as a connecting region or as a control region for said at least one pn-junction in the other epitaxially thickened region. This applies if the other thickened region comprises only one pn-junction, but also if said at least one bipolar transistor comprises two pn-junctions. Preferably, said at least one pn-junction extends approximately parallel to the surface of the semiconductor body. Such (a) pn-junction(s) is easy to form during an epitaxy process, and it can be also used very well in the formation of a bipolar transistor.
From the foregoing it follows that the invention is preferably used in a device in which the transistor forms a MOS transistor and which comprises a Bi(C)MOS IC (=Integrated Circuit). MOS transistors are very inexpensive, essential components for very many functions, such as a logic function. In addition to that, a bipolar transistor integrated in said other thickened region has a quality that suffices for many functions for which the presence of a bipolar transistor is indispensable, whilst in addition it can still be manufactured in a relatively simple and inexpensive manner.
A method of manufacturing a semiconductor device with a substrate and a semiconductor body of silicon that is provided at one location with a field effect or bipolar transistor comprising a semiconductor region which forms part of the transistor and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is formed adjacent to the surface of the semiconductor body, which semiconductor region is provided with an epitaxially thickened region, is according to the invention characterized in that the surface of the semiconductor body is provided with another epitaxially thickened region at a location other than the location where the transistor is formed and in that said other epitaxially thickened region is provided with at least one pn- junction. In this way a device according to the invention is obtained in a simple manner.
In an advantageous embodiment, said at least one pn-junction is formed in situ during the epitaxial process by means of which said other epitaxially thickened region is formed.
The invention will now be explained in more detail by means of a description of an embodiment thereof, wherein reference is made to the drawing, in which:
Fig. 1 is a schematic, cross-sectional view perpendicular to the thickness direction of an embodiment of a device according to the invention, and
Figs. 2-7 are schematic, cross-sectional views perpendicular to the thickness direction of the device of Fig. 1, showing successive stages of the manufacture of the device by means of an embodiment of the method according to the invention. The Figures are not drawn to scale, and some dimensions are exaggerated for the sake of clarity. Corresponding regions or parts are indicated by the same numerals as much as possible.
Fig. 1 is a schematic, cross-sectional view perpendicular to the thickness direction of an embodiment of a semiconductor device 10 according to the invention. The semiconductor device 10 comprises a substrate 12, of p-type silicon in this embodiment, and a semiconductor body 11 of silicon provided with an n-type epitaxial layer 16, two n-type epitaxial layers 16,17 in this embodiment. A gate dielectric layer 18, of a thermally formed silicon dioxide in this case, has been formed thereon. The semiconductor body 11 is provided with a field effect transistor or bipolar transistor Tl at a location A. The transistor Tl is not shown in the Figure, but it is provided with p-type (in this case) source and drain regions adjacent to the surface, which are separated from each other by an n-type (in this case) channel region, above which a silicon dioxide (in this case) gate dielectric is located. Present above the gate dielectric is a gate region comprising a p-type (in this case) polycrystalline silicon region surrounded by distance pieces or spacers. Present below the distance pieces or spacers are extension regions of the source and drain regions. The source and drain regions of the MOS transistor Tl are provided with an epitaxially thickened region, i.e. a p-type (in this case) doped epitaxial silicon region which is present on the p-type source and drain regions of silicon and which contributes to a low connection resistance of the source and drain regions.
At a location B on the semiconductor body 11 other than the location where the transistor Tl is present, the surface of the semiconductor body 11 is provided with another epitaxially thickened region 1 , which other epitaxially thickened region 1 comprises at least one pn-junction, two pn-junctions 2,3 in this case. The semiconductor body 11 of this example comprises a group of silicon semiconductor regions 13,14,15,16, in this case of the n-conductivity type. A p-type silicon semiconductor region 20 is positioned between the pn- junctions 2,3. Said other thickened region 1 thus comprises a bipolar transistor T2, which is defined in part by the connecting diagram of the various semiconductor regions 13,14,15,16 and 20 via the connecting conductors 30,31,32,33,34 that are located in an electrically insulating layer 40, of silicon dioxide in this case.
In this example, said other epitaxially thickened region 1 and said epitaxially thickened region have been formed simultaneously in a single epitaxial deposition process. In said epitaxially thickened region, the pn-junction(s) has (have) Ben (locally) removed by overdoping, in this case by means of an ion implantation with doping ions of the p- conductivity type, such as boron ions. A similar ion implantation has formed a p-type region 4 in this case, which is present in said other epitaxially thickened region 1 and which connects the p-type silicon semiconductor region 20 to the connecting conductors 31,33.
In this example, in which the transistor Tl comprises a field effect transistor with a gate region, the other epitaxially thickened region 1 is positioned beside or, as in this case, on either side of another gate region 5, which has been formed simultaneously with the gate region of the transistor Tl .
As already noted before, the position of the other, bipolar transistor T2 depends in part on the way in which the connecting conductors have been driven. A first possibility in this connection is that if the connecting conductors 30,34 function as a double connection for a double emitter region 13,14,13A,14A, the connections 31,33 will function as a double connection for a double base region 20,2OA via the p-type region 4. The collector of the npn-transistor T2 is in that case made up of the semiconductor regions 15, 16, which are provided with a connecting conductor (not shown). Said connecting conductor may be connected to the collector regions via a sunken n-type (in this case) semiconductor region. Another connecting possibility for the transistor T2 is provided if the connecting conductor 31 functions as an emitter connection and the connecting conductor 33 functions as a collector connection for the p-type semiconductor regions 20 and 2OA, respectively. In that case the semiconductor regions 15,16 form the base region of the lateral pnp (in this case) transistor T2.
The other gate region 5 may not be in use in the semiconductor device 10 of this example, but it may also advantageously function as a connecting region or as a control region (gate region) for the at least one pn-junction 2,3 in the other epitaxially thickened region 1. Thus, the other gate region 5 may have been used via a connecting conductor 32 for influencing the electrical field in the collector region 15,16 via the so-termed RESURF (= REduced SURface Field) effect. In the second connecting diagram of T2 as indicated above, the gate region 5 may have been used for influencing the base region or the emitter and collector regions. In this way the other bipolar transistor T2 actually forms a semiconductor component provided with four connections.
An important advantage of the semiconductor device 10 of this example is the fact that it may have been formed in a standard CMOS process (see Tl), in which only relatively few adaptations are needed in order to obtain bipolar transistors (see T2) that have relatively good characteristics. The latter means that said bipolar transistors are not as good as those obtained by using a genuine bipolar process or a bipolar (C)MOS process, to be true, but considerably better than those obtained with parasitic (bipolar) transistors that are normally present. The semiconductor device 10 of this example can be manufactured as follows by means of a method according to the invention.
Figs. 2-7 are schematic, cross-sectional views perpendicular to the thickness direction of the device of Fig. 1, showing successive stages of the manufacture of the device by means of an embodiment of the method according to the invention.
The starting point (see Fig. 2) is a p-type silicon substrate 12, on which an n- type epitaxial layer 16, in this case two n-type silicon layers 16,17, is deposited. A gate dielectric layer 18 is formed thereon, in this case by means of a thermally formed silicon dioxide. On said gate dielectric layer a gate region (not shown) for a MOS transistor Tl is formed at the location of part A of the semiconductor body 11, which gate region has the same structure and which is formed simultaneously with another gate region 5 that is formed at the location B on the semiconductor body 11. The other gate region 5 is in this case formed by means of photolithography and etching from a p-type polycrystalline silicon layer 5 A with a hard masking layer 50 of silicon dioxide present thereon, with spacers 19 being formed on either side thereof, in this case comprising an L-shaped silicon nitride region, on which an approximately rectangular silicon dioxide region is present.
At location A the source and drain regions of the MOS transistor Tl are formed by means of an ion implantation on either side of the gate region, which is identical to the other gate region 5. The other gate region 5 at location B of the semiconductor body 11 is screened by means of a masking layer (not shown) of a photoresist, for example.
Following this (see Fig. 3), another epitaxially thickened region 1 provided with two pn-junctions 2,3 on either side of the other gate region 5 and on either side of the gate region Tl is formed at location B simultaneously with the formation of an epitaxially thickened region at location A. The pn-junctions 2,3 extend (substantially) parallel to the surface of the semiconductor body 11 and are formed not only of a silicon compound used in the epitaxial deposition process but also of gaseous compounds of n-type or p-type contamination atoms such as phosphine or boron, which are supplied at the appropriate moments.
Then (see Fig. 4) the I-shaped part of the spacers 19 is removed by selective etching. The hard mask 50 is removed at the same time.
Then (see Fig. 5) and electrically insulating layer 60 is formed, which in this case, as in a number of standard CMOS processes, comprises a double layer of, for example, a 20 nm thick TEOS (=Tetra Ethyl Ortho Silicate) silicon dioxide layer 6OA and a 20 nm thick silicon nitride layer 6OB on top thereof. On said layer a masking layer 70 of a photoresist is patterned. Thus, part of the silicon nitride layer 6OB is selectively removed by etching, and subsequently an ion implantation of boron ions is carried out, forming a p-type region 4 that overdopes part of the n-type semiconductor regions 14,15,16 into p-type regions, forming as a p-type semiconductor region 10 located between the pn-junctions 2,3. Thus, the p-type region 4 extends in the form of extensions under the L-shaped silicon nitride parts of the spacers 19. On the one hand an npn- version of Tl can be structure in this manner whilst on the other hand this structure can readily make use of the other gate region 5 that can function in particular as a control region in the 4-terminal device.
It is noted that in a possible variant the extensions of the source and drain regions of the MOS transistor Tl can be formed simultaneously with this step at the location of part A of the semiconductor body 11.
Following this (see Fig. 6) the masking layer 70 is removed and a new masking layer 80 of a photoresist is patterned on the semiconductor body 11. Then another part of the silicon nitride layer 6OB is removed by selective etching, for example by means of hot phosphoric acid. Subsequently the higher doped n-type region 13 is formed by means of an ion implantation. Also with regard to this step it applies that in a possible modification an implantation that is commonly used in CMOS processes might be used for this purpose.
After removal of the mask 80 a structure is obtained (see Fig. 7) in which the action of the remaining parts 6OB of the silicon nitride layer has resulted in part of the less highly doped n-type semiconductor region 14 still being present at the surface between the highly doped n-type semiconductor region 13 and the p-type semiconductor region 20. Among other things this prevents the occurrence of a breakdown at an edge of the p-type region 20 during operation of the device 10. The various semiconductor regions are then provided in a self-aligning manner with contact regions that comprise a metal suicide. Such a suicide process is also used, simultaneously therewith, in the formation of the contact regions of the source, drain and gate regions of the MOS transistor Tl.
Then (see Fig. 1) a silicon dioxide layer 40 is applied, which is provided with openings by photolithography and etching. Following this, connecting conductors 30-34 can readily be formed, for example in the form of tungsten plugs. Said plugs are connected to the various semiconductor regions 13,20,5 A via metal suicide contact regions. After application of a separation technique, such as sawing or etching, individual devices 10 according to the invention can be obtained. The invention is not limited to the embodiment is that are shown herein, as many variations and modifications can be realized by those skilled in the art within the scope of the invention. Thus, the invention is suitable for use not only in a semi-discrete semiconductor device, but also in an integrated semiconductor device, such as a CI(C)MOS IC (=Integrated Circuit). In fact, the structure and the manufacture of the transistor as described in the examples are quite suitable for use in an IC.
It is furthermore noted that the device may comprise isolation regions such as STI (= Shallow hole Trench Isolation) isolation regions or further isolation regions obtained by LOCOS (=Local Oxidation Of Silicon) technique. Furthermore, an element such as germanium may be advantageously added to the silicon of the various semiconductor regions for improving the characteristics of the various transistors.
Many variations and modifications are possible also with regard to a method according to the invention.

Claims

CLAIMS:
1. A semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon that is provided at one location (A) with a field effect or bipolar transistor (Tl) with a semiconductor region which forms part of the transistor and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is adjacent to the surface of the semiconductor body (11), which semiconductor region is provided with an epitaxially thickened region, characterized in that the surface of the semiconductor body (11) is provided with another epitaxially thickened region (1) at a location (B) other than the location where the transistor (Tl) is present, and in that said other epitaxially thickened region (1) is provided with at least one pn-junction (2,3).
2. A semiconductor device (10) as claimed in claim 1, characterized in that said other epitaxially thickened region (1) is provided with two pn-junctions (2,3), which form part of another transistor (T2), which other transistor (T2) comprises a bipolar transistor.
3. A semiconductor device (10) as claimed in claim 1 or 2, characterized in that the epitaxially thickened region and the other epitaxially thickened region (1) have been formed simultaneously.
4. A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that the pn-junction(s) has (have) been removed from the epitaxially thickened region by overdoping.
5. A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that the epitaxially thickened region and the other epitaxially thickened region (1) comprise an implanted region (4) which overdopes said at least one pn-junction (2,3) at least locally.
6. A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that the transistor (Tl) comprises a field effect transistor provided with a gate region, and in that the other epitaxially thickened region is positioned beside or on either side of another gate region (5) that has been formed simultaneously with the gate region of the transistor (Tl).
7. A semiconductor device (10) as claimed in claim 6, characterized in that said other gate region (5) functions as a connecting region or as a control region for said at least one pn-junction (2,3) in the other epitaxially thickened region (1).
8. A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that said at least one pn-junction (2,3) extends approximately parallel to the surface of the semiconductor body (11).
9. A semiconductor device (10) as claimed in any one of the preceding claims, characterized in that the transistor (Tl) forms a MOS transistor and in that the device comprises a BiMOS or a BiCMOS IC.
10. A method of manufacturing a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon that is provided at one location with a field effect or bipolar transistor (Tl) with a semiconductor region which forms part of the transistor and which comprises a source or drain region of the field effect transistor or a base region of the bipolar transistor and which is formed adjacent to the surface of the semiconductor body
(11), which semiconductor region is provided with an epitaxially thickened region, characterized in that the surface of the semiconductor body (11) is provided with another epitaxially thickened region (1) at a location (B) other than the location where the transistor (Tl) is formed, and in that said other epitaxially thickened region (1) is provided with at least one pn-junction (2,3).
11. A method as claimed in claim 10, characterized in that said at least one pn- junction is formed in situ during the epitaxial process by means of which said other epitaxially thickened region (1) is formed.
PCT/IB2007/050210 2006-01-31 2007-01-22 Semiconductor device and method of manufacturing such a device WO2007088494A1 (en)

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