WO2007023951A1 - Substrate processing apparatus and substrate processing method - Google Patents

Substrate processing apparatus and substrate processing method Download PDF

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Publication number
WO2007023951A1
WO2007023951A1 PCT/JP2006/316747 JP2006316747W WO2007023951A1 WO 2007023951 A1 WO2007023951 A1 WO 2007023951A1 JP 2006316747 W JP2006316747 W JP 2006316747W WO 2007023951 A1 WO2007023951 A1 WO 2007023951A1
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WIPO (PCT)
Prior art keywords
substrate
film
processing
chamber
processed
Prior art date
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PCT/JP2006/316747
Other languages
French (fr)
Japanese (ja)
Inventor
Hidetada Kanemaru
Takebu Herai
Moyuru Yasuhara
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Tokyo Electron Limited
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Publication of WO2007023951A1 publication Critical patent/WO2007023951A1/en

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54—Apparatus specially adapted for continuous coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H01L21/02049—Dry cleaning only with gaseous HF
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices

Definitions

  • the present invention relates to a substrate processing apparatus and a substrate processing method for performing a predetermined process on a substrate to be processed such as a semiconductor wafer.
  • a thin film deposition process In general, in the manufacturing process of a semiconductor device, various processes such as a thin film deposition process, an oxidative diffusion process, and an annealing process are performed on a semiconductor wafer (hereinafter also simply referred to as “weno”). Etching treatment and the like are sequentially repeated. Thin films may be formed in multiple layers on a semiconductor wafer.
  • a substrate processing apparatus that performs such various processes, for example, a so-called cluster-type substrate processing system configured by commonly connecting a plurality of processing chambers to a single transfer chamber so that processing can be performed continuously. There is a device (see, for example, JP-A-2004-119635).
  • a cluster-type substrate processing system wafers are transported as if walking between processing chambers, and the necessary processing is performed continuously and efficiently in each processing chamber each time! / RU
  • the cleaned wafer is placed inside the substrate processing apparatus.
  • the film forming process is executed.
  • the natural acid film on the wafer is removed outside the substrate processing apparatus, the surface of the wafer is not removed when the wafer is taken into the substrate processing apparatus for film formation. If exposed to the atmosphere, a new natural acid film may be formed on the wafer surface. Depending on the thickness of this natural oxide film, the natural oxide film has a significant effect on the characteristics of the semiconductor device that is formed later. For example, a natural acid film with a film thickness of 0.5 nm or more on the wafer surface. When a new film is formed, it becomes a big problem when a gate insulating film with a film thickness of 65 nm or less is formed.
  • IPA isopropyl alcohol
  • JP-A-2002-166237 isopropyl alcohol
  • IPA molecules organic substances such as carbon
  • IPA molecules can adversely affect, for example, gate oxide and capsule properties (K. MOTAI, T. Itoga, and T. Me, Extended Abstruct of 1997, International Conference on SolidState Devices and Materials, Hamamatsu, pp 24-25 (1997)).
  • an object of the present invention is to include a natural oxide film on a substrate without using a water component and without using plasma. It is an object of the present invention to provide a substrate processing apparatus capable of removing a kimono and subsequently performing measurement processing and film formation processing without exposing the substrate to the atmosphere.
  • the present invention provides a plurality of processing chambers for performing a predetermined process on a substrate to be processed, and a plurality of processing chambers commonly connected to each of the plurality of processing chambers. And a common transfer chamber for carrying in and out of the substrate to be processed, and the plurality of processing chambers include deposits including a natural oxide film deposited on the substrate to be processed by plasma.
  • a deposit removal chamber for removing the gas component by chemical reaction and heat treatment, a film deposition chamber for performing a film deposition process on the substrate to be processed, and a measurement process for measuring the substrate to be processed
  • a substrate processing apparatus including a measurement processing chamber.
  • the deposit containing the natural acid film is removed by the chemical reaction with the soot gas component such as plasma and heat treatment, so that the water component is used like wet cleaning. Therefore, it is possible to prevent the occurrence of a watermark on the substrate to be processed.
  • plasma since plasma is not used, it is possible to prevent charge-up damage caused by plasma from being applied to the substrate to be processed.
  • the measurement process and film formation process can be executed continuously after the deposit removal process in the substrate processing apparatus. It is possible to prevent a natural oxide film from being newly formed on the substrate to be processed immediately before. In this way, since the deposits including the natural acid film can be reliably removed, the adhesion of the film formed on the substrate to be processed can be further improved by the next film formation process, and the strength can be improved. Can be further improved.
  • the deposit removal processing chamber includes a product generation processing chamber for generating a product by chemically reacting the deposit on the substrate to be processed with a gas component, and the product generation chamber.
  • the processing chamber is composed of two processing chambers, a product removal processing chamber for removing the product generated on the substrate to be processed by heat treatment.
  • the film forming chamber is formed in a first film forming chamber for forming a first film on the substrate to be processed and in the first film forming chamber.
  • the second film forming process chamber includes a second film forming process chamber for forming a second film on the first film.
  • the measurement processing chamber includes a film thickness measurement unit that measures a film thickness of a film formed on the substrate to be processed, and a particle measurement that measures particles on the substrate to be processed.
  • a film thickness measurement unit that measures a film thickness of a film formed on the substrate to be processed
  • a particle measurement that measures particles on the substrate to be processed.
  • a section In this case, both film thickness and particles can be measured in one measurement processing chamber, and throughput can be improved.
  • the measurement processing chamber includes an image processing unit for capturing and recognizing a surface image of the substrate to be processed.
  • pattern matching on the surface of the substrate to be processed can be performed, and for example, a measurement point on the substrate to be processed for measuring a film thickness or particles can be specified.
  • the present invention provides a plurality of processing chambers for performing predetermined processing on a substrate to be processed, a common transfer chamber commonly connected to the plurality of processing chambers, and the common transfer chamber provided in the common transfer chamber.
  • a plurality of vacuum processing apparatuses each including a transport mechanism for transporting a substrate to be processed; and a pass unit that connects the plurality of vacuum processing apparatuses to each other.
  • the plurality of processing chambers include: The deposit including the natural acid film deposited on the substrate to be processed is caused by plasma! A deposit removal treatment chamber for removal by chemical reaction and heat treatment with gas / gas components, a film formation treatment chamber for performing film formation on the substrate to be processed, and a measurement process for the substrate to be processed. And a measurement processing chamber for performing the substrate processing apparatus.
  • the deposit including the natural acid film is converted to a gas component such as plasma. Since it is removed by chemical reaction and heat treatment, water components are not used as in wet cleaning, so that it is possible to prevent the occurrence of watermarks on the substrate to be processed. In addition, since plasma is not used, it is possible to prevent charge-up damage caused by plasma from being applied to the substrate to be processed. In addition, measurement processing and film formation can be performed continuously after the deposit removal process in the substrate processing apparatus, so a natural oxide film is newly formed on the substrate to be processed immediately before the film formation process. Can be prevented. In this way, since the deposits including the natural acid film can be reliably removed, the adhesion of the film formed on the substrate to be processed can be further improved by the next film formation process, and the strength can be improved. Can be further improved.
  • a gas component such as plasma
  • the deposit removal processing chamber includes a product generation processing chamber for generating a product by chemically reacting the deposit on the substrate to be processed with a gas component, and the product generation chamber.
  • the processing chamber is composed of two processing chambers, a product removal processing chamber for removing the product generated on the substrate to be processed by heat treatment.
  • the film forming chamber is formed in a first film forming chamber for forming a first film on the substrate to be processed and the first film forming chamber.
  • the second film forming process chamber includes a second film forming process chamber for forming a second film on the first film.
  • the film forming chamber is formed in a first film forming chamber for forming a first film on the substrate to be processed and the first film forming chamber.
  • a plurality of sets of two processing chambers including a second film forming process chamber for forming a second film on the first film are included.
  • the film forming process can be executed in parallel in a plurality of film forming process chambers, so that the throughput of the entire apparatus can be greatly improved.
  • the film forming chamber is the substrate to be processed.
  • a first barrier layer film forming process chamber for forming a first barrier layer inside a contact hole or via hole formed in a processing substrate; and the first barrier film formed in the first barrier layer film forming process chamber
  • a second barrier layer deposition processing chamber for depositing the second barrier layer on the upper side of the layer.
  • the first barrier layer, the second barrier, etc. are removed after surely removing deposits such as a natural oxide film attached to the contact hole or via hole formed in the substrate to be processed.
  • a rear layer can be formed. As a result, the adhesion of these films can be further improved, and the strength can be further improved.
  • the film forming chamber has a base oxide film layer formed on the substrate to be processed by oxygen radicals.
  • a base oxide film forming process chamber for forming a film and a high dielectric for forming a high dielectric gate oxide film on a substrate on which the base oxide film layer is formed in the base oxide film forming process chamber And a body gate oxide film formation processing chamber.
  • the adhesion of these films (layers) can be further improved, and the strength can be further improved.
  • the present invention provides a deposit removing step for removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component not using plasma and heat treatment, and the deposit removal.
  • Substrate processing comprising: a measurement step for performing measurement processing of the substrate to be processed after the step; and a film forming step for performing film formation processing on the substrate to be processed after the measurement step. Is the method.
  • the deposition process is performed in a state in which deposits including the natural oxide film are reliably removed by continuously performing the deposit removal step, the measurement step, and the film deposition step. Can be broken. As a result, the adhesion of the film formed on the substrate to be processed can be further improved, and the strength can be further improved.
  • the deposit removing step includes a product generating step of generating a product by chemically reacting the deposit on the substrate to be processed with a gas component, and the product generating step. And a product removal step of removing the product generated on the substrate to be processed by heat treatment.
  • the film forming step includes a first film forming step of forming a first film on the substrate to be processed and the first film formed in the first film forming step.
  • the measurement step is a step of performing an inspection measurement process for inspecting whether or not the attached matter removing step is properly executed.
  • the measuring step further includes a film thickness measuring step for measuring a film thickness of the surface of the substrate to be processed on which the deposit removing step has been performed, and the deposit removing step on which the deposit has been removed.
  • a deposit measurement step for measuring deposits on the surface of the substrate to be processed, and the film thickness measurement step and the deposit measurement step are preferably performed in one measurement processing chamber. In this way, by measuring both the film thickness and particles (adhered matter), it is possible to reliably inspect whether the adhering material including the natural oxide film has been removed from the substrate to be processed.
  • the measurement step includes a process recipe for executing the deposit removal step based on the measurement results measured by the film thickness measurement step and the deposit measurement step. It further has a recipe correction step for correcting.
  • the deposit removal step according to the actual processing result can be executed. For this reason, the deposits including the natural acid film can be reliably removed from the substrate to be processed.
  • the measurement step determines whether or not to execute the next film formation step based on the measurement results measured by the film thickness measurement step and the deposit measurement step. It further has a judgment step of judging. In this case, for example, if the measurement results measured by the film thickness measurement step and the particle (adhered matter) measurement step are within an allowable range, it is determined that the next film forming step can be performed, while Otherwise, it may be determined that the next film forming step cannot be executed. Thus, the next film forming step can be executed in a state where the deposits including the natural oxide film on the substrate to be processed are always removed. As a result, the uniformity of the film quality of the film formed on the substrate to be processed can be ensured.
  • the measurement step includes an inspection measurement step for inspecting whether or not the deposit removal step is properly performed, and a film thickness of a base film on which the next film formation step is performed. And a base film thickness measuring step for measuring.
  • the measurement step includes a film thickness measurement step for measuring a film thickness of the surface of the substrate to be processed on which the deposit removal step has been performed, and a deposit removal step.
  • the film thickness measurement step, the deposit measurement step, and the base film thickness measurement step are executed in one measurement processing chamber.
  • the film thickness measurement for inspecting whether or not the deposit removal step has been properly executed and the film thickness measurement of the underlying film to be subjected to the next film formation process can be performed simultaneously. Processing time can be significantly reduced.
  • the present invention provides a deposit removing step for removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component not using plasma and heat treatment, A deposition step for performing a deposition process on the substrate to be processed after the deposit removing step; and a measurement step for performing a measurement process for the substrate to be processed after the deposition step.
  • This is a substrate processing method.
  • the measurement step includes a film thickness measurement step for measuring a film thickness of the film formed by the film formation step.
  • a film thickness measurement step for measuring a film thickness of the film formed by the film formation step.
  • the measurement step further includes a recipe correction step of correcting a process recipe for executing the film formation step based on the measurement result measured by the film thickness measurement step. .
  • a recipe correction step of correcting a process recipe for executing the film formation step based on the measurement result measured by the film thickness measurement step.
  • the present invention does not rely on plasma for a measurement step for measuring a substrate to be processed and a deposit including a natural oxide film deposited on the substrate to be processed after the measurement step.
  • a deposit removing step for removing the deposit by a chemical reaction with a gas component and a heat treatment; and a deposition step for performing a deposition process on the substrate to be processed after the deposit removing step.
  • This is a substrate processing method. In this way, the measurement step of the substrate to be processed may be performed before the deposit removal step.
  • the present invention provides a computer with a deposit removal step of removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component that does not depend on plasma and a heat treatment; It is a program for executing a measurement step for measuring a substrate to be processed and a film forming step for performing a film forming process on the substrate to be processed after the deposit removing step.
  • the present invention provides a computer with a deposit removal step of removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component that does not depend on plasma and a heat treatment;
  • the deposit removal step, the measurement step, and the film formation step can be continuously performed, and deposits including a natural oxide film can be reliably obtained.
  • the film forming process can be performed in the state of being removed. As a result, the adhesion of the film formed on the substrate to be treated can be further improved, and the strength can be further improved.
  • FIG. 1 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG.
  • FIG. 3 is a block diagram showing a configuration example of a control unit (system controller) shown in FIG.
  • FIG. 4 is a block diagram showing a configuration example of an EC (apparatus control unit) according to the first embodiment of the present invention.
  • FIG. 5 is a diagram showing another configuration example of the processing chamber in the substrate processing apparatus shown in FIG. 1.
  • FIG. 6 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a second embodiment of the present invention.
  • FIG. 7 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG.
  • FIG. 8 is a diagram showing another configuration example of the processing chamber in the substrate processing apparatus shown in FIG.
  • FIG. 9 is a diagram showing another configuration example of the processing chamber in the substrate processing apparatus shown in FIG.
  • FIG. 10 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a third embodiment of the present invention.
  • FIG. 11 is a block diagram showing a configuration example of the measurement processing chamber shown in FIG.
  • FIG. 12 is a block diagram showing a configuration example of an EC (apparatus control unit) according to the third embodiment of the present invention.
  • FIG. 13 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG.
  • FIG. 14 is a flowchart showing a specific example of measurement processing in the measurement processing chamber shown in FIG.
  • FIG. 1 is a schematic configuration diagram showing an example of a substrate processing apparatus according to the present embodiment.
  • this substrate processing apparatus 100 includes one common transfer chamber 102 formed in a substantially polygonal shape (for example, hexagonal shape) and a plurality of (for example, four) processing chambers configured to be evacuated.
  • 104 A to 104D the substrate processing apparatus 100 includes one common transfer chamber 102 formed in a substantially polygonal shape (for example, hexagonal shape) and a plurality of (for example, four) processing chambers configured to be evacuated.
  • the processing chambers 104A to 104D are connected to the peripheral surface of the common transfer chamber 102 via gate valves 106A to 106D, respectively.
  • each of the processing chambers 104A to 104D is provided with mounting tables 105A to 105D on which a substrate to be processed, for example, a semiconductor wafer (hereinafter also simply referred to as “wafer”) W is mounted.
  • wafer semiconductor wafer
  • Each of the processing chambers 104A to 104D can perform a predetermined process on the wafer W mounted on the mounting tables 105A to 105D, respectively.
  • the common transfer chamber 102 is connected to a substantially rectangular loading-side transfer chamber 110 via two load lock chambers 108A and 108B that are configured to be evacuated. Gate valves 107A and 107B are interposed at connecting portions between the load lock chambers 108A and 108B, the common transfer chamber 102, and the transfer-side transfer chamber 110, respectively.
  • the transfer-side transfer chamber 110 for example, three introduction ports 112A to 112C on which a cassette capable of holding a plurality of wafers W is placed and the wafer W is rotated to optically determine the amount of eccentricity for alignment.
  • the orienter 114 to perform is linked.
  • a transfer-side transfer mechanism 116 having two picks 116A and 116B for holding the wafer W and configured to bend, extend, swing, and move linearly is provided.
  • a transfer mechanism 118 having two picks 118A and 118B for holding the wafer W and configured to bend and stretch and turn is provided.
  • a control unit 200 is connected to the substrate processing apparatus 100. The control unit 200 controls each part of the substrate processing apparatus 100.
  • the transfer port 109A of the connecting portion between the common transfer chamber 102 and one of the two load lock chambers, for example, the load lock chamber 108A is configured to transfer the wafer W to the common transfer chamber. Used as a dedicated carry-in port for loading into 102, and used as a dedicated carry-out port for carrying wafer W out of the common transfer chamber 102, using the transfer port 109B at the connection between the common transfer chamber 102 and the other load lock chamber 108B. It is done.
  • the substrate processing apparatus 100 removes deposits on the wafer (for example, contamination and natural oxide film) by plasma reaction! / Chemical reaction with soot gas components and heat treatment.
  • the process and the film forming process for forming a predetermined thin film on the wafer that has been subjected to the deposit removal process are continuously executed.
  • the deposit removal process is performed without using water components and without using plasma.
  • This deposit removal processing includes, for example, a product generation process that generates a product by chemically reacting deposits including a natural acid film deposited on a wafer and a gas component, and the generation generated on the wafer. It consists of a two-stage process: a product removal process that removes products by heat treatment.
  • the product generation process is, for example, a COR (Chemical Oxide Removal) process.
  • the last treatment is, for example, a PHT (Post Heat Treatment) treatment.
  • COR processing involves deposits deposited on the wafer, such as oxide films such as natural oxide films, and ammonia (NH), for example.
  • gas molecules such as hydrogen fluoride (HF) gas
  • products mainly (N H) SiF.
  • HF hydrogen fluoride
  • wafers with COR processing are used.
  • the COR process and the PHT process correspond to the plasmaless etching process and the dry cleaning process (dry cleaning process) (COR process power without using water components and without using plasma). Because it can remove deposits such as natural acid film).
  • the selection ratio (removal rate) of the thermal acid film is high. More specifically, COR processing and PHT processing have a high thermal oxide film selectivity, but a low polysilicon selectivity. Therefore, the surface layer of the insulating film made of the SiO film, which is a thermal oxide film, and the pseudo-SiO layer having the same characteristics as the SiO film.
  • the growth time of a natural oxide film having a thickness of 3 angstroms is approximately 10 minutes, whereas COR processing and PHT processing are performed.
  • the growth time of a 3 ⁇ thick natural oxide film is approximately 2 hours or more. Therefore, in the cleaning process using the COR process and the PHT process, a new watermark is not generated, and the growth of the natural oxide film over time after the cleaning process is suppressed. Reliability can be improved.
  • the reaction proceeds in a dry environment. Specifically, water is not used for the reaction in the COR process. Even if water molecules are generated by the COR process, the water is generated in a gas state because the COR process is performed in a substantially vacuum state. Therefore, since water molecules do not adhere to the wafer in the liquid state, a watermark or the like is not generated on the wafer surface. Furthermore, since the PHT process is performed at a high temperature, no water marks or the like are generated on the wafer surface, and OH groups are not arranged on the exposed wafer surface. Therefore, since the wafer surface is not passivated and becomes hydrophilic, the wafer surface does not absorb moisture. For this reason, it is possible to prevent a decrease in wiring reliability of semiconductor devices.
  • the amount of product (complex) produced relaxes after a predetermined time. Specifically, after a predetermined time has passed, the amount of product produced will not increase even if the watermark is continuously exposed to a mixture of ammonia gas and hydrogen fluoride gas.
  • the amount of product produced is determined by gas mixture parameters such as gas pressure and volumetric flow ratio. Therefore, the amount of watermark removal can be controlled easily.
  • a barrier layer having a two-layer structure of, for example, a Ti film as a first film and a TiN film as a second film is formed inside a contact hole or via hole formed in a wafer.
  • Membrane processing is performed.
  • the extraneous matter removal process is being executed.
  • the adhesion and strength of the film can be improved.
  • the deposit removal process according to the present embodiment does not use plasma, it is possible to prevent charge-up damage caused by plasma from being applied to the underlying film of the wafer. For this reason, it is possible to perform a wiring force test without damage and to form a film having a good contact resistance.
  • the circuit configuration tends to have a multilayer wiring structure in response to the recent demand for higher density and higher integration. For this reason, an embedding technique for electrical connection between layers such as a contact hole which is a connection portion between a lower semiconductor device and an upper wiring layer and a via hole which is a connection portion between upper and lower wiring layers is important. Yes.
  • contact holes and via holes are filled with A1 (aluminum), W (tungsten), or alloys based on these.
  • a T-type film For example, a Ti film and a TiN film (for example, a TiN film) are formed.
  • TiSi is selectively grown in a self-aligned manner on the silicon diffusion layer at the bottom of the contact hole by reacting with the ground silicon substrate to obtain a good ohmic resistance.
  • the reaction gas is TiCl gas as described above.
  • a process of removing a natural oxide film formed on the base is performed prior to the film formation process.
  • a natural acid film is generally removed by dilute hydrofluoric acid, but inductively coupled plasma is formed using hydrogen gas and argon gas, and the natural acid film is removed by the plasma.
  • the Si diffusion layer surface was damaged and became non-uniformly amorphous.
  • the Ti film was formed by plasma CVD. As a result, the TiSi crystals formed become more uneven.
  • a water component is not used and plasma is used, so that it is formed on the wafer by a V-attachment removal process (for example, COR process and PHT process).
  • the Ti-based film and TiN-based film are formed after removing the natural oxide film in the contact hole or via hole.
  • a V-attachment removal process for example, COR process and PHT process.
  • the Ti-based film and TiN-based film are formed after removing the natural oxide film in the contact hole or via hole.
  • plasma-induced charge-up damage from being applied to the base before the Ti-based film and TiN-based film are formed. Therefore, even if a Ti film is formed by the plasma CVD method, a damage-free wiring force can be obtained, and a film having a good contact resistance can be formed.
  • the adhesion and strength of each of the Ti film and Ti N film can be improved.
  • the CVD-Ti film deposition process includes, for example, TiCl gas supply and gas
  • the temperature is set to 650 ° C.
  • the Ti-based film deposition process is not limited to the above.
  • an SFD (Sequential Flow Deposit ion) -Ti film forming process may be executed in which a Ti film is formed by plasma CVD at a temperature lower than 650 ° C. at 400 ° C. to 450 ° C.
  • SFD—Ti film deposition process for example, TiCl gas Of TiCl supply, Ar gas supply, H gas supply and plasma generation at the same time
  • an ALD-Ti film deposition process using an atomic layered deposition (ALD) technique may be executed.
  • the ALD-Ti film deposition process is performed, for example, by supplying only TiCl gas, then supplying Ar gas, supplying H gas, and generating plasma.
  • An ALD-Ti film may be formed by performing the process of supplying gas and generating plasma at the same time.
  • An ALD-Ti film may be formed by performing the steps described in (5).
  • the TiN film forming process as the second film forming process is, for example, as described above.
  • the substrate processing apparatus 100 removes deposits such as a natural oxide film on a wafer by using a chemical reaction and a heat treatment with a gas component that does not use a water component and does not depend on a plasma.
  • the deposit removal process to be performed and the film formation process for forming a predetermined thin film on the wafer subjected to the deposit removal process are continuously performed.
  • one of at least two processing chambers is configured as a deposit removal processing chamber, and the other is configured as a film forming processing chamber.
  • the deposit removal processing may be performed in such a manner that a plurality of steps are continuously performed.
  • the deposit removal processing chamber is constituted by a plurality of processing chambers. May be.
  • the deposit removal processing chamber is configured as the deposit removal processing chamber.
  • one processing chamber is configured as a product generation processing chamber, and the other processing chamber is configured as a product removal processing chamber.
  • the film formation chamber may be constituted by a plurality of processing chambers. Specifically, when a first film (for example, a Ti-based film) and a second film (for example, a TiN-based film) are continuously formed, two processing chambers 104A to 104D are formed. It can be configured as a membrane treatment chamber. In this case, one processing chamber is configured as a first film deposition processing chamber for depositing the first film, and the other processing chamber is configured as a second film deposition processing chamber for depositing the second film. As described above, the configuration of each of the processing chambers 104A to 104D is determined according to the contents of the deposit removal process and the film forming process performed by the substrate processing apparatus 100.
  • a wafer W in which contact holes or via holes are formed is introduced into the substrate processing apparatus 100, and the COR processing and the PHT processing as the deposit removal processing described above are continuously performed on the wafer W.
  • Fig. 2 shows a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 100 when the Ti film forming process and the TiN film forming process as the film forming process are successively executed. .
  • the processing chambers 104A, 104B, 104C, and 104D are configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, and a TiN film deposition processing chamber, respectively.
  • Processing in each of the processing chambers 104A to 104D is executed based on a process processing program 364 stored in program data storage means 360 provided in an EC (equipment control unit) 300 of the control unit 200 described later.
  • the CPU 310 of the EC300 reads a necessary processing program from the process processing program 364 and stores it in the processing data storage means 370. Necessary information is read from the stored process processing information (for example, process recipe information) 374, and each processing is executed. Details of the configuration of the control unit 200 will be described later.
  • the wafer W transfer process in the substrate processing apparatus 100 configured as shown in FIG. 2 will be described. Since the processing in the processing chambers 104A to 104D for the wafer W is performed in the order described above, the transfer path of the wafer W is as shown by the solid line arrows in FIG.
  • Such wafer transfer processing is executed based on a transfer processing program 362 stored in a program data storage means 360 (described later) provided in an EC (Equipment Control Unit) 300 of the control unit 200. That is, the CPU 310 of the EC 300 reads the necessary information from the transfer processing information (for example, transfer path information) 372 stored in the processing data storage means 370 and executes the transfer processing program 362 to execute the transfer processing of the wafer. To do.
  • a pre-process wafer W in which a contact hole or a via hole is formed is taken out from a cassette (including a carrier) installed in the central introduction port 112B.
  • a cassette including a carrier
  • one of the two load lock chambers 108A and 108B, in this case, the load lock chamber 108A is used for loading the wafer W before processing, and the other load lock chamber 108B is used for processing. Used to carry out used wafer W.
  • the wafers W are accommodated in the processing chambers 104A to 104D, respectively, and the force at which each processing is completed or almost finished.
  • the transfer process in the carry-in transfer chamber 110 will be described. If the processed wafer W that has been processed in the processing chamber 104D is accommodated in the loading load chamber 108B for unloading, the processed wafer W is transferred by the loading-side transfer mechanism 116. As shown in route XI1, the material is transported to and accommodated in the central introduction port 112B.
  • the unprocessed wafer W accommodated in the central introduction port 112B is transferred to the orienter 114 by the loading-side transfer mechanism 116 as shown in the transfer path XI2. Then, the orientation of the unprocessed wafer W is performed by the orienter 114, and then the aligned unprocessed wafer W is loaded by the loading side transfer mechanism 116 as shown in the transfer path X13. It is transported and housed in the load lock chamber 108A. The wafer W before processing waits in the load lock chamber 108A. The above transfer operation advances the processing of wafer W. Repeated every time.
  • the processed wafer W accommodated in the processing chamber 104D is taken out by the transfer mechanism 118 and transferred into the empty load lock chamber 108B as shown in the transfer path Yl1.
  • the processed wafer W accommodated in the processing chamber 104C is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104D as indicated by the transfer path Y12. Thereafter, processing in the processing chamber 104D is started.
  • the processed wafer W accommodated in the processing chamber 104B is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104C as indicated by the transfer path Y13. Thereafter, processing in the processing chamber 104C is started.
  • the processed wafer W accommodated in the processing chamber 104A is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104B as indicated by the transfer path Y14. Thereafter, processing in the processing chamber 104B is started.
  • the unprocessed UE and W that were waiting in the load lock chamber 108A are taken out by the transfer mechanism 118, and are transferred into the empty process chamber 104A as shown in the transfer path Y15. Is done. Thereafter, processing in the processing chamber 104A is started.
  • the configuration (arrangement) of the processing chambers 104A to 104D is not limited to that shown in FIG. Any of the processing chambers 104A to 104D may be configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, or a TiN film deposition processing chamber.
  • the wafers are transferred in the order of COR processing chamber ⁇ PHT processing chamber ⁇ Ti film deposition processing chamber ⁇ TiN film deposition processing chamber, so that processing chamber 104A ⁇ processing chamber 104B ⁇ processing The order of the chamber 104C ⁇ the processing chamber 104D is not necessary.
  • FIG. 3 is a block diagram illustrating a configuration example of the control unit (system controller) 200.
  • the control unit 200 includes an equipment control unit (EC Equipment Controller) 300, a plurality of module controllers (MC) 230A, 230B, 230C ..., EC300, and MC230A, 230B, 230C. And a switching hub (HUB) 220 for connecting the.
  • EC Equipment Controller equipment control unit
  • MC module controllers
  • MC module controllers
  • the EC 300 of the control unit 200 is connected to, for example, a MES (Manufacturing Execution System) 204 that manages the manufacturing process of the entire factory where the substrate processing apparatus 100 is installed, via a LAN (Local Area Network) 202. Yes.
  • the MES 204 is configured by a computer, for example. In cooperation with the control unit 200, the MES 204 feeds back real-time information on various processes in the factory to the core business system (not shown) and makes decisions on various processes in consideration of the burden of the entire factory (or the determination). Support).
  • the EC 300 constitutes a main control unit (master control unit) that controls the overall operation of the substrate processing apparatus 100 by supervising MC 230A, 230B, 230C,.
  • the switching hub 220 switches MC230A, 230B, 230C ... as the connection destination of EC300 according to the input signal of EC300 power.
  • Each of the MC230A, 230B, 230C,... Has a common transfer chamber 102 of the substrate processing apparatus 100, a processing chamber 104A to 104D, a load lock chamber 108A, 108B, a transfer chamber 110, an orienter 114, etc. Configures the sub-control unit (slave control unit) that controls the operation.
  • Each M C230A, 230B, 230C ... has a DIST (Distribution) board 234A, 234B, Each I / O (input / output) module 236A, 236B, 236, for example, via the GHOST network 206 by 234C. ⁇ ⁇ ⁇ [This is connected!
  • the GHOST network 206 is a network realized by an LSI called GHOST (General High-Speed Optimum Scalable Transceiver) installed in MC (module control unit). Up to 31 I / O modules can be connected to the GHO ST network 206.
  • MC corresponds to the master and the I / O module corresponds to the slave.
  • Each I / O module 236A, 236B, 236C ... is a plurality of IZO units connected to each component of each module (hereinafter referred to as "end device") such as the processing chambers 104A to 104D. 238A, 238 ⁇ , 238C... Power, and supply (transmit) control signals to each end device and receive (transmit) output signals from each end device.
  • end device such as the processing chambers 104A to 104D.
  • examples of the end device of the processing chamber 104 include a mass flow controller that controls the flow rate of the gas introduced into the processing chamber 104 and an APC valve that controls exhaust from the processing chamber 104.
  • Each GHOST network 206 is also connected to an IZO board (not shown) that controls input / output of digital signals, analog signals, and serial signals in the I / O units 238A, 238B, 238C,.
  • FIG. Fig. 4 is a block diagram showing a configuration example of EC300.
  • the EC300 is a RAM (Random Access Memory) with a CPU (Central Processing Unit) 310 that constitutes the EC main unit and a memory area that is used for various data processing performed by the CPU 310.
  • RAM Random Access Memory
  • CPU Central Processing Unit
  • display means 330 composed of a liquid crystal display that displays the operation screen and selection screen, etc., input of various data such as process recipe input and editing by the operator, and process recipe processing to a predetermined storage medium 'Input / output means 340 that can output various data such as log output, and notification means 350 such as an alarm device (for example, a buzzer) that notifies when an abnormality such as leakage occurs in the substrate processing apparatus 100; It is equipped with.
  • an alarm device for example, a buzzer
  • the EC 300 has a program data storage means 360 for storing processing programs for executing various processes of the substrate processing apparatus 100, and a program data storage means 360 for executing the processing programs.
  • Processing data storage means 370 in which information (data) necessary for the storage is stored.
  • the program data storage means 360 and the processing data storage means 370 are constructed in a storage area such as a node disk (HDD).
  • CPU 310, RAM 320, display means 330, input / output means 340, notification means 350, program data storage means 360, processing data storage means 370, etc. are a bus line such as a control bus or a data bus. Connected by. The nose line is also connected to the switching hub 220 and the like.
  • the CPU 310 reads necessary programs and necessary data from the program data storage means 360 and the processing data storage means 370 as necessary, and executes various processing programs.
  • each of the processing chambers 104A to 104D for example, when the wafer W is subjected to processing such as the above-described COR processing, PHT processing, Ti film forming processing, TiN film forming processing, etc.
  • the CPU 310 reads the process processing program to be executed in the program data storage means 360 and reads out the process recipe information corresponding to the processing to be executed from the process processing information 374 in the processing data storage means 370. Each process is executed based on this.
  • the CPU 310 performs a desired end device via the MC230, the GHOST network 206, and the IZO module 236 in the IZO module 236, which control the switching hub 220, the processing chambers 104A to 104D, according to each processing program. Each process is executed by transmitting a control signal to the.
  • the CPU 310 sends ammonia gas in the processing chamber 104A by transmitting a control signal to the mass flow controller of the gas introduction system in the processing chamber 104A (for example, the mass flow controller of the ammonia gas supply pipe and the hydrogen fluoride gas supply pipe).
  • the volume flow ratio of hydrogen fluoride gas and the volume flow ratio of hydrogen fluoride gas are adjusted to a desired value, while a control signal is sent to the vacuum pump (for example, ⁇ ) and pressure control valve (for example, APC valve) in the exhaust system. Is adjusted to a desired value.
  • the pressure gauge sends the pressure value in the processing chamber 104A to the CPU 310 of the EC300 as an output signal.
  • the CPU 310 determines (corrects) the mass flow controller of the ammonia gas supply pipe and the hydrogen fluoride gas supply pipe, the control parameters of the APC valve and the TMP, etc., based on the transmitted pressure value in the processing chamber 104A.
  • the CPU 310 transmits a control signal to the gas flow system mass flow controller (for example, the mass flow controller of the nitrogen gas supply pipe) and the exhaust system pressure adjustment valve (for example, the APC valve) of the processing chamber 104B. Adjust the pressure in 104B to the desired value.
  • the temperature of Ueno and W is adjusted to the desired temperature by sending a control signal to the stage heater.
  • the pressure gauge sends the pressure value in the processing chamber 104B to the CPU 310 of the EC300 as an output signal.
  • the CPU 310 determines (corrects) the control parameters of the nitrogen gas supply pipe MFC and the APC valve 69 based on the transmitted pressure value in the processing chamber 104B.
  • control unit 200 shown in Fig. 3 multiple end devices are not directly connected to EC300, so the IZO unit connected to multiple end devices is modularized to form a ⁇ module. is doing. Because it is connected to EC300 via this module power MC230 and switching knob 220, the communication system can be simplified.
  • the control signal transmitted by the CPU 310 of the EC300 includes the address of the collar connected to the desired end device and the address of the module including the collar. Therefore, the switching hub 220 can refer to the address of the input module in the control signal, and the GHOST 206 of the MC230 can also refer to the address of the I / O section in the control signal. That is, there is no need for the switching hub 220 and MC 230 to inquire the CPU 310 about the control signal transmission destination. This enables smooth transmission of control signals.
  • the substrate processing apparatus 100 before the film forming process, deposits such as a natural oxide film attached to the wafer do not use plasma.
  • deposits such as a natural oxide film attached to the wafer do not use plasma.
  • a kimono removal process for example, COR process and dredging process
  • film deposition can be performed continuously without exposing the wafer to the atmosphere, the adhesion and strength of the film can be improved.
  • the natural oxide film can be removed without using plasma, a wiring force without damage can be achieved, and a film having good contact resistance can be formed.
  • the COR process and the PHT process are effective as the previous processes in the process of forming the contact hole or via hole barrier layer.
  • the film forming process is not limited to this, and COR processing and PHT processing may be performed as a pre-process of other film forming processes as follows!
  • the gate insulating film of MOS devices has recently been required to have a thickness of less than lnm, equivalent to a silicon oxide film. This corresponds to a thickness of 3-4 atomic layers. At such a thin thickness, the silicon oxide film cannot be used due to an increase in tunneling current, diffusion of elements doped in the gate electrode, and a decrease in reliability. For this reason, the development of films with a high dielectric constant (so-called High-K films) is proceeding with great speed. That is, ZrO, HfO
  • Transition metal oxide films such as 2 2, rare earth oxide films such as La 2 O, and silicates thereof
  • composition transition layer composed of silicate is formed between these high dielectric constant films and the Si substrate, and a composition consisting of an intermediate state of Si intermediate state between the silicate layer and the Si substrate.
  • a transition layer is formed. Therefore, in order to prevent these composition transition layers from being formed, it is necessary to first form a base oxide film (for example, an SiO film) as an oxidation prevention layer. like this
  • a gate insulating film with such a high dielectric (High-K) material control at the atomic layer level is required. For this reason, before performing the film formation process of the gate insulating film, a deposit removal process (for example, a COR process and a PHT process), which is dry cleaning, is performed without using plasma to perform deposits such as a natural oxide film. By removing the film, the adhesion and strength of the film can be improved.
  • a deposit removal process for example, a COR process and a PHT process
  • a gate dielectric film (high dielectric gate dielectric film) of such a high dielectric (High-K) material it is very thin, preferably lnm on the wafer, that is, on the silicon substrate. After the base oxide film such as SiO film with the following thickness is formed first, High-K
  • a film for example, a silicate film such as HfSiO
  • the base oxide film is formed.
  • the reason corresponds to the first film forming process
  • the High-K film forming process corresponds to the second film forming process.
  • the base oxide film deposition process (first film deposition process) is performed, for example, by radical oxidation using an ultraviolet photoexcited oxygen radical.
  • a base oxide film having a film thickness equivalent to two to three molecular layers can be formed stably and with good reproducibility by the treatment of a silicon substrate with ultraviolet light-excited radical acid.
  • an oxygen atomic layer forms a SiO atom layer of, for example, about 0.5 nm as a base oxide film on the surface of the silicon substrate.
  • the processing time is, for example, 300 seconds.
  • the high-K film deposition process for example, metalorganic chemical vapor deposition (on the wafer with the base oxide film formed by the base oxide film deposition process (A metal oxide film (for example, a silicate film such as HfSiO) is formed by the MOCVD method.
  • a metal oxide film for example, a silicate film such as HfSiO
  • MOCVD method Metalorganic chemical vapor deposition
  • a source gas When a source gas is introduced onto the substrate in a heated state, the source gas is decomposed to form a thin film of a silicate film such as HfSiO on the substrate. Processing time in this case and
  • the substrate processing apparatus 100 continuously performs COR processing, PHT processing, base oxide film forming processing (UV processing), and high-K film forming processing (MOCVD processing).
  • At least two of the processing chambers 104A to 104D are configured as deposit removal processing chambers that perform COR processing and PHT processing, respectively, and the other two processing chamber forces are oxidized. It is configured as a film formation chamber that performs film formation (UV treatment) and high-K film formation (MOCVD).
  • the processing chamber 104A, 104B, 104C, and 104D forces in the substrate processing apparatus 100 are respectively COR processing chamber, PHT processing chamber, oxide film deposition processing (UV processing) chamber, and High-K film deposition.
  • Figure 5 shows an example of a process (MOCVD process) chamber.
  • the EC (equipment control unit) 300 program of the control unit 200 described above respectively. It is executed based on the process processing program 364 stored in the data storage means 360.
  • the CPU 310 of the EC300 reads out the necessary processing program from the process processing program 364 and reads out the necessary information from the process processing information (for example, process recipe information) 374 stored in the processing data storage means 370 to perform each processing. Execute.
  • FIG. 6 is a schematic configuration diagram of a substrate processing apparatus according to the second embodiment. Shown in Figure 6 As described above, in the substrate processing apparatus 101, a plurality of vacuum processing apparatuses having a plurality of processing chambers and a common transfer chamber are connected. The present invention can also be applied to the substrate processing apparatus 101 having such a configuration.
  • the common transfer chamber in the substrate processing apparatus 100 shown in FIG. 1 is represented as the first common transfer chamber 102.
  • Another second common transfer chamber 120 is interposed between the first common transfer chamber 102 and the two load port chambers 108A and 108B.
  • the second common transfer chamber 120 has a substantially polygonal shape (eg, an irregular heptagon), and two processing chambers 104E and 104F are connected to the two sides via gate valves 106E and 106F, respectively.
  • the vacuum processing apparatus having the first common transfer chamber 102 and the four processing chambers (process chambers 104A to 104D) connected to the first common transfer chamber 102 is an example of the first vacuum processing apparatus.
  • the two processing chambers (processing chambers 104E and 104F) connected thereto are examples of the second vacuum processing apparatus.
  • a pass section 122 that allows the two common transfer chambers 102 and 120 to communicate with each other and to temporarily hold the wafer W.
  • the wafer W is temporarily held by the pass portion 122.
  • the shape of the first common transfer chamber 102 is formed into an irregular heptagon in order to connect the path portion 122.
  • a gate valve 126 is provided at the junction between the first common transfer chamber 102 and the pass portion 122. By opening and closing the gate valve 126, communication between the common transfer chambers 102 and 120 can be established and shut off.
  • the processing chamber 104E and the processing chamber 104F as with the other processing chambers 104A to 104D, mounting tables 105E and 105F for holding the wafer W are provided.
  • the second common transfer chamber 120 similarly to the first common transfer chamber 102, a transfer mechanism 124 having two picks 124A and 124B that can be bent and stretched is provided.
  • the transfer mechanism 124 of the second common transfer chamber 120 can efficiently transfer the wafer by the same operation as the transfer mechanism 118 of the first common transfer chamber 102.
  • the transfer port 152A at the connecting portion between the second common transfer chamber 120 and one of the two load lock chambers, for example, the load lock chamber 108A, allows the wafer W to pass through the second common transfer chamber 120.
  • the transfer port 152B at the connection between the second common transfer chamber 120 and the other load lock chamber 108B is used as a dedicated transfer port for transferring the wafer W out of the second common transfer chamber 120. Used as
  • the substrate processing apparatus 101 also removes deposits such as a natural oxide film on the wafer by using a chemical reaction with a gas component such as water and a heat treatment without using a water component.
  • a gas component such as water and a heat treatment without using a water component.
  • the kimono removal process and the film forming process for forming a predetermined thin film on the wafer that has been subjected to the deposit removal process are continuously executed! / Speak.
  • At least one of the two processing chambers is configured as a deposit removal processing chamber, and the other is configured as a film forming processing chamber.
  • the deposit removal processing may be performed in such a manner that a plurality of steps are continuously performed.
  • the deposit removal processing chamber is constituted by a plurality of processing chambers. May be.
  • Two processing chambers may be configured as the deposit removal processing chamber.
  • one processing chamber is configured as a product generation processing chamber, and the other processing chamber is configured as a product removal processing chamber.
  • the film formation chamber may be constituted by a plurality of processing chambers. Specifically, when a first film (for example, a Ti-based film) and a second film (for example, a TiN-based film) are continuously formed, two processing chambers 104A to 104F are formed. It can be configured as a membrane treatment chamber. In this case, one processing chamber is configured as a first film deposition processing chamber for depositing the first film, and the other processing chamber is configured as a second film deposition processing chamber for depositing the second film. As described above, the configuration of each of the processing chambers 104A to 104F is determined according to the contents of the deposit removal process and the film forming process performed by the substrate processing apparatus 101.
  • a wafer W in which contact holes or via holes are formed is introduced into the substrate processing apparatus 101, and the wafer W is subjected to the above-described deposit removal processing.
  • Example of configuration of processing chamber in substrate processing apparatus 101 when Ti film forming process and TiN film forming process as film forming process are executed continuously after COR process and PHT process are executed ( Figure 7 shows an arrangement example.
  • the processing chambers 104A, 104B, 104C, and 104D are configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, and a TiN film deposition processing chamber, respectively.
  • a pre-process wafer W in which a contact hole or a via hole is formed is taken out from a cassette (including a carrier) installed in the central introduction port 112B.
  • a cassette including a carrier
  • one of the two load lock chambers 108A and 108B, in this case, the load lock chamber 108A is used for loading the wafer W before processing, and the other load lock chamber 108B is used for processing. Used to carry out used wafer W.
  • the wafers W are accommodated in the processing chambers 104A to 104D, respectively, and the force at which each processing is completed or almost finished.
  • the transfer processing of the wafer W in the transfer-side transfer chamber 110 shown in FIG. 7 is the same as the case shown in FIG. Therefore, detailed description thereof is omitted.
  • the transfer paths X21 to X23 shown in FIG. 7 correspond to the transfer paths XI1 to X13 shown in FIG.
  • the transfer process of the wafer W in the first common transfer chamber 102 is almost the same as the case shown in FIG. 2, but the transfer process in the first common transfer chamber 102 in FIG. W is conveyed to and from the pass unit 122. This is different from the case of FIG. 2 in which the wafer W is transferred between the load lock chambers 108A and 108B.
  • the transport paths Y21 to Y25 shown in FIG. 7 correspond to the transport paths ⁇ 11 to ⁇ 15 shown in FIG.
  • the wafer W is also transferred to the pass section 122 by the processing chamber 104D
  • the transfer path ⁇ 25 the wafer W is transferred from the pass section 122 to the process chamber 104A.
  • the wafer W before processing in which the contact hole or via hole is formed in this way is processed in COR chamber, PHT processing, Ti film deposition processing, TiN film in the processing chamber 104A to processing chamber 104D, respectively.
  • the film forming process is continuously performed.
  • the processing chamber 104A to the processing chamber 104D connected to the first common transfer chamber 102 are respectively connected to the COR processing chamber and the PHT processing chamber.
  • Ti film deposition chamber, and TiN film deposition chamber, the processing chambers 104E and 104F connected to the second common transfer chamber 120 are the processing chambers that perform other processing on the wafer. Can be configured.
  • the processing chamber 104E or the processing chamber 104F can be configured as a metal-based film deposition chamber for depositing a tungsten film or the like to be embedded in a contact hole or a via hole.
  • the wafer W processed by the processing chamber 104A to the processing chamber 104D is transferred to the processing chamber 104E or 104F, and the tungsten film is formed on the Ti film and TiN film barrier layer formed on the wafer W. Can be formed.
  • the plasmaless cleaning process in the contact hole or via hole, the Ti layer and TiN film deposition process, and the tungsten film filling process can be performed in succession.
  • the configuration (arrangement) of the processing chamber of the substrate processing apparatus 101 is not limited to the above.
  • the base oxide film forming process (UV process) and the high-K film forming process (MOCVD process) are performed as the film forming process, as shown in FIG.
  • Each may be configured as a base oxide film deposition process (UV process) chamber and a high-K film deposition process (MOCVD process) chamber. Since the transport process in this case is the same as that shown in FIG. 7, a detailed description thereof will be omitted.
  • the processing chamber 104A to the processing chamber 104D connected to the first common transfer chamber 102 are configured as film formation processing chambers, and the processing chambers 104E and 104F connected to the second common transfer chamber 120 are removed from the deposits. It may be configured as a post-processing chamber (for example, a COR processing chamber and a PHT processing chamber). In this case, for example, as shown in FIG. 9, the processing chambers 104A to 104D connected to the first common transfer chamber 102 may be configured as two systems of film forming processing chambers.
  • the processing chambers 104A and 104B connected to the first common transfer chamber 102 are connected to the first system, that is, the first ITi film deposition processing chamber and the first ITiN film.
  • the film forming chamber is configured, and the processing chambers 104C and 104D are configured as the second system, that is, the second Ti film forming chamber and the second TiN film forming chamber.
  • the film forming process may be executed using the same process recipe, or the film forming process may be executed using process recipes having different gas flow rates and pressures, for example. Good.
  • the processing chamber 104E and the processing chamber 104F connected to the second common transfer chamber 120 are configured as a COR processing chamber and a PHT processing chamber, respectively.
  • the transfer process of the substrate processing apparatus 101 configured as shown in FIG. 9 will be described.
  • the wafers W are processed in the order of the processing chambers 104E and 104F and accommodated in the pass unit 122.
  • the wafer W is transferred from the pass section 122 to the processing chambers 104A and 104B in that order and processed (first system).
  • the wafer W can be transferred from the pass section 122 to the processing chambers 104C and 104D in that order and processed (second system).
  • the processing power of these two systems can be selectively executed. These two systems may be executed in parallel, or only one of them may be executed continuously.
  • the transfer processing of the wafer W in the transfer-side transfer chamber 110 shown in FIG. 9 is the same as that shown in FIG. Therefore, detailed description thereof is omitted.
  • the transfer routes X31 to X33 shown in FIG. 9 correspond to the transfer routes XI1 to X13 shown in FIG.
  • the transfer mechanism 124 has already processed the wafer W in the process chamber 104B or the process chamber 104D accommodated in the pass unit 122. Wafer W is taken out and transferred into an empty load lock chamber 108B as shown in transfer path Z31. Next, the wafer W that has been processed in the processing chamber 104F is taken out by the transfer mechanism 124, and is transferred into the empty path unit 122 as indicated by the transfer path Z32. Subsequently, the processed weno and W are taken out in the processing chamber 104E by the transfer mechanism 124, and are transferred into the empty processing chamber 104F as shown in the transfer path Z33. Thereafter, processing in the processing chamber 104F is started.
  • the unprocessed wafer W waiting in the load lock chamber 108A is taken out by the transfer mechanism 124 and transferred into the empty process chamber 104E as indicated by the transfer path Z34. Thereafter, processing in the processing chamber 104E is started.
  • the processed wafer W accommodated in the processing chamber 104B is taken out by the transfer mechanism 118 and transferred to the transfer path Ya31. As shown in FIG.
  • the processed wafer W accommodated in the processing chamber 104A is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104B as indicated by the transfer path Ya32. Thereafter, processing in the processing chamber 104B is started.
  • the wafer W transferred from the second common transfer chamber 120 into the pass unit 122 is transferred to the transfer mechanism 1.
  • processing in the processing chamber 104A is started.
  • the processed wafer W accommodated in the processing chamber 104D is taken out by the transfer mechanism 118 and transferred to the transfer path.
  • the sheet is transported to an empty path unit 122.
  • the processed wafer W accommodated in the processing chamber 104C is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104D as indicated by the transfer path Yb32. Thereafter, processing in the processing chamber 104D is started.
  • the wafer W transferred from the second common transfer chamber 120 into the pass unit 122 is transferred to the transfer mechanism 1.
  • processing chambers 104A and 104B processing chambers 104A and 104B, processing chambers 104C and 104D
  • the COR process, the PHT process, the Ti film forming process, and the TiN film forming process are successively performed on the unprocessed wafer W on which the contact holes or via holes are formed.
  • the processing chamber 104A to the processing chamber 104D connected to the first common transfer chamber 102 are divided into two systems of Ti film deposition processing chamber and TiN film. Since it is configured as a film formation chamber, the throughput of the entire system can be greatly improved by executing these two systems in parallel. Because the deposition process (Ti film deposition process, TiN film deposition process) is usually more time consuming than the deposit removal process (COR process, PHT process here), If the cleaning process such as the COR process and PHT process is completed while the film forming process is being performed in the processing chamber of one system, the film forming process can be performed immediately in the processing system of the other system. It is.
  • the film forming chamber is concentrated on the side of the second common transfer chamber 120 (second vacuum processing apparatus), it can be easily distinguished from the processing chamber of the first common transfer chamber. Yes, that is, the efficiency in cleaning each film forming chamber and the second common transfer chamber 120 is high.
  • each vacuum processing apparatus can be cleaned, which is efficient.
  • FIG. 10 is a schematic configuration diagram showing an example of a substrate processing apparatus according to the third embodiment.
  • a measurement processing chamber 400 capable of measuring the film thickness of the wafer W and measuring particles (including the above deposits) is attached to the substrate processing apparatus 101 shown in FIG. Is.
  • the measurement processing chamber 400 may be attached to any position of the sides of the first common transfer chamber 102 and the second common transfer chamber 120 as long as they are vacant. In the configuration example shown in FIG. 10, the measurement processing chamber 400 is attached to the first common transfer chamber 102.
  • the measurement processing chamber 400 is controlled by an EC (equipment control unit) 300 of the control unit 200 shown in FIG.
  • an MC (module control unit) that controls the measurement processing chamber 400 is connected via the EC 300 and the switching hub 220 of the control unit 200 shown in FIG.
  • Each part of the measurement processing chamber 400 is connected to, for example, an IZO module 236K connected to the MC via a DISTC board.
  • the measurement processing chamber 400 includes a stage (turn table) 405 for placing and holding the wafer W, and a motor 407 for rotating the stage 405.
  • the motor 407 is driven based on a drive signal from a motor drive unit 408 configured by, for example, a motor drive.
  • the motor drive unit 408 is connected to the EC 300 via, for example, the I / O module 236 and the MC, and is controlled by a control signal from the MC or EC 300.
  • the measurement processing chamber 400 of the present embodiment includes a film thickness measurement unit 410 for measuring the film thickness of a thin film or the like formed on the wafer W, and pattern recognition by capturing a surface image of the wafer W.
  • An image processing unit 420 for performing measurement and a particle measurement unit 430 for measuring particles on the wafer W are provided.
  • the film thickness measurement unit 410 includes, for example, a light source 414 that emits laser light toward the wafer W, a light receiving unit 416 that receives light emitted from the light source 414 and reflected by the wafer W, and a light receiving unit 416. And a signal processing unit 412 for processing the received light signal.
  • the signal processing unit 412 is connected to the EC 300 via, for example, an I / O module 236. As a result, the EC 300 can receive data relating to the film thickness on the wafer W (eg, film thickness data, film thickness evaluation data, etc.) via the signal processing unit 412.
  • the film thickness measurement unit 410 measures the film thickness using the laser light from the light source 414, for example, by spectroscopic ellipsometry.
  • the spectroscopic ellipso method is an amount in which the amount of change in polarization (amplitude and phase difference) between the incident light of the laser beam and the reflected light from the wafer is proportional to the film thickness X optical constant. Based on the above, the film thickness is measured.
  • the image processing unit 420 includes an image sensor 424 such as a CCD (Charge Coupled Devices) that captures a surface image of the wafer W, and a signal processing unit 422 that processes an image signal from the image sensor 424. is doing.
  • the signal processing unit 422 is connected to the EC300 via the IZO module 236K. As a result, the EC 300 can receive the data related to the surface image of the wafer W via the signal processing unit 422.
  • the particle measuring unit 430 includes, for example, a light source 434 that emits laser light toward the wafer W, a light receiving unit 436 that receives scattered light emitted from the light source 434 and scattered on the wafer W, and a light receiving unit 436. And a signal processing unit 432 for processing the received light signal received at.
  • the signal processing unit 432 is connected to the EC 300 via a module 236. As a result, the EC 300 can receive data (for example, pixel data, particle evaluation data, etc.) regarding particles on the wafer W via the signal processing unit 432.
  • FIG. 12 is a block diagram illustrating a configuration example of the EC 300 according to the third embodiment.
  • the measurement processing program 460 of the measurement processing chamber 400 is added to the program data storage means 360 shown in FIG. 4, and the measurement processing information 470 is added to the processing data storage means 370.
  • the film thickness measurement unit 410, the image processing unit 420, and the particle measurement unit 430 are each configured as an optical system unit, and each optical system unit is configured to be movable in the radial direction of the wafer W. Yes.
  • the entire wafer surface can be measured by moving each optical system unit to the central force end of the wafer W while holding and rotating the wafer W on the stage 405.
  • the moving distance (scanning distance) of the optical system unit can be shortened, and the measurement processing chamber 400 can be saved in space. In other words, the measurement processing chamber 400 itself can be reduced in size.
  • the film thickness measurement unit 410, the image processing unit 420, and the particle measurement unit 430 may be configured as a single movable optical system unit.
  • the film thickness measurement unit 410 and the particle measurement unit 430 may be configured as a single movable optical system unit, and the image processing unit 420 may be fixed.
  • the measurement processing program 460 controls each part of the measurement processing chamber 400, such as the film thickness measurement program 462, the image processing program 464, the particle measurement program 466, and the stage drive program 468, and performs the measurement processing. Various programs for evaluating the measurement results are included.
  • the measurement processing information 470 includes film thickness evaluation information 472, particle evaluation information 474, and measurement condition recipe 476.
  • the stage drive program 468 is a program that controls the motor 407 of the stage 405 to control the rotation timing, rotation speed, rotation speed, and the like of the wafer W.
  • the film thickness measurement program 462 controls each part of the film thickness measurement unit 410 based on the measurement condition recipe 476 to execute the film thickness measurement of Weno and W, and based on the measurement result, the film thickness measurement program 462 An evaluation is performed. Specifically, for example, by moving the film thickness measurement unit 410 while rotating the wafer W, irradiating the wafer W with the laser light from the light source 414 and receiving the light reflected by the wafer W, The film thickness of the wafer W is measured.
  • film thickness measurement unit 410 is moved, and a laser beam with a light source of 414 is irradiated toward the measurement point of the wafer W to measure the film thickness of the wafer W. I do. If there are multiple measurement points for Ueno and W, irradiate each measurement point with laser light and measure the film thickness at each measurement point. Thus, for example, film thickness data can be obtained as a measurement result. Based on this film thickness data, for example, film thickness evaluation data for evaluating whether a target film thickness has been formed! / Is obtained and stored as film thickness evaluation information 472.
  • the image processing program 464 controls each part of the image processing unit 420 based on the measurement condition recipe 476, captures the surface image of the wafer W by the image sensor 424, and recognizes the pattern based on the imaging result.
  • the image processing such as is performed. For example, by performing pattern recognition processing based on the surface image of the wafer W, it is possible to specify a measurement point that is a target for film thickness measurement or particle measurement of the wafer W using pattern matching.
  • the particle measurement program 466 is based on the measurement condition recipe 476 and controls each part of the particle measurement unit 430 to execute the particle measurement on the surface of the wafer W and based on the measurement result.
  • Particle evaluation is performed. Specifically, for example For example, by moving the particle measuring unit 430 while rotating the wafer W and irradiating the wafer W with the laser light from the light source 434 and receiving the scattered light, the partial measurement of the wafer W is performed.
  • a measurement result for example, pixel data associated with the presence or absence of particles is obtained.
  • particle evaluation data consisting of binary data corresponding to whether or not the pixel data with a partition exceeds the set value is created. Memorized.
  • the substrate processing apparatus 103 also removes deposits such as a natural oxide film on the wafer by using a chemical reaction with a gas component such as a plasma without using a water component and a heat treatment.
  • the kimono removal process and the film forming process for forming a predetermined thin film on the wafer that has been subjected to the deposit removal process are continuously executed! / Speak.
  • a wafer W on which contact holes or via holes are formed is introduced into the substrate processing apparatus 103, and the COR processing and the PHT processing as the deposit removal processing described above are continuously performed on the wafer W.
  • Fig. 13 shows a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 103 when the Ti film forming process and the TiN film forming process as the film forming process are successively executed. .
  • the processing chambers 104A, 104B, 104C, and 104D forces connected to the first common transfer chamber 102 are respectively COR processing chamber, PHT processing chamber, Ti film deposition processing chamber, and TiN film. It is configured as a film formation chamber.
  • the wafer W transfer process in the substrate processing apparatus 103 configured as shown in FIG. 13 will be described. Since the processing in the processing chambers 104A to 104D for the wafer W is performed in the order described above, the transfer path of the wafer W is as shown by a solid arrow in FIG.
  • a pre-process wafer W in which a contact hole or a via hole is formed is taken out from a cassette (including a carrier) installed in the central introduction port 112B.
  • a cassette including a carrier
  • One of the two load lock chambers 108A and 108B The other load lock chamber, here the load lock chamber 108A, is used for loading the unprocessed wafer W, and the other load lock chamber 108B is used for unloading the processed wafer.
  • the wafer W that has undergone COR processing and PHT processing is subjected to film thickness measurement and particle measurement in the measurement processing chamber 400, and then the next film formation processing (Ti film formation processing and TiN film formation). (Membrane processing).
  • the wafers W are accommodated in the processing chambers 104A to 104D and the measurement processing chamber 400, respectively, and the force at which each processing is finished or almost finished.
  • the transfer processing of the wafer W in the loading-side transfer chamber 110 and the transfer processing of the wafer W in the second common transfer chamber 120 shown in FIG. 13 are the same as those shown in FIG. Therefore, the detailed explanation is omitted.
  • the transport paths X41 to X43, Z41, and Z42 shown in FIG. 13 correspond to the transport paths X21 to X23, Z21, and Z22 shown in FIG. 7, respectively.
  • the transfer process of the wafer W in the first common transfer chamber 102 will be described.
  • the wafer W is stored in the processing chamber 104D by the transfer mechanism 118, and the processed wafer W is taken out and transferred into the empty path unit 122 as indicated by the transfer path Y41.
  • the processed wafer W accommodated in the processing chamber 104C is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104D as indicated by the transfer path Y42. Thereafter, processing in the processing chamber 104D is started.
  • the wafer W that has been subjected to the measurement processing and stored in the measurement processing chamber 400 is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104C as indicated by the transfer path Y43. Thereafter, processing in the processing chamber 104C is started.
  • the processed wafer W accommodated in the processing chamber 104B is taken out by the transfer mechanism 118, and is loaded into the empty measurement processing chamber 400 as indicated by the transfer path Y44. Thereafter, measurement processing in the measurement processing chamber 400 is started.
  • the processed wafer W accommodated in the processing chamber 104A is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104B as indicated by the transfer path Y45. Thereafter, processing in the processing chamber 104B is started.
  • processing chamber 104A, 104B, 3 ⁇ 4 processing chamber 400, processing chamber 104C, 104D [trowel, respectively] COR processing, PHT processing, measurement processing, Ti film deposition processing, and TiN film deposition processing are performed in succession.
  • deposits such as a natural oxide film are removed from the inner wall and bottom of the contact hole or via hole of the wafer W by COR processing and PHT processing. Then, in the measurement processing chamber 400, film thickness measurement and particle measurement are performed, and it is confirmed whether or not deposits such as natural acid film have been (sufficiently) removed. Then, a barrier layer composed of a Ti film and a TiN film is formed by the following Ti film formation process and TiN film formation process. As a result, the noria layer can be formed in a state where the deposits such as the natural oxide film are reliably removed from the wafer W.
  • the measurement processing is performed in the measurement processing chamber 400 continuously after the deposit removal processing (COR processing and PHT processing). Therefore, whether or not the wafer deposit removal process has been properly executed can be reliably inspected by measuring the film thickness and particles (including deposits) of the wafer W concerned. Also, it is possible to expose the wafer to the atmosphere immediately after applying the deposit removal treatment to the wafer. Therefore, the measurement process can be performed continuously in the measurement processing chamber 400, so that the surface on which the deposits on the wafer have been removed (for example, the exposed surface such as the bottom of a contact hole formed on the wafer) is again applied. Inspection can be performed by measuring the film thickness on the wafer and performing the partial measurement without adhering to the natural oxide film. As a result, the effect of the deposit removal treatment can be accurately and reliably inspected.
  • the process recipe (process conditions for the deposit removal process) of the deposit removal process (COR process and PHT process) is corrected based on the measurement results of the film thickness measurement and particle measurement of the wafer W. You may do it. In this way, the deposit removal process (COR process and PHT process) can always be performed properly. As a result, the deposit removal process according to the actual processing result can be executed, so that deposits including the natural oxide film can be reliably removed from the wafer W.
  • the next film formation process (film formation step) is determined.
  • the next film forming process can be performed. It may be determined that execution is impossible.
  • the next film forming process can be executed in a state where the deposits including the natural oxide film on the wafer W are always removed. Therefore, the film quality of the film formed on the wafer W is uniform. Sex can be secured.
  • the measurement processing in the measurement processing chamber 400 performed after the deposit removal processing includes the following in addition to the measurement for checking whether or not the deposit removal processing as described above is properly performed.
  • the film thickness measurement of the base film on which the film forming process is performed may be included.
  • the film thickness on the surface of the wafer subjected to the deposit removal process (for example, the exposed surface of the bottom of the contact hole formed on the wafer) is measured, and the following While film thickness measurement is performed on a base film (for example, a base film formed on a wafer) on which film formation processing is performed, adhesion measurement on the surface on which the deposit removal process has been performed is also performed.
  • the film thickness measurement for inspecting whether the deposit removal process has been properly executed and the film thickness measurement of the base film to be subjected to the next film formation process are simultaneously executed.
  • the time required for the measurement process can be significantly reduced.
  • the measurement process in the measurement process chamber 400 may be performed after the film formation process.
  • the film thickness of the film formed by the film forming process can be measured.
  • the process recipe (process conditions for the film formation process) for executing the film formation process can be corrected.
  • the measurement process in the measurement process chamber 400 may be performed before the deposit removal process.
  • FIG. 14 is a flowchart illustrating an example of the measurement process.
  • a measurement condition recipe is set in step S110.
  • conditions such as the rotational speed of the stage 405 and the measurement range are set.
  • step S120 the wafer W is loaded into the measurement processing chamber 400, and in step S130, film thickness measurement and particle measurement are performed.
  • the wafer is aligned by, for example, notch detection, and the surface image of the wafer W is captured by the image processing unit 420 as necessary to perform pattern recognition. .
  • film thickness measurement and particle measurement are performed on a measurement point (or measurement range) obtained by pattern recognition.
  • the particle measurement unit 430 measures the particle on the surface of the wafer W while rotating the wafer W. Is done.
  • step S140 each evaluation data is created based on the measurement results of the film thickness measurement and the particle measurement.
  • step S150 the obtained measurement results and evaluation data are transmitted to EC 300 of control unit 200. Thereafter, in step S140, the wafer W is unloaded.
  • film thickness measurement and particle measurement can be performed immediately without changing the wafer state by, for example, forming a natural acid film on the wafer w.
  • film thickness measurement and particle measurement can be performed immediately after the COR process and the PHT process without exposing the wafer W to the atmosphere.
  • the next film forming process can be executed without, for example, a natural oxide film adhering to the wafer W.
  • the measurement processing chamber 400 is configured as one module (unit) of the substrate processing apparatus.
  • the measurement processing chamber 400 can be easily attached to an existing substrate processing apparatus.
  • the measurement processing can be executed simply by loading the wafer W into the measurement processing chamber 400. In other words, the time and labor required for film thickness measurement and particle measurement can be greatly reduced compared to the case where the measurement processing chamber is configured as a separate device.
  • the footprint is greatly increased compared to installing two devices so that each measurement can be performed in another device. Can be reduced. Further, since the measurement processing chamber 400 itself can be made compact, the footprint can be further reduced.
  • FIG. 13 shows the case where the natural oxide film is removed by performing the measurement process in the measurement processing chamber 400 after the COR process and the PHT process.
  • the present invention is not necessarily limited to this. Even after the film forming process (Ti film forming process, TiN film forming process), a measurement process is performed in the measurement processing chamber 400 to check whether or not a desired film thickness is formed. Good.
  • the measurement processing in the measurement processing chamber 400 may perform both the film thickness measurement and the particle measurement, or only V deviation.
  • the configuration of the processing chamber of the substrate processing apparatus 103 is not limited to that shown in FIG.
  • the processing chambers 104C and 104D are respectively formed in the base oxide film formation processing.
  • UV processing UV processing
  • MOCVD processing High-K film deposition processing
  • the transport process in this case is the same as that shown in FIG.
  • the mounting position of the measurement processing chamber 400 is not limited to the case shown in FIG.
  • a portion of the first common transfer chamber 102 and the second common transfer chamber 120 where the processing chamber can be attached can be installed anywhere.
  • the measurement processing chamber 400 is attached to a substrate processing apparatus of a type in which a plurality of common transfer chambers are connected as shown in FIG. 6, for example. I can't.
  • it may be attached to a substrate processing apparatus of a type having a single common transfer chamber as shown in FIG.
  • the common transfer chamber 102 is formed in a polygon of a heptagon or more so that the measurement processing chamber 400 can be mounted in addition to the processing chambers 104A to 104D. It is out.
  • the present invention may be applied to a system constituted by a plurality of equipment units, or may be applied to an apparatus that has the power of only one equipment.
  • a medium such as a storage medium storing software programs for realizing the various functions of the above embodiments is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus is supplied.
  • the computer CPU or MPU
  • the various functions of the above-described embodiments can be realized (achieved).
  • Examples of media such as storage media for supplying programs include flexible (floppy) disks, hard disks, optical disks, magneto-optical disks, CD-ROMs, CD-Rs, CD-RWs, DVD-ROMs, You can use DVD-RAM, DVD-RW, DVD + RW, magnetic tape, non-volatile memory card, ROM, or network download!

Abstract

A substrate processing apparatus is provided with a plurality of process chambers for performing prescribed processing to a substrate to be processed, and a common transfer chamber (102) which is commonly connected to the process chambers and carries in and out the substrates to and from the process chambers, respectively. The process chambers include adhered material removing process chambers (104A, 104B) for removing an adhered material including a native oxide adhered on the substrate by chemical reaction with a gas component not using plasma and heat treatment; film forming process chambers (104C, 104D) for forming a film on the substrate; and a measuring process chamber (400) for measuring the substrate.

Description

明 細 書  Specification
基板処理装置及び基板処理方法  Substrate processing apparatus and substrate processing method
技術分野  Technical field
[0001] 本発明は、半導体ウェハなどの被処理基板に所定の処理を施す基板処理装置及 び基板処理方法に関する。  The present invention relates to a substrate processing apparatus and a substrate processing method for performing a predetermined process on a substrate to be processed such as a semiconductor wafer.
背景技術  Background art
[0002] 一般に，半導体デバイスの製造工程においては，半導体ウェハ（以下，単に「ゥェ ノ、」とも称する。）に対して各種の処理、例えば薄膜の成膜処理，酸化拡散処理，ァ ニール処理，エッチング処理等が順次繰り返して施される。薄膜に関しては，半導体 ウェハ上に多層に形成される場合がある。このような各種の処理を行う基板処理装置 として，例えば連続して処理を行うことができるように複数の処理室を 1つの搬送室に 共通に連結して構成された，いわゆるクラスタ型の基板処理装置がある（例えば特開 2004— 119635号公報参照）。クラスタ型の基板処理装置では，ウェハを各処理室 間にいわば渡り歩くようにして搬送しつつ，その都度必要な処理が各処理室にて連 続的且つ効率的に行われるようになって!/、る。  In general, in the manufacturing process of a semiconductor device, various processes such as a thin film deposition process, an oxidative diffusion process, and an annealing process are performed on a semiconductor wafer (hereinafter also simply referred to as “weno”). Etching treatment and the like are sequentially repeated. Thin films may be formed in multiple layers on a semiconductor wafer. As a substrate processing apparatus that performs such various processes, for example, a so-called cluster-type substrate processing system configured by commonly connecting a plurality of processing chambers to a single transfer chamber so that processing can be performed continuously. There is a device (see, for example, JP-A-2004-119635). In a cluster-type substrate processing system, wafers are transported as if walking between processing chambers, and the necessary processing is performed continuously and efficiently in each processing chamber each time! / RU
[0003] ところで，ウェハ上には，パーティクル，金属，有機物，吸着分子等の表面被膜等 のコンタミネーシヨン、自然酸化膜（Silicon Native Oxide)などが付着する。従って，成 膜処理などを実行する前に，このような自然酸ィ匕膜などの付着物を除去することが必 要となる。  [0003] By the way, contamination such as surface coatings such as particles, metals, organic substances, adsorbed molecules, and natural oxide films (Silicon Native Oxide) adhere to the wafer. Therefore, it is necessary to remove such deposits such as a natural acid film before the film formation process is performed.
[0004] このため，従来は，例えば基板処理装置外で希フッ酸 (DHF)等を利用したウエット 洗浄によってウェハ上の自然酸化膜を除去した上で，当該洗浄されたウェハを基板 処理装置内に取込んで成膜処理を実行している。  For this reason, conventionally, after removing the natural oxide film on the wafer by wet cleaning using, for example, dilute hydrofluoric acid (DHF) outside the substrate processing apparatus, the cleaned wafer is placed inside the substrate processing apparatus. The film forming process is executed.
[0005] し力しながら，基板処理装置外でウェハ上の自然酸ィ匕膜が除去されたとしても，成 膜処理などを施すためにウェハを基板処理装置内に取込むときにウェハ表面が大 気に露出されれば，ウェハ表面に新たに自然酸ィ匕膜が生成されてしまう虞がある。こ の自然酸化膜の膜厚によっては，当該自然酸化膜がその後に形成される半導体デ バイスの特性に大きく影響する。例えばウェハ表面に膜厚 0. 5nm以上の自然酸ィ匕 膜が新たに形成されると，例えば膜厚 65nm以下のゲート絶縁膜を形成する場合に 大きな問題となってしまう。 [0005] However, even if the natural acid film on the wafer is removed outside the substrate processing apparatus, the surface of the wafer is not removed when the wafer is taken into the substrate processing apparatus for film formation. If exposed to the atmosphere, a new natural acid film may be formed on the wafer surface. Depending on the thickness of this natural oxide film, the natural oxide film has a significant effect on the characteristics of the semiconductor device that is formed later. For example, a natural acid film with a film thickness of 0.5 nm or more on the wafer surface. When a new film is formed, it becomes a big problem when a gate insulating film with a film thickness of 65 nm or less is formed.
[0006] また，上記ウエット洗浄によれば、ウェハ表面の自然酸ィ匕膜は除去されるが，ゥェ ハ表面に新たにウォータマーク (例えばウェハの搬送又は乾燥中に水滴を介して局 所的に形成されたシリコン酸化膜 (SiO )など）が発生する虞がある。例えば， DHF [0006] Further, according to the wet cleaning, the natural acid film on the wafer surface is removed, but a new watermark is formed on the wafer surface (for example, locally through water droplets during wafer transfer or drying). There is a possibility that a silicon oxide film (SiO.sub.2), etc. formed automatically will occur. For example, DHF
2  2
洗浄液によってウェハ表面の自然酸ィ匕膜が除去されることにより下地のシリコンが露 出してウェハ表面は疎水性となるが，ウェハを DHF洗浄液から引き上げるときにゥェ ハの表面に水滴が残留する可能性があり、当該水滴がスピン乾燥後にウォータマ一 クとなり得る。このようなウォータマークは，洗浄処理後に実行される成膜処理などに おける阻害要素となって、半導体デバイスの特性を劣化させる虞がある。  By removing the native oxide film on the wafer surface by the cleaning liquid, the underlying silicon is exposed and the wafer surface becomes hydrophobic. However, when the wafer is lifted from the DHF cleaning liquid, water droplets remain on the wafer surface. There is a possibility that the water drops can become water mark after spin drying. Such a watermark may be an impediment to the film forming process performed after the cleaning process and may deteriorate the characteristics of the semiconductor device.
[0007] 以上のようなウォータマークや自然酸ィ匕膜の発生を抑えるために，ウエット洗浄後 の乾燥工程にイソプロピルアルコール (IPA)を用いる方法がある（例えば特開 2002 166237号公報参照)。ところが， IPA乾燥後のウェハ表面には、 IPA分子 (炭素 等の有機物）が残留する可能性がある。 IPA分子は、例えばゲート酸ィ匕膜特性に悪 影響を与える可能性がある（K. MOTAI, T. Itoga, and T. Me, Extended Abstruct of 1997, International Conference on SolidState Devices and Materials, Hamamatsu, pp. 24- 25(1997)参照）。 [0007] In order to suppress the generation of the watermark and the natural acid film as described above, there is a method using isopropyl alcohol (IPA) in the drying process after the wet cleaning (see, for example, JP-A-2002-166237). However, IPA molecules (organic substances such as carbon) may remain on the wafer surface after IPA drying. IPA molecules can adversely affect, for example, gate oxide and capsule properties (K. MOTAI, T. Itoga, and T. Me, Extended Abstruct of 1997, International Conference on SolidState Devices and Materials, Hamamatsu, pp 24-25 (1997)).
[0008] そこで，近年では，上記ウエット洗浄方法によらずに，プラズマを用いたドライ洗浄 方法によってウェハ上の自然酸化膜を除去することが知られて!/、る。このようなドライ 洗浄方法として，例えば水素ガスとアルゴンガスとを用いて誘導結合プラズマを形成 し、当該プラズマによってウェハ上の自然酸ィ匕膜を除去することが知られている (例 えば特開平 04— 336426号公報参照)。このようなドライ洗浄方法によれば，ウエット 洗浄方法のように洗浄液などの水成分を用いな 、ので，ウォータマークが発生する 虞なく自然酸ィ匕膜を除去することができる。  [0008] Therefore, in recent years, it has been known that a natural oxide film on a wafer is removed by a dry cleaning method using plasma instead of the above wet cleaning method! As such a dry cleaning method, it is known to form inductively coupled plasma using, for example, hydrogen gas and argon gas, and to remove the natural oxide film on the wafer by the plasma (for example, Japanese Patent Laid-Open No. Hei. 04—See 336426). According to such a dry cleaning method, since a water component such as a cleaning solution is not used as in the wet cleaning method, it is possible to remove the natural oxide film without fear of generating a watermark.
[0009] しカゝしながら，プラズマ処理によってドライ洗浄方法を行う場合，プラズマ起因のチ ヤージアップダメージをウェハに負わせてしまう虞がある。このようなダメージを残した ままウェハ上に半導体デバイスを生成すると，例えばゲート絶縁膜の破壊などが起つ て，半導体デバイスの特性が劣化する等の問題がある。 [0010] ところで，ウェハ上の膜厚やパーティクルを測定することによって，実際にウェハ上 の自然酸ィ匕膜などの付着物が除去されたか否かにっ 、て検査を行うことができれば ,次の成膜処理によって成膜される膜質の均一性を確保することができる等利点も多 い。 However, when the dry cleaning method is performed by plasma processing, there is a risk of causing charge-up damage due to plasma to the wafer. If a semiconductor device is generated on the wafer with such damage remaining, there is a problem that the characteristics of the semiconductor device deteriorate due to, for example, destruction of the gate insulating film. [0010] By the way, by measuring the film thickness and particles on the wafer, whether or not deposits such as a natural acid film on the wafer have actually been removed can be inspected. There are also many advantages such as ensuring the uniformity of the film quality formed by this film forming process.
[0011] し力しながら，従来のパーティクル測定装置（例えば特開 2004— 327546号公報 参照)や膜厚測定装置 (特開平 03 - 283618号公報参照)では，ウェハ上の自然酸 化膜などの付着物を除去してカゝら連続してウェハ上の膜厚やパーティクルを測定す ることはできない。すなわち、上記ウエット洗浄などを基板処理装置外で実行した後， 上記の測定装置にウェハを搬入する際には、やはりウェハが大気に露出されてしま つて、ウェハ表面には新たに自然酸ィ匕膜が発生してしまう。  However, in conventional particle measuring devices (see, for example, Japanese Patent Application Laid-Open No. 2004-327546) and film thickness measuring devices (see Japanese Patent Application Laid-Open No. 03-283618), a natural oxide film on a wafer or the like is used. It is not possible to continuously measure the film thickness and particles on the wafer after removing the deposits. In other words, after carrying out the above-described wet cleaning or the like outside the substrate processing apparatus, when the wafer is carried into the above-described measuring apparatus, the wafer is still exposed to the atmosphere, and a new natural acid is added to the wafer surface. A film is generated.
発明の要旨  Summary of the Invention
[0012] そこで，本発明は，このような問題に鑑みてなされたもので，その目的とするところは ,水成分を用いず且つプラズマを用いずに基板上の自然酸ィ匕膜を含む付着物を除 去し，その後に基板を大気に露出することなく測定処理や成膜処理などを連続して 実行することができるような基板処理装置を提供することにある。  Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to include a natural oxide film on a substrate without using a water component and without using plasma. It is an object of the present invention to provide a substrate processing apparatus capable of removing a kimono and subsequently performing measurement processing and film formation processing without exposing the substrate to the atmosphere.
[0013] 上記課題を解決するために，本発明は，被処理基板に所定の処理を施す複数の 処理室と、前記複数の処理室に共通に連結され、前記複数の処理室の各々に対し て前記被処理基板の搬出入を行う共通搬送室と、を備え、前記複数の処理室には、 前記被処理基板上に付着された自然酸化膜を含む付着物をプラズマによらな!/ヽガス 成分との化学反応及び熱処理によって除去するための付着物除去処理室と，前記 被処理基板上に成膜処理を施すための成膜処理室と、前記被処理基板の測定処理 を行うための測定処理室と、が含まれて!/ヽることを特徴とする基板処理装置である。  In order to solve the above-described problems, the present invention provides a plurality of processing chambers for performing a predetermined process on a substrate to be processed, and a plurality of processing chambers commonly connected to each of the plurality of processing chambers. And a common transfer chamber for carrying in and out of the substrate to be processed, and the plurality of processing chambers include deposits including a natural oxide film deposited on the substrate to be processed by plasma. A deposit removal chamber for removing the gas component by chemical reaction and heat treatment, a film deposition chamber for performing a film deposition process on the substrate to be processed, and a measurement process for measuring the substrate to be processed A substrate processing apparatus including a measurement processing chamber.
[0014] 本発明によれば， 自然酸ィ匕膜を含む付着物がプラズマによらな ヽガス成分との化 学反応及び熱処理によって除去されるので，ウエット洗浄のように水成分が用いられ ることがなく，従って被処理基板上にウォータマークなどが発生することが防止され得 る。また，プラズマが用いられないため，被処理基板にプラズマ起因のチャージアツ プダメージが負わされることが防止され得る。また，基板処理装置内で、付着物除去 処理の後に、測定処理や成膜処理を連続して実行することができるので，成膜処理 の直前に被処理基板上に自然酸化膜が新たに形成されることが防止され得る。この ように， 自然酸ィ匕膜を含む付着物を確実に除去することができるので，次の成膜処理 によって被処理基板に形成される膜の密着性をより一層向上させることができ，強度 もより一層向上させることができる。 [0014] According to the present invention, the deposit containing the natural acid film is removed by the chemical reaction with the soot gas component such as plasma and heat treatment, so that the water component is used like wet cleaning. Therefore, it is possible to prevent the occurrence of a watermark on the substrate to be processed. In addition, since plasma is not used, it is possible to prevent charge-up damage caused by plasma from being applied to the substrate to be processed. In addition, the measurement process and film formation process can be executed continuously after the deposit removal process in the substrate processing apparatus. It is possible to prevent a natural oxide film from being newly formed on the substrate to be processed immediately before. In this way, since the deposits including the natural acid film can be reliably removed, the adhesion of the film formed on the substrate to be processed can be further improved by the next film formation process, and the strength can be improved. Can be further improved.
[0015] 好ましくは、前記付着物除去処理室は，前記被処理基板上の前記付着物をガス成 分と化学反応させて生成物を生成するための生成物生成処理室と、前記生成物生 成処理室にて前記被処理基板上に生成された前記生成物を熱処理により除去する ための生成物除去処理室と、の 2つの処理室により構成される。  [0015] Preferably, the deposit removal processing chamber includes a product generation processing chamber for generating a product by chemically reacting the deposit on the substrate to be processed with a gas component, and the product generation chamber. The processing chamber is composed of two processing chambers, a product removal processing chamber for removing the product generated on the substrate to be processed by heat treatment.
[0016] また、好ましくは、前記成膜処理室は、前記被処理基板上に第 1膜を成膜する第 1 膜成膜処理室と、前記第 1膜成膜処理室にて成膜された前記第 1膜上に第 2膜を成 膜する第 2膜成膜処理室と、の 2つの処理室により構成される。  [0016] Preferably, the film forming chamber is formed in a first film forming chamber for forming a first film on the substrate to be processed and in the first film forming chamber. In addition, the second film forming process chamber includes a second film forming process chamber for forming a second film on the first film.
[0017] また、好ましくは、前記測定処理室は、前記被処理基板上に成膜された膜の膜厚 を測定する膜厚測定部と、前記被処理基板上のパーティクルを測定するパーテイク ル測定部と、を備える。この場合， 1つの測定処理室で，膜厚とパーティクルの両方を 測定することができ，スループットを向上させることができる。  [0017] Preferably, the measurement processing chamber includes a film thickness measurement unit that measures a film thickness of a film formed on the substrate to be processed, and a particle measurement that measures particles on the substrate to be processed. A section. In this case, both film thickness and particles can be measured in one measurement processing chamber, and throughput can be improved.
[0018] また、好ましくは、前記測定処理室は、前記被処理基板の表面画像を撮像して認 識するための画像処理部を備える。この場合，被処理基板の表面のパターンマッチ ングなどを行うことができ、例えば膜厚やパーティクルを測定する被処理基板上の測 定ポイントを特定することができる。  [0018] Preferably, the measurement processing chamber includes an image processing unit for capturing and recognizing a surface image of the substrate to be processed. In this case, pattern matching on the surface of the substrate to be processed can be performed, and for example, a measurement point on the substrate to be processed for measuring a film thickness or particles can be specified.
[0019] また、本発明は、被処理基板に所定の処理を施す複数の処理室と、前記複数の処 理室に共通に連結された共通搬送室と、前記共通搬送室内に設けられた前記被処 理基板を搬送するための搬送機構と、をそれぞれ備えた複数の真空処理装置と、前 記複数の真空処理装置を互いに連結するパス部と、を備え、前記複数の処理室には 、前記被処理基板上に付着された自然酸ィ匕膜を含む付着物をプラズマによらな！/ヽガ ス成分との化学反応及び熱処理によって除去するための付着物除去処理室と，前記 被処理基板上に成膜処理を施すための成膜処理室と、前記被処理基板の測定処理 を行うための測定処理室と、が含まれて!/ヽることを特徴とする基板処理装置である。  [0019] Further, the present invention provides a plurality of processing chambers for performing predetermined processing on a substrate to be processed, a common transfer chamber commonly connected to the plurality of processing chambers, and the common transfer chamber provided in the common transfer chamber. A plurality of vacuum processing apparatuses each including a transport mechanism for transporting a substrate to be processed; and a pass unit that connects the plurality of vacuum processing apparatuses to each other. The plurality of processing chambers include: The deposit including the natural acid film deposited on the substrate to be processed is caused by plasma! A deposit removal treatment chamber for removal by chemical reaction and heat treatment with gas / gas components, a film formation treatment chamber for performing film formation on the substrate to be processed, and a measurement process for the substrate to be processed. And a measurement processing chamber for performing the substrate processing apparatus.
[0020] 本発明によっても， 自然酸ィ匕膜を含む付着物がプラズマによらな ヽガス成分との化 学反応及び熱処理によって除去されるので，ウエット洗浄のように水成分が用いられ ることがなく，従って被処理基板上にウォータマークなどが発生することが防止され得 る。また，プラズマが用いられないため，被処理基板にプラズマ起因のチャージアツ プダメージが負わされることが防止され得る。また，基板処理装置内で、付着物除去 処理の後に、測定処理や成膜処理を連続して実行することができるので，成膜処理 の直前に被処理基板上に自然酸化膜が新たに形成されることが防止され得る。この ように， 自然酸ィ匕膜を含む付着物を確実に除去することができるので，次の成膜処理 によって被処理基板に形成される膜の密着性をより一層向上させることができ，強度 もより一層向上させることができる。 [0020] According to the present invention, the deposit including the natural acid film is converted to a gas component such as plasma. Since it is removed by chemical reaction and heat treatment, water components are not used as in wet cleaning, so that it is possible to prevent the occurrence of watermarks on the substrate to be processed. In addition, since plasma is not used, it is possible to prevent charge-up damage caused by plasma from being applied to the substrate to be processed. In addition, measurement processing and film formation can be performed continuously after the deposit removal process in the substrate processing apparatus, so a natural oxide film is newly formed on the substrate to be processed immediately before the film formation process. Can be prevented. In this way, since the deposits including the natural acid film can be reliably removed, the adhesion of the film formed on the substrate to be processed can be further improved by the next film formation process, and the strength can be improved. Can be further improved.
[0021] 好ましくは、前記付着物除去処理室は，前記被処理基板上の前記付着物をガス成 分と化学反応させて生成物を生成するための生成物生成処理室と、前記生成物生 成処理室にて前記被処理基板上に生成された前記生成物を熱処理により除去する ための生成物除去処理室と、の 2つの処理室により構成される。  [0021] Preferably, the deposit removal processing chamber includes a product generation processing chamber for generating a product by chemically reacting the deposit on the substrate to be processed with a gas component, and the product generation chamber. The processing chamber is composed of two processing chambers, a product removal processing chamber for removing the product generated on the substrate to be processed by heat treatment.
[0022] また、好ましくは、前記成膜処理室は、前記被処理基板上に第 1膜を成膜する第 1 膜成膜処理室と、前記第 1膜成膜処理室にて成膜された前記第 1膜上に第 2膜を成 膜する第 2膜成膜処理室と、の 2つの処理室により構成される。  [0022] Preferably, the film forming chamber is formed in a first film forming chamber for forming a first film on the substrate to be processed and the first film forming chamber. In addition, the second film forming process chamber includes a second film forming process chamber for forming a second film on the first film.
[0023] あるいは、好ましくは、前記成膜処理室は、前記被処理基板上に第 1膜を成膜する 第 1膜成膜処理室と、前記第 1膜成膜処理室にて成膜された前記第 1膜上に第 2膜 を成膜する第 2膜成膜処理室と、の 2つの処理室の組を複数含んでいる。この場合， 例えば複数組の成膜処理室で並列して成膜処理を実行することができるので，装置 全体のスループットを大幅に向上させることができる。  Alternatively, preferably, the film forming chamber is formed in a first film forming chamber for forming a first film on the substrate to be processed and the first film forming chamber. In addition, a plurality of sets of two processing chambers including a second film forming process chamber for forming a second film on the first film are included. In this case, for example, the film forming process can be executed in parallel in a plurality of film forming process chambers, so that the throughput of the entire apparatus can be greatly improved.
[0024] 前記付着物除去処理室で処理される被処理基板が，コンタクトホールまたはビアホ ールが形成された被処理基板である場合には、好ましくは、前記成膜処理室は，前 記被処理基板に形成されたコンタクトホールまたはビアホールの内側に第 1バリア層 を成膜する第 1バリア層成膜処理室と、前記第 1バリア層成膜処理室にて成膜された 前記第 1バリア層の上側に第 2バリア層を成膜する第 2バリア層成膜処理室と、により 構成される。この場合、被処理基板に形成されたコンタクトホールまたはビアホール に付着された自然酸ィ匕膜などの付着物を確実に除去した上で，第 1バリア層，第 2バ リア層を成膜することができる。これにより，これらの膜の密着性をより一層向上させる ことができ，強度もより一層向上させることができる。 [0024] When the substrate to be processed in the deposit removal processing chamber is a substrate to be processed in which a contact hole or a via hole is formed, preferably, the film forming chamber is the substrate to be processed. A first barrier layer film forming process chamber for forming a first barrier layer inside a contact hole or via hole formed in a processing substrate; and the first barrier film formed in the first barrier layer film forming process chamber And a second barrier layer deposition processing chamber for depositing the second barrier layer on the upper side of the layer. In this case, the first barrier layer, the second barrier, etc. are removed after surely removing deposits such as a natural oxide film attached to the contact hole or via hole formed in the substrate to be processed. A rear layer can be formed. As a result, the adhesion of these films can be further improved, and the strength can be further improved.
[0025] 前記付着物除去処理室で処理される被処理基板が、シリコン基板である場合には 、好ましくは、前記成膜処理室は、前記被処理基板上に酸素ラジカルによってベース 酸化膜層を成膜するベース酸化膜層成膜処理室と、前記ベース酸化膜層成膜処理 室にて前記ベース酸化膜層が成膜された被処理基板に高誘電体ゲート酸化膜を成 膜する高誘電体ゲート酸化膜成膜処理室と、により構成される。この場合、シリコン基 板に付着された自然酸ィ匕膜などの付着物を確実に除去した上で，ベース酸ィ匕膜層， 高誘電体ゲート酸化膜を成膜することができる。これにより，これらの膜 (層）の密着性 をより一層向上させることができ，強度もより一層向上させることができる。  [0025] When the substrate to be processed to be processed in the deposit removal processing chamber is a silicon substrate, it is preferable that the film forming chamber has a base oxide film layer formed on the substrate to be processed by oxygen radicals. A base oxide film forming process chamber for forming a film and a high dielectric for forming a high dielectric gate oxide film on a substrate on which the base oxide film layer is formed in the base oxide film forming process chamber And a body gate oxide film formation processing chamber. In this case, it is possible to form the base oxide film layer and the high dielectric gate oxide film after reliably removing deposits such as a natural oxide film attached to the silicon substrate. As a result, the adhesion of these films (layers) can be further improved, and the strength can be further improved.
[0026] また、本発明は、被処理基板上に付着された自然酸化膜を含む付着物をプラズマ によらないガス成分との化学反応及び熱処理によって除去する付着物除去ステップ と、前記付着物除去ステップの後に、前記被処理基板の測定処理を行う測定ステツ プと，前記測定ステップの後に、当該被処理基板上に成膜処理を施す成膜ステップ と，を備えたことを特徴とする基板処理方法である。  [0026] Further, the present invention provides a deposit removing step for removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component not using plasma and heat treatment, and the deposit removal. Substrate processing comprising: a measurement step for performing measurement processing of the substrate to be processed after the step; and a film forming step for performing film formation processing on the substrate to be processed after the measurement step. Is the method.
[0027] 本発明によれば，付着物除去ステップと，測定ステップと，成膜ステップとを連続実 行することにより， 自然酸化膜を含む付着物を確実に除去した状態で成膜処理が行 われ得る。これにより，被処理基板に形成される膜の密着性をより一層向上させること ができ，強度もより一層向上させることができる。  [0027] According to the present invention, the deposition process is performed in a state in which deposits including the natural oxide film are reliably removed by continuously performing the deposit removal step, the measurement step, and the film deposition step. Can be broken. As a result, the adhesion of the film formed on the substrate to be processed can be further improved, and the strength can be further improved.
[0028] 好ましくは、前記付着物除去ステップは、前記被処理基板上の前記付着物をガス 成分と化学反応させて生成物を生成する生成物生成ステップと、前記生成物生成ス テツプにて前記被処理基板上に生成された前記生成物を熱処理により除去する生 成物除去ステップと、を有する。  [0028] Preferably, the deposit removing step includes a product generating step of generating a product by chemically reacting the deposit on the substrate to be processed with a gas component, and the product generating step. And a product removal step of removing the product generated on the substrate to be processed by heat treatment.
[0029] また、好ましくは、前記成膜ステップは、前記被処理基板上に第 1膜を成膜する第 1 成膜ステップと、前記第 1成膜ステップにて成膜された前記第 1膜上に第 2膜を成膜 する第 2成膜ステップと、を有する。  [0029] Preferably, the film forming step includes a first film forming step of forming a first film on the substrate to be processed and the first film formed in the first film forming step. A second film forming step of forming a second film thereon.
[0030] また、好ましくは、前記測定ステップは、前記付着物除去ステップが適正に実行さ れた力否かを検査する検査測定処理を行うステップである。 [0031] この場合，更に、前記測定ステップは，前記付着物除去ステップが施された前記被 処理基板の表面の膜厚測定を行う膜厚測定ステップと、前記付着物除去ステップが 施された前記被処理基板の表面の付着物測定を行う付着物測定ステップと、を有し ており、当該膜厚測定ステップ及び当該付着物測定ステップは、 1つの測定処理室 内で実行されることが好ましい。このように，膜厚とパーティクル (付着物）との両方を 測定することによって，被処理基板上から自然酸化膜を含む付着物が除去されたか 否かを確実に検査することができる。 [0030] Preferably, the measurement step is a step of performing an inspection measurement process for inspecting whether or not the attached matter removing step is properly executed. [0031] In this case, the measuring step further includes a film thickness measuring step for measuring a film thickness of the surface of the substrate to be processed on which the deposit removing step has been performed, and the deposit removing step on which the deposit has been removed. And a deposit measurement step for measuring deposits on the surface of the substrate to be processed, and the film thickness measurement step and the deposit measurement step are preferably performed in one measurement processing chamber. In this way, by measuring both the film thickness and particles (adhered matter), it is possible to reliably inspect whether the adhering material including the natural oxide film has been removed from the substrate to be processed.
[0032] また、更に好ましくは、前記測定ステップは、前記膜厚測定ステップ及び前記付着 物測定ステップによって測定された測定結果に基づ 、て、前記付着物除去ステップ を実行するためのプロセスレシピを補正するレシピ補正ステップを更に有する。この 場合、実際の処理結果に応じた付着物除去ステップを実行することができる。このた め，被処理基板上から自然酸ィ匕膜を含む付着物を確実に除去することができる。  Further preferably, the measurement step includes a process recipe for executing the deposit removal step based on the measurement results measured by the film thickness measurement step and the deposit measurement step. It further has a recipe correction step for correcting. In this case, the deposit removal step according to the actual processing result can be executed. For this reason, the deposits including the natural acid film can be reliably removed from the substrate to be processed.
[0033] あるいは、更に好ましくは、前記測定ステップは、前記膜厚測定ステップ及び前記 付着物測定ステップによって測定された測定結果に基づ 、て、次の成膜ステップを 実行するカゝ否かを判断する判断ステップを更に有する。この場合，例えば前記膜厚 測定ステップと前記パーティクル (付着物)測定ステップとにより測定された測定結果 が許容範囲内にあれば，次の成膜ステップを実行可能と判断する一方，許容範囲内 になければ、次の成膜ステップを実行不可能と判断するようにしてもよい。これにより ,常に被処理基板上の自然酸ィ匕膜を含む付着物が除去された状態で次の成膜ステ ップを実行することができる。これにより，被処理基板上に成膜される膜の膜質の均 一性を確保することができる。  Alternatively, more preferably, the measurement step determines whether or not to execute the next film formation step based on the measurement results measured by the film thickness measurement step and the deposit measurement step. It further has a judgment step of judging. In this case, for example, if the measurement results measured by the film thickness measurement step and the particle (adhered matter) measurement step are within an allowable range, it is determined that the next film forming step can be performed, while Otherwise, it may be determined that the next film forming step cannot be executed. Thus, the next film forming step can be executed in a state where the deposits including the natural oxide film on the substrate to be processed are always removed. As a result, the uniformity of the film quality of the film formed on the substrate to be processed can be ensured.
[0034] また、好ましくは、前記測定ステップは、前記付着物除去ステップが適正に実行さ れた力否かを検査する検査測定ステップと，次の成膜ステップが施される下地膜の 膜厚を測定する下地膜厚測定ステップと、を有する。  [0034] Preferably, the measurement step includes an inspection measurement step for inspecting whether or not the deposit removal step is properly performed, and a film thickness of a base film on which the next film formation step is performed. And a base film thickness measuring step for measuring.
[0035] この場合、更に好ましくは、前記測定ステップは、前記付着物除去ステップが施さ れた前記被処理基板の表面の膜厚測定を行う膜厚測定ステップと、前記付着物除 去ステップが施された前記被処理基板の表面の付着物測定を行う付着物測定ステツ プと、次の成膜ステップが施される下地膜の膜厚を測定する下地膜厚測定ステップと 、を有しており、当該膜厚測定ステップ、当該付着物測定ステップ及び当該下地膜 厚測定ステップは、 1つの測定処理室内で実行される。この場合、付着物除去ステツ プが適正に実行された力否かを検査するための膜厚測定と，次の成膜処理が施され る下地膜の膜厚測定とを同時に実行できるので，測定処理にかかる時間を大幅に短 縮することができる。 [0035] In this case, more preferably, the measurement step includes a film thickness measurement step for measuring a film thickness of the surface of the substrate to be processed on which the deposit removal step has been performed, and a deposit removal step. An adhering matter measuring step for measuring the adhering matter on the surface of the processed substrate, and a base film thickness measuring step for measuring a film thickness of the base film on which the next film forming step is performed, The film thickness measurement step, the deposit measurement step, and the base film thickness measurement step are executed in one measurement processing chamber. In this case, the film thickness measurement for inspecting whether or not the deposit removal step has been properly executed and the film thickness measurement of the underlying film to be subjected to the next film formation process can be performed simultaneously. Processing time can be significantly reduced.
[0036] あるいは、本発明は、被処理基板上に付着された自然酸化膜を含む付着物をブラ ズマによらないガス成分との化学反応及び熱処理によって除去する付着物除去ステ ップと、前記付着物除去ステップの後に、前記被処理基板上に成膜処理を施す成膜 ステップと、前記成膜ステップの後に、前記被処理基板の測定処理を行う測定ステツ プと、を備えたことを特徴とする基板処理方法である。  [0036] Alternatively, the present invention provides a deposit removing step for removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component not using plasma and heat treatment, A deposition step for performing a deposition process on the substrate to be processed after the deposit removing step; and a measurement step for performing a measurement process for the substrate to be processed after the deposition step. This is a substrate processing method.
[0037] この場合，好ましくは、前記測定ステップは，前記成膜ステップによって形成された 膜の膜厚測定を行う成膜厚測定ステップを有する。これにより、成膜後の状態につい てち検査することがでさる。  [0037] In this case, preferably, the measurement step includes a film thickness measurement step for measuring a film thickness of the film formed by the film formation step. Thus, it is possible to inspect the state after film formation.
[0038] 更に好ましくは、前記測定ステップは、前記成膜厚測定ステップによって測定され た測定結果に基づ 、て、前記成膜ステップを実行するためのプロセスレシピを補正 するレシピ補正ステップを更に有する。この場合、以降の被処理基板に対して、常に 適正な成膜処理を実行させることができる。  [0038] More preferably, the measurement step further includes a recipe correction step of correcting a process recipe for executing the film formation step based on the measurement result measured by the film thickness measurement step. . In this case, it is possible to always perform an appropriate film forming process on subsequent substrates to be processed.
[0039] あるいは、本発明は、被処理基板の測定処理を行う測定ステップと、前記測定ステ ップの後に、前記被処理基板上に付着された自然酸化膜を含む付着物をプラズマ によらないガス成分との化学反応及び熱処理によって除去する付着物除去ステップ と、前記付着物除去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステ ップと、を備えたことを特徴とする基板処理方法である。このように，被処理基板の測 定ステップは，付着物除去ステップの前に行われてもよ ヽ。  [0039] Alternatively, the present invention does not rely on plasma for a measurement step for measuring a substrate to be processed and a deposit including a natural oxide film deposited on the substrate to be processed after the measurement step. A deposit removing step for removing the deposit by a chemical reaction with a gas component and a heat treatment; and a deposition step for performing a deposition process on the substrate to be processed after the deposit removing step. This is a substrate processing method. In this way, the measurement step of the substrate to be processed may be performed before the deposit removal step.
[0040] あるいは、本発明は、コンピュータに，被処理基板上に付着された自然酸化膜を含 む付着物をプラズマによらないガス成分との化学反応及び熱処理によって除去する 付着物除去ステップと、被処理基板の測定処理を行う測定ステップと，前記付着物除 去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステップと，を実行さ せるためのプログラムである。 [0041] あるいは、本発明は、コンピュータに，被処理基板上に付着された自然酸化膜を含 む付着物をプラズマによらないガス成分との化学反応及び熱処理によって除去する 付着物除去ステップと、被処理基板の測定処理を行う測定ステップと，前記付着物除 去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステップと，を実行さ せるためのプログラムを記録したコンピュータ読み取り可能な記録媒体である。 [0040] Alternatively, the present invention provides a computer with a deposit removal step of removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component that does not depend on plasma and a heat treatment; It is a program for executing a measurement step for measuring a substrate to be processed and a film forming step for performing a film forming process on the substrate to be processed after the deposit removing step. [0041] Alternatively, the present invention provides a computer with a deposit removal step of removing deposits including a natural oxide film deposited on a substrate to be processed by a chemical reaction with a gas component that does not depend on plasma and a heat treatment; A computer readable recording of a program for executing a measurement step for measuring a substrate to be processed and a film forming step for performing a film forming process on the substrate to be processed after the deposit removing step. Recording medium.
[0042] このようなプログラムまたは記録媒体に記録されたプログラムによれば，付着物除去 ステップと，測定ステップと，成膜ステップとを連続実行することができ， 自然酸化膜を 含む付着物を確実に除去した状態で成膜処理が行われ得る。これにより，被処理基 板に形成される膜の密着性をより一層向上させることができ，強度もより一層向上さ せることができる。  [0042] According to such a program or a program recorded on a recording medium, the deposit removal step, the measurement step, and the film formation step can be continuously performed, and deposits including a natural oxide film can be reliably obtained. The film forming process can be performed in the state of being removed. As a result, the adhesion of the film formed on the substrate to be treated can be further improved, and the strength can be further improved.
図面の簡単な説明  Brief Description of Drawings
[0043] [図 1]図 1は、本発明の第 1の実施の形態に係る基板処理装置の構成例を示す断面 図である。  FIG. 1 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a first embodiment of the present invention.
[図 2]図 2は、図 1に示す基板処理装置における処理室の構成例を示す図である。  2 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG.
[図 3]図 3は、図 1に示す制御部（システムコントローラ）の構成例を示すブロック図で ある。  FIG. 3 is a block diagram showing a configuration example of a control unit (system controller) shown in FIG.
[図 4]図 4は、本発明の第 1の実施の形態の EC (装置制御部）の構成例を示すブロッ ク図である。  FIG. 4 is a block diagram showing a configuration example of an EC (apparatus control unit) according to the first embodiment of the present invention.
[図 5]図 5は、図 1に示す基板処理装置における処理室の他の構成例を示す図であ る。  FIG. 5 is a diagram showing another configuration example of the processing chamber in the substrate processing apparatus shown in FIG. 1.
[図 6]図 6は、本発明の第 2の実施の形態に係る基板処理装置の構成例を示す断面 図である。  FIG. 6 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a second embodiment of the present invention.
[図 7]図 7は、図 6に示す基板処理装置における処理室の構成例を示す図である。  FIG. 7 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG.
[図 8]図 8は、図 6に示す基板処理装置における処理室の他の構成例を示す図であ る。  8 is a diagram showing another configuration example of the processing chamber in the substrate processing apparatus shown in FIG.
[図 9]図 9は、図 6に示す基板処理装置における処理室の他の構成例を示す図であ る。  9 is a diagram showing another configuration example of the processing chamber in the substrate processing apparatus shown in FIG.
[図 10]図 10は、本発明の第 3の実施の形態に係る基板処理装置の構成例を示す断 面図である。 FIG. 10 is a cross-sectional view showing a configuration example of a substrate processing apparatus according to a third embodiment of the present invention. FIG.
[図 11]図 11は、図 10に示す測定処理室の構成例を示すブロック図である。  FIG. 11 is a block diagram showing a configuration example of the measurement processing chamber shown in FIG.
[図 12]図 12は、本発明の第 3の実施の形態の EC (装置制御部）の構成例を示すブ ロック図である。  FIG. 12 is a block diagram showing a configuration example of an EC (apparatus control unit) according to the third embodiment of the present invention.
[図 13]図 13は、図 10に示す基板処理装置における処理室の構成例を示す図である  13 is a diagram showing a configuration example of a processing chamber in the substrate processing apparatus shown in FIG.
[図 14]図 14は、図 10に示す測定処理室における測定処理の具体例を示すフローチ ヤートである。 FIG. 14 is a flowchart showing a specific example of measurement processing in the measurement processing chamber shown in FIG.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0044] 以下、添付図面を参照しながら，本発明の好適な実施の形態について詳細に説明 する。なお，本明細書及び図面において，実質的に同一の機能構成を有する構成 要素については，同一の符号を付して重複説明を省略する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.
[0045] (第 1の実施の形態に係る基板処理装置の構成例） (Configuration example of substrate processing apparatus according to first embodiment)
先ず，本発明の第 1の実施の形態に係る基板処理装置の構成例を図面を参照しな がら説明する。  First, a configuration example of a substrate processing apparatus according to a first embodiment of the present invention will be described with reference to the drawings.
[0046] 図 1は、本実施の形態に係る基板処理装置の 1例を示す概略構成図である。図 1に 示すように，この基板処理装置 100は，略多角形状 (例えば六角形状）に形成された 1つ共通搬送室 102と，真空引き可能に構成された複数 (例えば 4つ）の処理室 104 A〜104Dと、を備える真空処理装置を有する。  FIG. 1 is a schematic configuration diagram showing an example of a substrate processing apparatus according to the present embodiment. As shown in FIG. 1, this substrate processing apparatus 100 includes one common transfer chamber 102 formed in a substantially polygonal shape (for example, hexagonal shape) and a plurality of (for example, four) processing chambers configured to be evacuated. 104 A to 104D.
[0047] 各処理室 104A〜104Dは、共通搬送室 102の周面に、それぞれゲートバルブ 10 6A〜106Dを介して連結されている。また，各処理室 104A〜104Dには、被処理 基板例えば半導体ウェハ（以下，単に「ウェハ」とも称する。）Wを載置する載置台 10 5A〜105Dが設けられている。各処理室 104A〜104Dは、それぞれ載置台 105A 〜105Dに載置されたウェハ Wに対して、所定の処理を施し得るようになっている。  [0047] The processing chambers 104A to 104D are connected to the peripheral surface of the common transfer chamber 102 via gate valves 106A to 106D, respectively. In addition, each of the processing chambers 104A to 104D is provided with mounting tables 105A to 105D on which a substrate to be processed, for example, a semiconductor wafer (hereinafter also simply referred to as “wafer”) W is mounted. Each of the processing chambers 104A to 104D can perform a predetermined process on the wafer W mounted on the mounting tables 105A to 105D, respectively.
[0048] 共通搬送室 102には，真空引き可能に構成された 2つのロードロック室 108A, 10 8Bを介して、略長方形状の搬入側搬送室 110が連結されている。ロードロック室 10 8A, 108Bと共通搬送室 102及び搬入側搬送室 110との連結部には、それぞれゲ ートバルブ 107A, 107Bが介在されている。 [0049] 搬入側搬送室 110には，ウェハ Wを複数枚収容できるカセットを載置する例えば 3 つの導入ポート 112A〜 112C及びウェハ Wを回転してこの偏心量を光学的に求め て位置合わせを行うオリエンタ 114が連結されて 、る。 [0048] The common transfer chamber 102 is connected to a substantially rectangular loading-side transfer chamber 110 via two load lock chambers 108A and 108B that are configured to be evacuated. Gate valves 107A and 107B are interposed at connecting portions between the load lock chambers 108A and 108B, the common transfer chamber 102, and the transfer-side transfer chamber 110, respectively. [0049] In the transfer-side transfer chamber 110, for example, three introduction ports 112A to 112C on which a cassette capable of holding a plurality of wafers W is placed and the wafer W is rotated to optically determine the amount of eccentricity for alignment. The orienter 114 to perform is linked.
[0050] 搬入側搬送室 110内には，ウェハ Wを保持する 2つのピック 116A, 116Bを有して 屈伸，旋回，昇降及び直線移動可能に構成された搬入側搬送機構 116が設けられ ている。また，共通搬送室 102内には，ウェハ Wを保持する 2つのピック 118A, 118 Bを有して屈伸及び旋回可能に構成された搬送機構 118が設けられている。基板処 理装置 100には，制御部 200が接続されている。そして、この制御部 200により、基 板処理装置 100の各部が制御されるようになって 、る。  [0050] In the transfer-side transfer chamber 110, a transfer-side transfer mechanism 116 having two picks 116A and 116B for holding the wafer W and configured to bend, extend, swing, and move linearly is provided. . In the common transfer chamber 102, a transfer mechanism 118 having two picks 118A and 118B for holding the wafer W and configured to bend and stretch and turn is provided. A control unit 200 is connected to the substrate processing apparatus 100. The control unit 200 controls each part of the substrate processing apparatus 100.
[0051] なお，本実施の形態では、共通搬送室 102と 2つのロードロック室の内のいずれか 一方，例えばロードロック室 108A、との連結部の搬送口 109Aは、ウェハ Wを共通 搬送室 102内へ搬入する搬入専用口として用いられ、共通搬送室 102と他方のロー ドロック室 108Bとの連結部の搬送口 109Bは、ウェハ Wを共通搬送室 102から外へ 搬出する搬出専用口として用いられる。  [0051] In the present embodiment, the transfer port 109A of the connecting portion between the common transfer chamber 102 and one of the two load lock chambers, for example, the load lock chamber 108A, is configured to transfer the wafer W to the common transfer chamber. Used as a dedicated carry-in port for loading into 102, and used as a dedicated carry-out port for carrying wafer W out of the common transfer chamber 102, using the transfer port 109B at the connection between the common transfer chamber 102 and the other load lock chamber 108B. It is done.
[0052] (ウェハ処理の具体例） [0052] (Specific example of wafer processing)
本実施の形態に係る基板処理装置 100は，ウェハ上の付着物（例えばコンタミネー シヨンや自然酸化膜など)をプラズマによらな!/ヽガス成分との化学反応及び熱処理に よって除去する付着物除去処理と，当該付着物除去処理が施されたウェハ上に所定 の薄膜を形成する成膜処理と、を連続して実行するようになって ヽる。  The substrate processing apparatus 100 according to the present embodiment removes deposits on the wafer (for example, contamination and natural oxide film) by plasma reaction! / Chemical reaction with soot gas components and heat treatment. The process and the film forming process for forming a predetermined thin film on the wafer that has been subjected to the deposit removal process are continuously executed.
[0053] (付着物除去処理） [0053] (Adherent removal treatment)
先ず，成膜処理の前処理として実行される付着物除去処理について、詳細に説明 される。  First, the deposit removal process executed as a pre-process of the film forming process will be described in detail.
[0054] 本実施の形態では，水成分を用いず且つプラズマを用いな 、付着物除去処理が 実行される。この付着物除去処理は，例えばウェハに付着された自然酸ィ匕膜を含む 付着物とガス成分とを化学反応させて生成物を生成する生成物生成処理と，ウェハ 上に生成された当該生成物を熱処理により除去する生成物除去処理と、の 2段階の 処理によって構成される。  In the present embodiment, the deposit removal process is performed without using water components and without using plasma. This deposit removal processing includes, for example, a product generation process that generates a product by chemically reacting deposits including a natural acid film deposited on a wafer and a gas component, and the generation generated on the wafer. It consists of a two-stage process: a product removal process that removes products by heat treatment.
[0055] 生成物生成処理は、例えば COR (Chemical Oxide Removal)処理であり，生成物除 去処理は、例えば PHT (Post Heat Treatment)処理である。 COR処理は，ウェハ上 に付着された付着物例えば自然酸化膜などの酸化膜と、例えばアンモニア (NH ) [0055] The product generation process is, for example, a COR (Chemical Oxide Removal) process. The last treatment is, for example, a PHT (Post Heat Treatment) treatment. COR processing involves deposits deposited on the wafer, such as oxide films such as natural oxide films, and ammonia (NH), for example.
3 ガス及び弗化水素 (HF)ガスなどのガス分子と、を化学反応させて、生成物（主に (N H ) SiF )を生成する処理である。 PHT処理は， COR処理が施されたウェハを 3 This is a process that chemically reacts gas and gas molecules such as hydrogen fluoride (HF) gas to produce products (mainly (N H) SiF). For PHT processing, wafers with COR processing are used.
4 2 6 4 2 6
加熱して， COR処理の化学反応によってウェハ上に生成された生成物を気化 (昇華 When heated, the product generated on the wafer by the chemical reaction of the COR process is vaporized (sublimation)
)させてウェハから除去する処理である。 ) To remove from the wafer.
[0056] このように， COR処理及び PHT処理は，プラズマレスエッチング処理及びドライタリ 一-ング処理 (乾燥洗浄処理）に相当する（COR処理力 水成分を用いず且つブラ ズマを用いずにウェハの自然酸ィ匕膜などの付着物を除去することができるため)。 [0056] Thus, the COR process and the PHT process correspond to the plasmaless etching process and the dry cleaning process (dry cleaning process) (COR process power without using water components and without using plasma). Because it can remove deposits such as natural acid film).
[0057] アンモニアガス及び弗化水素ガスを反応ガスとして用いた場合について、 COR処 理及び PHT処理の化学反応式を具体的に示す。 [0057] The chemical reaction formulas of the COR treatment and the PHT treatment are specifically shown in the case where ammonia gas and hydrogen fluoride gas are used as the reaction gas.
[0058] [COR処理の化学反応式] [0058] [Chem chemical reaction formula]
SiO +4HF → SiF + 2H O†  SiO + 4HF → SiF + 2H O †
2 4 2  2 4 2
SiF + 2NH + 2HF→ (NH ) SiF  SiF + 2NH + 2HF → (NH) SiF
4 3 4 2 6  4 3 4 2 6
[0059] [PHT処理の化学反応式]  [0059] [PHT treatment chemical reaction formula]
(NH ) SiF → SiF † + 2NH † + 2HF†  (NH) SiF → SiF † + 2NH † + 2HF †
4 2 6 4 3  4 2 6 4 3
上述した化学反応を利用した COR処理及び PHT処理は，以下の特性を有する。 なお， PHT処理においては， N 及び H も若干量発生する。  COR processing and PHT processing using the chemical reaction described above have the following characteristics. In the PHT process, a small amount of N and H is also generated.
2 2  twenty two
[0060] [COR処理及び PHT処理の特性]  [0060] [Characteristics of COR processing and PHT processing]
(1)熱酸ィ匕膜の選択比（除去速度）が高い。より詳細には、 COR処理及び PHT処理 は，熱酸化膜の選択比が高い一方，ポリシリコンの選択比が低い。従って，熱酸化膜 である SiO 膜からなる絶縁膜の表層や SiO 膜と同様の特性を有する疑似 SiO 層  (1) The selection ratio (removal rate) of the thermal acid film is high. More specifically, COR processing and PHT processing have a high thermal oxide film selectivity, but a low polysilicon selectivity. Therefore, the surface layer of the insulating film made of the SiO film, which is a thermal oxide film, and the pseudo-SiO layer having the same characteristics as the SiO film.
2 2 2 またはシリコン表層の自然酸ィ匕膜及びウォータマークを効率よく除去することができる [0061] (2)表層や疑似 SiO 層が除去された絶縁膜の表面における自然酸ィ匕膜の成長速  [0061] (2) Growth of the natural oxide film on the surface of the insulating film from which the surface layer or the pseudo-SiO layer has been removed. Speed
2  2
度が遅い。具体的には、ウエットエッチングによって表面が露出したウェハの表面に おいては，厚さ 3オングストロームの自然酸ィ匕膜の成長時間が略 10分であるのに対 して， COR処理及び PHT処理によって表面が露出したウェハの表面においては， 厚さ 3オングストロームの自然酸ィ匕膜の成長時間は略 2時間以上である。従って， CO R処理及び PHT処理による洗浄工程では，ウォータマークが新たに発生することは なく，さらに洗浄工程後の時間経過による自然酸ィ匕膜の成長も抑制されるので，半導 体デバイスの信頼性を向上させることができる。 Slow. Specifically, on the surface of a wafer whose surface is exposed by wet etching, the growth time of a natural oxide film having a thickness of 3 angstroms is approximately 10 minutes, whereas COR processing and PHT processing are performed. On the wafer surface where the surface is exposed by The growth time of a 3 Å thick natural oxide film is approximately 2 hours or more. Therefore, in the cleaning process using the COR process and the PHT process, a new watermark is not generated, and the growth of the natural oxide film over time after the cleaning process is suppressed. Reliability can be improved.
[0062] (3)ドライ環境において反応が進行する。具体的には、 COR処理において水を反応 に用いることはない。また COR処理によって水分子が発生したとしても， COR処理は 略真空状態で行われるため，水分子は気体状態で発生する。従って，水分子が液体 状態でウェハに付着することはな 、ので，ウェハの表面にウォータマーク等が発生す ることはない。更に PHT処理は高温下で行われるため，ウェハの表面にウォータマ ーク等が発生することはなく，表面が露出したウェハの表面に OH基が配されることも ない。従って，ウェハの表面が不動態化（passivate)されて親水性になることがないの で，ウェハの表面は吸湿することもない。このため，半導体デバイスの配線信頼性の 低下を防止することができる。  [0062] (3) The reaction proceeds in a dry environment. Specifically, water is not used for the reaction in the COR process. Even if water molecules are generated by the COR process, the water is generated in a gas state because the COR process is performed in a substantially vacuum state. Therefore, since water molecules do not adhere to the wafer in the liquid state, a watermark or the like is not generated on the wafer surface. Furthermore, since the PHT process is performed at a high temperature, no water marks or the like are generated on the wafer surface, and OH groups are not arranged on the exposed wafer surface. Therefore, since the wafer surface is not passivated and becomes hydrophilic, the wafer surface does not absorb moisture. For this reason, it is possible to prevent a decrease in wiring reliability of semiconductor devices.
[0063] (4)生成物 (錯体)の生成量は所定時間が経過すると緩和する。具体的には、所定 時間が経過すると，それ以降はウォータマークをアンモニアガス及び弗化水素ガスの 混合気体に暴露し続けても，生成物の生成量は増加しない。また生成物の生成量は ,混合気体の圧力，体積流量比等の混合気体のパラメータによって決定される。従つ て，ウォータマークの除去量の制御を容易に行うことができる。  [0063] (4) The amount of product (complex) produced relaxes after a predetermined time. Specifically, after a predetermined time has passed, the amount of product produced will not increase even if the watermark is continuously exposed to a mixture of ammonia gas and hydrogen fluoride gas. The amount of product produced is determined by gas mixture parameters such as gas pressure and volumetric flow ratio. Therefore, the amount of watermark removal can be controlled easily.
[0064] (5)パーティクルの発生が非常に少ない。具体的には、例えば 2000枚のウェハにお ける自然酸ィ匕膜の除去を実行しても，処理室内や処理室の内壁等にパーティクルの 付着がほとんど観察されない。従って、半導体デバイスにおいてパーティクルを介し た配線の短絡等が発生することがなく，半導体デバイスの信頼性を向上させることが できる。  [0064] (5) Very few particles are generated. Specifically, for example, even when removal of a natural oxide film on 2000 wafers is performed, adhesion of particles is hardly observed on the processing chamber or the inner wall of the processing chamber. Therefore, there is no short circuit of wiring via particles in the semiconductor device, and the reliability of the semiconductor device can be improved.
[0065] (成膜処理）  [0065] (Film formation process)
次に，成膜処理について説明する。ここでは，成膜処理として、ウェハに形成され たコンタクトホールまたはビアホールの内側に例えば第 1膜としての Ti系膜及び第 2 膜としての TiN系膜の 2層構造のバリア層を成膜する成膜処理が実行される。このよ うな成膜処理を実行する前に，上述したような水成分を用いず且つプラズマを用いな い付着物除去処理が実行されている。これにより，膜の密着性及び強度を向上させ ることができる。また，本実施の形態に係る付着物除去処理では、プラズマが用いら れな 、ため，ウェハの下地膜にプラズマ起因のチャージアップダメージを負わせるこ とが防止され得る。このため，ダメージのない配線力卩ェを行うことができ，また、良好な コンタクト抵抗を有する膜を成膜することができる。 Next, the film forming process will be described. Here, as a film forming process, a barrier layer having a two-layer structure of, for example, a Ti film as a first film and a TiN film as a second film is formed inside a contact hole or via hole formed in a wafer. Membrane processing is performed. Before performing such a film formation process, do not use the water component as described above and do not use plasma. The extraneous matter removal process is being executed. As a result, the adhesion and strength of the film can be improved. In addition, since the deposit removal process according to the present embodiment does not use plasma, it is possible to prevent charge-up damage caused by plasma from being applied to the underlying film of the wafer. For this reason, it is possible to perform a wiring force test without damage and to form a film having a good contact resistance.
[0066] 半導体デバイスの製造においては，最近の高密度化および高集積化の要請に対 応して，回路構成を多層配線構造にする傾向にある。このため，下層の半導体デバ イスと上層の配線層との接続部であるコンタクトホールや上下の配線層同士の接続 部であるビアホールなどの層間の電気的接続のための埋め込み技術が重要になつ ている。このようなコンタクトホールやビアホールの埋め込みには，一般的に A1 (アル ミニゥム）や W (タングステン），あるいはこれらを主体とする合金が用いられる。このよ うな金属や合金と下層のシリコン (Si)基板やポリシリコン (poly— Si)層とのコンタクト を形成するために，これらの埋め込みに先立ってコンタクトホールやビアホールの内 側に T係膜 (例えば Ti膜)と TiN系膜 (例えば TiN膜)とを成膜することが行われてい る。  In the manufacture of semiconductor devices, the circuit configuration tends to have a multilayer wiring structure in response to the recent demand for higher density and higher integration. For this reason, an embedding technique for electrical connection between layers such as a contact hole which is a connection portion between a lower semiconductor device and an upper wiring layer and a via hole which is a connection portion between upper and lower wiring layers is important. Yes. In general, contact holes and via holes are filled with A1 (aluminum), W (tungsten), or alloys based on these. In order to form a contact between such a metal or alloy and the underlying silicon (Si) substrate or polysilicon (poly-Si) layer, a T-type film ( For example, a Ti film and a TiN film (for example, a TiN film) are formed.
[0067] これらの膜の成膜には，デバイスの微細化および高集積化が進んでも電気抵抗が 増加せず良質な膜を形成することができ，し力もステップカバレッジを良好にすること ができる CVD (Chemical Vapor Deposition:化学気相成長）法が用いられている。例 えば TiCl を反応ガスとして CVD法により Ti膜を成膜することにより、当該 Ti膜を下  [0067] In the formation of these films, even if the device is miniaturized and highly integrated, a high-quality film can be formed without increasing the electrical resistance, and the step force can be improved. The CVD (Chemical Vapor Deposition) method is used. For example, when Ti film is formed by CVD method using TiCl as a reaction gas,
4  Four
地のシリコン基板と反応させてコンタクトホールの底のシリコン拡散層上に自己整合 的に TiSi を選択成長させ，良好なォーミック抵抗を得ている。  TiSi is selectively grown in a self-aligned manner on the silicon diffusion layer at the bottom of the contact hole by reacting with the ground silicon substrate to obtain a good ohmic resistance.
2  2
[0068] このような CVD— Ti膜を成膜する場合，反応ガスとしては上述したように TiCl ガ  [0068] When such a CVD-Ti film is formed, the reaction gas is TiCl gas as described above.
4 スが一般的に用いられ，還元ガスとしては H ガス等が用いられる。 TiCl ガスの結  4 gas is generally used, and H gas or the like is used as the reducing gas. TiCl gas bonding
2 4 合エネルギーはかなり高く，熱エネルギー単独では 1200°C程度の高温でなければ 分解しない。従って，プラズマエネルギーを併用するプラズマ CVD法によって，通常 ,プロセス温度 650°C程度で成膜を行っている。  2 4 The combined energy is quite high, and thermal energy alone does not decompose unless it is as high as 1200 ° C. Therefore, deposition is usually performed at a process temperature of about 650 ° C by plasma CVD using plasma energy.
[0069] ここで，このようなメタル成膜においては，良好なコンタクト抵抗を得るために，成膜 処理に先立って下地の上に形成された自然酸化膜を除去する処理が施される。この ような自然酸ィ匕膜の除去は、一般的に希弗酸により行われてきたが，水素ガスとアル ゴンガスを用いて誘導結合プラズマを形成して当該プラズマによって自然酸ィ匕膜を 除去することちある。 Here, in such metal film formation, in order to obtain good contact resistance, a process of removing a natural oxide film formed on the base is performed prior to the film formation process. this Such a natural acid film is generally removed by dilute hydrofluoric acid, but inductively coupled plasma is formed using hydrogen gas and argon gas, and the natural acid film is removed by the plasma. There are many things.
[0070] しカゝしながら，以上のような従来のプラズマ CVD法で Ti膜を成膜すると，粒径が不 均一な TiSi 結晶が形成されてしまう傾向がある。すなわち，従来は TiSi 膜の成膜  [0070] However, when a Ti film is formed by the conventional plasma CVD method as described above, TiSi crystals having a nonuniform particle size tend to be formed. In other words, conventional TiSi film deposition
2 2 に先立ってアルゴンプラズマを用いたドライ洗浄によって自然酸化膜除去を行って ヽ たので， Si拡散層表面がダメージを受けて不均一にアモルファス化しており，その状 態でプラズマ CVDで Ti膜を成膜すると，形成される TiSi 結晶が一層不均一になつ  Since the natural oxide film was removed by dry cleaning using argon plasma prior to 22, the Si diffusion layer surface was damaged and became non-uniformly amorphous. In this state, the Ti film was formed by plasma CVD. As a result, the TiSi crystals formed become more uneven.
2  2
てしまうのである。そして，このような不均一な状態の TiSi 結晶は比較的疎に存在  It will end up. And such non-uniform TiSi crystals exist relatively sparsely
2  2
するため，比抵抗が高いとともに TiSi 膜と下地との接触が不均一となる。したがって  As a result, the resistivity is high and the contact between the TiSi film and the substrate becomes uneven. Therefore
2  2
,コンタクト抵抗が増加してしまう。  Therefore, the contact resistance increases.
[0071] この点，本実施の形態によれば，前処理として、水成分を用いず且つプラズマを用 Vヽな ヽ付着物除去処理 (例えば COR処理及び PHT処理）によってウェハ上に形成 されたコンタクトホールまたはビアホール内の自然酸ィ匕膜を除去した上で， Ti系膜及 び TiN系膜が成膜される。これにより， Ti系膜及び TiN系膜を成膜する前の下地に、 プラズマ起因のチャージアップダメージを負わせることを防止することができる。従つ て，プラズマ CVD法で Ti膜を成膜しても，ダメージのない配線力卩ェを行うことができ， また、良好なコンタクト抵抗を有する膜を成膜することができる。また， Ti系膜及び Ti N系膜の各膜の密着性，強度も向上させることができる。  [0071] In this regard, according to the present embodiment, as a pre-process, a water component is not used and plasma is used, so that it is formed on the wafer by a V-attachment removal process (for example, COR process and PHT process). The Ti-based film and TiN-based film are formed after removing the natural oxide film in the contact hole or via hole. As a result, it is possible to prevent plasma-induced charge-up damage from being applied to the base before the Ti-based film and TiN-based film are formed. Therefore, even if a Ti film is formed by the plasma CVD method, a damage-free wiring force can be obtained, and a film having a good contact resistance can be formed. In addition, the adhesion and strength of each of the Ti film and Ti N film can be improved.
[0072] ここで，第 1膜成膜処理としての Ti系膜成膜処理の具体例を説明する。 Ti系膜成 膜処理としては，例えば上述したようにプラズマ CVDにより Ti膜を成膜する CVD— T i膜成膜処理が行われる。 CVD—Ti膜成膜処理は、例えば TiCl ガスの供給と ガ  Here, a specific example of the Ti-based film deposition process as the first film deposition process will be described. For example, as described above, a CVD-Ti film formation process that forms a Ti film by plasma CVD is performed as the Ti film formation process. The CVD-Ti film deposition process includes, for example, TiCl gas supply and gas
4  Four
スの供給と H ガスの供給とプラズマ発生とを同時期に行う工程と， NH ガスの供給  Gas supply, H gas supply and plasma generation at the same time, and NH gas supply
2 3  twenty three
と Arガスの供給と H ガスの供給とプラズマ発生とを同時期に行う工程と、によって C  And Ar gas supply, H gas supply and plasma generation at the same time,
2  2
VD— Ti膜を成膜する処理である。この場合，温度は 650°Cに設定される。  This is a process to form a VD-Ti film. In this case, the temperature is set to 650 ° C.
[0073] なお， Ti系膜成膜処理は，上記に限られない。例えば，上記 650°Cよりも低温の 40 0°C〜450°Cにてプラズマ CVDにより Ti膜を成膜する SFD (Sequential Flow Deposit ion)—Ti膜成膜処理を実行してもよい。 SFD— Ti膜成膜処理は、例えば TiCl ガス の供給と Arガスの供給と H ガスの供給とプラズマ発生とを同時期に行う行程と TiCl [0073] The Ti-based film deposition process is not limited to the above. For example, an SFD (Sequential Flow Deposit ion) -Ti film forming process may be executed in which a Ti film is formed by plasma CVD at a temperature lower than 650 ° C. at 400 ° C. to 450 ° C. SFD—Ti film deposition process, for example, TiCl gas Of TiCl supply, Ar gas supply, H gas supply and plasma generation at the same time
2  2
ガスの供給のみを止める工程とを複数回繰返した後に， NH ガスの供給と Arガス After repeating the process of stopping only the gas supply multiple times, the NH gas supply and Ar gas
4 3 4 3
の供給と H ガスの供給とプラズマ発生とを同時期に行う工程を行うことによって， SF  By performing the process of supplying H 2 gas, supplying H gas and generating plasma at the same time,
2  2
D— Ti膜を成膜する処理である。  D—Ti film forming process.
[0074] さらに，他の Ti膜成膜処理として，原子層堆積（ALD: Atomic Layered Deposition) の手法を用いた ALD—Ti膜成膜処理を実行してもよ ヽ。 ALD— Ti膜成膜処理は， 例えば TiCl ガスのみを供給した後に Arガスの供給と H ガスの供給とプラズマ生 [0074] Furthermore, as another Ti film deposition process, an ALD-Ti film deposition process using an atomic layered deposition (ALD) technique may be executed. The ALD-Ti film deposition process is performed, for example, by supplying only TiCl gas, then supplying Ar gas, supplying H gas, and generating plasma.
4 2  4 2
成とを同時期に行う工程を複数回繰返した後に， NH ガスの供給と Arガスの供給と  After repeating the process of simultaneous formation multiple times, the NH gas supply and Ar gas supply
3  Three
H ガスの供給とプラズマ発生とを同時期に行う工程を行うことによって， ALD-Ti By performing the process of supplying H gas and generating plasma at the same time, ALD-Ti
2 2
膜を成膜する処理である。  This is a process for forming a film.
[0075] また， TiCl ガスの供給と Arガスの供給とプラズマ生成とを同時期に行った後に H [0075] In addition, after supplying TiCl gas, Ar gas, and plasma generation at the same time, H
4 2 ガスを供給する工程を複数回繰返した後， NH ガスの供給と Arガスの供給と H  4 2 After repeating the gas supply process several times, supply NH gas, Ar gas, and H
3 2 ガスの供給とプラズマ発生とを同時期に行う工程を行うことによって， ALD— Ti膜を 成膜するようにしてもよ ヽ。  3 2 An ALD-Ti film may be formed by performing the process of supplying gas and generating plasma at the same time.
[0076] さらに， TiCl ガスの供給と Arガスの供給とプラズマ生成とを同時期に行った後に [0076] Further, after TiCl gas supply, Ar gas supply, and plasma generation are performed at the same time,
4  Four
H ガスの供給と Arガスの供給とプラズマ発生とを同時期に行う工程を複数回繰返し The process of supplying H gas, Ar gas, and generating plasma at the same time is repeated several times.
2 2
た後， NH ガスの供給と Arガスの供給と H ガスの供給とプラズマ発生とを同時期  After that, NH gas supply, Ar gas supply, H gas supply and plasma generation
3 2  3 2
に行う工程を行うことによって， ALD— Ti膜を成膜するようにしてもよい。  An ALD-Ti film may be formed by performing the steps described in (5).
[0077] 一方，第 2膜成膜処理としての TiN系膜成膜処理は，例えば上述したように、 TiCl [0077] On the other hand, the TiN film forming process as the second film forming process is, for example, as described above.
4 ガス及び NH ガスを反応ガスとして用い，設定温度を 500〜610°Cに設定として，  4 Gas and NH gas were used as reaction gases, and the set temperature was set to 500 to 610 ° C.
3  Three
熱 CVDにより TiN膜を成膜する処理である。  This is a process for forming a TiN film by thermal CVD.
[0078] (処理室の構成例） [0078] (Configuration example of processing chamber)
次に，上記のような処理を実行するための基板処理装置 100における処理室の構 成例 (配置例）を説明する。本実施の形態に係る基板処理装置 100は，上述したよう に、ウェハ上の自然酸ィ匕膜などの付着物を水成分を用いず且つプラズマによらない ガス成分との化学反応及び熱処理によって除去する付着物除去処理と，当該付着 物除去処理が施されたウェハ上に所定の薄膜を形成する成膜処理と、を連続して実 行するようになっている。 [0079] このため，処理室 104A〜104Dのうち、少なくとも 2つの処理室の一方が付着物除 去処理室として構成され他方が成膜処理室として構成される。 Next, a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 100 for performing the above processing will be described. As described above, the substrate processing apparatus 100 according to the present embodiment removes deposits such as a natural oxide film on a wafer by using a chemical reaction and a heat treatment with a gas component that does not use a water component and does not depend on a plasma. The deposit removal process to be performed and the film formation process for forming a predetermined thin film on the wafer subjected to the deposit removal process are continuously performed. [0079] For this reason, of the processing chambers 104A to 104D, one of at least two processing chambers is configured as a deposit removal processing chamber, and the other is configured as a film forming processing chamber.
[0080] また，付着物除去処理は、上述したように、複数段階の処理を連続して実行するよ うになつていてもよく，その場合には付着物除去処理室を複数の処理室で構成しても よい。具体的には、例えば上述したような生成物生成処理 (例えば COR処理）と生成 物除去処理 (例えば PHT処理）との 2段階の処理によって行う場合には、処理室 104 A〜104Dのうちの 2つの処理室を付着物除去処理室として構成してもよい。この場 合，一方の処理室が生成物生成処理室として構成され，他方の処理室が生成物除 去処理室として構成される。  [0080] In addition, as described above, the deposit removal processing may be performed in such a manner that a plurality of steps are continuously performed. In that case, the deposit removal processing chamber is constituted by a plurality of processing chambers. May be. Specifically, for example, in the case of performing the two-stage processing of the product generation processing (for example, COR processing) and the product removal processing (for example, PHT processing) as described above, one of the processing chambers 104A to 104D. Two processing chambers may be configured as the deposit removal processing chamber. In this case, one processing chamber is configured as a product generation processing chamber, and the other processing chamber is configured as a product removal processing chamber.
[0081] また、成膜処理は、異なる膜を連続して成膜するようにしてもょ ヽ。その場合には、 成膜処理室が複数の処理室で構成され得る。具体的には、第 1膜 (例えば Ti系膜)と 第 2膜 (例えば TiN系膜)とを連続して成膜する場合には、処理室 104A〜104Dのう ちの 2つの処理室が成膜処理室として構成され得る。この場合，一方の処理室が第 1 膜を成膜する第 1膜成膜処理室として構成され，他方の処理室が第 2膜を成膜する 第 2膜成膜処理室として構成される。このように，基板処理装置 100によって実行さ れる付着物除去処理と成膜処理との内容に応じて、各処理室 104A〜104Dの構成 が決定される。  [0081] Further, in the film forming process, different films may be successively formed. In that case, the film formation chamber may be constituted by a plurality of processing chambers. Specifically, when a first film (for example, a Ti-based film) and a second film (for example, a TiN-based film) are continuously formed, two processing chambers 104A to 104D are formed. It can be configured as a membrane treatment chamber. In this case, one processing chamber is configured as a first film deposition processing chamber for depositing the first film, and the other processing chamber is configured as a second film deposition processing chamber for depositing the second film. As described above, the configuration of each of the processing chambers 104A to 104D is determined according to the contents of the deposit removal process and the film forming process performed by the substrate processing apparatus 100.
[0082] ここで，例えばコンタクトホールまたはビアホールが形成されたウェハ Wが基板処理 装置 100に導入され，このウェハ Wに対して上述したような付着物除去処理としての COR処理及び PHT処理が連続して実行された後，成膜処理としての Ti膜成膜処理 及び TiN膜成膜処理が連続して実行される場合の基板処理装置 100における処理 室の構成例（配置例）を図 2に示す。  Here, for example, a wafer W in which contact holes or via holes are formed is introduced into the substrate processing apparatus 100, and the COR processing and the PHT processing as the deposit removal processing described above are continuously performed on the wafer W. Fig. 2 shows a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 100 when the Ti film forming process and the TiN film forming process as the film forming process are successively executed. .
[0083] 図 2に示す構成例では，処理室 104A, 104B, 104C, 104D力 それぞれ、 COR 処理室， PHT処理室， Ti膜成膜処理室， TiN膜成膜処理室として構成されている。 各処理室 104A〜104Dにおける処理は、それぞれ，後述する制御部 200の EC (装 置制御部） 300に設けられたプログラムデータ記憶手段 360に記憶されたプロセス処 理プログラム 364に基づいて実行される。すなわち， EC300の CPU310がプロセス 処理プログラム 364から必要な処理プログラムを読出し、処理データ記憶手段 370に 記憶されたプロセス処理情報 (例えばプロセスレシピ情報） 374から必要な情報を読 み出して、各処理を実行する。なお、制御部 200の構成の詳細は後述する。 In the configuration example shown in FIG. 2, the processing chambers 104A, 104B, 104C, and 104D are configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, and a TiN film deposition processing chamber, respectively. Processing in each of the processing chambers 104A to 104D is executed based on a process processing program 364 stored in program data storage means 360 provided in an EC (equipment control unit) 300 of the control unit 200 described later. . That is, the CPU 310 of the EC300 reads a necessary processing program from the process processing program 364 and stores it in the processing data storage means 370. Necessary information is read from the stored process processing information (for example, process recipe information) 374, and each processing is executed. Details of the configuration of the control unit 200 will be described later.
[0084] (基板搬送処理の具体例）  [0084] (Specific example of substrate transfer processing)
次に，図 2に示すような構成の基板処理装置 100におけるウェハ Wの搬送処理に ついて説明する。ウェハ Wに対する各処理室 104A〜104Dでの処理は上記の順序 で行われるので，ウェハ Wの搬送経路は図 2に示す実線矢印のようになる。このよう なウェハ搬送処理は，制御部 200の EC (装置制御部） 300に設けられる後述のプロ グラムデータ記憶手段 360に記憶された搬送処理プログラム 362に基づいて実行さ れる。すなわち， EC300の CPU310が処理データ記憶手段 370に記憶される搬送 処理情報 (例えば搬送経路情報） 372から必要な情報を読み出して、搬送処理プロ グラム 362を実行することによって、ウェハの搬送処理を実行するのである。  Next, the wafer W transfer process in the substrate processing apparatus 100 configured as shown in FIG. 2 will be described. Since the processing in the processing chambers 104A to 104D for the wafer W is performed in the order described above, the transfer path of the wafer W is as shown by the solid line arrows in FIG. Such wafer transfer processing is executed based on a transfer processing program 362 stored in a program data storage means 360 (described later) provided in an EC (Equipment Control Unit) 300 of the control unit 200. That is, the CPU 310 of the EC 300 reads the necessary information from the transfer processing information (for example, transfer path information) 372 stored in the processing data storage means 370 and executes the transfer processing program 362 to execute the transfer processing of the wafer. To do.
[0085] ここでは、一例として、中央の導入ポート 112Bに設置されたカセット (キャリアも含 む）から例えばコンタクトホールまたはビアホールが形成された処理前ウェハ Wが取り 出されるものとしている。また、 2つのロードロック室 108A, 108Bのうちのいずれか一 方のロードロック室，ここではロードロック室 108A、が処理前ウェハ Wの搬入用に用 いられ，他方のロードロック室 108Bが処理済ウェハ Wの搬出用に用いられる。今， 各処理室 104A〜104D内にはそれぞれウェハ Wが収容されていて、それぞれの処 理が終了している力、あるいは、ほぼ終了しかけているものとする。  Here, as an example, it is assumed that, for example, a pre-process wafer W in which a contact hole or a via hole is formed is taken out from a cassette (including a carrier) installed in the central introduction port 112B. In addition, one of the two load lock chambers 108A and 108B, in this case, the load lock chamber 108A, is used for loading the wafer W before processing, and the other load lock chamber 108B is used for processing. Used to carry out used wafer W. Now, it is assumed that the wafers W are accommodated in the processing chambers 104A to 104D, respectively, and the force at which each processing is completed or almost finished.
[0086] さて、先ず，搬入側搬送室 110内の搬送処理について説明する。搬出用のロード口 ック室 108B内に，処理室 104Dでの処理が終了した処理済のウェハ Wが収容され ているものとすると、この処理済ウェハ Wは，搬入側搬送機構 116によって、搬送経 路 XI 1に示すように、中央の導入ポート 112Bへ搬送されて収容される。  First, the transfer process in the carry-in transfer chamber 110 will be described. If the processed wafer W that has been processed in the processing chamber 104D is accommodated in the loading load chamber 108B for unloading, the processed wafer W is transferred by the loading-side transfer mechanism 116. As shown in route XI1, the material is transported to and accommodated in the central introduction port 112B.
[0087] 一方，中央の導入ポート 112Bに収容されている処理前のウェハ Wは，搬入側搬 送機構 116によって、搬送経路 XI 2に示すように、オリエンタ 114へ搬送される。そし て、オリエンタ 114で処理前のウェハ Wの位置合わせが行われる、その後，位置合わ せされた処理前のウェハ Wは、搬入側搬送機構 116によって、搬送経路 X13に示す ように、搬入用のロードロック室 108A内へ搬送され、収容される。処理前のウェハ W は、ロードロック室 108A内で待機する。以上の搬送操作は，ウェハ Wの処理が進む 毎に、繰り返し行われる。 On the other hand, the unprocessed wafer W accommodated in the central introduction port 112B is transferred to the orienter 114 by the loading-side transfer mechanism 116 as shown in the transfer path XI2. Then, the orientation of the unprocessed wafer W is performed by the orienter 114, and then the aligned unprocessed wafer W is loaded by the loading side transfer mechanism 116 as shown in the transfer path X13. It is transported and housed in the load lock chamber 108A. The wafer W before processing waits in the load lock chamber 108A. The above transfer operation advances the processing of wafer W. Repeated every time.
[0088] 次に，共通搬送室 102内でのウェハの搬送処理について説明する。先ず，搬送機 構 118によって、処理室 104Dに収容されていた処理済のウェハ Wが取り出され，搬 送経路 Yl 1に示すように、空き状態のロードロック室 108B内に搬送される。  Next, wafer transfer processing in the common transfer chamber 102 will be described. First, the processed wafer W accommodated in the processing chamber 104D is taken out by the transfer mechanism 118 and transferred into the empty load lock chamber 108B as shown in the transfer path Yl1.
[0089] 次いで，搬送機構 118によって、処理室 104C内に収容されていた処理済のゥェ ハ Wが取り出され，搬送経路 Y12に示すように、空き状態の処理室 104D内へ搬入 される。その後，処理室 104D内での処理が開始される。  Next, the processed wafer W accommodated in the processing chamber 104C is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104D as indicated by the transfer path Y12. Thereafter, processing in the processing chamber 104D is started.
[0090] 続いて，搬送機構 118によって、処理室 104B内に収容されていた処理済のウェハ Wが取り出され，搬送経路 Y13に示すように、空き状態の処理室 104C内へ搬入さ れる。その後，処理室 104C内での処理が開始される。  Subsequently, the processed wafer W accommodated in the processing chamber 104B is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104C as indicated by the transfer path Y13. Thereafter, processing in the processing chamber 104C is started.
[0091] 次いで，搬送機構 118によって、処理室 104A内に収容されていた処理済のゥェ ハ Wが取り出され，搬送経路 Y14に示すように、空き状態の処理室 104B内へ搬入 される。その後，処理室 104B内での処理が開始される。  Next, the processed wafer W accommodated in the processing chamber 104A is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104B as indicated by the transfer path Y14. Thereafter, processing in the processing chamber 104B is started.
[0092] 続いて，搬送機構 118によって、ロードロック室 108A内で待機していた処理前のゥ エノ、 Wが取り出され，搬送経路 Y15に示すように、空き状態の処理室 104A内へ搬 入される。その後，処理室 104A内での処理が開始される。  [0092] Subsequently, the unprocessed UE and W that were waiting in the load lock chamber 108A are taken out by the transfer mechanism 118, and are transferred into the empty process chamber 104A as shown in the transfer path Y15. Is done. Thereafter, processing in the processing chamber 104A is started.
[0093] なお，ウェハ Wの搬出入の際には，各ゲートバルブ 106A〜106D, 107A, 107B のうち必要なゲートバルブのみが開閉操作される。また、各処理室 104A〜104Dに てウエノ、 Wの処理が完了する毎に、上記の操作が繰り返し行われる。  [0093] When the wafer W is loaded / unloaded, only the necessary gate valves among the gate valves 106A to 106D, 107A, 107B are opened / closed. In addition, the above operation is repeated each time the processing of Ueno and W is completed in each of the processing chambers 104A to 104D.
[0094] このようにして，コンタクトホールまたはビアホールが形成された処理前のウェハ W に対して、処理室 104A〜処理室 104Dにて、それぞれ COR処理， PHT処理， Ti膜 成膜処理， TiN膜成膜処理が連続して施される。従って，ウェハ Wのコンタクトホー ルまたはビアホールの内壁には， COR処理及び PHT処理によって自然酸化膜など の付着物が除去された状態で， Ti膜成膜処理及び TiN膜成膜処理によって Ti膜及 び TiN膜のバリア層が成膜される。  [0094] In this way, for the unprocessed wafer W on which contact holes or via holes are formed, in the processing chamber 104A to the processing chamber 104D, COR processing, PHT processing, Ti film deposition processing, TiN film, respectively. The film forming process is continuously performed. Therefore, on the inner wall of the contact hole or via hole of the wafer W, the deposits such as the natural oxide film are removed by the COR process and the PHT process, and the Ti film and the TiN film are formed. And a TiN barrier layer is formed.
[0095] これにより，膜の密着性及び強度が向上される。また，ウェハの下地膜にプラズマ 起因のチャージアップダメージを負わせることが防止されるので，ダメージのな 、配 線加工を行うことができ，良好なコンタクト抵抗を有する膜を成膜することができる。 [0096] なお，各処理室 104A〜104Dの構成（配置）は、図 2に示すものに限られない。各 処理室 104A〜104Dのうちのどの処理室を COR処理室， PHT処理室， Ti膜成膜 処理室， TiN膜成膜処理室として構成してもよい。従って，ウェハの搬送順序につい ても， COR処理室→PHT処理室→Ti膜成膜処理室→TiN膜成膜処理室と ヽぅ順 に搬送されるので，処理室 104A→処理室 104B→処理室 104C→処理室 104Dと いう順でなくてもよい。 This improves the adhesion and strength of the film. In addition, since it is possible to prevent plasma-induced charge-up damage from being applied to the underlying film of the wafer, wiring processing can be performed without damage, and a film having good contact resistance can be formed. . [0096] The configuration (arrangement) of the processing chambers 104A to 104D is not limited to that shown in FIG. Any of the processing chambers 104A to 104D may be configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, or a TiN film deposition processing chamber. Therefore, the wafers are transferred in the order of COR processing chamber → PHT processing chamber → Ti film deposition processing chamber → TiN film deposition processing chamber, so that processing chamber 104A → processing chamber 104B → processing The order of the chamber 104C → the processing chamber 104D is not necessary.
[0097] (制御部の構成例）  [0097] (Configuration example of control unit)
次に、基板処理装置 100の制御部 200の構成例を図 3を参照しながら説明する。 図 3は，制御部（システムコントローラ） 200の構成例を示すブロック図である。図 3に 示すように，制御部 200は，装置制御部（EC Equipment Controller) 300と，複数の モジュール制御部（MC : Module Controller) 230A, 230B, 230C…と， EC300と 各 MC230A, 230B, 230C…とをそれぞれ接続するスイッチングハブ（HUB) 220 と、を備えている。  Next, a configuration example of the control unit 200 of the substrate processing apparatus 100 will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration example of the control unit (system controller) 200. As shown in Fig. 3, the control unit 200 includes an equipment control unit (EC Equipment Controller) 300, a plurality of module controllers (MC) 230A, 230B, 230C ..., EC300, and MC230A, 230B, 230C. And a switching hub (HUB) 220 for connecting the.
[0098] 制御部 200の EC300は、例えば LAN (Local Area Network) 202を介して、基板 処理装置 100が設置される工場全体の製造工程を管理する MES (Manufacturing E xecution System) 204に接続されている。 MES204は例えばコンピュータにより構成 される。 MES204は，制御部 200と連携して、工場における各種工程に関するリアル タイム情報を基幹業務システム（図示しない）にフィードバックするとともに，工場全体 の負担等を考慮して各種工程に関する判断を行う（あるいは判断を支援する）ように なっている。  [0098] The EC 300 of the control unit 200 is connected to, for example, a MES (Manufacturing Execution System) 204 that manages the manufacturing process of the entire factory where the substrate processing apparatus 100 is installed, via a LAN (Local Area Network) 202. Yes. The MES 204 is configured by a computer, for example. In cooperation with the control unit 200, the MES 204 feeds back real-time information on various processes in the factory to the core business system (not shown) and makes decisions on various processes in consideration of the burden of the entire factory (or the determination). Support).
[0099] EC300は， MC230A, 230B, 230C…を統括して基板処理装置 100全体の動作 を制御する主制御部（マスタ制御部）を構成する。スイッチングハブ 220は， EC300 力らの帘 U御信号に応じて、 EC300の接続先としての MC230A, 230B, 230C…を 切換える。  [0099] The EC 300 constitutes a main control unit (master control unit) that controls the overall operation of the substrate processing apparatus 100 by supervising MC 230A, 230B, 230C,. The switching hub 220 switches MC230A, 230B, 230C ... as the connection destination of EC300 according to the input signal of EC300 power.
[0100] 各 MC230A, 230B, 230C…は、それぞれ，基板処理装置 100の共通搬送室 10 2,処理室 104A〜104D,ロードロック室 108A, 108B,搬送室 110,オリエンタ 11 4等の各モジュールの動作を制御する副制御部 (スレーブ制御部）を構成する。各 M C230A, 230B, 230C…は、それぞれ， DIST (Distribution)ボード 234A, 234B, 234C…によって、例えば GHOSTネットワーク 206を介して、各 I/O (入出力）モジ ユーノレ 236A, 236B, 236。· · ·【こ接続されて!ヽる。ここで、 GHOSTネットワーク 206 とは， MC (モジュール制御部）に搭載された GHOST (General High-Speed Optimu m Scalable Transceiver)と称される LSIによって実現されるネットワークである。 GHO STネットワーク 206には、最大で 31個の I/Oモジュールを接続することができる。な お， GHOSTネットワーク 206では、 MCがマスタに相当し， I/Oモジュールがスレー ブに相当する。 [0100] Each of the MC230A, 230B, 230C,... Has a common transfer chamber 102 of the substrate processing apparatus 100, a processing chamber 104A to 104D, a load lock chamber 108A, 108B, a transfer chamber 110, an orienter 114, etc. Configures the sub-control unit (slave control unit) that controls the operation. Each M C230A, 230B, 230C ... has a DIST (Distribution) board 234A, 234B, Each I / O (input / output) module 236A, 236B, 236, for example, via the GHOST network 206 by 234C. · · · [This is connected! Here, the GHOST network 206 is a network realized by an LSI called GHOST (General High-Speed Optimum Scalable Transceiver) installed in MC (module control unit). Up to 31 I / O modules can be connected to the GHO ST network 206. In the GHOST network 206, MC corresponds to the master and the I / O module corresponds to the slave.
[0101] 各 I/Oモジュール 236A, 236B, 236C…は、それぞれ，処理室 104A〜104D などの各モジュールの各構成要素（以下， 「エンドデバイス」と称する。）に接続された 複数の IZO部 238A, 238Β, 238C…力 なり，各エンドデバイスへの制御信号の 供給 (伝達)及び各エンドデバイスからの出力信号の受信 (伝達)を行う。例えば、処 理室 104のエンドデバイスとしては，処理室 104内に導入されるガスの流量を制御す るマスフローコントローラ及び処理室 104からの排気を制御する APCバルブ、などが 挙げられる。  [0101] Each I / O module 236A, 236B, 236C ... is a plurality of IZO units connected to each component of each module (hereinafter referred to as "end device") such as the processing chambers 104A to 104D. 238A, 238Β, 238C… Power, and supply (transmit) control signals to each end device and receive (transmit) output signals from each end device. For example, examples of the end device of the processing chamber 104 include a mass flow controller that controls the flow rate of the gas introduced into the processing chamber 104 and an APC valve that controls exhaust from the processing chamber 104.
[0102] 各 GHOSTネットワーク 206には， I/O部 238A, 238B, 238C…におけるデジタ ル信号，アナログ信号，シリアル信号の入出力を制御する IZOボード（図示しない） も接続される。  [0102] Each GHOST network 206 is also connected to an IZO board (not shown) that controls input / output of digital signals, analog signals, and serial signals in the I / O units 238A, 238B, 238C,.
[0103] ここで，図 3に示す EC300の構成例について、図 4を参照しながら説明する。図 4 は EC300の構成例を示すブロック図である。図 4に示すように， EC300は、 EC本体 を構成する CPU (中央処理装置） 310と， CPU310が行う各種データ処理のために 使用されるメモリエリア等が設けられた RAM (ランダム ·アクセス 'メモリ） 320と，操作 画面や選択画面などを表示する液晶ディスプレイなどで構成される表示手段 330と， オペレータによるプロセスレシピの入力や編集など種々のデータの入力及び所定の 記憶媒体へのプロセスレシピゃプロセス 'ログの出力など種々のデータの出力を行う ことができる入出力手段 340と，基板処理装置 100に漏電等の異常が発生した際に 報知する警報器 (例えばブザー)などの報知手段 350と、を備えて 、る。  Here, a configuration example of the EC 300 shown in FIG. 3 will be described with reference to FIG. Fig. 4 is a block diagram showing a configuration example of EC300. As shown in Fig. 4, the EC300 is a RAM (Random Access Memory) with a CPU (Central Processing Unit) 310 that constitutes the EC main unit and a memory area that is used for various data processing performed by the CPU 310. ) 320, display means 330 composed of a liquid crystal display that displays the operation screen and selection screen, etc., input of various data such as process recipe input and editing by the operator, and process recipe processing to a predetermined storage medium 'Input / output means 340 that can output various data such as log output, and notification means 350 such as an alarm device (for example, a buzzer) that notifies when an abnormality such as leakage occurs in the substrate processing apparatus 100; It is equipped with.
[0104] また， EC300は，基板処理装置 100の種々の処理を実行するための処理プロダラ ムを記憶するプログラムデータ記憶手段 360と，前記処理プログラムを実行するため に必要な情報 (データ）が記憶される処理データ記憶手段 370と、を更に備える。プ ログラムデータ記憶手段 360及び処理データ記憶手段 370は、例えばノヽードデイス ク (HDD)などの記憶領域に構築される。 [0104] Further, the EC 300 has a program data storage means 360 for storing processing programs for executing various processes of the substrate processing apparatus 100, and a program data storage means 360 for executing the processing programs. Processing data storage means 370 in which information (data) necessary for the storage is stored. The program data storage means 360 and the processing data storage means 370 are constructed in a storage area such as a node disk (HDD).
[0105] CPU310と， RAM320と，表示手段 330と，入出力手段 340と，報知手段 350と， プログラムデータ記憶手段 360と，処理データ記憶手段 370等とは，制御バスゃデ ータバス等のバスラインにより接続されている。このノ スラインには，上記スイッチング ハブ 220なども接続されて 、る。 [0105] CPU 310, RAM 320, display means 330, input / output means 340, notification means 350, program data storage means 360, processing data storage means 370, etc. are a bus line such as a control bus or a data bus. Connected by. The nose line is also connected to the switching hub 220 and the like.
[0106] CPU310は、必要に応じて、プログラムデータ記憶手段 360及び処理データ記憶 手段 370から必要なプログラムや必要なデータを読み出して，各種の処理プログラム を実行する。 The CPU 310 reads necessary programs and necessary data from the program data storage means 360 and the processing data storage means 370 as necessary, and executes various processing programs.
[0107] ここで，上述したような構成の制御部 200による基板処理装置 100の制御例につい て説明する。  [0107] Here, an example of control of the substrate processing apparatus 100 by the control unit 200 having the above-described configuration will be described.
[0108] 各処理室 104A〜104Dにおいて，例えばウェハ Wに上述したような COR処理， P HT処理， Ti膜成膜処理， TiN膜成膜処理などのプロセス処理が施される場合， EC 300の CPU310は、プログラムデータ記憶手段 360のプロセス処理プログラム 364 力 実行する処理プログラムを読出し，また、処理データ記憶手段 370のプロセス処 理情報 374から実行する処理に対応するプロセスレシピの情報を読出し、これらに基 づいて各処理を実行する。より具体的には， CPU310は，各処理プログラムに応じて 、スイッチングハブ 220、処理室 104A〜104Dを制御する MC230, GHOSTネット ワーク 206及び IZOモジュール 236における IZO部 238を介して，所望のエンドデ バイスに制御信号を送信することによって各処理を実行する。  [0108] In each of the processing chambers 104A to 104D, for example, when the wafer W is subjected to processing such as the above-described COR processing, PHT processing, Ti film forming processing, TiN film forming processing, etc. The CPU 310 reads the process processing program to be executed in the program data storage means 360 and reads out the process recipe information corresponding to the processing to be executed from the process processing information 374 in the processing data storage means 370. Each process is executed based on this. More specifically, the CPU 310 performs a desired end device via the MC230, the GHOST network 206, and the IZO module 236 in the IZO module 236, which control the switching hub 220, the processing chambers 104A to 104D, according to each processing program. Each process is executed by transmitting a control signal to the.
[0109] 例えば COR処理室として構成された処理室 104Aにおいて，ウェハ Wに COR処 理が施される場合について説明する。この場合， CPU310は、処理室 104Aのガス 導入系のマスフローコントローラ（例えばアンモニアガス供給管及び弗化水素ガス供 給管のマスフローコントローラ）に制御信号を送信することによって、処理室 104Aに おけるアンモニアガス及び弗化水素ガスの体積流量比を所望の値に調節する一方， 排気系の真空ポンプ (例えば ΤΜΡ)及び圧力調整バルブ (例えば APCバルブ）に制 御信号を送信することによって、処理室 104A内の圧力を所望の値に調整する。この とき，圧力計が処理室 104A内の圧力値を出力信号として EC300の CPU310に送 信する。 CPU310は、送信されてきた処理室 104A内の圧力値に基づいて，アンモ ニァガス供給管及び弗化水素ガス供給管のマスフローコントローラや， APCバルブ 及び TMPの制御パラメータ等を決定 (修正)する。 [0109] For example, a case where COR processing is performed on the wafer W in the processing chamber 104A configured as a COR processing chamber will be described. In this case, the CPU 310 sends ammonia gas in the processing chamber 104A by transmitting a control signal to the mass flow controller of the gas introduction system in the processing chamber 104A (for example, the mass flow controller of the ammonia gas supply pipe and the hydrogen fluoride gas supply pipe). In addition, the volume flow ratio of hydrogen fluoride gas and the volume flow ratio of hydrogen fluoride gas are adjusted to a desired value, while a control signal is sent to the vacuum pump (for example, ΤΜΡ) and pressure control valve (for example, APC valve) in the exhaust system. Is adjusted to a desired value. this At this time, the pressure gauge sends the pressure value in the processing chamber 104A to the CPU 310 of the EC300 as an output signal. The CPU 310 determines (corrects) the mass flow controller of the ammonia gas supply pipe and the hydrogen fluoride gas supply pipe, the control parameters of the APC valve and the TMP, etc., based on the transmitted pressure value in the processing chamber 104A.
[0110] また、 PHT処理室として構成された処理室 104Bにおいて，ウェハ Wに PHT処理 が施される場合について説明する。この場合、 CPU310は、処理室 104Bのガス供 給系のマスフローコントローラ（例えば窒素ガス供給管のマスフローコントローラ）及び 排気系の圧力調整バルブ (例えば APCバルブ）に制御信号を送信することによって 、処理室 104B内の圧力を所望の値に調整する。一方，ステージヒータに制御信号を 送信することによってウエノ、 Wの温度を所望の温度に調整する。このとき，圧力計が 処理室 104B内の圧力値を出力信号として EC300の CPU310に送信する。 CPU3 10は、送信されてきた処理室 104B内の圧力値に基づいて，窒素ガス供給管の MF Cや APCバルブ 69の制御パラメータを決定 (修正）する。  [0110] The case where the PHT process is performed on the wafer W in the process chamber 104B configured as the PHT process chamber will be described. In this case, the CPU 310 transmits a control signal to the gas flow system mass flow controller (for example, the mass flow controller of the nitrogen gas supply pipe) and the exhaust system pressure adjustment valve (for example, the APC valve) of the processing chamber 104B. Adjust the pressure in 104B to the desired value. On the other hand, the temperature of Ueno and W is adjusted to the desired temperature by sending a control signal to the stage heater. At this time, the pressure gauge sends the pressure value in the processing chamber 104B to the CPU 310 of the EC300 as an output signal. The CPU 310 determines (corrects) the control parameters of the nitrogen gas supply pipe MFC and the APC valve 69 based on the transmitted pressure value in the processing chamber 104B.
[0111] 図 3に示す制御部（システムコントローラ） 200では，複数のエンドデバイスが EC30 0に直接接続されな 、で，複数のエンドデバイスに接続された IZO部がモジュール 化されて ΙΖΟモジュールを構成している。この ΙΖΟモジュール力 MC230及びスィ ツチングノヽブ 220を介して EC300に接続されているため，通信系統が簡素化され得 る。  [0111] In the control unit (system controller) 200 shown in Fig. 3, multiple end devices are not directly connected to EC300, so the IZO unit connected to multiple end devices is modularized to form a ΙΖΟ module. is doing. Because it is connected to EC300 via this module power MC230 and switching knob 220, the communication system can be simplified.
[0112] ここで， EC300の CPU310が送信する制御信号には，所望のエンドデバイスに接 続された ΙΖΟ部のアドレス，及び、その ΙΖΟ部を含む ΙΖΟモジュールのアドレスが 含まれている。このため，スイッチングハブ 220は、制御信号における ΙΖΟモジユー ルのアドレスを参照し， MC230の GHOST206も、制御信号における I/O部のアド レスを参照することができる。すなわち，スイッチングハブ 220と MC230とが CPU31 0に制御信号の送信先の問い合わせを行う必要が無い。これにより，制御信号の円 滑な伝達を実現することができる。  [0112] Here, the control signal transmitted by the CPU 310 of the EC300 includes the address of the collar connected to the desired end device and the address of the module including the collar. Therefore, the switching hub 220 can refer to the address of the input module in the control signal, and the GHOST 206 of the MC230 can also refer to the address of the I / O section in the control signal. That is, there is no need for the switching hub 220 and MC 230 to inquire the CPU 310 about the control signal transmission destination. This enables smooth transmission of control signals.
[0113] このように，第 1の実施の形態に係る基板処理装置 100では，成膜処理を行う前に ,ウェハに付着された自然酸ィ匕膜などの付着物がプラズマを用いな 、付着物除去処 理 (例えば COR処理及び ΡΗΤ処理)を実行することによって除去された後， 当該ゥ ェハを大気に露出することなぐ連続して成膜処理を実行することができるため，膜の 密着性と強度とを向上させることができる。また，プラズマを用いないで自然酸ィ匕膜を 除去できるので，ダメージのない配線力卩ェを行うことができ，良好なコンタクト抵抗を 有する膜を成膜することができる。 As described above, in the substrate processing apparatus 100 according to the first embodiment, before the film forming process, deposits such as a natural oxide film attached to the wafer do not use plasma. After removal by executing a kimono removal process (for example, COR process and dredging process), Since film deposition can be performed continuously without exposing the wafer to the atmosphere, the adhesion and strength of the film can be improved. In addition, since the natural oxide film can be removed without using plasma, a wiring force without damage can be achieved, and a film having good contact resistance can be formed.
[0114] なお，上記のようにコンタクトホールまたはビアホールのバリア層を成膜する処理で は，前工程として COR処理及び PHT処理を行うことが有効であることを説明した。し かしながら，成膜処理としてはこれに限られるものではなく，以下のような他の成膜処 理の前工程として COR処理及び PHT処理を行うようにしてもよ!、。  [0114] As described above, it has been explained that the COR process and the PHT process are effective as the previous processes in the process of forming the contact hole or via hole barrier layer. However, the film forming process is not limited to this, and COR processing and PHT processing may be performed as a pre-process of other film forming processes as follows!
[0115] (成膜処理の他の具体例）  [0115] (Other specific examples of film formation)
ここで，本発明に適用可能な成膜処理の他の具体例について説明する。ここでは， 前工程として COR処理及び PHT処理を行うことが有効な成膜処理として、 MOSFE Tなどの MOSデバイスのゲート絶縁膜を高誘電体 (High— K)材料により成膜する 処理について説明する。  Here, another specific example of the film forming process applicable to the present invention will be described. Here, as an effective film-forming process, the process of forming the gate insulating film of a MOS device such as MOSFET with a high dielectric (High-K) material is explained as the pre-process. .
[0116] MOSデバイスのゲート絶縁膜は，微細化の進展により，近年ではシリコン酸ィ匕膜相 当で lnm以下の厚さの膜が必要とされて 、る。これは 3〜4原子層の厚さに相当する 。このくらい薄くなると，トンネル電流の増大，ゲート電極にドープした元素の拡散，信 頼性の低下等により，シリコン酸ィ匕膜は使えない。このため，誘電率が高い膜 (いわ ゆる High— K膜)の開発が非常な勢いで進められている。すなわち， ZrO , HfO  [0116] With the progress of miniaturization, the gate insulating film of MOS devices has recently been required to have a thickness of less than lnm, equivalent to a silicon oxide film. This corresponds to a thickness of 3-4 atomic layers. At such a thin thickness, the silicon oxide film cannot be used due to an increase in tunneling current, diffusion of elements doped in the gate electrode, and a decrease in reliability. For this reason, the development of films with a high dielectric constant (so-called High-K films) is proceeding with great speed. That is, ZrO, HfO
2 2 などの遷移金属酸化膜， La O などの希土類酸ィ匕膜、及び、それらのシリケートな  Transition metal oxide films such as 2 2, rare earth oxide films such as La 2 O, and silicates thereof
2 3  twenty three
どが，高い誘電率を有すること，高い熱的安定性を有すること，及び、 Si中の正孔と 電子に対して高いエネルギー障壁を有することから，次世代の MOSFETなどの MO Sデバイスにおけるゲート絶縁膜として精力的に研究されている。  However, it has a high dielectric constant, high thermal stability, and a high energy barrier against holes and electrons in Si. It is energetically studied as an insulating film.
[0117] ところが、これらの高誘電率膜と Si基板との間には，シリケートからなる組成遷移層 が形成され，シリケート層と Si基板の間に Siの中間酸ィ匕状態カゝらなる組成遷移層が 形成されてしまう。従って，これら組成遷移層が形成されることを防止するために，先 に酸ィ匕防止層としてベース酸ィ匕膜 (例えば SiO 膜)を成膜する必要がある。このよう [0117] However, a composition transition layer composed of silicate is formed between these high dielectric constant films and the Si substrate, and a composition consisting of an intermediate state of Si intermediate state between the silicate layer and the Si substrate. A transition layer is formed. Therefore, in order to prevent these composition transition layers from being formed, it is necessary to first form a base oxide film (for example, an SiO film) as an oxidation prevention layer. like this
2  2
にベース酸ィ匕膜をシリケート層と Si基板との間に介在させることによって、デバイス特 性の劣化，つまり移動度の低下を防止することができる。 [0118] このような高誘電体 (High— K)材料によるゲート絶縁膜の成膜に際しては、原子 層レベルでの制御が必要である。このため，ゲート絶縁膜の成膜処理を実行する前 に，プラズマを用いな 、ドライクリーニングである付着物除去処理 (例えば COR処理 及び PHT処理)を実行して自然酸ィ匕膜などの付着物を除去することによって，膜の 密着性と強度とを向上させることができる。 In addition, by interposing the base oxide film between the silicate layer and the Si substrate, it is possible to prevent deterioration of device characteristics, that is, decrease in mobility. [0118] When forming a gate insulating film with such a high dielectric (High-K) material, control at the atomic layer level is required. For this reason, before performing the film formation process of the gate insulating film, a deposit removal process (for example, a COR process and a PHT process), which is dry cleaning, is performed without using plasma to perform deposits such as a natural oxide film. By removing the film, the adhesion and strength of the film can be improved.
[0119] また，もしプラズマを用いて自然酸ィ匕膜を除去すれば，ゲート絶縁膜を成膜する下 地にプラズマ励起のチャージアップダメージを負わせてしまう虞がある。このように下 地にダメージを残したままゲート酸ィ匕膜を成膜すると，そのダメージの程度によっては 、ゲート酸ィ匕膜の破壊を招いて， MOSデバイス自体の特性が劣化する虞がある。こ の点，本実施の形態に係る付着物除去処理 (例えば COR処理及び PHT処理）によ れば，プラズマが用いられないため，ゲート絶縁膜を成膜する下地にダメージを与え ることがない。このため， MOSデバイスの特性が劣化することを防止することができる  [0119] Moreover, if the natural oxide film is removed using plasma, there is a risk that plasma-excited charge-up damage will be caused to the underlying layer on which the gate insulating film is formed. If a gate oxide film is formed with damages left in this manner, depending on the extent of the damage, the gate oxide film may be destroyed and the characteristics of the MOS device itself may be degraded. . In this regard, according to the deposit removal processing (for example, COR processing and PHT processing) according to the present embodiment, since the plasma is not used, the substrate on which the gate insulating film is formed is not damaged. . This prevents the degradation of MOS device characteristics.
[0120] このような高誘電体 (High— K)材料のゲート絶縁膜 (高誘電体ゲート絶縁膜)を成 膜する処理においては，ウェハ上すなわちシリコン基板上に、非常に薄い，好ましく は lnm以下の膜厚の、 SiO 膜などのベース酸ィ匕膜を先に成膜した後で， High— K [0120] In the process of forming a gate dielectric film (high dielectric gate dielectric film) of such a high dielectric (High-K) material, it is very thin, preferably lnm on the wafer, that is, on the silicon substrate. After the base oxide film such as SiO film with the following thickness is formed first, High-K
2  2
膜 (例えば HfSiO などのシリケート膜)が成膜される。ここで，ベース酸化膜成膜処  A film (for example, a silicate film such as HfSiO) is formed. Here, the base oxide film is formed.
2  2
理が前記第 1膜成膜処理に相当し， High— K膜成膜処理が前記第 2膜成膜処理に 相当する。  The reason corresponds to the first film forming process, and the High-K film forming process corresponds to the second film forming process.
[0121] ベース酸化膜成膜処理 (第 1膜成膜処理)は，例えば紫外光励起酸素ラジカルを 使ったラジカル酸ィ匕処理によって行われる。具体的には、シリコン基板の紫外光励起 ラジカル酸ィ匕処理によって， 2〜3分子層に相当する膜厚のベース酸ィ匕膜を安定に 再現性良く形成することができる。このように、酸素ラジカルによって、シリコン基板上 の表面にベース酸ィ匕膜として例えば略 0. 5nm程度の SiO 原子層が形成される。こ  [0121] The base oxide film deposition process (first film deposition process) is performed, for example, by radical oxidation using an ultraviolet photoexcited oxygen radical. Specifically, a base oxide film having a film thickness equivalent to two to three molecular layers can be formed stably and with good reproducibility by the treatment of a silicon substrate with ultraviolet light-excited radical acid. As described above, an oxygen atomic layer forms a SiO atom layer of, for example, about 0.5 nm as a base oxide film on the surface of the silicon substrate. This
2  2
の場合の処理時間は、例えば 300秒である。  In this case, the processing time is, for example, 300 seconds.
[0122] High— K膜成膜処理 (第 2膜成膜処理)では，ベース酸化膜成膜処理によってべ 一ス酸ィ匕膜が形成されたウェハ上に，例えば有機金属化学気相堆積 (MOCVD)法 などにより、金属酸ィ匕膜 (例えば HfSiO などのシリケート膜)が形成される。具体的 には、例えばベース酸ィ匕膜として SiO 原子層が形成された基板を 400〜600°Cに [0122] In the high-K film deposition process (second film deposition process), for example, metalorganic chemical vapor deposition (on the wafer with the base oxide film formed by the base oxide film deposition process ( A metal oxide film (for example, a silicate film such as HfSiO) is formed by the MOCVD method. concrete For example, a substrate on which an SiO atomic layer is formed as a base oxide film is heated to 400 to 600 ° C.
2  2
加熱した状態で，基板上に原料ガスが導入されると，当該原料ガスが分解して、基板 上に例えば HfSiO などのシリケート膜の薄膜が形成される。この場合の処理時間と  When a source gas is introduced onto the substrate in a heated state, the source gas is decomposed to form a thin film of a silicate film such as HfSiO on the substrate. Processing time in this case and
2  2
しては、例えば 343秒である。  For example, it is 343 seconds.
[0123] (処理室の他の構成例） [0123] (Other configuration examples of the processing chamber)
次に，このような処理を実行するための基板処理装置 100における処理室の構成 例を説明する。本実施の形態に係る基板処理装置 100は， COR処理， PHT処理， ベース酸化膜成膜処理 (UV処理) , High— K膜成膜処理 (MOCVD処理)を連続 して実行する。  Next, a configuration example of the processing chamber in the substrate processing apparatus 100 for performing such processing will be described. The substrate processing apparatus 100 according to the present embodiment continuously performs COR processing, PHT processing, base oxide film forming processing (UV processing), and high-K film forming processing (MOCVD processing).
[0124] このため，処理室 104A〜104Dのうち、少なくとも 2つの処理室力 それぞれ、 CO R処理， PHT処理を実行する付着物除去処理室として構成され，他の 2つの処理室 力 それぞれ、酸化膜成膜処理 (UV処理)， High— K膜成膜処理 (MOCVD処理） を実行する成膜処理室として構成される。  [0124] For this reason, at least two of the processing chambers 104A to 104D are configured as deposit removal processing chambers that perform COR processing and PHT processing, respectively, and the other two processing chamber forces are oxidized. It is configured as a film formation chamber that performs film formation (UV treatment) and high-K film formation (MOCVD).
[0125] ここで，基板処理装置 100における処理室 104A, 104B, 104C, 104D力 それ ぞれ、 COR処理室， PHT処理室，酸化膜成膜処理 (UV処理)室， High— K膜成膜 処理 (MOCVD処理)室として構成された例を図 5に示す。酸化膜成膜処理 (UV処 理）室における処理，及び、 High— K膜成膜処理 (MOCVD処理）室における処理 については，それぞれ、上述した制御部 200の EC (装置制御部） 300のプログラム データ記憶手段 360に記憶されたプロセス処理プログラム 364に基づいて実行され る。 EC300の CPU310は、プロセス処理プログラム 364から必要な処理プログラムを 読出すと共に、処理データ記憶手段 370に記憶されたプロセス処理情報 (例えばプ ロセスレシピ情報） 374から必要な情報を読み出して、各処理を実行する。  [0125] Here, the processing chamber 104A, 104B, 104C, and 104D forces in the substrate processing apparatus 100 are respectively COR processing chamber, PHT processing chamber, oxide film deposition processing (UV processing) chamber, and High-K film deposition. Figure 5 shows an example of a process (MOCVD process) chamber. Regarding the processing in the oxide film deposition process (UV process) chamber and the process in the High-K film deposition process (MOCVD process) chamber, the EC (equipment control unit) 300 program of the control unit 200 described above, respectively. It is executed based on the process processing program 364 stored in the data storage means 360. The CPU 310 of the EC300 reads out the necessary processing program from the process processing program 364 and reads out the necessary information from the process processing information (for example, process recipe information) 374 stored in the processing data storage means 370 to perform each processing. Execute.
[0126] なお，各処理室 104A〜104Dを図 5に示すように構成した場合の基板処理装置 1 00におけるウェハ Wの搬送については，図 2に示す構成の場合と同様であるため， その詳細な説明を省略する。  Note that the transfer of the wafer W in the substrate processing apparatus 100 when the processing chambers 104A to 104D are configured as shown in FIG. 5 is the same as that in the configuration shown in FIG. The detailed explanation is omitted.
[0127] (第 2の実施の形態に係る基板処理装置の構成例）  (Configuration example of substrate processing apparatus according to second embodiment)
次に，第 2の実施の形態に係る基板処理装置の構成例を図面を参照しながら説明 する。図 6は、第 2の実施の形態に係る基板処理装置の概略構成図である。図 6に示 すように，基板処理装置 101では、複数の処理室と共通搬送室とを有する真空処理 装置が、複数連結されている。このような構成の基板処理装置 101においても、本発 明を適用することができる。 Next, a configuration example of the substrate processing apparatus according to the second embodiment will be described with reference to the drawings. FIG. 6 is a schematic configuration diagram of a substrate processing apparatus according to the second embodiment. Shown in Figure 6 As described above, in the substrate processing apparatus 101, a plurality of vacuum processing apparatuses having a plurality of processing chambers and a common transfer chamber are connected. The present invention can also be applied to the substrate processing apparatus 101 having such a configuration.
[0128] 図 6に示す基板処理装置 101では，図 1に示す基板処理装置 100における共通搬 送室が第 1共通搬送室 102として表されて 、る。第 1共通搬送室 102と 2つのロード口 ック室 108A, 108Bとの間に、別の第 2共通搬送室 120が介在されている。第 2共通 搬送室 120は，略多角形 (例えば変則的な七角形）に構成されており，その 2つの辺 に 2つの処理室 104E, 104Fがそれぞれゲートバルブ 106E, 106Fを介して連結さ れている。なお，第 1共通搬送室 102とこれに接続される 4つの処理室 (処理室 104 A〜104D)とを有する真空処理装置は、第 1真空処理装置の一例であり，第 2共通 搬送室 120とこれに接続される 2つの処理室（処理室 104E, 104F)とを有する真空 処理装置は、第 2真空処理装置の一例である。  In the substrate processing apparatus 101 shown in FIG. 6, the common transfer chamber in the substrate processing apparatus 100 shown in FIG. 1 is represented as the first common transfer chamber 102. Another second common transfer chamber 120 is interposed between the first common transfer chamber 102 and the two load port chambers 108A and 108B. The second common transfer chamber 120 has a substantially polygonal shape (eg, an irregular heptagon), and two processing chambers 104E and 104F are connected to the two sides via gate valves 106E and 106F, respectively. ing. The vacuum processing apparatus having the first common transfer chamber 102 and the four processing chambers (process chambers 104A to 104D) connected to the first common transfer chamber 102 is an example of the first vacuum processing apparatus. And the two processing chambers (processing chambers 104E and 104F) connected thereto are examples of the second vacuum processing apparatus.
[0129] 第 1共通搬送室 102と第 2共通搬送室 120との間には，両共通搬送室 102, 120を 連通すると共にウェハ Wを一時的に保持できるパス部 122が設けられている。第 1共 通搬送室 102と第 2共通搬送室 120との間でウェハを搬送する際には，このパス部 1 22にてウェハ Wが一時的に保持されるようになっている。この場合，第 1共通搬送室 102の形状は，パス部 122を連結するために、変則的な七角形に成形されている。 第 1共通搬送室 102とパス部 122の接合部には、ゲートバルブ 126が設けられている 。このゲートバルブ 126を開閉することにより，両共通搬送室 102, 120間の連通及 び遮断が可能である。  [0129] Between the first common transfer chamber 102 and the second common transfer chamber 120, there is provided a pass section 122 that allows the two common transfer chambers 102 and 120 to communicate with each other and to temporarily hold the wafer W. When the wafer is transferred between the first common transfer chamber 102 and the second common transfer chamber 120, the wafer W is temporarily held by the pass portion 122. In this case, the shape of the first common transfer chamber 102 is formed into an irregular heptagon in order to connect the path portion 122. A gate valve 126 is provided at the junction between the first common transfer chamber 102 and the pass portion 122. By opening and closing the gate valve 126, communication between the common transfer chambers 102 and 120 can be established and shut off.
[0130] 処理室 104E及び処理室 104F内には，他の処理室 104A〜104Dと同様に、ゥェ ハ Wを保持する載置台 105E, 105Fがそれぞれ設けられている。また，第 2共通搬 送室 120内には，第 1共通搬送室 102と同様に， 2つのピック 124A, 124Bを有する 屈伸及び旋回可能になされた搬送機構 124が設けられている。第 2共通搬送室 120 の搬送機構 124は，第 1共通搬送室 102の搬送機構 118と同様な操作で、ウェハを 効率的に搬送するようになって 、る。  [0130] In the processing chamber 104E and the processing chamber 104F, as with the other processing chambers 104A to 104D, mounting tables 105E and 105F for holding the wafer W are provided. In the second common transfer chamber 120, similarly to the first common transfer chamber 102, a transfer mechanism 124 having two picks 124A and 124B that can be bent and stretched is provided. The transfer mechanism 124 of the second common transfer chamber 120 can efficiently transfer the wafer by the same operation as the transfer mechanism 118 of the first common transfer chamber 102.
[0131] なお，第 2共通搬送室 120と 2つのロードロック室の内のいずれか一方，例えばロー ドロック室 108A、との連結部の搬送口 152Aは、ウェハ Wを第 2共通搬送室 120内 へ搬入する搬入専用口として用いられ，第 2共通搬送室 120と他方のロードロック室 108Bとの連結部の搬送口 152Bは、ウェハ Wを第 2共通搬送室 120から外へ搬出 する搬出専用口として用いられる。 [0131] Note that the transfer port 152A at the connecting portion between the second common transfer chamber 120 and one of the two load lock chambers, for example, the load lock chamber 108A, allows the wafer W to pass through the second common transfer chamber 120. The transfer port 152B at the connection between the second common transfer chamber 120 and the other load lock chamber 108B is used as a dedicated transfer port for transferring the wafer W out of the second common transfer chamber 120. Used as
[0132] (処理室の構成例）  [0132] (Configuration example of processing chamber)
次に，図 6に示す基板処理装置 101における処理室の構成例 (配置例）を説明す る。本実施の形態に係る基板処理装置 101も，ウェハ上の自然酸化膜などの付着物 を水成分を用 ヽず且つプラズマによらな ヽガス成分との化学反応及び熱処理によつ て除去する付着物除去処理と，当該付着物除去処理が施されたウェハ上に所定の 薄膜を形成する成膜処理と、を連続して実行するようになって！/ヽる。  Next, a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 101 shown in FIG. 6 will be described. The substrate processing apparatus 101 according to the present embodiment also removes deposits such as a natural oxide film on the wafer by using a chemical reaction with a gas component such as water and a heat treatment without using a water component. The kimono removal process and the film forming process for forming a predetermined thin film on the wafer that has been subjected to the deposit removal process are continuously executed! / Speak.
[0133] このため，処理室 104A〜104Fのうち、少なくとも 2つの処理室の一方が付着物除 去処理室として構成され他方が成膜処理室として構成される。  [0133] For this reason, of the processing chambers 104A to 104F, at least one of the two processing chambers is configured as a deposit removal processing chamber, and the other is configured as a film forming processing chamber.
[0134] また，付着物除去処理は、上述したように、複数段階の処理を連続して実行するよ うになつていてもよく，その場合には付着物除去処理室を複数の処理室で構成しても よい。具体的には、例えば上述したような生成物生成処理 (例えば COR処理）と生成 物除去処理 (例えば PHT処理）との 2段階の処理によって行う場合には、処理室 104 A〜104Fのうちの 2つの処理室を付着物除去処理室として構成してもよい。この場 合，一方の処理室が生成物生成処理室として構成され，他方の処理室が生成物除 去処理室として構成される。  [0134] In addition, as described above, the deposit removal processing may be performed in such a manner that a plurality of steps are continuously performed. In that case, the deposit removal processing chamber is constituted by a plurality of processing chambers. May be. Specifically, for example, in the case of performing the two-stage processing of the product generation processing (for example, COR processing) and the product removal processing (for example, PHT processing) as described above, Two processing chambers may be configured as the deposit removal processing chamber. In this case, one processing chamber is configured as a product generation processing chamber, and the other processing chamber is configured as a product removal processing chamber.
[0135] また、成膜処理は、異なる膜を連続して成膜するようにしてもょ ヽ。その場合には、 成膜処理室が複数の処理室で構成され得る。具体的には、第 1膜 (例えば Ti系膜)と 第 2膜 (例えば TiN系膜)とを連続して成膜する場合には、処理室 104A〜104Fのう ちの 2つの処理室が成膜処理室として構成され得る。この場合，一方の処理室が第 1 膜を成膜する第 1膜成膜処理室として構成され，他方の処理室が第 2膜を成膜する 第 2膜成膜処理室として構成される。このように，基板処理装置 101によって実行さ れる付着物除去処理と成膜処理との内容に応じて、各処理室 104A〜104Fの構成 が決定される。  [0135] In addition, in the film forming process, different films may be successively formed. In that case, the film formation chamber may be constituted by a plurality of processing chambers. Specifically, when a first film (for example, a Ti-based film) and a second film (for example, a TiN-based film) are continuously formed, two processing chambers 104A to 104F are formed. It can be configured as a membrane treatment chamber. In this case, one processing chamber is configured as a first film deposition processing chamber for depositing the first film, and the other processing chamber is configured as a second film deposition processing chamber for depositing the second film. As described above, the configuration of each of the processing chambers 104A to 104F is determined according to the contents of the deposit removal process and the film forming process performed by the substrate processing apparatus 101.
[0136] ここで，例えばコンタクトホールまたはビアホールが形成されたウェハ Wが基板処理 装置 101に導入され，このウェハ Wに対して上述したような付着物除去処理としての COR処理及び PHT処理が連続して実行された後，成膜処理としての Ti膜成膜処理 及び TiN膜成膜処理が連続して実行される場合の基板処理装置 101における処理 室の構成例（配置例）を図 7に示す。 Here, for example, a wafer W in which contact holes or via holes are formed is introduced into the substrate processing apparatus 101, and the wafer W is subjected to the above-described deposit removal processing. Example of configuration of processing chamber in substrate processing apparatus 101 when Ti film forming process and TiN film forming process as film forming process are executed continuously after COR process and PHT process are executed ( Figure 7 shows an arrangement example.
[0137] 図 7に示す構成例では，処理室 104A, 104B, 104C, 104D力 それぞれ、 COR 処理室， PHT処理室， Ti膜成膜処理室， TiN膜成膜処理室として構成されている。  In the configuration example shown in FIG. 7, the processing chambers 104A, 104B, 104C, and 104D are configured as a COR processing chamber, a PHT processing chamber, a Ti film deposition processing chamber, and a TiN film deposition processing chamber, respectively.
[0138] (ウェハの搬送処理）  [0138] (Transfer processing of wafer)
次に，図 7に示すような構成の基板処理装置 101におけるウェハ Wの搬送処理に ついて説明する。ウェハ Wに対する各処理室 104A〜104Dでの処理は上記の順序 で行われるので，ウェハ Wの搬送経路は図 7に示す実線矢印のようになる。  Next, the wafer W transfer process in the substrate processing apparatus 101 configured as shown in FIG. 7 will be described. Since the processing in the processing chambers 104A to 104D for the wafer W is performed in the above-described order, the transfer path of the wafer W is as shown by a solid arrow in FIG.
[0139] ここでは、一例として、中央の導入ポート 112Bに設置されたカセット (キャリアも含 む）から例えばコンタクトホールまたはビアホールが形成された処理前ウェハ Wが取り 出されるものとしている。また、 2つのロードロック室 108A, 108Bのうちのいずれか一 方のロードロック室，ここではロードロック室 108A、が処理前ウェハ Wの搬入用に用 いられ，他方のロードロック室 108Bが処理済ウェハ Wの搬出用に用いられる。今， 各処理室 104A〜104D内にはそれぞれウェハ Wが収容されていて、それぞれの処 理が終了している力、あるいは、ほぼ終了しかけているものとする。  Here, as an example, it is assumed that, for example, a pre-process wafer W in which a contact hole or a via hole is formed is taken out from a cassette (including a carrier) installed in the central introduction port 112B. In addition, one of the two load lock chambers 108A and 108B, in this case, the load lock chamber 108A, is used for loading the wafer W before processing, and the other load lock chamber 108B is used for processing. Used to carry out used wafer W. Now, it is assumed that the wafers W are accommodated in the processing chambers 104A to 104D, respectively, and the force at which each processing is completed or almost finished.
[0140] まず，図 7に示す搬入側搬送室 110内のウェハ Wの搬送処理は，図 2に示す場合 と同様である。このため，その詳細な説明は省略する。この場合，図 7に示す搬送経 路 X21〜X23が、それぞれ図 2に示す搬送経路 XI 1〜X13に相当する。  First, the transfer processing of the wafer W in the transfer-side transfer chamber 110 shown in FIG. 7 is the same as the case shown in FIG. Therefore, detailed description thereof is omitted. In this case, the transfer paths X21 to X23 shown in FIG. 7 correspond to the transfer paths XI1 to X13 shown in FIG.
[0141] また，第 1共通搬送室 102内のウェハ Wの搬送処理は，図 2に示す場合とほぼ同 様であるが，図 7における第 1共通搬送室 102内の搬送処理においては、ウェハ W はパス部 122との間で搬送される。この点で，ウェハ Wをロードロック室 108A, 108B との間で搬送する図 2の場合と相違する。  [0141] Further, the transfer process of the wafer W in the first common transfer chamber 102 is almost the same as the case shown in FIG. 2, but the transfer process in the first common transfer chamber 102 in FIG. W is conveyed to and from the pass unit 122. This is different from the case of FIG. 2 in which the wafer W is transferred between the load lock chambers 108A and 108B.
[0142] 具体的には，図 7に示す搬送経路 Y21〜Y25が、それぞれ図 2に示す搬送経路 Υ 11〜Υ15に相当する。ここで，搬送経路 Y21については、ウェハ Wが処理室 104D 力もパス部 122へ搬送され，搬送経路 Υ25については、ウェハ Wがパス部 122から 処理室 104Aへ搬送される。これらの点で，搬送経路 Yl l, Y15とは異なっている。  Specifically, the transport paths Y21 to Y25 shown in FIG. 7 correspond to the transport paths Υ11 to Υ15 shown in FIG. Here, in the transfer path Y21, the wafer W is also transferred to the pass section 122 by the processing chamber 104D, and in the transfer path Υ25, the wafer W is transferred from the pass section 122 to the process chamber 104A. These points are different from the transport paths Yl l and Y15.
[0143] 第 2共通搬送室 120内のウェハ Wの搬送処理については，先ず、搬送機構 124に よって、パス部 122に収容されていた処理済のウェハ Wが取り出され，搬送経路 Z21 に示すように、空き状態のロードロック室 108B内に搬送される。次いで，ロードロック 室 108A内で待機していた処理前のウェハ W力 搬送機構 124によって取り出され， 搬送経路 Z22に示すように、パス部 122内へ搬送される。 [0143] Concerning the transfer processing of the wafer W in the second common transfer chamber 120, first, the transfer mechanism 124 Therefore, the processed wafer W accommodated in the pass section 122 is taken out and transferred into the empty load lock chamber 108B as shown in the transfer path Z21. Next, it is taken out by the unprocessed wafer W force transfer mechanism 124 waiting in the load lock chamber 108A, and transferred into the pass section 122 as indicated by the transfer path Z22.
[0144] なお，ウェハ Wの搬出入の際には，各ゲートバルブ 106A〜106F, 107A, 107B , 126のうち必要なゲートバルブのみが開閉操作される。そして，各処理室 104A〜 104Dにてウェハ Wの処理が完了する毎に、上記の操作が繰り返し行われる。  [0144] When the wafer W is loaded / unloaded, only the necessary gate valves among the gate valves 106A to 106F, 107A, 107B, 126 are opened / closed. Then, each time the processing of the wafer W is completed in each of the processing chambers 104A to 104D, the above operation is repeated.
[0145] このようにして，コンタクトホールまたはビアホールが形成された処理前のウェハ W に対して、処理室 104A〜処理室 104Dにて、それぞれ COR処理， PHT処理， Ti膜 成膜処理， TiN膜成膜処理が連続して施される。  [0145] The wafer W before processing in which the contact hole or via hole is formed in this way is processed in COR chamber, PHT processing, Ti film deposition processing, TiN film in the processing chamber 104A to processing chamber 104D, respectively. The film forming process is continuously performed.
[0146] このように，図 7に示す処理室の構成 (配置）によれば，第 1共通搬送室 102に接続 された処理室 104A〜処理室 104Dが、それぞれ、 COR処理室， PHT処理室， Ti 膜成膜処理室， TiN膜成膜処理室として構成されているため，第 2共通搬送室 120 に接続された処理室 104E, 104Fについては，ウェハに他の処理を施す処理室とし て構成することができる。  Thus, according to the configuration (arrangement) of the processing chamber shown in FIG. 7, the processing chamber 104A to the processing chamber 104D connected to the first common transfer chamber 102 are respectively connected to the COR processing chamber and the PHT processing chamber. , Ti film deposition chamber, and TiN film deposition chamber, the processing chambers 104E and 104F connected to the second common transfer chamber 120 are the processing chambers that perform other processing on the wafer. Can be configured.
[0147] 例えば、処理室 104E又は処理室 104Fは，コンタクトホールまたはビアホール内に 埋込むためのタングステン膜などを成膜する金属系膜成膜室として構成され得る。こ の場合には，処理室 104A〜処理室 104Dによって処理されたウェハ Wが処理室 10 4E又は 104Fに搬送されて，ウェハ Wに形成された Ti膜及び TiN膜のバリア層上に 、タングステン膜が形成され得る。これにより，コンタクトホールまたはビアホール内の プラズマレス洗浄処理， Ti膜及び TiN膜のノ リア層成膜処理，タングステン膜の埋込 み処理、を連続して行うことができる。  [0147] For example, the processing chamber 104E or the processing chamber 104F can be configured as a metal-based film deposition chamber for depositing a tungsten film or the like to be embedded in a contact hole or a via hole. In this case, the wafer W processed by the processing chamber 104A to the processing chamber 104D is transferred to the processing chamber 104E or 104F, and the tungsten film is formed on the Ti film and TiN film barrier layer formed on the wafer W. Can be formed. As a result, the plasmaless cleaning process in the contact hole or via hole, the Ti layer and TiN film deposition process, and the tungsten film filling process can be performed in succession.
[0148] なお，基板処理装置 101の処理室の構成 (配置）は，上記のものに限られない。例 えば、成膜処理としてベース酸化膜成膜処理 (UV処理)及び High— K膜成膜処理 (MOCVD処理）を行う場合には，図 8に示すように、処理室 104C, 104Dを、それ ぞれ、ベース酸化膜成膜処理 (UV処理)室， High— K膜成膜処理 (MOCVD処理 )室として構成してもよい。この場合の搬送処理は，図 7に示す場合と同様であるため ,その詳細な説明を省略する。 [0149] また，第 1共通搬送室 102に接続された処理室 104A〜処理室 104Dを成膜処理 室として構成し，第 2共通搬送室 120に接続された処理室 104E, 104Fを付着物除 去処理室 (例えば COR処理室及び PHT処理室）として構成してもよい。この場合， 例えば図 9に示すように、第 1共通搬送室 102に接続された処理室 104A〜 104Dを 2系統の成膜処理室として構成してもよ ヽ。 Note that the configuration (arrangement) of the processing chamber of the substrate processing apparatus 101 is not limited to the above. For example, when the base oxide film forming process (UV process) and the high-K film forming process (MOCVD process) are performed as the film forming process, as shown in FIG. Each may be configured as a base oxide film deposition process (UV process) chamber and a high-K film deposition process (MOCVD process) chamber. Since the transport process in this case is the same as that shown in FIG. 7, a detailed description thereof will be omitted. [0149] Further, the processing chamber 104A to the processing chamber 104D connected to the first common transfer chamber 102 are configured as film formation processing chambers, and the processing chambers 104E and 104F connected to the second common transfer chamber 120 are removed from the deposits. It may be configured as a post-processing chamber (for example, a COR processing chamber and a PHT processing chamber). In this case, for example, as shown in FIG. 9, the processing chambers 104A to 104D connected to the first common transfer chamber 102 may be configured as two systems of film forming processing chambers.
[0150] 具体的には、図 9に示すように、第 1共通搬送室 102に接続された処理室 104A, 1 04Bを、第 1系統，すなわち、第 ITi膜成膜処理室，第 ITiN膜成膜処理室として構 成し，処理室 104C, 104Dを、第 2系統，すなわち、第 2Ti膜成膜処理室，第 2TiN 膜成膜処理室として構成する。この第 1系統と第 2系統では、同じプロセスレシピで成 膜処理を実行するようにしてもょ 、し，例えばガス流量や圧力などが異なるプロセスレ シピで成膜処理を実行するようにしてもよい。一方，第 2共通搬送室 120に接続され た処理室 104E,処理室 104Fを、それぞれ、 COR処理室， PHT処理室として構成 する。  [0150] Specifically, as shown in FIG. 9, the processing chambers 104A and 104B connected to the first common transfer chamber 102 are connected to the first system, that is, the first ITi film deposition processing chamber and the first ITiN film. The film forming chamber is configured, and the processing chambers 104C and 104D are configured as the second system, that is, the second Ti film forming chamber and the second TiN film forming chamber. In the first system and the second system, the film forming process may be executed using the same process recipe, or the film forming process may be executed using process recipes having different gas flow rates and pressures, for example. Good. On the other hand, the processing chamber 104E and the processing chamber 104F connected to the second common transfer chamber 120 are configured as a COR processing chamber and a PHT processing chamber, respectively.
[0151] ここで，図 9に示すように構成された基板処理装置 101の搬送処理について説明す る。図 9に示すように，第 2共通搬送室 120内では、ウェハ Wは処理室 104E, 104F の順に処理されてパス部 122に収容される。そして，第 1共通搬送室 102内では，ゥ ェハ Wはパス部 122から処理室 104A, 104Bに当該順に搬送されて処理される（第 1系統)。同時に，ウェハ Wはパス部 122から処理室 104C, 104Dに当該順に搬送 されて処理され得る（第 2系統)。これら 2つの系統の処理力 選択的に実行可能であ る。これら 2系統の処理は、並列して実行してもよいし，いずれか一方の系統のみの 処理を連続に実行してもよ ヽ。  Here, the transfer process of the substrate processing apparatus 101 configured as shown in FIG. 9 will be described. As shown in FIG. 9, in the second common transfer chamber 120, the wafers W are processed in the order of the processing chambers 104E and 104F and accommodated in the pass unit 122. In the first common transfer chamber 102, the wafer W is transferred from the pass section 122 to the processing chambers 104A and 104B in that order and processed (first system). At the same time, the wafer W can be transferred from the pass section 122 to the processing chambers 104C and 104D in that order and processed (second system). The processing power of these two systems can be selectively executed. These two systems may be executed in parallel, or only one of them may be executed continuously.
[0152] ここで，図 9に示す搬入側搬送室 110内のウェハ Wの搬送処理は，図 2に示す場 合と同様である。このため，その詳細な説明は省略する。この場合，図 9に示す搬送 経路 X31〜X33が、それぞれ図 2に示す搬送経路 XI 1〜X13に相当する。  Here, the transfer processing of the wafer W in the transfer-side transfer chamber 110 shown in FIG. 9 is the same as that shown in FIG. Therefore, detailed description thereof is omitted. In this case, the transfer routes X31 to X33 shown in FIG. 9 correspond to the transfer routes XI1 to X13 shown in FIG.
[0153] 次に，第 2共通搬送室 120内のウェハ Wの搬送処理については、先ず、搬送機構 124によって、パス部 122に収容されていた処理室 104B又は処理室 104Dにて処 理済のウェハ Wが取り出され，搬送経路 Z31に示すように、空き状態のロードロック 室 108B内に搬送される。 [0154] 次いで，搬送機構 124によって、処理室 104Fにて処理済のウェハ Wが取り出され ,搬送経路 Z32に示すように、空き状態のパス部 122内に搬送される。続いて，搬送 機構 124によって、処理室 104Eにて処理済のウエノ、 Wが取り出され，搬送経路 Z3 3に示すように、空き状態の処理室 104F内へ搬入される。その後，処理室 104F内 での処理が開始される。 Next, for the transfer process of the wafer W in the second common transfer chamber 120, first, the transfer mechanism 124 has already processed the wafer W in the process chamber 104B or the process chamber 104D accommodated in the pass unit 122. Wafer W is taken out and transferred into an empty load lock chamber 108B as shown in transfer path Z31. Next, the wafer W that has been processed in the processing chamber 104F is taken out by the transfer mechanism 124, and is transferred into the empty path unit 122 as indicated by the transfer path Z32. Subsequently, the processed weno and W are taken out in the processing chamber 104E by the transfer mechanism 124, and are transferred into the empty processing chamber 104F as shown in the transfer path Z33. Thereafter, processing in the processing chamber 104F is started.
[0155] 次いで，ロードロック室 108A内で待機していた処理前のウェハ Wが搬送機構 124 によって取り出され，搬送経路 Z34に示すように、空き状態の処理室 104E内へ搬入 される。その後，処理室 104E内での処理が開始される。  Next, the unprocessed wafer W waiting in the load lock chamber 108A is taken out by the transfer mechanism 124 and transferred into the empty process chamber 104E as indicated by the transfer path Z34. Thereafter, processing in the processing chamber 104E is started.
[0156] 次に，第 1共通搬送室 102内のウェハ Wの搬送処理について説明する。第 1共通 搬送室 102内のウェハに対しては，上述したように、 2系統の処理が実行可能である  Next, the transfer process of the wafer W in the first common transfer chamber 102 will be described. As described above, two systems of processing can be performed on the wafer in the first common transfer chamber 102.
[0157] 第 1系統 (処理室 104A, 104B)で処理を行う場合は，先ず、搬送機構 118によつ て、処理室 104Bに収容されていた処理済のウェハ Wが取り出され，搬送経路 Ya31 に示すように、空き状態のパス部 122に搬送される。 [0157] When processing is performed in the first system (processing chambers 104A and 104B), first, the processed wafer W accommodated in the processing chamber 104B is taken out by the transfer mechanism 118 and transferred to the transfer path Ya31. As shown in FIG.
[0158] 次いで，搬送機構 118によって、処理室 104A内に収容されていた処理済のゥェ ハ Wが取り出され，搬送経路 Ya32に示すように、空き状態の処理室 104B内へ搬入 される。その後，処理室 104B内での処理が開始される。 [0158] Next, the processed wafer W accommodated in the processing chamber 104A is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104B as indicated by the transfer path Ya32. Thereafter, processing in the processing chamber 104B is started.
[0159] 続いて，第 2共通搬送室 120からパス部 122内に搬送されたウェハ Wが搬送機構 1Subsequently, the wafer W transferred from the second common transfer chamber 120 into the pass unit 122 is transferred to the transfer mechanism 1.
18によって取り出され，搬送経路 Ya33に示すように、空き状態の処理室 104A内へ 搬入される。その後，処理室 104A内での処理が開始される。 18 and is carried into the empty processing chamber 104A as shown in the transfer route Ya33. Thereafter, processing in the processing chamber 104A is started.
[0160] 一方，第 2系統 (処理室 104C, 104D)で処理を行う場合は，先ず、搬送機構 118 によって、処理室 104Dに収容されていた処理済のウェハ Wが取り出され，搬送経路On the other hand, when processing is performed in the second system (processing chambers 104C and 104D), first, the processed wafer W accommodated in the processing chamber 104D is taken out by the transfer mechanism 118 and transferred to the transfer path.
Yb31に示すように、空き状態のパス部 122に搬送される。 As indicated by Yb31, the sheet is transported to an empty path unit 122.
[0161] 次いで，搬送機構 118によって、処理室 104C内に収容されていた処理済のゥェ ハ Wが取り出され，搬送経路 Yb32に示すように、空き状態の処理室 104D内へ搬入 される。その後，処理室 104D内での処理が開始される。 Next, the processed wafer W accommodated in the processing chamber 104C is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104D as indicated by the transfer path Yb32. Thereafter, processing in the processing chamber 104D is started.
[0162] 続いて，第 2共通搬送室 120からパス部 122内に搬送されたウェハ Wが搬送機構 1Subsequently, the wafer W transferred from the second common transfer chamber 120 into the pass unit 122 is transferred to the transfer mechanism 1.
18によって取り出され，搬送経路 Yb33に示すように、空き状態の処理室 104C内へ 搬入される。その後，処理室 104C内での処理が開始される。 18 into the empty processing chamber 104C as shown in the transfer path Yb33. It is brought in. Thereafter, processing in the processing chamber 104C is started.
[0163] なお，ウェハ Wの搬出入の際には，各ゲートバルブ 106A〜106F, 107A, 107B[0163] When the wafer W is loaded and unloaded, each gate valve 106A to 106F, 107A, 107B
、 126のうち必要なゲートバルブのみが開閉操作される。また、処理室 104E及び 10Of the 126, only the necessary gate valves are opened and closed. Processing chambers 104E and 10
4F,処理室 104A及び 104B,処理室 104C及び 104Dにて処理が行われ，ウェハ4F, processing chambers 104A and 104B, processing chambers 104C and 104D
Wの処理が完了する毎に、上記の操作が繰り返し行われる。 Each time the process of W is completed, the above operation is repeated.
[0164] このようにして，コンタクトホールまたはビアホールが形成された処理前のウェハ W に対して、 COR処理， PHT処理， Ti膜成膜処理， TiN膜成膜処理が連続して施さ れる。 In this way, the COR process, the PHT process, the Ti film forming process, and the TiN film forming process are successively performed on the unprocessed wafer W on which the contact holes or via holes are formed.
[0165] このように，図 9に示す処理室の構成によれば，第 1共通搬送室 102に接続された 処理室 104A〜処理室 104Dが、 2系統の Ti膜成膜処理室及び TiN膜成膜処理室 として構成されているため，これら 2系統の処理を並列して実行することにより，装置 全体のスループットを大幅に向上させることができる。というのも，通常は，成膜処理（ ここでは Ti膜成膜処理， TiN膜成膜処理)の方が付着物除去処理 (ここでは COR処 理， PHT処理)よりも時間が力かるので，一方の系統の処理室で成膜処理を実行し ている間に COR処理， PHT処理などの洗浄処理が終了すれば，他方の系統の処 理室で成膜処理を直ぐに実行することができるからである。  Thus, according to the configuration of the processing chamber shown in FIG. 9, the processing chamber 104A to the processing chamber 104D connected to the first common transfer chamber 102 are divided into two systems of Ti film deposition processing chamber and TiN film. Since it is configured as a film formation chamber, the throughput of the entire system can be greatly improved by executing these two systems in parallel. Because the deposition process (Ti film deposition process, TiN film deposition process) is usually more time consuming than the deposit removal process (COR process, PHT process here), If the cleaning process such as the COR process and PHT process is completed while the film forming process is being performed in the processing chamber of one system, the film forming process can be performed immediately in the processing system of the other system. It is.
[0166] また，一つの第 2共通搬送室 120の側 (第 2真空処理装置）に成膜処理室を集中さ せているので，第 1共通搬送室の処理室と区別することが容易であり，すなわち、各 成膜処理室や第 2共通搬送室 120のクリーニングを行う際の効率がよい。このように 真空処理装置 (第 1真空処理装置と第 2真空処理装置)を処理の種類によって分ける ことによって，例えば各真空処理装置ごとにクリーニングを行うこともでき、効率がよい  [0166] In addition, since the film forming chamber is concentrated on the side of the second common transfer chamber 120 (second vacuum processing apparatus), it can be easily distinguished from the processing chamber of the first common transfer chamber. Yes, that is, the efficiency in cleaning each film forming chamber and the second common transfer chamber 120 is high. Thus, by separating the vacuum processing apparatuses (the first vacuum processing apparatus and the second vacuum processing apparatus) according to the type of processing, for example, each vacuum processing apparatus can be cleaned, which is efficient.
[0167] (第 3の実施の形態に係る基板処理装置の構成例） [0167] (Configuration Example of Substrate Processing Apparatus According to Third Embodiment)
次に，本発明の第 3の実施の形態に係る基板処理装置の構成例を図面を参照しな 力 説明する。図 10は、第 3の実施の形態に係る基板処理装置の一例を示す概略 構成図である。図 10に示す基板処理装置 103は，図 7に示す基板処理装置 101に 、ウェハ Wの膜厚の測定及びパーティクル (上記付着物を含む)の測定を行うことが できる測定処理室 400を取付けたものである。 [0168] 測定処理室 400は，第 1共通搬送室 102及び第 2共通搬送室 120の各辺のうち， 空いている部分であれば、どの位置に取付けてもよい。図 10に示す構成例では、測 定処理室 400は、第 1共通搬送室 102に取付けられている。なお，測定処理室 400 は，図 10に示す制御部 200の EC (装置制御部） 300によって制御されるようになつ ている。この場合，図 3に示す制御部 200の EC300及びスイッチングハブ 220を介し て、測定処理室 400を制御する MC (モジュール制御部）が接続されている。この MC に DISTCボードを介して接続される例えば IZOモジュール 236Kに、測定処理室 4 00の各部が接続されている。これにより，測定処理室 400と制御部 200の EC300と の間で、制御信号やデータのやり取りが行われ得る。 Next, a configuration example of the substrate processing apparatus according to the third embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a schematic configuration diagram showing an example of a substrate processing apparatus according to the third embodiment. In the substrate processing apparatus 103 shown in FIG. 10, a measurement processing chamber 400 capable of measuring the film thickness of the wafer W and measuring particles (including the above deposits) is attached to the substrate processing apparatus 101 shown in FIG. Is. [0168] The measurement processing chamber 400 may be attached to any position of the sides of the first common transfer chamber 102 and the second common transfer chamber 120 as long as they are vacant. In the configuration example shown in FIG. 10, the measurement processing chamber 400 is attached to the first common transfer chamber 102. The measurement processing chamber 400 is controlled by an EC (equipment control unit) 300 of the control unit 200 shown in FIG. In this case, an MC (module control unit) that controls the measurement processing chamber 400 is connected via the EC 300 and the switching hub 220 of the control unit 200 shown in FIG. Each part of the measurement processing chamber 400 is connected to, for example, an IZO module 236K connected to the MC via a DISTC board. As a result, control signals and data can be exchanged between the measurement processing chamber 400 and the EC 300 of the control unit 200.
[0169] ここで，測定処理室 400の構成例を図 11に示す。この測定処理室 400は，ウェハ Wを載置して保持するステージ（ターンテーブル） 405と，このステージ 405を回転さ せるためのモータ 407と、を備えている。モータ 407は、例えばモータドライブなどで 構成されるモータ駆動部 408からの駆動信号に基づ 、て駆動される。モータ駆動部 408は，例えば I/Oモジュール 236Κ及び前記 MCを介して EC300に接続されて おり，当該 MC又は EC300からの制御信号によって制御される。  Here, a configuration example of the measurement processing chamber 400 is shown in FIG. The measurement processing chamber 400 includes a stage (turn table) 405 for placing and holding the wafer W, and a motor 407 for rotating the stage 405. The motor 407 is driven based on a drive signal from a motor drive unit 408 configured by, for example, a motor drive. The motor drive unit 408 is connected to the EC 300 via, for example, the I / O module 236 and the MC, and is controlled by a control signal from the MC or EC 300.
[0170] 本実施の形態の測定処理室 400は，ウェハ Wに形成された薄膜などの膜厚を測定 するための膜厚測定部 410と，ウェハ Wの表面画像を撮像してパターン認識などを 行うための画像処理部 420と，ウェハ W上のパーティクルを測定するためのパーティ クル測定部 430と、を有している。  [0170] The measurement processing chamber 400 of the present embodiment includes a film thickness measurement unit 410 for measuring the film thickness of a thin film or the like formed on the wafer W, and pattern recognition by capturing a surface image of the wafer W. An image processing unit 420 for performing measurement and a particle measurement unit 430 for measuring particles on the wafer W are provided.
[0171] 膜厚測定部 410は，ウェハ Wへ向けて例えばレーザ光を照射する光源 414と，光 源 414から照射されてウェハ Wによって反射された光を受光する受光部 416と，受光 部 416で受光した受光信号を処理する信号処理部 412と、を有している。信号処理 部 412は、例えば I/Oモジュール 236Κを介して EC300に接続されている。これに より， EC300は、信号処理部 412を介して、ウェハ W上の膜厚に関するデータ (例え ば膜厚データ，膜厚評価データなど)を受信可能である。  The film thickness measurement unit 410 includes, for example, a light source 414 that emits laser light toward the wafer W, a light receiving unit 416 that receives light emitted from the light source 414 and reflected by the wafer W, and a light receiving unit 416. And a signal processing unit 412 for processing the received light signal. The signal processing unit 412 is connected to the EC 300 via, for example, an I / O module 236. As a result, the EC 300 can receive data relating to the film thickness on the wafer W (eg, film thickness data, film thickness evaluation data, etc.) via the signal processing unit 412.
[0172] 膜厚測定部 410は，光源 414からのレーザ光を用いて、例えば分光エリプソ法によ つて膜厚を測定する。分光エリプソ法とは，一般に，レーザ光の入射光とウェハから の反射光との偏光変化量 (振幅，位相差)が膜厚 X光学定数に比例する量であるこ とに基づいて、膜厚を測定する方法である。 [0172] The film thickness measurement unit 410 measures the film thickness using the laser light from the light source 414, for example, by spectroscopic ellipsometry. In general, the spectroscopic ellipso method is an amount in which the amount of change in polarization (amplitude and phase difference) between the incident light of the laser beam and the reflected light from the wafer is proportional to the film thickness X optical constant. Based on the above, the film thickness is measured.
[0173] 画像処理部 420は，ウェハ Wの表面画像を撮像する CCD (Charge Coupled Devic es)などの撮像素子 424と，当該撮像素子 424からの画像信号を処理する信号処理 部 422と、を有している。信号処理部 422は、 IZOモジュール 236Kを介して EC30 0に接続されている。これにより， EC300は、信号処理部 422を介して、ウェハ Wの 表面画像に関するデータを受信可能である。  [0173] The image processing unit 420 includes an image sensor 424 such as a CCD (Charge Coupled Devices) that captures a surface image of the wafer W, and a signal processing unit 422 that processes an image signal from the image sensor 424. is doing. The signal processing unit 422 is connected to the EC300 via the IZO module 236K. As a result, the EC 300 can receive the data related to the surface image of the wafer W via the signal processing unit 422.
[0174] パーティクル測定部 430は，ウェハ Wへ向けて例えばレーザ光を照射する光源 43 4と，光源 434から照射されてウェハ W上で散乱した散乱光を受光する受光部 436と ,受光部 436で受光した受光信号を処理する信号処理部 432と、を有している。信 号処理部 432は、 ΙΖΟモジュール 236Κを介して EC300に接続されている。これに より， EC300は、信号処理部 432を介して、ウェハ W上のパーティクルに関するデー タ（例えばピクセルデータ，パーティクル評価データなど）を受信可能である。  The particle measuring unit 430 includes, for example, a light source 434 that emits laser light toward the wafer W, a light receiving unit 436 that receives scattered light emitted from the light source 434 and scattered on the wafer W, and a light receiving unit 436. And a signal processing unit 432 for processing the received light signal received at. The signal processing unit 432 is connected to the EC 300 via a module 236. As a result, the EC 300 can receive data (for example, pixel data, particle evaluation data, etc.) regarding particles on the wafer W via the signal processing unit 432.
[0175] 次に，第 3の実施の形態に係る制御部 200の EC300の構成例について、図面を 参照しながら説明する。図 12は、第 3の実施の形態に係る EC300の構成例を示す ブロック図である。図 12に示す EC300では，図 4に示すプログラムデータ記憶手段 3 60に測定処理室 400の測定処理プログラム 460が加えられるとともに，処理データ 記憶手段 370に測定処理情報 470が加えられている。  Next, a configuration example of the EC 300 of the control unit 200 according to the third embodiment will be described with reference to the drawings. FIG. 12 is a block diagram illustrating a configuration example of the EC 300 according to the third embodiment. In the EC 300 shown in FIG. 12, the measurement processing program 460 of the measurement processing chamber 400 is added to the program data storage means 360 shown in FIG. 4, and the measurement processing information 470 is added to the processing data storage means 370.
[0176] 膜厚測定部 410,画像処理部 420及びパーティクル測定部 430は、それぞれ、光 学系ユニットとして構成されており、各光学系ユニットは、ウェハ Wの半径方向に移動 可能に構成されている。これにより，ステージ 405にてウェハ Wを保持して回転させ ながら、各光学系ユニットをウェハ Wの中心力 端部まで移動させることにより，ゥェ ハ全面の測定処理を行うことができる。これにより，光学系ユニットの移動距離（走査 距離)を短くすることができ，測定処理室 400の省スペース化を図ることができる。す なわち、測定処理室 400自体を小型化することができる。なお，膜厚測定部 410,画 像処理部 420及びパーティクル測定部 430を、移動可能な一つの光学系ユニットと して構成してもよい。また、膜厚測定部 410及びパーティクル測定部 430を移動可能 な一つの光学系ユニットとして構成し，画像処理部 420は固定するということでもよい [0177] 測定処理プログラム 460は，膜厚測定プログラム 462,画像処理プログラム 464,パ 一ティクル測定プログラム 466,ステージ駆動プログラム 468などの、測定処理室 40 0の各部を制御して測定処理を行って測定結果を評価するための各種のプログラム を含んでいる。また，測定処理情報 470は，膜厚評価情報 472,パーティクル評価情 報 474及び測定条件レシピ 476を含んで 、る。 [0176] The film thickness measurement unit 410, the image processing unit 420, and the particle measurement unit 430 are each configured as an optical system unit, and each optical system unit is configured to be movable in the radial direction of the wafer W. Yes. As a result, the entire wafer surface can be measured by moving each optical system unit to the central force end of the wafer W while holding and rotating the wafer W on the stage 405. As a result, the moving distance (scanning distance) of the optical system unit can be shortened, and the measurement processing chamber 400 can be saved in space. In other words, the measurement processing chamber 400 itself can be reduced in size. The film thickness measurement unit 410, the image processing unit 420, and the particle measurement unit 430 may be configured as a single movable optical system unit. Alternatively, the film thickness measurement unit 410 and the particle measurement unit 430 may be configured as a single movable optical system unit, and the image processing unit 420 may be fixed. [0177] The measurement processing program 460 controls each part of the measurement processing chamber 400, such as the film thickness measurement program 462, the image processing program 464, the particle measurement program 466, and the stage drive program 468, and performs the measurement processing. Various programs for evaluating the measurement results are included. The measurement processing information 470 includes film thickness evaluation information 472, particle evaluation information 474, and measurement condition recipe 476.
[0178] ステージ駆動プログラム 468は，ステージ 405のモータ 407を制御して，ウェハ Wの 回転タイミング，回転数，回転速度などを制御するプログラムである。  [0178] The stage drive program 468 is a program that controls the motor 407 of the stage 405 to control the rotation timing, rotation speed, rotation speed, and the like of the wafer W.
[0179] 膜厚測定プログラム 462は，測定条件レシピ 476に基づいて膜厚測定部 410の各 部を制御して、ウエノ、 Wの膜厚測定を実行すると共に，その測定結果に基づいて膜 厚評価を行うものである。具体的には、例えば、ウェハ Wを回転させながら膜厚測定 部 410を移動しつつ光源 414からのレーザ光をウェハ Wに向けて照射しウェハ Wに よって反射された光を受光することにより，ウェハ Wの膜厚測定が行われる。  [0179] The film thickness measurement program 462 controls each part of the film thickness measurement unit 410 based on the measurement condition recipe 476 to execute the film thickness measurement of Weno and W, and based on the measurement result, the film thickness measurement program 462 An evaluation is performed. Specifically, for example, by moving the film thickness measurement unit 410 while rotating the wafer W, irradiating the wafer W with the laser light from the light source 414 and receiving the light reflected by the wafer W, The film thickness of the wafer W is measured.
[0180] より好ましくは，ウェハ Wを静止させた状態で、膜厚測定部 410を移動し，光源 414 力ものレーザ光をウェハ Wの測定ポイントに向けて照射して，ウェハ Wの膜厚測定を 行う。ウエノ、 Wの測定ポイントが複数ある場合には，各測定ポイントにレーザ光を照 射して，各測定ポイントごとに膜厚測定を行う。これにより，測定結果として例えば膜 厚データが得られる。そして，この膜厚データに基づいて、例えば目標の膜厚が形成 されて!/ヽるかなどを評価するための膜厚評価データが作成され，これが膜厚評価情 報 472として記憶される。  [0180] More preferably, while the wafer W is stationary, the film thickness measurement unit 410 is moved, and a laser beam with a light source of 414 is irradiated toward the measurement point of the wafer W to measure the film thickness of the wafer W. I do. If there are multiple measurement points for Ueno and W, irradiate each measurement point with laser light and measure the film thickness at each measurement point. Thus, for example, film thickness data can be obtained as a measurement result. Based on this film thickness data, for example, film thickness evaluation data for evaluating whether a target film thickness has been formed! / Is obtained and stored as film thickness evaluation information 472.
[0181] 画像処理プログラム 464は，測定条件レシピ 476に基づいて画像処理部 420の各 部を制御して、撮像素子 424によってウェハ Wの表面画像を撮像すると共に、その 撮像結果に基づいてパターン認識などの画像処理を行うものである。例えば、ウェハ Wの表面画像に基づいてパターン認識処理を行うことにより，パターンマッチングを 利用して、ウェハ Wの膜厚測定やパーティクル測定の対象となる測定ポイントを特定 することができる。  [0181] The image processing program 464 controls each part of the image processing unit 420 based on the measurement condition recipe 476, captures the surface image of the wafer W by the image sensor 424, and recognizes the pattern based on the imaging result. The image processing such as is performed. For example, by performing pattern recognition processing based on the surface image of the wafer W, it is possible to specify a measurement point that is a target for film thickness measurement or particle measurement of the wafer W using pattern matching.
[0182] パーティクル測定プログラム 466は，測定条件レシピ 476に基づ!/、てパーティクル 測定部 430の各部を制御して、ウェハ Wの表面のパーティクル測定を実行すると共 に，その測定結果に基づいてパーティクル評価を行うものである。具体的には、例え ば、ウェハ Wを回転させながらパーティクル測定部 430を移動しつつ光源 434からの レーザ光をウェハ Wに向けて照射し散乱光を受光することにより，ウェハ Wのパーテ イタル測定が行われる。測定結果として、例えば、パーティクルの有無と関連づけられ たピクセルデータが得られる。そして，このピクセルデータに基づいて、例えばパーテ イタル有りのピクセルデータが設定値を越えているか否かに対応した 2値ィ匕データか らなるパーティクル評価データが作成され，これが膜厚評価情報 472として記憶され る。 [0182] The particle measurement program 466 is based on the measurement condition recipe 476 and controls each part of the particle measurement unit 430 to execute the particle measurement on the surface of the wafer W and based on the measurement result. Particle evaluation is performed. Specifically, for example For example, by moving the particle measuring unit 430 while rotating the wafer W and irradiating the wafer W with the laser light from the light source 434 and receiving the scattered light, the partial measurement of the wafer W is performed. As a measurement result, for example, pixel data associated with the presence or absence of particles is obtained. Based on this pixel data, for example, particle evaluation data consisting of binary data corresponding to whether or not the pixel data with a partition exceeds the set value is created. Memorized.
[0183] (処理室の構成例）  [0183] (Configuration example of processing chamber)
次に，図 10に示す基板処理装置 103における処理室の構成例（配置例）を説明す る。本実施の形態に係る基板処理装置 103も，ウェハ上の自然酸化膜などの付着物 を水成分を用 ヽず且つプラズマによらな ヽガス成分との化学反応及び熱処理によつ て除去する付着物除去処理と，当該付着物除去処理が施されたウェハ上に所定の 薄膜を形成する成膜処理と、を連続して実行するようになって！/ヽる。  Next, a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 103 shown in FIG. 10 will be described. The substrate processing apparatus 103 according to the present embodiment also removes deposits such as a natural oxide film on the wafer by using a chemical reaction with a gas component such as a plasma without using a water component and a heat treatment. The kimono removal process and the film forming process for forming a predetermined thin film on the wafer that has been subjected to the deposit removal process are continuously executed! / Speak.
[0184] ここで，例えばコンタクトホールまたはビアホールが形成されたウェハ Wが基板処理 装置 103に導入され，このウェハ Wに対して上述したような付着物除去処理としての COR処理及び PHT処理が連続して実行された後，成膜処理としての Ti膜成膜処理 及び TiN膜成膜処理が連続して実行される場合の基板処理装置 103における処理 室の構成例（配置例）を図 13に示す。  [0184] Here, for example, a wafer W on which contact holes or via holes are formed is introduced into the substrate processing apparatus 103, and the COR processing and the PHT processing as the deposit removal processing described above are continuously performed on the wafer W. Fig. 13 shows a configuration example (arrangement example) of the processing chamber in the substrate processing apparatus 103 when the Ti film forming process and the TiN film forming process as the film forming process are successively executed. .
[0185] 図 13に示す構成例では，第 1共通搬送室 102に接続された処理室 104A, 104B , 104C, 104D力 それぞれ、 COR処理室， PHT処理室， Ti膜成膜処理室， TiN 膜成膜処理室として構成されて ヽる。  In the configuration example shown in FIG. 13, the processing chambers 104A, 104B, 104C, and 104D forces connected to the first common transfer chamber 102 are respectively COR processing chamber, PHT processing chamber, Ti film deposition processing chamber, and TiN film. It is configured as a film formation chamber.
[0186] (ウェハの搬送処理）  [0186] (Wafer transfer processing)
このような図 13に示す構成の基板処理装置 103におけるウェハ Wの搬送処理につ いて説明する。ウェハ Wに対する各処理室 104A〜104Dでの処理は上記の順序で 行われるので，ウェハ Wの搬送経路は図 13に示す実線矢印のようになる。  The wafer W transfer process in the substrate processing apparatus 103 configured as shown in FIG. 13 will be described. Since the processing in the processing chambers 104A to 104D for the wafer W is performed in the order described above, the transfer path of the wafer W is as shown by a solid arrow in FIG.
[0187] ここでは、一例として、中央の導入ポート 112Bに設置されたカセット (キャリアも含 む）から例えばコンタクトホールまたはビアホールが形成された処理前ウェハ Wが取り 出されるものとしている。また、 2つのロードロック室 108A, 108Bのうちのいずれか一 方のロードロック室，ここではロードロック室 108A、が処理前ウェハ Wの搬入用に用 いられ，他方のロードロック室 108Bが処理済ウエノ、 Wの搬出用に用いられる。また， ここでは、 COR処理及び PHT処理が終了したウェハ Wは、測定処理室 400にて膜 厚測定及びパーティクル測定を受けた後で，次の成膜処理 (Ti膜成膜処理及び TiN 膜成膜処理）に移るようになつている。今，各処理室 104A〜104D内及び測定処理 室 400内にはそれぞれウェハ Wが収容されていて、それぞれの処理が終了している 力 あるいは、ほぼ終了しかけているものとする。 Here, as an example, it is assumed that, for example, a pre-process wafer W in which a contact hole or a via hole is formed is taken out from a cassette (including a carrier) installed in the central introduction port 112B. One of the two load lock chambers 108A and 108B The other load lock chamber, here the load lock chamber 108A, is used for loading the unprocessed wafer W, and the other load lock chamber 108B is used for unloading the processed wafer. In addition, here, the wafer W that has undergone COR processing and PHT processing is subjected to film thickness measurement and particle measurement in the measurement processing chamber 400, and then the next film formation processing (Ti film formation processing and TiN film formation). (Membrane processing). Now, it is assumed that the wafers W are accommodated in the processing chambers 104A to 104D and the measurement processing chamber 400, respectively, and the force at which each processing is finished or almost finished.
[0188] まず，図 13に示す搬入側搬送室 110内のウェハ Wの搬送処理及び第 2共通搬送 室 120内のウェハ Wの搬送処理は，図 7に示す場合と同様である。このため，その詳 細な説明は省略する。この場合，図 13に示す搬送経路 X41〜X43, Z41, Z42が、 それぞれ図 7に示す搬送経路 X21〜X23, Z21, Z22に相当する。  First, the transfer processing of the wafer W in the loading-side transfer chamber 110 and the transfer processing of the wafer W in the second common transfer chamber 120 shown in FIG. 13 are the same as those shown in FIG. Therefore, the detailed explanation is omitted. In this case, the transport paths X41 to X43, Z41, and Z42 shown in FIG. 13 correspond to the transport paths X21 to X23, Z21, and Z22 shown in FIG. 7, respectively.
[0189] 次に，第 1共通搬送室 102内のウェハ Wの搬送処理について説明する。まず、搬 送機構 118によって、処理室 104Dに収容されて!、た処理済のウェハ Wが取り出さ れ，搬送経路 Y41に示すように、空き状態のパス部 122内に搬送される。  Next, the transfer process of the wafer W in the first common transfer chamber 102 will be described. First, the wafer W is stored in the processing chamber 104D by the transfer mechanism 118, and the processed wafer W is taken out and transferred into the empty path unit 122 as indicated by the transfer path Y41.
[0190] 次いで，搬送機構 118によって、処理室 104C内に収容されていた処理済のゥェ ハ Wが取り出され，搬送経路 Y42に示すように、空き状態の処理室 104D内へ搬入 される。その後，処理室 104D内での処理が開始される。  [0190] Next, the processed wafer W accommodated in the processing chamber 104C is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104D as indicated by the transfer path Y42. Thereafter, processing in the processing chamber 104D is started.
[0191] 続いて，搬送機構 118によって、測定処理室 400に収容されていた測定処理済み のウェハ Wが取り出され，搬送経路 Y43に示すように、空き状態の処理室 104C内 へ搬入される。その後，処理室 104C内での処理が開始される。  [0191] Subsequently, the wafer W that has been subjected to the measurement processing and stored in the measurement processing chamber 400 is taken out by the transfer mechanism 118, and is loaded into the empty processing chamber 104C as indicated by the transfer path Y43. Thereafter, processing in the processing chamber 104C is started.
[0192] 次いで，搬送機構 118によって、処理室 104Bに収容されていた処理済のウェハ W が取り出され，搬送経路 Y44に示すように、空き状態の測定処理室 400内へ搬入さ れる。その後，測定処理室 400内での測定処理が開始される。  [0192] Next, the processed wafer W accommodated in the processing chamber 104B is taken out by the transfer mechanism 118, and is loaded into the empty measurement processing chamber 400 as indicated by the transfer path Y44. Thereafter, measurement processing in the measurement processing chamber 400 is started.
[0193] 次いで，搬送機構 118によって、処理室 104A内に収容されていた処理済のゥェ ハ Wが取り出され，搬送経路 Y45に示すように、空き状態の処理室 104B内へ搬入 される。その後，処理室 104B内での処理が開始される。  [0193] Next, the processed wafer W accommodated in the processing chamber 104A is taken out by the transfer mechanism 118, and is transferred into the empty processing chamber 104B as indicated by the transfer path Y45. Thereafter, processing in the processing chamber 104B is started.
[0194] 続いて，パス部 122内にウェハ Wが搬入されると，当該ウェハ Wが搬送機構 118に よって取り出され，搬送経路 Y46に示すように、空き状態の処理室 104A内へ搬入さ れる。その後，処理室 104A内での処理が開始される。 [0194] Subsequently, when the wafer W is loaded into the pass section 122, the wafer W is taken out by the transfer mechanism 118 and is transferred into the empty processing chamber 104A as indicated by the transfer path Y46. It is. Thereafter, processing in the processing chamber 104A is started.
[0195] なお，ウェハ Wの搬出入の際には，各ゲートバルブ 106A〜106D, 107A, 107B , 406のうち必要なゲートバルブのみが開閉操作される。そして，各処理室 104A〜 104D,測定処理室 400にてウェハ Wの処理が完了する毎に、上記の操作が繰り返 し行われる。 [0195] When the wafer W is loaded / unloaded, only the necessary gate valves among the gate valves 106A to 106D, 107A, 107B, 406 are opened / closed. Each time the processing of the wafer W is completed in each of the processing chambers 104A to 104D and the measurement processing chamber 400, the above operation is repeated.
[0196] このようにして，コンタクトホールまたはビアホールが形成された処理前のウェハ W 【こ対して、処理室 104A, 104B, ¾定処理室 400,処理室 104C, 104D【こて、それ ぞれ COR処理， PHT処理，測定処理， Ti膜成膜処理， TiN膜成膜処理が連続して 施される。  [0196] Wafer W before processing in which contact holes or via holes are formed in this way [In contrast, processing chamber 104A, 104B, ¾ processing chamber 400, processing chamber 104C, 104D [trowel, respectively] COR processing, PHT processing, measurement processing, Ti film deposition processing, and TiN film deposition processing are performed in succession.
[0197] すなわち、まず、 COR処理及び PHT処理によって、ウェハ Wのコンタクトホールま たはビアホールの内壁及び底部から、自然酸ィ匕膜などの付着物が除去される。そし て，測定処理室 400にて、膜厚測定とパーティクル測定とが行われて，実際に自然 酸ィ匕膜などの付着物が（十分に）除去されたか否かが確認される。その上で，次の Ti 膜成膜処理及び TiN膜成膜処理によって、 Ti膜及び TiN膜からなるバリア層が成膜 される。これにより，ウェハ Wから自然酸ィ匕膜などの付着物が確実に除去された状態 で、ノリア層を形成することができる。  That is, first, deposits such as a natural oxide film are removed from the inner wall and bottom of the contact hole or via hole of the wafer W by COR processing and PHT processing. Then, in the measurement processing chamber 400, film thickness measurement and particle measurement are performed, and it is confirmed whether or not deposits such as natural acid film have been (sufficiently) removed. Then, a barrier layer composed of a Ti film and a TiN film is formed by the following Ti film formation process and TiN film formation process. As a result, the noria layer can be formed in a state where the deposits such as the natural oxide film are reliably removed from the wafer W.
[0198] また， 1つの測定処理室 400で膜厚測定とパーティクル測定とを行うことができるの で， COR処理及び PHT処理によって自然酸化膜除去が適正に実行されたか否かを より確実に検査することができる。例えば、 PHT処理が過剰の場合は、酸化膜が形 成されてしまうことがあるが，このような状態は膜厚測定によって検査 (検出）すること ができる。また、 PHT処理が不足の場合は， COR処理で形成された錯体がバイプロ ダクト（副生成物）として残ってしまうことがあるが，この状態はパーティクル測定によつ て検査 (検出）することができる。  [0198] In addition, since it is possible to perform film thickness measurement and particle measurement in one measurement processing chamber 400, it is more reliably inspected whether natural oxide film removal has been properly performed by COR processing and PHT processing. can do. For example, when PHT treatment is excessive, an oxide film may be formed, but such a state can be inspected (detected) by measuring the film thickness. In addition, if the PHT treatment is insufficient, the complex formed by the COR treatment may remain as a biproduct (by-product). This state can be inspected (detected) by particle measurement. it can.
[0199] 以上のように，本実施の形態に力かる基板処理装置によれば，付着物除去処理 (C OR処理及び PHT処理）の後に連続して測定処理室 400にて測定処理が実施され るので，ウェハの付着物除去処理が適正に実行されたか否かを，当該ウェハ Wの膜 厚やパーティクル (付着物を含む）を測定することによって、確実に検査することがで きる。し力も，ウェハに付着物除去処理を施した直後に，当該ウェハを大気に晒すこ となく，連続して測定処理室 400にて測定処理を施すことができるため，ウェハ上の 付着物が除去された表面 (例えばウェハ上に形成されたコンタクトホールの底部など の露出表面）に再び自然酸化膜が付着することなく，ウェハ上の膜厚測定やパーテ イタル測定を実施して検査を行うことができる。これにより，付着物除去処理の効果を 、的確かつ確実に検査することができる。 [0199] As described above, according to the substrate processing apparatus of the present embodiment, the measurement processing is performed in the measurement processing chamber 400 continuously after the deposit removal processing (COR processing and PHT processing). Therefore, whether or not the wafer deposit removal process has been properly executed can be reliably inspected by measuring the film thickness and particles (including deposits) of the wafer W concerned. Also, it is possible to expose the wafer to the atmosphere immediately after applying the deposit removal treatment to the wafer. Therefore, the measurement process can be performed continuously in the measurement processing chamber 400, so that the surface on which the deposits on the wafer have been removed (for example, the exposed surface such as the bottom of a contact hole formed on the wafer) is again applied. Inspection can be performed by measuring the film thickness on the wafer and performing the partial measurement without adhering to the natural oxide film. As a result, the effect of the deposit removal treatment can be accurately and reliably inspected.
[0200] この場合，ウェハ Wの膜厚測定やパーティクル測定の測定結果に基づいて、付着 物除去処理（COR処理及び PHT処理）のプロセスレシピ (付着物除去処理のための プロセス条件）を補正するようにしてもよい。こうすることにより，常に付着物除去処理 ( COR処理及び PHT処理)を適正に実行することができる。これにより，実際の処理 結果に応じた付着物除去処理を実行することができるため，ウェハ W上から自然酸 化膜を含む付着物を確実に除去することができる。  [0200] In this case, the process recipe (process conditions for the deposit removal process) of the deposit removal process (COR process and PHT process) is corrected based on the measurement results of the film thickness measurement and particle measurement of the wafer W. You may do it. In this way, the deposit removal process (COR process and PHT process) can always be performed properly. As a result, the deposit removal process according to the actual processing result can be executed, so that deposits including the natural oxide film can be reliably removed from the wafer W.
[0201] また，膜厚測定とパーティクル測定との測定結果に基づ 、て，次の成膜処理 (成膜 ステップ)を実行する力否かを判断するようにしてもよい。この場合，例えば膜厚測定 とパーティクル測定とにより測定された測定結果が許容範囲内にあれば，次の成膜 処理を実行可能と判断する一方、許容範囲になければ、次の成膜処理を実行不可 能と判断するようにしてもよい。これにより，常にウェハ W上の自然酸ィ匕膜を含む付着 物が除去された状態で次の成膜処理を実行することができるので，ウエノ、 W上に成 膜される膜の膜質の均一性を確保することができる。  [0201] Further, based on the measurement results of the film thickness measurement and the particle measurement, it may be determined whether or not the power to execute the next film formation process (film formation step) is determined. In this case, for example, if the measurement results measured by the film thickness measurement and the particle measurement are within the allowable range, it is determined that the next film forming process can be performed. It may be determined that execution is impossible. As a result, the next film forming process can be executed in a state where the deposits including the natural oxide film on the wafer W are always removed. Therefore, the film quality of the film formed on the wafer W is uniform. Sex can be secured.
[0202] また，付着物除去処理後に行われる測定処理室 400における測定処理は，上述し たような付着物除去処理が適正に実行された力否かを検査するための測定の他に， 次の成膜処理が施される下地膜の膜厚測定を含んでいてもよい。この場合には，測 定処理室 400内で、ウェハ上の付着物除去処理が施された表面 (例えばウェハ上に 形成されたコンタクトホールの底部などの露出表面）の膜厚測定と、次の成膜処理が 施される下地膜 (例えばウェハ上に形成された下地となる膜)の膜厚測定と、が行わ れる一方，付着物除去処理が施された表面の付着物測定も行われる。これによれば ,付着物除去処理が適正に実行されたカゝ否かを検査するための膜厚測定と，次の成 膜処理が施される下地膜の膜厚測定とが同時に実行されるので，測定処理に力かる 時間を大幅に短縮することができる。 [0203] さらに，測定処理室 400における測定処理は，成膜処理後に実行されてもよい。こ の場合には，例えば当該成膜処理により形成された膜の膜厚測定が行われ得る。こ れにより，成膜処理が適正に実行されたか否かを、当該膜厚測定によって検査する ことができる。また，このように測定された測定結果に基づいて，成膜処理を実行する ためのプロセスレシピ (成膜処理のプロセス条件）を補正することもできる。これにより ,以降のウェハの処理において常に適正な成膜処理を実行できる。なお，測定処理 室 400における測定処理は，付着物除去処理前に行われてもよい。 [0202] In addition, the measurement processing in the measurement processing chamber 400 performed after the deposit removal processing includes the following in addition to the measurement for checking whether or not the deposit removal processing as described above is properly performed. The film thickness measurement of the base film on which the film forming process is performed may be included. In this case, in the measurement processing chamber 400, the film thickness on the surface of the wafer subjected to the deposit removal process (for example, the exposed surface of the bottom of the contact hole formed on the wafer) is measured, and the following While film thickness measurement is performed on a base film (for example, a base film formed on a wafer) on which film formation processing is performed, adhesion measurement on the surface on which the deposit removal process has been performed is also performed. According to this, the film thickness measurement for inspecting whether the deposit removal process has been properly executed and the film thickness measurement of the base film to be subjected to the next film formation process are simultaneously executed. As a result, the time required for the measurement process can be significantly reduced. [0203] Furthermore, the measurement process in the measurement process chamber 400 may be performed after the film formation process. In this case, for example, the film thickness of the film formed by the film forming process can be measured. As a result, it is possible to inspect whether or not the film forming process has been properly executed by measuring the film thickness. In addition, based on the measurement results measured in this way, the process recipe (process conditions for the film formation process) for executing the film formation process can be corrected. Thus, it is possible to always perform an appropriate film forming process in subsequent wafer processing. The measurement process in the measurement process chamber 400 may be performed before the deposit removal process.
[0204] (測定処理室の測定処理）  [0204] (Measurement process in the measurement process chamber)
ここで，このような測定処理室 400における測定処理について、図面を参照しなが ら説明する。図 14は、測定処理の一例を示すフローチャートである。図 14に示すよう に，まず、ステップ S110にて、測定条件レシピの設定が行われる。具体的には、測 定処理情報 470の測定条件レシピ 476に基づ 、て、例えばステージ 405の回転速 度や測定範囲などの条件が設定される。  Here, the measurement process in the measurement process chamber 400 will be described with reference to the drawings. FIG. 14 is a flowchart illustrating an example of the measurement process. As shown in Fig. 14, first, a measurement condition recipe is set in step S110. Specifically, on the basis of the measurement condition recipe 476 of the measurement processing information 470, conditions such as the rotational speed of the stage 405 and the measurement range are set.
[0205] 次いで，ステップ S 120にて、測定処理室 400にウェハ Wが搬入され，ステップ S 13 0にて、膜厚測定とパーティクル測定とが実行される。このとき，膜厚測定及びパーテ イタル測定に先立って，例えばノッチ検出によるウェハの位置合わせが行われ，必要 に応じて、画像処理部 420によりウェハ Wの表面画像が撮像されてパターン認識が 行われる。そして，例えばパターン認識によって得られた測定ポイント（または測定範 囲）について、膜厚測定とパーティクル測定とが実施される。このとき，例えばウェハ Wを静止させた状態で膜厚測定部 410によってウェハ Wの測定ポイントの膜厚測定 が行われてから，ウェハ Wを回転させながらパーティクル測定部 430によってウェハ W表面のパーティクル測定が行われる。  [0205] Next, in step S120, the wafer W is loaded into the measurement processing chamber 400, and in step S130, film thickness measurement and particle measurement are performed. At this time, prior to the film thickness measurement and the partition measurement, the wafer is aligned by, for example, notch detection, and the surface image of the wafer W is captured by the image processing unit 420 as necessary to perform pattern recognition. . Then, for example, film thickness measurement and particle measurement are performed on a measurement point (or measurement range) obtained by pattern recognition. At this time, for example, after the film thickness measurement unit 410 measures the film thickness at the measurement point of the wafer W while the wafer W is stationary, the particle measurement unit 430 measures the particle on the surface of the wafer W while rotating the wafer W. Is done.
[0206] 続いて，ステップ S140にて、膜厚測定とパーティクル測定との測定結果に基づい て、それぞれの評価データが作成される。ステップ S150にて、得られた測定結果及 び評価データが、制御部 200の EC300へ送信される。その後、ステップ S140にて、 ウェハ Wが搬出される。  [0206] Subsequently, in step S140, each evaluation data is created based on the measurement results of the film thickness measurement and the particle measurement. In step S150, the obtained measurement results and evaluation data are transmitted to EC 300 of control unit 200. Thereafter, in step S140, the wafer W is unloaded.
[0207] 以上のように，基板処理装置 103の第 1共通搬送室 102に測定処理室 400が接続 されたことにより，処理済みのウェハ Wを大気に露出することなく，膜厚測定やパーテ イタル測定を直ちに実施することができる。すなわち，ウェハ wに例えば自然酸ィ匕膜 が生成されるなどしてウェハの状態が変質することなく，膜厚測定やパーティクル測 定を直ちに実施することができる。例えば、上述したように、 COR処理及び PHT処理 の後に，ウェハ Wを大気に露出することなく，直ちに膜厚測定やパーティクル測定を 実施することができる。これにより，ウェハ Wに例えば自然酸ィ匕膜が付着することなく ,次の成膜処理を実行することができる。 [0207] As described above, since the measurement processing chamber 400 is connected to the first common transfer chamber 102 of the substrate processing apparatus 103, the processed wafer W is not exposed to the atmosphere, and film thickness measurement and Ital measurements can be performed immediately. In other words, film thickness measurement and particle measurement can be performed immediately without changing the wafer state by, for example, forming a natural acid film on the wafer w. For example, as described above, film thickness measurement and particle measurement can be performed immediately after the COR process and the PHT process without exposing the wafer W to the atmosphere. As a result, the next film forming process can be executed without, for example, a natural oxide film adhering to the wafer W.
[0208] 本実施の形態では，測定処理室 400を基板処理装置の 1つのモジュール（ユニット )として構成している。これにより，既存の基板処理装置に対しても、測定処理室 400 を容易に取付けることができる。また，測定処理室 400を基板処理装置にモジュール (ユニット）として取付けているため，ウェハ Wを測定処理室 400に搬入するだけで測 定処理を実行できる。すなわち，測定処理室を別の装置として構成する場合に比し て、膜厚測定やパーティクル測定にかかる時間と手間を大幅に軽減することができる In this embodiment, the measurement processing chamber 400 is configured as one module (unit) of the substrate processing apparatus. As a result, the measurement processing chamber 400 can be easily attached to an existing substrate processing apparatus. In addition, since the measurement processing chamber 400 is attached to the substrate processing apparatus as a module (unit), the measurement processing can be executed simply by loading the wafer W into the measurement processing chamber 400. In other words, the time and labor required for film thickness measurement and particle measurement can be greatly reduced compared to the case where the measurement processing chamber is configured as a separate device.
[0209] また，膜厚測定及びパーティクル測定を 1つの測定処理室 400にて行うので，各測 定を別の装置にて行うべく装置を 2台設置することに比して，フットプリントを大幅に削 減させることができる。また，測定処理室 400自体をコンパクトィ匕することができるので ,フットプリントをより一層削減することができる。 [0209] In addition, since film thickness measurement and particle measurement are performed in one measurement processing chamber 400, the footprint is greatly increased compared to installing two devices so that each measurement can be performed in another device. Can be reduced. Further, since the measurement processing chamber 400 itself can be made compact, the footprint can be further reduced.
[0210] なお，図 13は、 COR処理及び PHT処理の後に測定処理室 400で測定処理を行う こと〖こよって、自然酸化膜が除去されて 、るか否かを検査する場合にっ 、て示して!/ヽ るが，本発明は必ずしもこれに限定されない。成膜処理 (Ti膜成膜処理， TiN膜成膜 処理)の後にも測定処理室 400で測定処理を行って、所望の膜厚が成膜されている か否かを検査するようにしてもよい。また，測定処理室 400による測定処理は，上述し たように膜厚測定及びパーティクル測定の両方を行ってもょ ヽが， Vヽずれか一方を行 うのみでもよい。  [0210] FIG. 13 shows the case where the natural oxide film is removed by performing the measurement process in the measurement processing chamber 400 after the COR process and the PHT process. As shown !, the present invention is not necessarily limited to this. Even after the film forming process (Ti film forming process, TiN film forming process), a measurement process is performed in the measurement processing chamber 400 to check whether or not a desired film thickness is formed. Good. In addition, as described above, the measurement processing in the measurement processing chamber 400 may perform both the film thickness measurement and the particle measurement, or only V deviation.
[0211] また，基板処理装置 103の処理室の構成は，図 13に示すものに限られない。例え ば、成膜処理としてベース酸化膜成膜処理 (UV処理)及び High— K膜成膜処理（ MOCVD処理）を行う場合には，処理室 104C, 104Dを、それぞれ、ベース酸化膜 成膜処理 (UV処理)室， High— K膜成膜処理 (MOCVD処理)室として構成しても よい。この場合の搬送処理は，図 13に示す場合と同様である。 [0211] The configuration of the processing chamber of the substrate processing apparatus 103 is not limited to that shown in FIG. For example, when base oxide film formation processing (UV processing) and high-K film formation processing (MOCVD processing) are performed as film formation processing, the processing chambers 104C and 104D are respectively formed in the base oxide film formation processing. (UV processing) chamber, High-K film deposition processing (MOCVD processing) chamber Good. The transport process in this case is the same as that shown in FIG.
[0212] また，測定処理室 400の取付け位置は，図 10に示す場合に限られない。例えば、 第 1共通搬送室 102及び第 2共通搬送室 120のうち処理室を取付けられる部分には ,どこにでも取付けることができる。さらに，本実施の形態では，測定処理室 400を、 例えば図 6に示すような複数の共通搬送室が連結されたタイプの基板処理装置に取 付けた場合について説明されているが，これに限られない。例えば、図 1に示すよう な単一の共通搬送室を有するタイプの基板処理装置に取付けられてもよ 、。例えば 図 1に示すような基板処理装置であれば、共通搬送室 102を 7角形以上の多角形に 構成することにより，処理室 104A〜104Dに追カ卩して測定処理室 400を取付けるこ とがでさる。 [0212] Further, the mounting position of the measurement processing chamber 400 is not limited to the case shown in FIG. For example, a portion of the first common transfer chamber 102 and the second common transfer chamber 120 where the processing chamber can be attached can be installed anywhere. Furthermore, in the present embodiment, a case is described in which the measurement processing chamber 400 is attached to a substrate processing apparatus of a type in which a plurality of common transfer chambers are connected as shown in FIG. 6, for example. I can't. For example, it may be attached to a substrate processing apparatus of a type having a single common transfer chamber as shown in FIG. For example, in the case of a substrate processing apparatus as shown in FIG. 1, the common transfer chamber 102 is formed in a polygon of a heptagon or more so that the measurement processing chamber 400 can be mounted in addition to the processing chambers 104A to 104D. It is out.
[0213] また，本発明は，複数の機器カゝら構成されるシステムに適用されてもよいし， 1つの 機器のみ力もなる装置に適用されてもよい。  [0213] In addition, the present invention may be applied to a system constituted by a plurality of equipment units, or may be applied to an apparatus that has the power of only one equipment.
[0214] また、前記各実施の形態の各種機能を実現するためのソフトウェアのプログラムを 記憶した記憶媒体等の媒体をシステム或いは装置に供給して，当該システム或いは 装置のコンピュータ (CPUや MPU)に当該記憶媒体等の媒体に格納されたプロダラ ムを読み出させて実行させることによって、前記各実施の形態の各種機能は実現 (達 成)され得る。  [0214] Further, a medium such as a storage medium storing software programs for realizing the various functions of the above embodiments is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus is supplied. By reading and executing a program stored in a medium such as the storage medium, the various functions of the above-described embodiments can be realized (achieved).
[0215] この場合，そのようなプログラム自体、及び、そのようなプログラムを記憶した記憶媒 体等の媒体も、本発明の保護範囲に含まれるべきである。  In this case, such a program itself and a medium such as a storage medium storing such a program should also be included in the protection scope of the present invention.
[0216] プログラムを供給するための記憶媒体等の媒体としては，例えば，フレキシブル (フ ロッピー）ディスク，ハードディスク，光ディスク，光磁気ディスク， CD-ROM, CD— R, CD-RW, DVD-ROM, DVD -RAM, DVD-RW, DVD+RW,磁気テー プ，不揮発性のメモリカード， ROM,或いはネットワークを介したダウンロードなどを 用!/、ることができる。  [0216] Examples of media such as storage media for supplying programs include flexible (floppy) disks, hard disks, optical disks, magneto-optical disks, CD-ROMs, CD-Rs, CD-RWs, DVD-ROMs, You can use DVD-RAM, DVD-RW, DVD + RW, magnetic tape, non-volatile memory card, ROM, or network download!
[0217] なお，記憶媒体等の媒体力 読み出されるプログラムのみを実行することにより前 記各実施の形態の機能が実現される場合だけでなく，当該プログラムの指示に基づ いてコンピュータ上で稼動している OSなどが実際の処理の一部または全部を行って 前記各実施の形態の機能が実現される場合にも，そのようなプログラム自体、及び、 そのようなプログラムを記憶した記憶媒体等の媒体は、本発明の保護範囲に含まれ るべさである。 [0217] It should be noted that not only when the functions of the above-described embodiments are realized by executing only a program that is read out of the medium power of a storage medium or the like, but is operated on a computer based on the instructions of the program. Even when an OS or the like performs part or all of the actual processing to realize the functions of the above embodiments, such a program itself, and A medium such as a storage medium storing such a program should be included in the protection scope of the present invention.
[0218] さらに，記憶媒体等の媒体力も読み出されるプログラムが，コンピュータに挿入され た機能拡張ボードやコンピュータに接続された機能拡張ユニットに備わるメモリに書 き込まれた後で，当該プログラムの指示に基づいて当該機能拡張ボードあるいは当 該機能拡張ユニットに備わった CPUなどが実際の処理の一部または全部を行って 前記各実施の形態の機能が実現される場合にも，そのようなプログラム自体、及び、 そのようなプログラムを記憶した記憶媒体等の媒体は、本発明の保護範囲に含まれ るべさである。  [0218] Furthermore, after a program for reading out the medium power of a storage medium or the like is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the program is instructed. Even when the functions of the above-described embodiments are realized by the CPU of the function expansion board or the function expansion unit performing part or all of the actual processing based on the functions, the program itself, A medium such as a storage medium storing such a program should be included in the protection scope of the present invention.
[0219] 以上，添付図面を参照しながら、本発明の好適な実施の形態について説明したが ,本発明は係る例に限定されない。当業者であれば，特許請求の範囲に記載された 範疇内において，各種の変更例または修正例に想到し得ることは明らかであり，それ らについても当然に本発明の技術的範囲に属するものと了解される。  [0219] While the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, which naturally belong to the technical scope of the present invention. It is understood.

Claims

請求の範囲 The scope of the claims
[1] 被処理基板に所定の処理を施す複数の処理室と、  [1] A plurality of processing chambers for performing predetermined processing on a substrate to be processed;
前記複数の処理室に共通に連結され、前記複数の処理室の各々に対して前記被 処理基板の搬出入を行う共通搬送室と、  A common transfer chamber that is commonly connected to the plurality of processing chambers, and that carries the substrate into and out of each of the plurality of processing chambers;
を備え、  With
前記複数の処理室には、  In the plurality of processing chambers,
前記被処理基板上に付着された自然酸ィ匕膜を含む付着物をプラズマによらな ヽガ ス成分との化学反応及び熱処理によって除去するための付着物除去処理室と， 前記被処理基板上に成膜処理を施すための成膜処理室と、  A deposit removing treatment chamber for removing deposits including a natural acid film deposited on the substrate to be processed by a chemical reaction with a gas component such as plasma and heat treatment; and on the substrate to be processed. A film forming process chamber for performing a film forming process on
前記被処理基板の測定処理を行うための測定処理室と、  A measurement processing chamber for measuring the substrate to be processed;
が含まれている  It is included
ことを特徴とする基板処理装置。  A substrate processing apparatus.
[2] 前記付着物除去処理室は，  [2] The deposit removal treatment chamber
前記被処理基板上の前記付着物をガス成分と化学反応させて生成物を生成する ための生成物生成処理室と、  A product generation processing chamber for generating a product by chemically reacting the deposit on the substrate to be processed with a gas component;
前記生成物生成処理室にて前記被処理基板上に生成された前記生成物を熱処 理により除去するための生成物除去処理室と、  A product removal processing chamber for removing the product generated on the substrate to be processed in the product generation processing chamber by heat treatment;
の 2つの処理室により構成されて 、る  It consists of two processing chambers
ことを特徴とする請求項 1に記載の基板処理装置。  The substrate processing apparatus according to claim 1, wherein:
[3] 前記成膜処理室は、 [3] The film forming chamber is
前記被処理基板上に第 1膜を成膜する第 1膜成膜処理室と、  A first film deposition chamber for depositing a first film on the substrate to be treated;
前記第 1膜成膜処理室にて成膜された前記第 1膜上に第 2膜を成膜する第 2膜成 膜処理室と、  A second film formation processing chamber for forming a second film on the first film formed in the first film formation processing chamber;
の 2つの処理室により構成されて 、る  It consists of two processing chambers
ことを特徴とする請求項 1に記載の基板処理装置。  The substrate processing apparatus according to claim 1, wherein:
[4] 前記測定処理室は、 [4] The measurement processing chamber includes:
前記被処理基板上に成膜された膜の膜厚を測定する膜厚測定部と、  A film thickness measuring unit for measuring the film thickness of the film formed on the substrate to be processed;
前記被処理基板上のパーティクルを測定するパーティクル測定部と、 を備えることを特徴とする請求項 1に記載の基板処理装置。 A particle measuring unit for measuring particles on the substrate to be processed; The substrate processing apparatus according to claim 1, further comprising:
[5] 前記測定処理室は、前記被処理基板の表面画像を撮像して認識するための画像 処理部を備える [5] The measurement processing chamber includes an image processing unit for capturing and recognizing a surface image of the substrate to be processed.
ことを特徴とする請求項 1に記載の基板処理装置。  The substrate processing apparatus according to claim 1, wherein:
[6] 被処理基板に所定の処理を施す複数の処理室と、前記複数の処理室に共通に連 結された共通搬送室と、前記共通搬送室内に設けられた前記被処理基板を搬送す るための搬送機構と、をそれぞれ備えた複数の真空処理装置と、 [6] A plurality of processing chambers for performing a predetermined process on the substrate to be processed, a common transfer chamber commonly connected to the plurality of processing chambers, and the substrate to be processed provided in the common transfer chamber are transferred. A plurality of vacuum processing devices each comprising a transport mechanism for
前記複数の真空処理装置を互いに連結するパス部と、  A path unit connecting the plurality of vacuum processing apparatuses to each other;
を備え、  With
前記複数の処理室には、  In the plurality of processing chambers,
前記被処理基板上に付着された自然酸ィ匕膜を含む付着物をプラズマによらな ヽガ ス成分との化学反応及び熱処理によって除去するための付着物除去処理室と， 前記被処理基板上に成膜処理を施すための成膜処理室と、  A deposit removing treatment chamber for removing deposits including a natural acid film deposited on the substrate to be processed by a chemical reaction with a gas component such as plasma and heat treatment; and on the substrate to be processed. A film forming process chamber for performing a film forming process on
前記被処理基板の測定処理を行うための測定処理室と、  A measurement processing chamber for measuring the substrate to be processed;
が含まれている  It is included
ことを特徴とする基板処理装置。  A substrate processing apparatus.
[7] 前記付着物除去処理室は， [7] The deposit removal treatment chamber
前記被処理基板上の前記付着物をガス成分と化学反応させて生成物を生成する ための生成物生成処理室と、  A product generation processing chamber for generating a product by chemically reacting the deposit on the substrate to be processed with a gas component;
前記生成物生成処理室にて前記被処理基板上に生成された前記生成物を熱処 理により除去するための生成物除去処理室と、  A product removal processing chamber for removing the product generated on the substrate to be processed in the product generation processing chamber by heat treatment;
の 2つの処理室により構成されて 、る  It consists of two processing chambers
ことを特徴とする請求項 6に記載の基板処理装置。  The substrate processing apparatus according to claim 6, wherein:
[8] 前記成膜処理室は、 [8] The film forming chamber is
前記被処理基板上に第 1膜を成膜する第 1膜成膜処理室と、  A first film deposition chamber for depositing a first film on the substrate to be treated;
前記第 1膜成膜処理室にて成膜された前記第 1膜上に第 2膜を成膜する第 2膜成 膜処理室と、  A second film formation processing chamber for forming a second film on the first film formed in the first film formation processing chamber;
の 2つの処理室により構成されて 、る ことを特徴とする請求項 6に記載の基板処理装置。 It consists of two processing chambers The substrate processing apparatus according to claim 6, wherein:
[9] 前記成膜処理室は、 [9] The film forming chamber is
前記被処理基板上に第 1膜を成膜する第 1膜成膜処理室と、  A first film deposition chamber for depositing a first film on the substrate to be treated;
前記第 1膜成膜処理室にて成膜された前記第 1膜上に第 2膜を成膜する第 2膜成 膜処理室と、  A second film formation processing chamber for forming a second film on the first film formed in the first film formation processing chamber;
の 2つの処理室の組を複数含んで!/、る  Including multiple pairs of two processing chambers!
ことを特徴とする請求項 6に記載の基板処理装置。  The substrate processing apparatus according to claim 6, wherein:
[10] 前記付着物除去処理室で処理される被処理基板は，コンタクトホールまたはビアホ ールが形成された被処理基板であり， [10] The substrate to be processed in the deposit removal processing chamber is a substrate to be processed in which contact holes or via holes are formed.
前記成膜処理室は，  The film forming chamber is
前記被処理基板に形成されたコンタクトホールまたはビアホールの内側に第 1バリ ァ層を成膜する第 1バリア層成膜処理室と、  A first barrier layer deposition processing chamber for depositing a first barrier layer inside a contact hole or via hole formed in the substrate to be treated;
前記第 1バリア層成膜処理室にて成膜された前記第 1バリア層の上側に第 2バリア 層を成膜する第 2バリア層成膜処理室と、  A second barrier layer deposition processing chamber for depositing a second barrier layer above the first barrier layer deposited in the first barrier layer deposition treatment chamber;
により構成されている  Consists of
ことを特徴とする請求項 1または 6に記載の基板処理装置。  The substrate processing apparatus according to claim 1, wherein the substrate processing apparatus is a substrate processing apparatus.
[11] 前記付着物除去処理室で処理される被処理基板は、シリコン基板であり， [11] The substrate to be processed in the deposit removal processing chamber is a silicon substrate,
前記成膜処理室は、  The film forming chamber is
前記被処理基板上に酸素ラジカルによってベース酸化膜層を成膜するベース酸化 膜層成膜処理室と、  A base oxide film forming process chamber for forming a base oxide film layer by oxygen radicals on the substrate to be processed;
前記ベース酸化膜層成膜処理室にて前記ベース酸化膜層が成膜された被処理基 板に高誘電体ゲート酸化膜を成膜する高誘電体ゲート酸化膜成膜処理室と、 により構成されている  A high dielectric gate oxide film forming treatment chamber for forming a high dielectric gate oxide film on a substrate on which the base oxide film layer is formed in the base oxide film forming film processing chamber; Has been
ことを特徴とする請求項 1または 6に記載の基板処理装置。  The substrate processing apparatus according to claim 1, wherein the substrate processing apparatus is a substrate processing apparatus.
[12] 被処理基板上に付着された自然酸化膜を含む付着物をプラズマによらな！/ヽガス成 分との化学反応及び熱処理によって除去する付着物除去ステップと、 [12] The deposits including the natural oxide film deposited on the substrate are treated with plasma! A deposit removal step that is removed by a chemical reaction with the soot / gas component and heat treatment;
前記付着物除去ステップの後に、前記被処理基板の測定処理を行う測定ステップ と， 前記測定ステップの後に、当該被処理基板上に成膜処理を施す成膜ステップと， を備えたことを特徴とする基板処理方法。 A measurement step of performing measurement processing of the substrate to be processed after the deposit removal step; And a film forming step of performing a film forming process on the substrate to be processed after the measuring step.
[13] 前記付着物除去ステップは、  [13] The deposit removing step includes:
前記被処理基板上の前記付着物をガス成分と化学反応させて生成物を生成する 生成物生成ステップと、  A product generation step of generating a product by chemically reacting the deposit on the substrate to be processed with a gas component;
前記生成物生成ステップにて前記被処理基板上に生成された前記生成物を熱処 理により除去する生成物除去ステップと、  A product removal step of removing the product generated on the substrate to be processed in the product generation step by heat treatment;
を有することを特徴とする請求項 12に記載の基板処理方法。  13. The substrate processing method according to claim 12, further comprising:
[14] 前記測定ステップは、前記付着物除去ステップが適正に実行されたカゝ否かを検査 する検査測定処理を行うステップである [14] The measurement step is a step of performing an inspection measurement process for inspecting whether or not the deposit removal step is properly executed.
ことを特徴とする請求項 13に記載の基板処理方法。  The substrate processing method according to claim 13.
[15] 前記測定ステップは， [15] The measurement step includes:
前記付着物除去ステップが施された前記被処理基板の表面の膜厚測定を行う膜 厚測定ステップと、  A film thickness measurement step for measuring a film thickness of the surface of the substrate to be processed that has been subjected to the deposit removal step;
前記付着物除去ステップが施された前記被処理基板の表面の付着物測定を行う 付着物測定ステップと、  An adhering matter measuring step for measuring an adhering matter on the surface of the substrate to be processed which has been subjected to the adhering matter removing step;
を有しており、  Have
当該膜厚測定ステップ及び当該付着物測定ステップは、 1つの測定処理室内で実 行される  The film thickness measurement step and the deposit measurement step are performed in one measurement processing chamber.
ことを特徴とする請求項 14に記載の基板処理方法。  15. The substrate processing method according to claim 14, wherein:
[16] 前記測定ステップは、前記膜厚測定ステップ及び前記付着物測定ステップによつ て測定された測定結果に基づ 、て、前記付着物除去ステップを実行するためのプロ セスレシピを補正するレシピ補正ステップを更に有している [16] The measurement step includes a recipe for correcting a process recipe for executing the deposit removal step based on the measurement results measured by the film thickness measurement step and the deposit measurement step. It further has a correction step
ことを特徴とする請求項 15に記載の基板処理方法。  16. The substrate processing method according to claim 15, wherein:
[17] 前記測定ステップは、前記膜厚測定ステップ及び前記付着物測定ステップによつ て測定された測定結果に基づ ヽて、次の成膜ステップを実行する力否かを判断する 判断ステップを更に有して 、る [17] The measurement step determines whether or not it is possible to execute the next film formation step based on the measurement results measured by the film thickness measurement step and the deposit measurement step. Have more
ことを特徴とする請求項 15に記載の基板処理方法。 16. The substrate processing method according to claim 15, wherein:
[18] 前記測定ステップは、 [18] The measurement step includes:
前記付着物除去ステップが適正に実行されたカゝ否かを検査する検査測定ステップ と，  An inspection measurement step for inspecting whether or not the deposit removal step is properly performed;
次の成膜ステップが施される下地膜の膜厚を測定する下地膜厚測定ステップと、 を有することを特徴とする請求項 13に記載の基板処理方法。  14. The substrate processing method according to claim 13, comprising: a base film thickness measuring step for measuring a film thickness of the base film on which the next film forming step is performed.
[19] 前記測定ステップは、 [19] The measurement step includes:
前記付着物除去ステップが施された前記被処理基板の表面の膜厚測定を行う膜 厚測定ステップと、  A film thickness measurement step for measuring a film thickness of the surface of the substrate to be processed that has been subjected to the deposit removal step;
前記付着物除去ステップが施された前記被処理基板の表面の付着物測定を行う 付着物測定ステップと、  An adhering matter measuring step for measuring an adhering matter on the surface of the substrate to be processed which has been subjected to the adhering matter removing step;
次の成膜ステップが施される下地膜の膜厚を測定する下地膜厚測定ステップと、 を有しており、  A base film thickness measurement step for measuring the film thickness of the base film on which the next film formation step is performed, and
当該膜厚測定ステップ、当該付着物測定ステップ及び当該下地膜厚測定ステップ は、 1つの測定処理室内で実行される  The film thickness measurement step, the deposit measurement step, and the base film thickness measurement step are executed in one measurement processing chamber.
ことを特徴とする請求項 15に記載の基板処理方法。  16. The substrate processing method according to claim 15, wherein:
[20] 前記成膜ステップは、 [20] The film forming step includes
前記被処理基板上に第 1膜を成膜する第 1成膜ステップと、  A first film forming step of forming a first film on the substrate to be processed;
前記第 1成膜ステップにて成膜された前記第 1膜上に第 2膜を成膜する第 2成膜ス テツプと、  A second film forming step for forming a second film on the first film formed in the first film forming step;
を有することを特徴とする請求項 12に記載の基板処理方法。  13. The substrate processing method according to claim 12, further comprising:
[21] 被処理基板上に付着された自然酸ィ匕膜を含む付着物をプラズマによらな 、ガス成 分との化学反応及び熱処理によって除去する付着物除去ステップと、 [21] A deposit removing step for removing deposits including a natural acid film deposited on a substrate to be processed by a chemical reaction with a gas component and a heat treatment such as plasma,
前記付着物除去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステツ プと、  A film forming step of performing a film forming process on the substrate to be processed after the deposit removing step;
前記成膜ステップの後に、前記被処理基板の測定処理を行う測定ステップと、 を備えたことを特徴とする基板処理方法。  A substrate processing method comprising: a measurement step of performing measurement processing of the substrate to be processed after the film forming step.
[22] 前記測定ステップは，前記成膜ステップによって形成された膜の膜厚測定を行う成 膜厚測定ステップを有する ことを特徴とする請求項 21に記載の基板処理方法。 [22] The measurement step includes a film thickness measurement step for measuring a film thickness of the film formed by the film formation step. The substrate processing method according to claim 21, wherein:
[23] 前記測定ステップは、前記成膜厚測定ステップによって測定された測定結果に基 づ 、て、前記成膜ステップを実行するためのプロセスレシピを補正するレシピ補正ス テツプを更に有している [23] The measurement step further includes a recipe correction step for correcting a process recipe for executing the film formation step based on the measurement result measured by the film formation thickness measurement step.
ことを特徴とする請求項 22に記載の基板処理方法。  The substrate processing method according to claim 22, wherein:
[24] 被処理基板の測定処理を行う測定ステップと、 [24] a measurement step for performing measurement processing of the substrate to be processed;
前記測定ステップの後に、前記被処理基板上に付着された自然酸ィ匕膜を含む付 着物をプラズマによらないガス成分との化学反応及び熱処理によって除去する付着 物除去ステップと、  After the measuring step, the deposit removing step for removing the deposit including the natural acid film deposited on the substrate to be processed by a chemical reaction with a gas component not based on plasma and a heat treatment;
前記付着物除去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステツ プと、  A film forming step of performing a film forming process on the substrate to be processed after the deposit removing step;
を備えたことを特徴とする基板処理方法。  A substrate processing method comprising:
[25] コンピュータに， [25]
被処理基板上に付着された自然酸化膜を含む付着物をプラズマによらな！/ヽガス成 分との化学反応及び熱処理によって除去する付着物除去ステップと、  The deposits including the natural oxide film deposited on the substrate to be processed are caused by plasma! A deposit removal step that is removed by a chemical reaction with the soot / gas component and heat treatment;
被処理基板の測定処理を行う測定ステップと，  A measurement step for measuring the substrate to be processed;
前記付着物除去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステツ プと，  A film forming step of performing a film forming process on the substrate to be processed after the deposit removing step;
を実行させるためのプログラム。  A program for running
[26] コンピュータに， [26]
被処理基板上に付着された自然酸化膜を含む付着物をプラズマによらな！/ヽガス成 分との化学反応及び熱処理によって除去する付着物除去ステップと、  The deposits including the natural oxide film deposited on the substrate to be processed are caused by plasma! A deposit removal step that is removed by a chemical reaction with the soot / gas component and heat treatment;
被処理基板の測定処理を行う測定ステップと，  A measurement step for measuring the substrate to be processed;
前記付着物除去ステップの後に、前記被処理基板上に成膜処理を施す成膜ステツ プと，  A film forming step of performing a film forming process on the substrate to be processed after the deposit removing step;
を実行させるためのプログラムを記録したコンピュータ読み取り可能な記録媒体。  The computer-readable recording medium which recorded the program for performing this.
PCT/JP2006/316747 2005-08-25 2006-08-25 Substrate processing apparatus and substrate processing method WO2007023951A1 (en)

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JP7146853B2 (en) * 2020-07-03 2022-10-04 デクセリアルズ株式会社 Method for manufacturing optical film
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