WO2006117950A1 - 情報処理装置における電力制御装置 - Google Patents
情報処理装置における電力制御装置 Download PDFInfo
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- WO2006117950A1 WO2006117950A1 PCT/JP2006/306274 JP2006306274W WO2006117950A1 WO 2006117950 A1 WO2006117950 A1 WO 2006117950A1 JP 2006306274 W JP2006306274 W JP 2006306274W WO 2006117950 A1 WO2006117950 A1 WO 2006117950A1
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- power
- program
- power control
- information
- state
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a power control device in an information processing device.
- the information processing apparatus In the information processing apparatus
- microprocessors including microcomputers, microcontrollers, and digital signal processors
- sequencers including static configuration logic, and dynamically reconfigurable logic.
- static configuration logic including static configuration logic, and dynamically reconfigurable logic.
- program unit in this specification includes a process unit, a thread unit, and a task unit.
- Patent Document 1 JP-A-8-152945
- Patent Document 2 JP-A-8-6681
- Figures 34 and 35 show the transition processes of efficient scheduling and inefficient scheduling from the viewpoint of power consumption.
- a power control device is a device that controls power consumed inside an information processing device, and stores power control information for each program in a storage area that is distinguished by program identification information.
- the power context reference means for referring to the power control information about the desired program from the power context storage means, and the power control information referred to by the power context reference means, the information processing device And a power state changing means for changing a state of power consumed internally.
- the power control apparatus further includes a power control register that stores power control information for a program being executed in the information processing apparatus, and the power context reference unit is in parallel with instruction execution of the information processing apparatus.
- Power context save / restore control means for saving / returning the contents of the power control register to / from the power context storage means, and the power state changing means is stored in the power control information stored in the power control register. Based on this, it is preferable to change the state of the power consumed inside the information processing apparatus. This allows power control information to be saved and restored without degrading program processing performance, even in a system that frequently switches and processes multiple programs. Control becomes possible.
- the power context reference means refers to power control information of a first program different from a program being executed in the information processing apparatus when the first program is not executed. It is preferable to include a means of prior reference. As a result, even in a system that executes multiple programs, the process for changing the power state and the schedule process for program allocation can be performed in advance before executing the program allocation, which degrades the program processing performance. Power control can be implemented without any problems.
- the power state changing means is prior to execution of the first program based on power control information of the first program referenced by the power context advance reference means. It is preferable to change the power state in advance. Yes. As a result, the processor can be changed to a power state capable of executing the first program more quickly, and performance degradation due to waiting for the power state change can be suppressed.
- the power context advance reference means refers to power control information corresponding to the first program prior to execution of the first program, and determines a power state change time and program allocation. It is preferable to prohibit the change of the power state when it is determined that the change of the power state is not effective based on the time information. As a result, performance degradation due to mismatch between the processor state and the power control state can be efficiently suppressed.
- the power control information includes a success rate or a failure rate of past power allocation
- the power context reference unit is based on the success rate or the failure rate of the power control information. It is preferable to include speculative power state change determination means for determining whether or not to change the power state when executing the program. This effectively suppresses performance degradation due to mismatch between the processor state and the power control state.
- the power context reference unit selects a program that minimizes a current power state and a power change from power control information for each program stored in the power context storage unit, and It preferably includes a program schedule means to be assigned to the information processing apparatus. As a result, the total power consumption during the execution of multiple programs can be efficiently reduced.
- the power context reference means rearranges the power control information for each program stored in the power context storage means in the order of the program that minimizes the power change between the programs, It is preferable that program schedule means to be assigned to the information processing apparatus is included. As a result, the total power consumption when executing multiple programs can be efficiently reduced.
- a load detection unit that detects a current operation state of the information processing device, a power state detection unit that detects a current power state of the information processing device, and the load detection unit
- the detected load and the power information detected by the power state detecting means The load power determination means for determining in advance that the current program operation cannot be continued from the information, and the program schedule means for switching the program when it is determined that the continuation cannot be performed. Is preferable. As a result, it is possible to suppress performance degradation due to waiting for the power state change, and at the same time, it is possible to more actively implement power state change control because the performance degradation is small.
- Another power control apparatus of the present invention is an apparatus that controls power consumed in a plurality of physical processors, and stores information for identifying a power supply group to which the physical processors physically belong. It is characterized by comprising power supply group storage means and program schedule means for deciding which physical processor to allocate each program based on the contents of the power supply group storage means.
- FIG. 1 is a block diagram showing a configuration of a power control apparatus according to a first embodiment of the present invention.
- FIG. 2 is a diagram illustrating a logical configuration example of a power context storage device.
- FIG. 3 is a diagram illustrating a logical configuration example of a power context storage device.
- FIG. 4 is a diagram illustrating a logical configuration example of power control information.
- FIG. 5 is a diagram showing a detailed configuration example of the power state change device.
- FIG. 6 is a diagram illustrating a detailed configuration example of the power state change device.
- FIG. 7 is a block diagram showing a configuration of a power control apparatus according to a second embodiment of the present invention.
- FIG. 8 is a block diagram showing a configuration of a power control apparatus according to a third embodiment of the present invention.
- FIG. 9 is a diagram showing a detailed configuration example of the power advance control device.
- FIG. 10 is a diagram showing an operation timing of the power control apparatus according to the third embodiment of the present invention.
- FIG. 11 is a flowchart for explaining an operation procedure of the power control apparatus according to the third embodiment of the present invention.
- FIG. 12 is a block diagram showing a configuration of a power control apparatus according to a fourth embodiment of the present invention.
- FIG. 13 is a diagram illustrating a detailed configuration example of the speculative power state change determination device.
- FIG. 14 is a flowchart for explaining an operation procedure of the power control apparatus according to the fourth embodiment of the present invention.
- FIG. 15 is a flowchart showing an example of a procedure for calculating a past success rate.
- FIG. 16 is a block diagram showing a configuration of a device that calculates a success rate.
- FIG. 17 is a block diagram illustrating an example of a configuration of a device that updates information in the power context storage device with a value corresponding to the operation state of the program when the program is switched.
- FIG. 18 is a diagram illustrating a detailed configuration example of the speculative power state change determination device.
- FIG. 19 is a flowchart showing an example of a procedure for calculating a normal minimum time.
- FIG. 20 is a block diagram showing a configuration of a power control apparatus according to a sixth embodiment of the present invention.
- FIG. 21 is a diagram illustrating a detailed configuration example of a power scheduler.
- FIG. 22 is a flowchart for explaining an operation procedure of the power control apparatus according to the sixth embodiment of the present invention.
- FIG. 23 is a diagram showing an operation timing of the power control apparatus according to the sixth embodiment of the present invention.
- FIG. 24 is a diagram illustrating a detailed configuration example of a power scheduler.
- FIG. 25 is a block diagram showing a configuration of a power control apparatus according to an eighth embodiment of the present invention.
- FIG. 26 is a diagram illustrating a detailed configuration example of the load power determination device.
- FIG. 27 is a flowchart for explaining an operation procedure of the power control apparatus according to the eighth embodiment of the present invention.
- FIG. 28 is a block diagram showing a configuration of a power control apparatus according to a ninth embodiment of the present invention.
- FIG. 29 is a diagram showing a logical configuration example of a power supply group storage device.
- FIG. 30 is a diagram showing a physical arrangement example of a processor and a power supply group storage device.
- FIG. 31 is a diagram showing an example of program allocation for heat distribution.
- FIG. 32 is a diagram illustrating an example of an ideal voltage change.
- FIG. 33 is a diagram showing an example of voltage change with a realistic transition time.
- FIG. 34 is a diagram showing an example of efficient scheduling with a power consumption viewpoint.
- FIG. 35 is a diagram showing an example of inefficient scheduling with respect to power consumption.
- FIG. 1 is a block diagram showing the configuration of the power control apparatus 100 according to the first embodiment.
- Figure 1 shows the power controller 100 installed inside the microprocessor 1000 (information processor).
- the power controller 100 can also be installed outside the microprocessor 1000 (information processor). It is.
- the power context storage device ZA105 is connected to the processor bus access control device ZA104 and can read and write from the microprocessor 1000.
- the power context storage device ZA105 is connected to the power context reference device ZB101, and outputs power control information ZA103 corresponding to the identification number requested from the power context reference device ZB101 to the power context reference device ZB101.
- the power state changing device ZA101 changes the power state of the microprocessor 1000 to reduce power consumption based on the power control information ZA103 supplied from the power context reference device ZB101.
- the power context reference device ZB101 accesses the power context storage device ZA105 in parallel with the processor bus access control device ZA104, but the power context reference device ZB101 uses the processor bus access control device ZA104.
- a configuration may be adopted in which the power context storage device ZA105 is accessed.
- the power control register ZA102 (FIG. 7) indicating the power control information for only the current program is not necessarily required. Based on the information in the storage device ZA105, the power state change device ZA101 is controlled.
- Power Context Storage ZA105 runs on single or multiple physical processors It is possible to effectively reduce the power consumption of the entire system by storing the power context of the program group to be executed, referring to these power contexts in advance, and performing calculations as necessary.
- the power context storage device ZA105 can be configured by a flip-flop group having an SRAM structure. It is also possible to share information other than power information in a memory space accessible by the microprocessor 1000.
- FIG. 2 shows a configuration example of the power context storage device ZA105.
- the storage area power of the power control information ZA103 corresponding to the identification number (ID) for identifying the program is configured.
- the power contest storage device ZA105 is configured using SRAM (Static Random Access Memory), it is possible to perform writing in addition to reading of the power control information ZA103.
- SRAM Static Random Access Memory
- FIG. 3 shows an example in which a program identification number (ID) is also stored as power control information ZA103 in the power context storage device ZA105.
- ID program identification number
- FIG. 4 does not necessarily need to include all of the power indicating the content example of the power control information ZA103.
- the power supply voltage information represents, for example, a voltage for supplying power to the information processing apparatus, and is used for control for reducing power consumption during operation of the information processing apparatus.
- the threshold voltage information is used for control for reducing leakage power in an information processing apparatus using a semiconductor fine process.
- the clock frequency information represents the frequency of the clock supplied to the information processing apparatus, and power reduction is realized by making this variable.
- the clock stop information is used for reduction control of unnecessary power consumption by stopping the clock supply to a circuit area unnecessary for operation.
- Tr stop information is used for output transistor stop control in order to suppress toggling of signals unnecessary for operation, or power gating Tr inserted in series in a MOS circuit to reduce leakage power. Used for stop control.
- the control target block information is a target for performing power control indicated by the power control information ZA103. Used to identify a block.
- the state change success rate information is used to perform power control based on the past success rate of speculative power state change, as will be described later.
- the preceding state change condition information specifies an activation condition for changing the power state prior to the start of the corresponding program.
- the operation mode information specifies a mode number for specifying a voltage and a frequency. For example, high
- the mode number identifies the high-speed operation mode that operates at V ⁇ voltage and high! ⁇ frequency, and the low-speed mode that operates at low! ⁇ voltage and low! ⁇ frequency, reducing the amount of information and simplifying the power setting.
- the state change condition information specifies a state condition of the information processing apparatus for the corresponding program to change the power. For example, address information during execution of the program, privilege level status, memory access status such as cache miss, etc. are specified, and the power change is activated only when these match.
- the state change permission information specifies that the corresponding program is prohibited or permitted to change power.
- FIG. 5 and FIG. 6 show an example of the power state changing device ZA101.
- Figure 5 shows an example of changing the supply voltage using a DC-DC converter for given power supply voltage conditions and threshold voltage conditions.
- Figure 6 shows an example of changing the supplied clock according to the power factor condition and the division ratio condition as clock frequency information.
- FIG. 7 is a block diagram showing the configuration of the power control apparatus 200 according to the second embodiment.
- the power state change device ZA101 is connected to the power control register ZA102 and changes the power state of the microprocessor 1000 to reduce power consumption based on the contents of the power control information ZA103 supplied from the power control register ZA102. I do.
- the power control information ZA103 held by the power control register ZA102 is the power control register Reading Z rewriting can be performed via the processor bus access control device ZA104 connected to ZA102.
- the microprocessor 1000 can change the microprocessor 1000 to an appropriate power state and reduce power consumption by rewriting the contents of the power control register ZA102 with the program itself to be executed.
- the microprocessor 1000 can read the contents of the power context storage device ZA105 via the processor bus access control device ZA104 and perform Z rewriting.
- a program executed by the microprocessor 1000 can change the contents of the power control register ZA102 with the contents of the storage area prepared for each program of the power context storage device ZA105. It is possible to realize power control under conditions.
- the power context storage device ZA105 can be configured by a flip-flop group having an SRAM structure. It is also possible to share information other than power information in a memory space accessible by the microprocessor 1000.
- the power context reference device ZB101 includes a power context save / return control device ZA106.
- the power context save / restore control device ZA106 is connected to the power control register ZA102 and the power context storage device ZA105, and can read and rewrite the stored contents of each.
- the power context save / restore control device ZA106 can access the power control register ZA102 and the power context storage device ZA105 without occupying the port session, so the power control register ZA102 It is also possible to replace the contents of the power context storage device ZA105.
- FIG. 8 is a block diagram showing the configuration of the power control apparatus 300 according to the third embodiment.
- This power control device 300 may be provided inside the microphone port processor 1000 as well as the power control devices 100 and 200 shown in FIGS. 1 and 7, or may be provided outside the microprocessor 1000. Good.
- the power context reference device ZB101 includes a power advance control device ZC101.
- the power advance control device ZC101 obtains the power control information Z A103 from the power context storage device ZA105, performs a calculation for changing the power state based on this, and supplies the power control information ZA1 03 to the power state change device ZA101. To do.
- the power state changing device ZA101 changes the power state of the microphone processor 1000 based on the supplied power control information ZA103.
- FIG. 9 shows an example of the internal configuration of the power advance control device ZC 101.
- the power leading control device ZC101 receives the identification number ZC201 of the program to be executed next by the microprocessor 1 000 by the program scheduler by hardware or the program scheduler by the operating system, and stores it in the identification number holding register ZC202. Store.
- the contents of the identification number holding register ZC202 are supplied to the power context storage device ZA105 as the identification number ZC203, and the power context storage device ZA105 obtains the power control information ZA103 corresponding to the identification number ZC203 and stores it as power. Record in control information holding register ZC204.
- the comparator ZC205 compares the power state ZC206 of the microprocessor 1000 with the contents of the power control information Z A103, and notifies the power change timing controller ZC207 of the result.
- the power state ZC206 and the power control information ZA103 represent the power supply voltage.
- the selector ZC208 selects the program switching request ZC209 side from the program scheduler. That is, after waiting for the timing at which the program is switched, the voltage state change request ZC210 is notified to the power state changing device ZA101. This prevents the microprocessor 1000 from malfunctioning during execution of a program that requires a high operating voltage due to a state change to a voltage below the operable voltage.
- power change timing controller ZC207 starts preparation for changing power before program switching.
- the down counter ZC211 is started and the result is a predetermined value (here In the case of zero)
- the voltage state change request ZC210 is notified to the power state changing device ZA101 via the selector ZC208.
- the power state required by the program can be changed before switching to the program.
- FIG. 10 shows the operation timing of this embodiment.
- program A and program B specify voltage VI as power control information ZA103
- program C and program D specify voltage V2.
- power state ZC206 is at voltage VI, and power control information ZA103 of program C indicates voltage V2.
- the comparator ZC205 determines that the power state ZC206 is larger as a comparison result between the power state ZC206 and the power control information ZA103, and causes the selector ZC208 to select the program switching request ZC209 side. Since the program switching request ZC209 is asserted at the time of program switching, the power switching request ZC210 is not notified until the program switching. As a result, the power state change is waited until program B is interrupted.
- the comparison result of the comparator ZC205 determines that the power control information Z A103 side is large, so the power change timing controller ZC207 counts the counter and then precedes the program switching. Initiate power state change.
- FIG. 11 shows an example of the execution procedure of the present embodiment.
- step ZC301 power control information ZA103 corresponding to the identification number of the program assigned next is acquired.
- step ZC302 the power control information ZA103 is compared with the power state ZC206 of the microprocessor 1000.
- the power state ZC In this example assuming voltage as the power state, the power state ZC
- the procedure ZC303 is selected. If the 206 side is high, the procedure ZC304 is selected.
- Procedure ZC303 waits for a power change until program switching by normal scheduling.
- step ZC304 calculation of timing for changing the power condition is started. In this example, timing adjustment by timer ZC211 is shown.
- step ZC305 a power change is waited until the timing condition is completed.
- the count value of timer ZC211 is shown as a condition.
- Procedure after completion of waiting ZC306 requests the power state changing device ZA101 to change the power state based on the power control information ZA103.
- FIG. 12 is a block diagram showing the configuration of the power control apparatus 400 according to the fourth embodiment.
- the power control device 400 may be provided inside the microprocessor 1000 as in the power control devices 100 and 200 shown in FIGS. 1 and 7, or may be provided outside the microprocessor 1000. .
- the power context reference device ZB101 includes a speculative power state change device ZD101.
- the speculative power state change device ZD101 obtains the power control information ZA103 from the power context storage device ZA105, performs calculation for changing the power state based on this, and supplies the power control information ZA103 to the power state change device ZA101. To do.
- the power state changing device ZA101 changes the power of the microphone port processor 1000 based on the supplied power control information ZA103.
- FIG. 13 shows an example of the internal configuration of the speculative power state changing device ZD101.
- the speculative power state change device ZD101 receives the identification number ZD201 of the program to be executed next in the microprocessor 1000 by the program scheduler by hardware or the program scheduler by the operating system, and stores the identification number holding register ZD202. To store.
- the contents of the identification number holding register ZD202 are supplied as the identification number ZD203 to the power context storage device ZA105, and the power context storage device ZA105 obtains the power control information ZA103 corresponding to the identification number Z D203 and stores it as the power. Record in the control information holding register ZD204.
- the comparator ZD205 compares the success rate Z D206 of the past power change in the content of the power control information ZA103 with the specified limit value ZD207 of the success rate.
- the past power change The success rate ZD206 consists of the number of times the power change has failed continuously, and the specified limit value ZD207 is
- the output of 05 is asserted.
- comparator ZD205 is logically ANDed with the power change permission bit in power control information ZD204 (ZD208), and the result is used as power change request ZD209, and the power state change device Notify ZA101.
- FIG. 14 shows an example of the implementation procedure of the present embodiment.
- step ZD301 power control information ZA103 corresponding to the identification number of the program assigned next is acquired.
- step ZD302 it is determined from the contents of the state change permission bit of the power control information ZA103 whether the program is permitted for power control, and the program is not permitted for power control! Completes the procedure without making a power state change request.
- step ZD303 the power state change control should be performed based on the success rate of the past power state change in the content of the power control information ZA103. If it is determined that it should be suppressed, the procedure is completed without requesting to change the power state. On the contrary, if it is determined that the change should be performed, in step ZD304, based on the contents of the power control information ZA103, the power state change device ZA101 is notified of the power state change request.
- FIG. 15 shows an example of calculating a past success rate in the present embodiment. Here, an example is shown in which the calculation is based on the number of failures as the success rate.
- step ZD401 based on the margin, the microprocessor 1000 calculates and determines the force that can cause a malfunction in the combination of the current power state and the load state. Shown in form.)
- step ZD402 When it is determined in step ZD401 that the power state has no margin and is in a state (power hazard state), in step ZD402, a value corresponding to the state change success rate in the power control information is increased.
- a simple example is 1 each time a power hazard condition is detected. Although it is increased, a method of adding a weighted value according to the margin can be easily configured.
- step ZD401 If it is determined in step ZD401 that there is a margin in the power state, and if a program switching request is received in step ZD404, the success rate is calculated in further subsequent step ZD405.
- one of the mounting methods is a method of simply subtracting a value.
- the success rate can be calculated based on whether the total value exceeds a certain threshold regardless of the degree of success or failure.
- step ZD405 when power allocation is successful, a method of clearing the success rate value to an initial value (eg, 0) can be used. In this case, it is possible to configure a judgment method that makes the value exceed the threshold only when N failures occur consecutively.
- an initial value eg, 0
- FIG. 16 is a block diagram illustrating a configuration of a device that calculates the success rate.
- the selector ZD501 supplies a value (+1) that is a failure number addition value in the case of a power hazard state, and a value that is a success number subtraction value if it is not in a power hazard state ( -
- Adder ZD502 adds the current state change success rate value supplied from power control information ZD204 and the addition / subtraction value supplied from selector ZD501.
- the failure rate information register ZD503 writes the value supplied from the adder ZD502 when the program switch information is asserted. Further, the state change success rate field of the power context storage device ZA105 is updated with this value.
- FIG. 17 illustrates a configuration of an apparatus that updates information in the power context storage device ZA105 with a value corresponding to the operating state of a program when switching programs, as in the present embodiment.
- the power allocation success and failure determination mechanism can be used to more safely reduce the power.
- the power state margin can be calculated and the power control information for the corresponding program in the power context storage device ZA105 can be updated.
- the power control information of the power context storage device ZA105 can be updated with a lower voltage value.
- the margin is small, it can be updated with a higher voltage value. This can reduce performance degradation due to power allocation failure and dynamically reduce power consumption.
- FIG. 18 shows another example of the internal configuration of the speculative power state changing device ZD101.
- the speculative power state change device ZD101 receives the identification number ZD201 of the program to be executed next by the microprocessor 1000 by the hardware program scheduler or the operating system program scheduler, and stores the identification number holding register ZD202. To store.
- the contents of the identification number holding register ZD202 are supplied to the power context storage device ZA105 as the identification number ZD203, and the power context storage device ZA105 obtains the power control information ZA103 corresponding to the identification number Z D203. Record in the control information holding register ZD204.
- the difference calculator ZE101 calculates the difference between the power state ZE102 of the microprocessor 1000 and the power information of the power control information ZA103.
- the power supply voltage is exemplified as the power state.
- the difference calculator ZE101 calculates and outputs the voltage difference between the two.
- the power transition time table ZE103 calculates and outputs the time required to change the input power state value.
- the transition time required to change the voltage difference O.lmV is stored in the form of a table and output.
- the table may be composed of rewritable registers and memories, or it may be composed of combinational logic.
- the comparator ZE104 compares the output of the power-transition time table ZE103 with the normal minimum time ZE105 in the content of the power control information ZA 103. If the normal minimum time ZE105 is smaller, the power change Request ZE106 is notified to the power status change device ZA101. [0108] Normal time minimum time ZE105 stores the minimum time unit executed for each switching unit in the normal time excluding emergency such as interruption of the corresponding program.
- FIG. 19 shows a calculation procedure for the normal minimum time ZE105.
- ZE201 start program allocation time measurement using a timer after program switching. This can be done by newly initializing and counting the timer, or by using a shared timer that is always running and recording the timer value at the start of the program.
- step ZE203 After the program switch is detected in step ZE202, it is determined in step ZE203 whether the current program switch is an emergency switch due to normal switching force or interruption.
- step ZE204 After determining that the current program switch is a normal switch in step ZE203, the program allocation time is calculated in step ZE204.
- the current timer value itself is used.
- the current timer value is also recorded and the timer at the start of the recorded program is used. The allocation time is calculated by subtracting the value.
- step ZE205 the value of the normal minimum time ZE105 stored in the power control information holding register ZD204 is compared with the current program allocation time calculated in the above ZE204, and the smaller value is determined in step ZE206. Usually, it is stored in the corresponding field of the power context storage device ZA105 as the minimum time.
- FIG. 20 is a block diagram showing a configuration of a power control apparatus 600 according to the sixth embodiment.
- This power control device 600 is similar to the power control devices 100 and 200 shown in FIG. 1 and FIG. It may be provided inside the microprocessor 1000 or may be provided outside the microprocessor 1000.
- the power context reference device ZB101 includes a power scheduler ZF101.
- the power scheduler ZF101 obtains the power control information ZA103 corresponding to the program identification number from the power context storage device ZA105, performs calculation for changing the power state based on this, and uses the power control information ZA103 as the power state change device.
- ZA101 is supplied, and program allocation information ZF102 is supplied to program allocation device ZF103.
- the power state changing device ZA101 changes the power of the microphone mouth processor 1000 based on the supplied power control information ZA103.
- the program assignment device ZF103 assigns the program identified by the supplied program assignment information ZF102 to the microprocessor 1000.
- FIG. 21 shows an example of the internal configuration of the power scheduler ZF101.
- the power scheduler ZF101 holds the program information to be allocated to the microprocessor 1000 and uses the state control machine ZF201 that performs allocation control to assign an identification number for each program that can be allocated to the power context storage device ZA105 via the ID holding register ZF201.
- the power control information ZA103 is received and stored in the power control information holding register ZD 204.
- the subtractor ZF 203 calculates a difference between the power control information ZA103 output from the power control information holding register ZD204 and the power state ZF204 of the microprocessor 1000.
- a supply voltage power supply voltage
- a voltage difference is output.
- the subtractor ZF206 calculates the difference between the power state ZF204 and the minimum difference candidate holding register ZF205.
- the comparator ZF207 compares the output of the subtractor ZF203 with the output of the subtractor ZF206, and asserts the write request ZF208 if the output value of the subtractor ZF203 is smaller.
- the write request ZF208 is notified to the minimum difference candidate holding register ZF205 after the logical product (AND) with the timing adjustment signal from the state control machine ZF201, and is notified of the minimum difference.
- the candidate holding register ZF205 stores the current power control information ZA103 as a new minimum difference candidate.
- the minimum difference candidate holding register ZF205 stores the current power information, the program identification number having the smallest difference value, and the power state control information. ZA103 can be stored.
- power change request ZF209 and program switching request ZF210 are asserted and notified to power state changer ZA101 and program allocation unit ZF103 as a power and program change request.
- the power and program allocation status are changed respectively.
- FIG. 22 shows an example of the execution procedure of the present embodiment.
- step ZF301 power control information ZA103 corresponding to the identification number of the program assigned next is acquired.
- step ZF302 the power value of the power control information ZA103 is compared with the current power state value ZF204 of the microprocessor 1000, and if closer, in step ZF303, the corresponding program identification
- the number and power control information ZA103 are stored in the minimum difference candidate holding register ZF205 as a candidate to be assigned to the next program.
- FIG. 23 shows the operation timing of this embodiment.
- power scheduler ZF101 searches programs B, C, and D to which programs can be allocated for a program having the smallest difference from the current power state (here, voltage state). It is determined that the power difference of program B is the smallest, and program B is notified to program allocation device ZF103 as the next program switching target. In addition, the power status change device ZA101 is notified of the power status change.
- program C that minimizes the difference in power state is selected as a candidate to be assigned next.
- the power advance control device ZC101 shown in the third embodiment may be used to change the power state before switching to the program C to suppress performance degradation. Is possible.
- FIG. 24 shows another example of the internal configuration of the power scheduler ZF101.
- the power scheduler ZF101 holds the program information to be allocated to the microprocessor 1000 and uses the state control machine ZF201 to perform allocation control, and assigns an identification number for each program that can be allocated to the power context storage device ZA105 via the ID holding register ZF201.
- the power control information ZA103 is received and stored in the power control information holding register ZD 204.
- the subtractor ZG101 calculates the difference between the previous minimum value register ZG103 that holds the previously determined minimum difference and the power control information ZA103.
- the subtractor ZG102 calculates the difference between the previous minimum value register ZG103 that holds the previously determined minimum difference and the minimum difference candidate holding register ZF205 that holds the current minimum difference.
- the comparator ZG103 compares the results of the subtractor ZG101 and the subtractor ZG102, and the subtractor ZG103
- the state control machine ZF201 stores the contents of the minimum difference candidate holding register ZF205 in the previous minimum value register. Control is performed to write to the star ZG103, and control is performed to write the contents of the previous minimum value register ZG103 to the rearranged program table ZG104.
- the program with the smallest power difference can be extracted, and then the program with the smallest power difference is sequentially extracted, such as the next program with the smallest power difference.
- the program identification information is recorded in the rearranged program table ZG104 in the order of programs with the smallest power difference.
- the comparison method it is possible to rearrange the power differences in order. It is also possible to perform the rearrangement process by software processing that does not require any software.
- the state control machine ZF201 sends a power control state change request ZA103 and a program assignment request ZF102 to the power state change device ZA101 and the program assignment device ZF103 according to the order of the rearranged program table ZG104. Notify, change power state and switch programs.
- FIG. 25 is a block diagram showing a configuration of a power control apparatus 800 according to the eighth embodiment.
- the power control device 800 may be provided inside the microprocessor 1000 as in the power control devices 100 and 200 shown in FIGS. 1 and 7, or may be provided outside the microprocessor 1000. .
- the power context reference device ZB101 includes a power scheduler ZF101.
- the power scheduler ZF101 obtains the power control information ZA103 corresponding to the program identification number from the power context storage device ZA105, performs calculation for changing the power state based on this, and uses the power control information ZA103 as the power state change device.
- ZA101 is supplied, and program allocation information ZF102 is supplied to program allocation device ZF103.
- the power status change device ZA101 changes the power of the microphone port processor 1000 based on the supplied power control information ZA103.
- the program allocation device ZF103 allocates the program identified by the supplied program allocation information ZF102 to the microprocessor 1000.
- the load power determination device ZH101 receives the power state ZH102 and the load state ZH103 of the microprocessor 1000 as input, and compares the current power state with the current power state.
- the power control hazard notification ZH104 is output to the power scheduler ZF101. This also has the meaning of a program switching request to the power scheduler ZF101.
- the power scheduler ZF101 searches for a program that can be allocated in the current power state, and assigns the program allocation to the program allocation.
- Device ZF103 Further, if possible, the power state change device ZA101 is notified of a power state change notification for reducing the power.
- FIG. 26 shows an example of the internal configuration of the load power determination device ZH101.
- the load power conversion table ZH201 outputs an operable power state value according to the input load state ZH103.
- the load state ZH101 indicates the current operation state of the microprocessor 1000, and includes the number of memory accesses, the number of instruction executions, the operation frequency, and the like. For example, assuming the number of memory accesses, the number of instruction executions, and the operating frequency as the load state ZH101, the power supply voltage value at which the microprocessor 1000 can operate without malfunctioning is output under each execution load state.
- Table ZH201 can be composed of rewritable registers and memories, or it can be composed of combinational logic.
- the comparator ZH202 compares the output of the load power conversion table ZH201 with the current power state ZH102 of the microprocessor 1000. If the current power state is smaller, the comparator ZH202 sets the power control hazard ZH104 to the power scheduler ZF. Notify 101.
- the power scheduler ZF101 can execute another program that does not generate a wait state for the power state to transition to a state that does not cause a malfunction, thereby preventing system performance deterioration due to waiting. it can.
- FIG. 27 shows an example of the execution procedure of the present embodiment.
- step ZH301 compare the power state of the microprocessor 1000 with the load state as needed to monitor that the power state causing the malfunction cannot be approached. If the power status becomes insufficient, proceed to step ZH302 and there is a program that can operate in the current power status. Search if it exists.
- step ZH303 wait until the power state becomes appropriate for the operating load.
- step ZH304 If there is a program that can operate in the current power state, the assignment is changed to the operable program in step ZH304, and the execution of the microprocessor 1000 is continued.
- the contents of the power context storage device ZA105 must be set to a safe value in order to operate more safely at the next program allocation. It is also possible to update with.
- This dynamic power condition change can be easily combined with the power allocation success and failure determination mechanism shown in the fourth embodiment, for example.
- FIG. 28 is a block diagram showing a configuration of a power control apparatus 900 according to the ninth embodiment.
- the power control device 900 is a device for realizing efficient reduction of the total power consumption when executing a plurality of programs without depending on the number of installed processors in a system having a plurality of physical processors. is there.
- the power scheduler ZF101 acquires the power supply group information ZI102 from the power supply group storage device ZI101, based on this, determines the processor to which each program is to be executed and determines the program information to be assigned to the program assignment device ZF103. Notify the power status change device ZA101 of the power status change.
- FIG. 29 shows an example of the storage configuration method of the power supply group information ZI102.
- FIG. 29 (a) shows a method of preparing a storage area for each physical processor identification number and indicating to which power supply group the corresponding processor belongs.
- Processors with processor numbers 0 and 3 physically belong to power group 0, processors with processor number 1 belong to power group 1, and processors with processor number 2 belong to power group 2.
- This method requires storage areas according to the number of physical processors.
- four processors are physically designed and implemented with three types of power supply groups, indicating that there are three types of power supply groups that can be controlled independently. For example, in this example, the power supply voltages of processor number 0 and processor number 3 cannot be changed individually. Therefore, assigning a program under power conditions close to processor number 0 and processor number 3 is a good way to reduce power consumption.
- FIG. 29 (b) shows a method of preparing a storage area for each power supply group and indicating whether a processor with an incorrect processor number belongs to the corresponding power supply group.
- the stored value is 1, it indicates that the processor belongs to the power group. Therefore, for example, the processor of processor number 0 and processor number 3 belongs to power supply group number 0.
- FIG. 30 shows an example of physical arrangement of a plurality of physical processors and power supply group storage devices.
- FIG. 30 (a) shows a configuration example corresponding to FIG. 29 (a), and each processor has a power supply group storage device.
- FIG. 30 (b) shows a configuration example corresponding to FIG. 29 (b), which has a power supply group storage device common to the processors.
- the configuration example shown in Fig. 30 (a) and (b) may be a group of processors between different LSIs that describe an example in which multiple processors are mounted on the same LSI.
- the other logic units may not be configuration examples.
- each program is allocated for the purpose of efficiently reducing the total power consumption when executing a plurality of programs.
- the first method is a method of alternately allocating programs based on the power state as follows when the physical processor numbers are arranged as usual. This As shown in Figure 31 (a), the highest power is assigned to # 0, the lowest power is assigned to # 1, the second highest power is assigned to # 2, and the power is Is the second lowest, assigns the thing to # 3, and so on.
- the second method is a method in which physical processor numbers are designed and arranged discontinuously.
- physical processor numbers are positioned discontinuously in the row or column direction (incremental relationship that is not a fixed value).
- Program allocation is performed in order of physical processor numbers in the order of power consumption. Because the processor numbers are discontinuous, the program is naturally distributed.
- the present invention generally relates to information processing devices such as a microprocessor (including a microcomputer, a microcontroller, and a digital signal processor), a sequencer, a static configuration logic, a dynamically reconfigurable logic, etc. Applicable.
- a microprocessor including a microcomputer, a microcontroller, and a digital signal processor
- sequencer including a sequencer, a static configuration logic, a dynamically reconfigurable logic, etc. Applicable.
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Abstract
Description
Claims
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JP2007514509A JP4838240B2 (ja) | 2005-04-27 | 2006-03-28 | 情報処理装置における電力制御装置 |
US11/919,421 US8156348B2 (en) | 2005-04-27 | 2006-03-28 | Power controller in information processor |
US13/404,975 US20120166824A1 (en) | 2005-04-27 | 2012-02-24 | Power controller in information processor |
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US13/404,975 Division US20120166824A1 (en) | 2005-04-27 | 2012-02-24 | Power controller in information processor |
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US (2) | US8156348B2 (ja) |
JP (2) | JP4838240B2 (ja) |
CN (2) | CN100527089C (ja) |
TW (1) | TW200705166A (ja) |
WO (1) | WO2006117950A1 (ja) |
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Also Published As
Publication number | Publication date |
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JPWO2006117950A1 (ja) | 2008-12-18 |
CN101539802A (zh) | 2009-09-23 |
US20090313490A1 (en) | 2009-12-17 |
CN100527089C (zh) | 2009-08-12 |
US8156348B2 (en) | 2012-04-10 |
JP5091986B2 (ja) | 2012-12-05 |
TW200705166A (en) | 2007-02-01 |
JP4838240B2 (ja) | 2011-12-14 |
JP2010250858A (ja) | 2010-11-04 |
US20120166824A1 (en) | 2012-06-28 |
CN101167055A (zh) | 2008-04-23 |
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