WO2006114941A1 - クロック発生回路およびオーディオシステム - Google Patents
クロック発生回路およびオーディオシステム Download PDFInfo
- Publication number
- WO2006114941A1 WO2006114941A1 PCT/JP2006/304467 JP2006304467W WO2006114941A1 WO 2006114941 A1 WO2006114941 A1 WO 2006114941A1 JP 2006304467 W JP2006304467 W JP 2006304467W WO 2006114941 A1 WO2006114941 A1 WO 2006114941A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- frequency
- signal
- khz
- clock
- division ratio
- Prior art date
Links
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 3
- 238000005070 sampling Methods 0.000 description 11
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 8
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 8
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 8
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 8
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 7
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000005236 sound signal Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Definitions
- the present invention relates to a clock generation circuit and an audio system that generate clock signals having a plurality of frequencies.
- Patent Document 1 JP 2002-260324 A (Page 3-6, Fig. 1-6)
- the present invention has been created in view of the above points, and an object of the present invention is to provide a clock generation circuit and an audio system capable of simplifying the configuration. Means for solving the problem
- the clock generation circuit of the present invention has a 32.768 kHz shared frequency.
- An oscillator that generates a reference frequency signal using a crystal resonator having an oscillation frequency, and a phase-locked loop circuit that generates a signal that is synchronized with the reference frequency signal generated by the oscillator and has a frequency M times the reference frequency signal
- a first frequency divider that generates a first clock signal having a frequency that is an integer multiple of 32 kHz by dividing the signal generated by the phase-locked loop circuit by a frequency division ratio N1
- a phase-locked loop Generated by a phase-locked loop circuit and a second divider that generates a second clock signal having a frequency that is an integer multiple of 38 kHz by dividing the signal generated by the loop circuit by a division ratio N2.
- a third frequency divider that generates a third clock signal having a frequency that is an integral multiple of 48 kHz by dividing the frequency-divided signal by a frequency division ratio N3.
- two types of clock signals required for processing audio data with a sampling frequency of 32 kHz and 48 kHz, which are commonly used in digital audio, and a 38 kHz clock signal required for stereo modulation processing are combined into one. It can be generated by a common clock generation circuit using a phase-locked loop (PLL) circuit, and the configuration can be simplified.
- PLL phase-locked loop
- the 32.768 kHz crystal unit is used for generating the reference frequency of watches, and is inexpensive.
- the frequency division ratio N1 of the first frequency divider is (32.768 XM) Z. It is desirable to set it to a value determined by (32 X N4) or a value obtained by dividing this value by the power of 2. Specifically, by setting such a division ratio, it becomes possible to generate a clock signal having a frequency of 32 kHz or a power of two.
- the frequency division ratio N2 of the second frequency divider is (32.768 XM) Z. It should be set to a value determined by (38 X N4) or a value obtained by dividing this value by the number of powers of 2. Specifically, by setting such a division ratio, it becomes possible to generate a clock signal having a frequency that is 38 kHz or a power of two.
- the frequency division ratio N3 of the third frequency divider is (32.768 XM) Z. It is desirable to set it to a value determined by (48 X N4) or a value obtained by dividing this value by the power of 2. Ingredients By physically setting such a division ratio, it becomes possible to generate a clock signal having a frequency of 48 kHz or a power of two.
- Nl, N2, N3, N4, and M described above are preferably integer values. Thereby, the configuration of the frequency divider can be simplified.
- the audio system of the present invention is an audio process for performing an audio data reproduction operation using at least one of the clock generation circuit described above and the first and third clock signals generated by the clock generation circuit.
- audio data reproduced by the audio processing unit are input, and the second clock signal generated by the clock generation circuit is used to perform FM stereo modulation processing and FM modulation processing on the input audio data.
- an FM transmitter that transmits the signal.
- two types of clock signals, 32kHz and 48kHz, input to the audio processing unit and 38kHz clock signal input to the FM transmitter can be generated by a common clock generation circuit. It is possible to simplify the apparatus configuration.
- FIG. 1 is a diagram illustrating a configuration of an audio system according to an embodiment.
- FIG. 2 is a diagram showing a detailed configuration of a clock generation circuit.
- VCO Voltage controlled oscillator
- FIG. 1 is a diagram illustrating a configuration of an audio system according to an embodiment.
- the audio system of this embodiment includes an audio processing unit 100, an FM transmitter 200, and a clock generation circuit 300.
- Most of the configurations of the video processing unit 100, the FM transmitter 200, and the clock generation circuit 300 have a CMOS process on a semiconductor substrate! / ⁇ is formed as a one-chip component using a MOS process (however, these Crystal oscillator 10 that cannot be formed by this process (explained later) and drive mechanism etc.). By using these processes, it is possible to reduce the size and power consumption of one-chip components and the entire audio system formed on the semiconductor substrate.
- the audio processing unit 100 performs digital audio reproduction processing corresponding to each of a plurality of sampling frequencies. For example, the audio processing unit 100 selectively performs an audio data playback operation with a sampling frequency of 32 kHz input to a DV D drive force (not shown) and an audio data playback operation with a sampling frequency of 32 kHz or 48 kHz recorded in MP3 format. .
- the clock signals of 32 kHz and 48 kHz required for these playback operations are manpowered by 300 clock generation circuits.
- FM transmitter 200 performs FM stereo modulation processing and FM modulation processing on the audio data generated by the reproduction operation by audio processing unit 100, and transmits the FM-modulated signal from antenna 220. This signal is received by an external FM receiver, and an audio sound corresponding to the audio data output from the audio processing unit 100 is output from the speaker of this FM receiver.
- the FM transmitter 200 includes a stereo modulation unit 210 that performs FM stereo modulation processing.
- Stereo modulation section 210 generates stereo composite data (composite data) by performing stereo modulation processing that synchronizes the audio data for LZR input from audio processing section 100 with the 38 kHz subcarrier.
- the required 38 kHz clock signal is input to the clock generator circuit 300.
- the clock generation circuit 300 uses a 32.768 kHz crystal resonator, a first clock signal CLK1 having a frequency of 32 kHz, and a second clock signal C having a frequency of 38 kHz.
- LK2 and a clock signal CLK3 having a frequency of 48 kHz are generated.
- FIG. 2 is a diagram showing a detailed configuration of the clock generation circuit 300.
- the clock generation circuit 300 includes a crystal resonator 10, an oscillator (OSC) 12, a frequency divider 14, 26, 30, 32, 34, a phase comparator (PD) 20, a low-pass filter ( LPF) 22 and voltage controlled oscillator (VCO) 24.
- OSC oscillator
- PD phase comparator
- LPF low-pass filter
- VCO voltage controlled oscillator
- the crystal resonator 10 has a resonance frequency of 32.768 kHz.
- the crystal unit 10 is widely used for watches and can be obtained at low cost.
- the oscillator 12 performs an oscillation operation of 32.768 kHz using the crystal resonator 10 as a part of the resonance circuit and outputs an oscillation signal.
- the phase comparator 20 compares the phase of the reference frequency signal fr with the phase of the output signal of the frequency divider 26 input to the other input terminal, and outputs a signal corresponding to the phase difference.
- the low pass filter 22 smoothes the output signal of the phase comparator 20 and generates a control voltage to be applied to the voltage controlled oscillator 24.
- phase comparator 20 the low-pass filter 22, the voltage-controlled oscillator 24, and the frequency divider 26 described above constitute a phase-locked loop (PLL) circuit, which is synchronized with a reference frequency signal of 8.192kHz, and A signal having a frequency (58.368 MHz) 7125 times the reference frequency signal is generated and output by this PLL circuit.
- PLL phase-locked loop
- Output signal of PLL circuit The frequency of is 58.368MHz, so dividing it by 1536 generates the 38kHz clock signal CLK2.
- the clock generation circuit 300 of the present embodiment two types of clock signals CLK1 and CLK3 necessary for processing audio data having sampling frequencies of 32 kHz and 48 kHz, which are widely used in digital audio,
- the 38 kHz clock signal CLK2 necessary for the stereo modulation processing can be generated using one PLL circuit, and the configuration of the clock generation circuit 300 and the audio system using the clock generation circuit 300 can be simplified.
- the 32.768 kHz crystal unit 10 is used for generating a reference frequency for a watch and is available at low cost, the use of this crystal unit 10 can reduce the cost.
- the frequency division ratio N1 of the frequency divider 30 is set to a value determined by (32.768 ⁇ M) Z (32 ⁇ N4).
- the power to generate the clock signal CLK1 ' having a frequency obtained by multiplying 32kHz by the power of 2
- the clock signal CLK1 of 32kHz can be easily generated by dividing this clock signal CLK1'.
- the division ratio N1 to the value determined by (32.768 XM) Z (32 X N4) divided by 4, the clock signal that matches the 128 kHz sampling frequency used in MP3 etc. It can also be generated directly.
- the frequency division ratio N2 of the frequency divider 32 is set to a value determined by (32.768 XM) / (38 X N4).
- a 32.768 kHz crystal resonator 10 is used.
- a 38 kHz clock signal CLK2 can be generated.
- the division ratio N2 can be obtained by dividing the value determined by (32.768 XM) / (38 X N4) by the power of 2 (2, 4, 8, ..., 2 n). Good.
- the power to generate a clock signal CLK2 ' having a frequency obtained by multiplying 38kHz by the power of 2
- the clock signal CLK2' By dividing this clock signal CLK2', it is possible to easily generate the clock signal CLK2 of 38kHz. it can.
- the frequency division ratio N3 of the frequency divider 34 is set to a value determined by (32.768 ⁇ M) / (48 ⁇ N4).
- this division ratio N3 can be obtained by dividing the value determined by (32.768 XM) / (48 X N4) by the power of 2 (2, 4, 8, ..., 2 ").
- the power to generate a clock signal CLK3 ′ having a frequency obtained by multiplying 48 kHz by a power of 2 By dividing this clock signal CLK3 ′, a 48 kHz clock signal CLK3 can be easily obtained. Also, by setting the division ratio N3 to the value determined by (32.768 XM) / (48 X N4) divided by 2, the 96 kHz sampling frequency used by MP3 etc. It is also possible to directly generate a clock signal that matches
- each of the division ratios N3 of 34 an integer value, the configuration of each frequency divider can be simplified, thereby further simplifying the configuration of the clock generation circuit 300 and the audio system using the same. Become.
- the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.
- the oscillation signal of the oscillator 12 is input to the phase comparator 20 via the frequency divider 14.
- the frequency divider 14 is omitted and the oscillation signal of the oscillator 12 is used as a reference frequency signal as a phase frequency signal. It may be input directly to the comparator 20.
- a single phase-locked loop (PLL) circuit It can be generated by the common clock generation circuit used, and the configuration can be simplified.
- the 32.768 kHz crystal unit is used for generating the reference frequency of a watch and is inexpensive, so using this crystal unit makes it possible to reduce costs.
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007514487A JPWO2006114941A1 (ja) | 2005-04-25 | 2006-03-08 | クロック発生回路およびオーディオシステム |
EP06715387A EP1876712A1 (en) | 2005-04-25 | 2006-03-08 | Clock generating circuit and audio system |
US11/908,602 US20090225990A1 (en) | 2005-04-25 | 2006-04-25 | Clock generating circuit and audio system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005-125875 | 2005-04-25 | ||
JP2005125875 | 2005-04-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006114941A1 true WO2006114941A1 (ja) | 2006-11-02 |
Family
ID=37214572
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/304467 WO2006114941A1 (ja) | 2005-04-25 | 2006-03-08 | クロック発生回路およびオーディオシステム |
Country Status (6)
Country | Link |
---|---|
US (1) | US20090225990A1 (ja) |
EP (1) | EP1876712A1 (ja) |
JP (1) | JPWO2006114941A1 (ja) |
CN (1) | CN101189798A (ja) |
TW (1) | TW200642288A (ja) |
WO (1) | WO2006114941A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011155565A (ja) * | 2010-01-28 | 2011-08-11 | Nippon Telegr & Teleph Corp <Ntt> | クロック・データリカバリ回路 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4300372B1 (ja) * | 2008-02-27 | 2009-07-22 | オンキヨー株式会社 | オーディオ装置、スイッチング電源及びスイッチング制御方法 |
US8525498B2 (en) * | 2008-07-31 | 2013-09-03 | Monolithic Power Systems, Inc. | Average input current limit method and apparatus thereof |
TWI599889B (zh) * | 2017-03-14 | 2017-09-21 | 芯籟半導體股份有限公司 | 自動產生時脈的通用序列匯流排控制器及其使用方法 |
CN115250397A (zh) * | 2021-04-28 | 2022-10-28 | 华为技术有限公司 | Tws耳机和tws耳机的播放方法及装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002100997A (ja) * | 2000-09-25 | 2002-04-05 | Toshiba Corp | Fmトランスミッタ及び当該fmトランスミッタを備えたコンピュータシステム |
JP2004056717A (ja) * | 2002-07-24 | 2004-02-19 | Renesas Technology Corp | 半導体装置、システムボードおよび多相クロック発生回路 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6292062B1 (en) * | 2000-02-10 | 2001-09-18 | Silicon Wave, Inc. | Method and apparatus for implementing a high-precision interval timer utilizing multiple oscillators including a non-optimal oscillator |
-
2006
- 2006-03-08 JP JP2007514487A patent/JPWO2006114941A1/ja active Pending
- 2006-03-08 WO PCT/JP2006/304467 patent/WO2006114941A1/ja active Application Filing
- 2006-03-08 CN CNA2006800138833A patent/CN101189798A/zh active Pending
- 2006-03-08 EP EP06715387A patent/EP1876712A1/en not_active Withdrawn
- 2006-03-15 TW TW095108763A patent/TW200642288A/zh unknown
- 2006-04-25 US US11/908,602 patent/US20090225990A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002100997A (ja) * | 2000-09-25 | 2002-04-05 | Toshiba Corp | Fmトランスミッタ及び当該fmトランスミッタを備えたコンピュータシステム |
JP2004056717A (ja) * | 2002-07-24 | 2004-02-19 | Renesas Technology Corp | 半導体装置、システムボードおよび多相クロック発生回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011155565A (ja) * | 2010-01-28 | 2011-08-11 | Nippon Telegr & Teleph Corp <Ntt> | クロック・データリカバリ回路 |
Also Published As
Publication number | Publication date |
---|---|
EP1876712A1 (en) | 2008-01-09 |
JPWO2006114941A1 (ja) | 2008-12-18 |
CN101189798A (zh) | 2008-05-28 |
TW200642288A (en) | 2006-12-01 |
US20090225990A1 (en) | 2009-09-10 |
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