WO2006094319A1 - Unite d'acquisition - Google Patents

Unite d'acquisition Download PDF

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Publication number
WO2006094319A1
WO2006094319A1 PCT/AT2006/000056 AT2006000056W WO2006094319A1 WO 2006094319 A1 WO2006094319 A1 WO 2006094319A1 AT 2006000056 W AT2006000056 W AT 2006000056W WO 2006094319 A1 WO2006094319 A1 WO 2006094319A1
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WO
WIPO (PCT)
Prior art keywords
circuit arrangement
data stream
determining
digital data
register
Prior art date
Application number
PCT/AT2006/000056
Other languages
German (de)
English (en)
Inventor
Wilfried Gappmair
Wolfgang Kogler
Original Assignee
Technische Universität Graz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technische Universität Graz filed Critical Technische Universität Graz
Priority to DE112006000510T priority Critical patent/DE112006000510A5/de
Publication of WO2006094319A1 publication Critical patent/WO2006094319A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Definitions

  • the invention relates to an acquisition unit for a digital TDMA modem, comprising a circuit arrangement for determining an optimal sampling time of a digital data stream, which is generated by oversampling with a predetermined number of samples per symbol from a baseband signal, a circuit arrangement for determining the beginning of a transmission frame and a Circuit arrangement for determining the carrier frequency of a digital data stream.
  • TDMA time-division multiple access
  • the transmitting stations do not operate continuously but are periodically allocated time slots into which they can pack their data (frames, bursts).
  • each of these stations generally has different transmission and propagation conditions, which may change over time.
  • a useful reception of the individual data packets is only guaranteed if the demodulator knows the relevant transmission parameters or can reliably determine and track them (synchronization).
  • the modulation method and the form of the baseband pulse In many cases, such as in satellite-based data links, the latter is usually band-limited in the narrower sense and interference-free, d. H. that the first Nyquist criterion is met.
  • the carrier frequency, the carrier phase, the symbol rate and the optimum sampling time meant.
  • the nominal values of carrier frequency and symbol rate are known on the receiver side;
  • TDMA this is also the case for the beginning of a transmission frame (preamble, synchronization word), which essentially supports the synchronization process in this case.
  • acquisition a combination of parameters has to be found which is close to the global optimum.
  • the process must be very efficient, especially in TDMA systems, which is ensured by the pre-known synchronization word.
  • the subsequent processing stages can be initialized, for example the tracking for carrier phase and sampling time.
  • TDMA modems operate with a separate arrangement for determining the optimum sampling time. Downstream of this unit, the determination of frame start, carrier frequency and carrier phase takes place in a further unit. For the separate determination of the optimum sampling time, the transmitted message must be preceded by a preamble, followed by a synchronization word for determining the carrier frequency, the beginning of the frame and the carrier phase.
  • a disadvantage of such solutions is that especially with very short data packets, the necessary overhead for the synchronization of the receiver is very large compared to the length of the message. Especially for transmission links with limited system bandwidth, this leads to an inefficient use of the system bandwidth, especially for smaller packet lengths.
  • the object of the invention is to provide a TDMA modem of the type mentioned, which avoids the known disadvantages and allows a more efficient use of the system bandwidth, especially for smaller package lengths.
  • a combined circuit arrangement is formed with a common data input, which comprises the circuit arrangement for determining the beginning of a transmission frame and the circuit arrangement for determining the optimum sampling time.
  • the circuit arrangement according to the invention can reduce the guard time thereby increased between the data packets to the extent of the length of the preamble.
  • the combined circuit arrangement with a common data input comprises the circuit arrangement for determining the carrier frequency of a digital data stream.
  • the frequency estimation in the combined circuit arrangement can be made, whereby the structure is further simplified.
  • the circuit arrangement for determining the beginning of a transmission frame and the circuit arrangement for determining the carrier frequency of a digital data stream of the circuit arrangement are connected upstream for determining an optimum sampling time.
  • the circuit arrangement already works with the frequency-corrected sampling values to determine an optimum sampling instant.
  • the combined circuit arrangement is preceded by a matched filter.
  • the circuit arrangement for determining the beginning of a transmission frame comprises a first shift register, the register length of the product of the number of samples per symbol and the length of a Synchronization word in symbols of a predetermined modulation method corresponds.
  • the samples can be read in succession from the register at a distance from the oversampling and compared with the stored synchronization word until an optimal match is found.
  • a frequency correction unit is connected downstream.
  • the sampeis are frequency-corrected for further processing.
  • At least one unit for forming the absolute value of the added-up and frequency-corrected products from the conjugate-complex synchronization word and the incoming sampeis is connected downstream of the output of the frequency correction unit.
  • the circuit arrangement for determining an optimum sampling time comprises at least a second shift register, wherein the second shift register preferably has an odd number shift register cells, in particular with an odd number of samples per symbol, the number of shift register cells of the number of samples per Symbol, or that if there are even numbers of samples per symbol, the number of shift register cells equals the number of samples per symbol minus one.
  • the second shift register preferably has an odd number shift register cells, in particular with an odd number of samples per symbol, the number of shift register cells of the number of samples per Symbol, or that if there are even numbers of samples per symbol, the number of shift register cells equals the number of samples per symbol minus one.
  • the second shift register has a first cell block, a middle cell and a second cell block, wherein the first cell block and the second cell block comprise the same number of cells, and the middle cell to an input of one Decision logic is connected, or that the second shift register has a first cell block, two middle cells and a second cell block, wherein the first cell block and the second cell block comprise the same number of cells, and the two middle cells are connected to an input of an average unit whose Output connected to the input of the decision logic.
  • the entries of the first cell block and the entries of the second cell block are available for further processing, for example for comparison, whereby the middle cell or the mean value of the two middle cells can function as a decision criterion.
  • the first cell block and the second cell block are connected to inputs of at least one summing unit, and that in each case at least one output of the summing units is connected to a subtraction unit. Thereby, the total amount of the first cell block can be compared with the total amount of the second cell block.
  • At least one output of the subtraction unit is connected both by means of at least one delay element and directly to inputs of the decision logic. Thereby, the values of the subtraction unit can be compared for two consecutive processing steps.
  • a variant of the invention can be that at least one output of the decision logic with at least one input of a circuit arrangement for determining a phase position of the digital data stream in relation to reference data, preferably the synchronization word, and / or at least one input of a circuit arrangement for determining the beginning of a data frame , wherein preferably the circuit arrangement for determining the phase position of the digital data stream in relation to reference data and / or the circuit arrangement for Determining the start of a data frame are part of the combined data input common circuitry.
  • Correction of the digital data stream with at least one correction factor preferably a frequency correction factor and / or a tracking unit, are conductively connected.
  • the invention further relates to a method for synchronizing a digital TDMA
  • Baseband signal is generated, wherein from the digital data stream, a carrier frequency of the digital data stream, the beginning of a transmission frame, an optimal sampling time and a phase position of the digital data stream in relation to reference data are determined, and the digital data stream is corrected before output with at least one correction value.
  • the object of the invention is to provide a method for synchronizing a digital TDMA
  • this is achieved by determining the beginning of the transmission frame and the optimum sampling instant in a combined circuit arrangement with a common data input.
  • guard time between the successive data packets can be reduced to the extent of the preamble, or these can be saved by themselves
  • Carrier frequency of the digital data stream in the combined circuit arrangement is determined with a common data input. This further simplifies the process.
  • the carrier frequency of the digital data stream and the optimal Sampling time the incoming digital data stream is filtered in a matched filter. This can ensure that only the desired
  • Another possible embodiment may be that the carrier frequency of the digital data stream is detected in a manner known per se, a frequency correction factor is formed and the digital data stream is frequency-corrected. This stands for the
  • the amount sum is formed from the frequency-corrected samples of the digital data stream.
  • a variant of the invention may be that the sum of sums are successively loaded into a second shift register with odd-numbered register length, the
  • Register entries wherein the number of first register entries is equal to the number of second register entries and the middle register entry to an input of a
  • first register entries and the second register entries are each added up, and the first and second register entry totals formed in this way are subtracted from each other. This is the
  • a further possible embodiment may be that two successive results of the subtraction of the register entry sums are provided as inputs to the decision logic, and the decision logic at one output provides a synchronization pulse indicative of the optimum sampling instant if the two consecutive results of the subtraction have different signs , and the middle register entry is above a predefinable correlation threshold. As a result, a maximum is detected and communicated to a subsequent processing stage of the optimal sampling.
  • Synchronization pulse a carrier phase value and / or a frame start signal in a conventional manner in the combined circuit arrangement with common data input can be determined.
  • the digital data stream with the frequency correction factor and / or the carrier phase value and / or the frame start signal is corrected and / or to more
  • the invention further relates to a computer program product directly in the internal
  • Memory of a computer can be loaded and includes software code sections, with which the steps of the method according to any one of claims 14 to 24 are executed when the computer program product is running on a computer.
  • the method according to the invention can be flexibly integrated into an application.
  • the invention further relates to a data carrier with a computer program product
  • Claim 25 Thus, such a computer program product is transportable and storable.
  • the invention further relates to a digital TDMA modem with an acquisition unit according to one of claims 1 to 13.
  • the existing system bandwidth can be used much better, especially for smaller packet lengths, as can be dispensed with the preamble and the extended "guard time" ,
  • the invention further relates to a digital TDMA modem, wherein a method according to any one of claims 14 to 24, in particular by means of a computer program product according to
  • Claim 25 is implemented. As a result, such a modem can be flexibly used and retrofitted.
  • FIG. 1 is a block diagram of a conventional acquisition unit of a digital TDMA
  • FIG. 2 shows a block diagram of an acquisition unit according to the invention for a digital
  • FIG. 3 shows a further embodiment of an acquisition unit according to FIG. 2;
  • FIG. 4 is a block diagram of the circuitry for determining the beginning of a
  • Fig. 5 is a block diagram of the circuitry for determining the optimum
  • FIGS. 2 and 3 show an acquisition unit for a digital TDMA modem, comprising a circuit arrangement for determining an optimum sampling time 1 of a digital one
  • Symbol of the data stream is generated from a baseband signal, a circuit arrangement for determining the beginning of a transmission frame 2 and a circuit arrangement for determining the carrier frequency 3 of a digital data stream, wherein a combined
  • Circuit arrangement 4 is formed with a common data input 30, which the
  • Circuit arrangement for determining the beginning of a transmission frame 2 and the
  • Circuit arrangement for determining the optimum sampling time 1 comprises.
  • Fig. 1 shows a block diagram of a conventional acquisition unit for a digital
  • the process is fed by the samples Zk at the output of a matched filter 5.
  • Sample time 31 operates with no data support (non-data-aided)
  • Delay element 25 delays the incoming data stream accordingly by Lt symbols.
  • Interpolator 22 is provided. As a result, the samples Yk serve to determine the
  • the respective delay elements 25, 26 are used solely to delay the respective symbol streams, in each case by those for the calculations require observation lengths Lt and Lc, respectively, so that the respective circuit arrangement can be loaded in parallel and the respective value can be calculated. If no preamble, but the synchronization word and a part of the subsequent payload data is used for the known determination of the optimum sampling time, then a correspondingly large gap (guard time) between the data packets is necessary for such an arrangement, which also uses the existing bandwidth only insufficient becomes (analogous to the use of a preamble).
  • An acquisition unit has no separate unit 31 for determining an optimum sampling time of a digital oversampled data stream, which is arranged after a matched filter 5 in the signal path and requires a preamble in the signal to determine the optimum sampling time.
  • the determination of the optimum sampling time takes place in a combined circuit arrangement 4 with a common data input, whereby the circuit arrangement for determining the start of a transmission frame 2 (correlation unit) and preferably the circuit arrangement for determining the carrier frequency 3 of a digital data stream are combined in the combined circuit arrangement 4 ,
  • the common acquisition uses feedforward determination methods for carrier frequency and phase, as known from the technical literature, and that this philosophy is also not affected by the determination of the optimum sampling time (no transient or stability problems as is the case with backward coupled solutions). Furthermore, it can be provided that the invention is applicable to all linear modulation techniques and all baseband pulses, as long as they are bandwidth limited and complying with the first Nyquist criterion. Furthermore, it can be provided that the invention works transparently with respect to the selected length Lc.
  • the guard time between two data packets long without the use of a preamble is at least Lt + Lc symbols (or a proportional factor thereto) long, can be shortened by at least Lt symbols (or a proportional factor thereto). This ensures an increase in the efficiency of the TDMA system, which is the more significant the smaller the packet lengths are.
  • the combined circuit arrangement according to the invention can be used for any type of sampling.
  • the determined optimum sampling instant may subsequently be characterized by the nearest sampled value.
  • interpolative methods may be provided to calculate the correlation maximum, which corresponds to the optimum sampling time.
  • the combined circuit arrangement 4 is preceded by a signal-matched filter 5. Furthermore, it can be provided that in the combined circuit arrangement 4, the circuit arrangement for determining the start of a transmission frame 2 (correlation unit) and the circuit arrangement for determining the carrier frequency 3 of a digital data stream Circuit arrangement for determining an optimum sampling time 1 are connected upstream.
  • the combined circuit arrangement 4 according to the preferred arrangement according to FIG. 2 comprises the circuit arrangement for determining the start of a transmission frame 2, the circuit arrangement for determining the optimum sampling instant 1 and the circuit arrangement for determining the carrier frequency of a digital data stream 3.
  • circuit arrangements 1, 2, 3 downstream, but structurally preferably integrated into the combined circuit 4 the circuit arrangement for determining a phase position 19 of the digital data stream in relation to reference data, preferably the synchronization word, and / or the circuit arrangement 20 for determining the beginning of a data frame.
  • the circuit arrangement for determining the beginning of a transmission frame 2 comprises a first shift register 6 having a register length LcNos, where Lc is the length of the synchronization word UW and Nos the degree of oversampling (number of samples per symbol).
  • the samples Zk as available at the output of the matched filter 5, are loaded into the first shift register 6. Its content is tapped at a distance Nos, the respective samples (marked in black) multiplied by the conjugate-complex synchronization word UW * (to eliminate the data modulation) and supplied to the circuitry for determining the carrier frequency 3 of a digital data stream.
  • the samples previously frequency-corrected in a frequency correction unit 8 are added in an adding unit 29, and in an amount forming unit 9, the sum amount for the further determination of the optimum sampling time is formed.
  • the circuit arrangement for determining the carrier frequency 3 of a digital data stream further supplies a frequency correction value v to a complex phase shifter 21 for frequency correction of the digital data stream.
  • the accumulated sum of sums are forwarded to the circuitry for determining an optimum sampling time 1.
  • the correlation maximum can not be calculated or searched in the known solution until all samples that are above a predefinable threshold have been received. This fact has a negative effect insofar as in such solutions a register has to be implemented which caches the samples for determining the maximum amount; their number is generally not constant, which requires a variable register length that is not very elegant, especially for hardware solutions.
  • the circuit arrangement for determining the optimum sampling instant 1 comprises at least a second shift register 10, wherein the second shift register 10 preferably has an odd number shift register cells 11, wherein in particular in an odd oversampling Nos, the number of shift register cells 11 the value of Nos or, in the case of an even oversampling Nos, the number of shift register cells 11 corresponds to the value of Nos minus one.
  • FIG. 1 A preferred embodiment of such a circuit arrangement 1 is shown in FIG.
  • the second shift register 10 is fed stepwise with the amount sums from the amount forming unit 9. It can be provided that the second shift register 10 has a first cell block 12, a middle cell 13 (marked in black) and a second cell block 14, wherein the first cell block 12 and the second cell block 14 comprise the same number of cells 11, and the middle one Cell 13 is connected to the third input C of a decision logic 15.
  • the second shift register 10 has a first cell block 12, two middle cells and a second cell block 14, the first cell block 12 and the second cell block 14 comprises the same number of cells 11, and the two middle cells are connected to an input of an average unit whose output is connected to the third input C of the decision logic 15.
  • the first cell block 12 and the second cell block 14 are preferably connected to inputs of at least one summing unit 16, wherein in each case at least one output of the summing units 16 is connected to a subtraction unit 17.
  • the output of the subtraction unit 17 is connected both to an input of a delay element 18 and directly to a second input B of a decision logic 15.
  • the output of the delay element 18 is connected to a first input A of the decision logic 15.
  • the middle cell 13 is connected to a third input C of the decision logic 15 or, in the case of two middle cells, the output of an average unit.
  • a predefinable correlation threshold is applied to a fourth input D of the decision logic 15.
  • the decision logic 15 provides a synchronization pulse to an output E for the beginning of the transmission frame and / or the data frame, for the calculation of the carrier phase as well as for the index of that sample which is closest to the optimum sampling time, exactly if the first and the second Input A, B of the decision logic 15 have the first time different sign and the third input C is above the voltage applied to the fourth input D correlation threshold.
  • the synchronization pulse is supplied to a downstream circuit arrangement for determining a phase position 19 of the digital data stream in relation to reference data and / or to an input of a circuit arrangement for determining the start of a data frame 20, wherein preferably the circuit arrangement for determining the phase position 19 of the digital data stream in relation to reference data and / or the circuit arrangement for determining the start of a data frame 20 are part of the combined circuit arrangement 4 with common data input.
  • the outputs of the combined circuit 4 are, as already partially explained, connected to a complex phase shifter 21 and / or to a tracking unit 23, to the complex phase shifter 21 preferably a frequency correction signal v is supplied and the tracking unit 23 preferably at least one value for the Phase position of the digital data stream in relation to reference data and / or a signal for the beginning of a data frame is sent.
  • FIG. 3 shows an arrangement in which the circuit arrangement for determining the carrier frequency 3 of a digital data stream is not integrated into the common circuit arrangement 4. Rather, this is accommodated together with a special correlation unit 32 in a separate circuit arrangement. The incoming data stream is frequency-corrected in front of the common circuit 4, whereby the structure of the common circuit 4 can be simplified.
  • an acquisition unit can preferably be provided to construct an acquisition unit according to the invention by means of hardware components (such as digital gates, PGAs or FPGAs).
  • the invention further includes a digital TDMA modem with a described

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

L'invention concerne une unité d'acquisition pour un modem AMRT, comprenant un ensemble circuit destiné à déterminer un instant d'échantillonnage optimal (1) d'un flux de données numériques, généré à partir d'un signal de bande de base par suréchantillonnage avec un nombre prédéfinissable d'échantillons par symbole, un ensemble circuit destiné à déterminer le début d'une trame de transmission (2) et un ensemble circuit destiné à déterminer la fréquence porteuse (3) d'un flux de données numériques. L'objectif de cette invention est de permettre une utilisation plus efficace de la bande passante du système principalement dans le cas de longueurs de paquets plus petites. A cet effet, un ensemble circuit combiné (4), pourvu d'une entrée de données commune (30), comprend l'ensemble circuit destiné à déterminer le début d'une trame de transmission (2) et l'ensemble circuit destiné à déterminer l'instant d'échantillonnage optimal (1).
PCT/AT2006/000056 2005-03-08 2006-02-15 Unite d'acquisition WO2006094319A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112006000510T DE112006000510A5 (de) 2005-03-08 2006-02-15 Akquisitionseinheit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
ATA391/2005 2005-03-08
AT3912005A AT501481B8 (de) 2005-03-08 2005-03-08 Akquisitionseinheit

Publications (1)

Publication Number Publication Date
WO2006094319A1 true WO2006094319A1 (fr) 2006-09-14

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Family Applications (1)

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PCT/AT2006/000056 WO2006094319A1 (fr) 2005-03-08 2006-02-15 Unite d'acquisition

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AT (1) AT501481B8 (fr)
DE (1) DE112006000510A5 (fr)
WO (1) WO2006094319A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19904956A1 (de) * 1999-02-06 2001-01-18 Univ Dresden Tech Verfahren und Vorrichtung zur optimalen Einstellung des Abtastzeitpunktes bei digitaler Zusatzdatenübertragung in analogen TV-Kanälen
WO2001095553A1 (fr) * 2000-06-07 2001-12-13 Siemens Information And Communication Networks S.P.A. Procede permettant d'estimer la phase de rythme des symboles a la reception de signaux de donnees
WO2003075505A1 (fr) * 2002-03-06 2003-09-12 Hitachi Kokusai Electric Inc. Procede de detection de synchronisation et son circuit, et station radio de base
US6654432B1 (en) * 1998-06-08 2003-11-25 Wireless Facilities, Inc. Joint maximum likelihood frame and timing estimation for a digital receiver

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4599732A (en) * 1984-04-17 1986-07-08 Harris Corporation Technique for acquiring timing and frequency synchronization for modem utilizing known (non-data) symbols as part of their normal transmitted data format
US6058150A (en) * 1997-09-30 2000-05-02 Wireless Access, Inc. Method and apparatus for combined timing recovery, frame synchronization and frequency offset correction in a receiver
WO1999021323A2 (fr) * 1997-10-20 1999-04-29 Wireless Facilities Inc. Systeme hertzien a porteuse multimedia

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6654432B1 (en) * 1998-06-08 2003-11-25 Wireless Facilities, Inc. Joint maximum likelihood frame and timing estimation for a digital receiver
DE19904956A1 (de) * 1999-02-06 2001-01-18 Univ Dresden Tech Verfahren und Vorrichtung zur optimalen Einstellung des Abtastzeitpunktes bei digitaler Zusatzdatenübertragung in analogen TV-Kanälen
WO2001095553A1 (fr) * 2000-06-07 2001-12-13 Siemens Information And Communication Networks S.P.A. Procede permettant d'estimer la phase de rythme des symboles a la reception de signaux de donnees
WO2003075505A1 (fr) * 2002-03-06 2003-09-12 Hitachi Kokusai Electric Inc. Procede de detection de synchronisation et son circuit, et station radio de base

Also Published As

Publication number Publication date
DE112006000510A5 (de) 2008-01-24
AT501481A4 (de) 2006-09-15
AT501481B1 (de) 2006-09-15
AT501481B8 (de) 2007-02-15

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