WO2006072975A1 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
WO2006072975A1
WO2006072975A1 PCT/JP2005/000013 JP2005000013W WO2006072975A1 WO 2006072975 A1 WO2006072975 A1 WO 2006072975A1 JP 2005000013 W JP2005000013 W JP 2005000013W WO 2006072975 A1 WO2006072975 A1 WO 2006072975A1
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WIPO (PCT)
Prior art keywords
film
insulating film
gate insulating
gate electrode
semiconductor device
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PCT/JP2005/000013
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French (fr)
Japanese (ja)
Inventor
Masaomi Yamaguchi
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Fujitsu Limited
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Priority to PCT/JP2005/000013 priority Critical patent/WO2006072975A1/en
Publication of WO2006072975A1 publication Critical patent/WO2006072975A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same.
  • MOS Metal Oxide Semiconductor
  • SiO 2 silicon dioxide
  • SiON silicon oxynitride
  • Insulative metal oxide films such as ⁇ film have a high relative dielectric constant (about 20) and a barrier height against silicon crystals. In view of the influence on the channel, it is regarded as the most promising next-generation gate insulating film.
  • Patent Document 1 discloses that a damaged layer is intentionally formed on the surface layer of a ⁇ film by plasma in order to etch the ⁇ film formed by heat treatment, and the damaged layer is wet-etched.
  • Patent Document 2 discloses a technique related to the present invention.
  • Patent Document 1 Japanese Patent Laid-Open No. 2003-234325
  • Patent Document 2 JP-A-2002-198521
  • An object of the present invention is to provide a MOS transistor using an insulating metal oxide film as a gate insulating film
  • An object of the present invention is to provide a semiconductor device capable of improving the characteristics of the semiconductor device and a method for manufacturing the same.
  • a step of forming an insulating metal oxide film as a gate insulating film on a semiconductor substrate a step of forming a sacrificial film on the gate insulating film, Removing the sacrificial film from above the gate insulating film; forming the gate electrode conductive film on the gate insulating film after removing the sacrificial film; and patterning the gate electrode conductive film.
  • the surface layer portion of the insulating metal oxide film constituting the gate insulating film is weakly bonded to surrounding elements. Unstable metal atoms are absorbed by the sacrificial film, and only the stable metal atoms are left on the surface layer of the gate insulating film by strongly bonding with the surroundings. Therefore, in the step of forming the gate electrode conductive film containing silicon on the gate insulating film, the metal atoms on the surface layer of the gate insulating film are difficult to diffuse into the gate conductive film. Fermi level pinning associated with atoms can be suppressed. As a result, the MOS transistor can be prevented from increasing power consumption S and the power consumption of the transistor can be prevented from increasing.
  • the diffusion of metal atoms from the gate insulating film to the sacrificial film is promoted by heat, so that unstable metal atoms having a weak binding force are removed from the gate insulating film.
  • Surface force can also be reliably removed, and the above Fermi level pinning can be more effectively suppressed.
  • the number of metal atoms per unit area of the insulating metal oxide diffused from the gate insulating film to the gate electrode is 1 X ⁇ 12 (cm " 2 )
  • the number of metal atoms per unit area of the insulating metal oxide diffused from the gate insulating film to the gate electrode is 1 X ⁇ 12 (cm " 2 )
  • FIG. 1 is a cross-sectional view of a MOS transistor Tr that employs a ⁇ film as a gate insulating film.
  • FIG. 2 is a graph showing the gate voltage (Vg) -drain current (Id) characteristics of a MOS transistor.
  • FIG. 3 is a cross-sectional view (part 1) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
  • FIG. 4 is a cross-sectional view (part 2) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
  • FIG. 5 is a cross-sectional view (part 3) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
  • FIG. 6 is a cross-sectional view (part 4) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
  • FIG. 7 is a graph showing the relationship between the remaining thickness of the sacrificial film and the immersion time when a TMAH solution is used as an etching solution.
  • FIG. 8 is a CV curve of each MOS transistor according to the embodiment of the present invention and a comparative example.
  • FIG. 9 is a graph obtained by calculating the shift amount AVl of the flat band voltage Vl of each MOS transistor of the embodiment of the present invention and the comparative example.
  • the gate insulating film has an EOT force of .2-1.4 nm and a leakage current of 8 mA / cm 2 or less.
  • a high value (90% or more of SiO film) is required for the mobility of the channel under the gate insulating film.
  • An example of a high dielectric constant insulating film that satisfies such a requirement is an insulating metal oxide film such as “ ⁇ ”.
  • Figure 1 shows a cross section of a ⁇ -type MOS transistor Tr that uses the ⁇ film as a gate insulating film.
  • FIG. 1 A first figure.
  • the MOS transistor Tr includes a buffer layer 2 made of silicon oxide on a silicon substrate 1 and
  • a gate electrode 4 made of polysilicon is formed on the gate insulating film 3.
  • an oxide silicon film is formed as an insulating sidewall 5 on the side of the gate electrode 4, and a ⁇ -type source and drain formed by ion implantation using the insulating sidewall 5 as a mask. Region 6 is formed in the surface layer of silicon substrate 1.
  • FIG. 2 is a graph showing the gate voltage (Vg) -drain current (Id) characteristics of the MOS transistor.
  • Vg gate voltage
  • Id drain current
  • a silicon dioxide film is used.
  • Vg higher than 1 must be applied to the gate electrode.
  • the threshold voltage Vth of the transistor is higher when the HlSiO film is used than when the silicon dioxide film is used as the gate insulating film.
  • An increase in voltage of Vth is not preferable because it causes an increase in power consumption in the transistor.
  • the increase in threshold voltage Vth as described above is caused by the use of the ⁇ film as a gate insulating film as described above, and various models can be considered as its mechanism.
  • the inventor of the present application moves the Hf atom in the gate insulating film 3 into the gate electrode 4 made of polysilicon as shown in the dotted circle in FIG. Join When it is formed, pay attention to the model.
  • the Hf-Si bond is a metal bond, an energy level is formed in the forbidden band. Therefore, when a voltage is applied to the gate electrode 4, carriers that have moved from the valence band and the conduction band are trapped in their levels. Since the trapped carriers act to fix the Fermi level, the drain current Id does not increase even when a certain amount of voltage is applied to the gate electrode 4, and the threshold value as described in FIG. Causes high voltage.
  • the phenomenon in which the Fermi level is fixed in this way is the Fermi level peering (Fermi level
  • 3 to 6 are cross-sectional views of the semiconductor device according to this embodiment in the middle of manufacture.
  • a p-type silicon (semiconductor) substrate 10 having a (100) surface is formed on an STI (Shallow Trench).
  • a silicon dioxide film is buried in the trench 10a to form an element isolation insulating film 11.
  • the element isolation structure is not limited to STI,
  • LuCuS Lical Oxidation of; silicon
  • n-type impurities such as phosphorus are ion-implanted into a transistor formation region of the silicon substrate 10 defined by the element isolation insulating film 11 to form an n-well 13.
  • the ion implantation is performed using a thermal oxide film (not shown) formed on the surface of the silicon substrate 10 as a through film, and after the n-well 13 is formed, the thermal oxide film is removed. .
  • the surface of the silicon substrate 10 is subjected to thermal oxidation, so that the silicon oxide having a thickness of about 1 mm is obtained.
  • a film is formed and used as a buffer layer 12.
  • MOCVD Metal Organic CVD
  • a ⁇ film is formed as a gate insulating film 14 on the notch layer 12 to a thickness of about 4 nm.
  • H N (CH)) and SiH (N (CH)) used in MOCVD are liquid at room temperature (20 ° C).
  • the silicon substrate 10 After publishing with nitrogen, it is introduced above the silicon substrate 10 together with a carrier gas such as nitrogen.
  • a carrier gas such as nitrogen.
  • the flow rates of the carrier gas and NO gas are not particularly limited, but in this embodiment, the total flow rate of carrier gas is about 500 sccm, and the flow rate of NO gas is about 300 sccm.
  • the pressure of the film forming atmosphere is not particularly limited, but in this embodiment, the pressure is set to about 30 Pa.
  • the gate insulating film 14 is not limited to a ⁇ film as long as it is an insulating metal oxide film.
  • Examples of such an insulating metal oxide film include a ZrSiON film, an AlSiON film, a TaSiON film, a TiSiON film, and a YSiON film in addition to the ⁇ film.
  • the TaSiON film is a gas obtained by publishing TPE (Tantalum Pent ethoxyd: Ta (OC H)), which is a liquid material, with nitrogen.
  • the ⁇ film in this specification does not have to be a stoichiometric film, and the atomic ratio of Hf, Si, O, and N varies by 1: 1: 1: 1. It ’s okay.
  • the gate insulating film 14 is subjected to a heat treatment in a nitrogen atmosphere at a substrate temperature of 800 ° C and a processing time of 30 seconds, and the ⁇ constituting the gate insulating film 14 is sintered. .
  • a heat treatment is also called PDA (Post Deposition Anneal).
  • the substrate temperature is 600 ° C
  • the pressure is 27 Pa
  • the flow rate of silane (SiH) is 120 sccm.
  • a polysilicon film is formed on the gate insulating film 14 to a thickness of about 110 by a low pressure CVD method, and this is used as the sacrificial film 15.
  • the sacrificial film 15 is not limited to a polysilicon film as long as it is a film containing silicon.
  • a film examples include an amorphous silicon film, a silicide film, and a silicate film in addition to the polysilicon film.
  • amorphous silicon films are silane, disilane (SiH), etc.
  • the silicide film has a target of a refractory metal such as cobalt and a silicon target separately disposed above the silicon substrate 10 and strikes the surface of these targets with a sputtering gas such as Ar, in the gas phase or in the gate. It can be formed by reacting a refractory metal and silicon on the insulating film 14.
  • the silicate film is made of a liquid material such as tridimethylamino hydride silicon (SiH (N (CH);)).
  • Hf atoms in the vicinity of the surface of the gate insulating film 14 are unstable and have weak bonds with surrounding 0 elements, Si elements, N elements, and the like. Such unstable Hf atoms are easily diffused into the sacrificial film 15 away from the gate insulating film 14 and form Hf-Si bonds in the sacrificial film 15 as shown in the dotted circle. To do. Therefore, after the sacrificial film 15 is formed, the unstable H source element also removes the surface layer partial force of the gate insulating film 14.
  • the sacrificial film 15 is subjected to heat treatment to promote the diffusion of Hf atoms into the sacrificial film 15 by thermal energy.
  • the heat treatment is performed, for example, in a nitrogen atmosphere under conditions where the substrate temperature is 800 ° C. and the processing time is 30 seconds.
  • the sacrificial film 15 is exposed to a hydrofluoric acid solution at room temperature diluted 1: 200 (volume ratio) with water for about 1 minute to naturally oxidize silicon formed on the surface of the sacrificial film 15. Remove the membrane The Next, in order to remove the hydrofluoric acid remaining on the surface of the sacrificial film 15, the sacrificial film 15 is immersed in pure water at room temperature for about 10 minutes for cleaning.
  • the sacrificial film 15 that has absorbed the H source element is immersed in an etching solution, and the sacrificial film 15 is selectively wet-etched to be removed from the gate insulating film 14.
  • the etchant used at this time is not particularly limited as long as the etchant of the gate insulating film 14 is lower than the etch rate of the sacrificial film 15.
  • TMAH Tetramethyl ammonium nydr oxide: (N (Cri)
  • TMAH Tetramethyl ammonium nydr oxide: (N (Cri)
  • FIG. 7 is a graph showing the relationship between the remaining thickness of the sacrificial film 15 and the immersion time when a TMAH solution having a liquid temperature of 0 ° C. is used as an etching solution. As shown in the figure, the sacrificial film 15 originally formed with a thickness of 11 Onm is almost etched after about 15 minutes.
  • the liquid temperature of the TMAH solution is set to 40 ° C.
  • the etching time is set to 30 minutes so that the sacrificial film 15 is over-etched for 15 minutes, and the sacrificial film is formed using the TMAH solution.
  • the sacrificial film 15 is etched in this way, the weakly bonded Hf atoms that have moved from the underlying gate insulating film 14 into the sacrificial film 15 are also removed, so that the surface layer of the gate insulating film 14 is removed. Will leave only the H source, which is strongly bound to the surrounding elements.
  • the exposed surface of the gate insulating film 14 is washed with water for about 10 minutes at room temperature, and the TMAH solution remaining on the gate insulating film 14 is washed and poured.
  • the gate insulating film 14 is immersed in a boiling SC2 solution for about 10 minutes, and the metal compound on the surface is completely etched. And remove.
  • the SC2 solution used in this etching is hydrochloric acid. , Hydrogen peroxide, and pure water mixed at a predetermined ratio.
  • the gate insulating film 14 is washed with water at room temperature for about 10 minutes to wash away the SC2 solution, thereby completing the series of wet etching described above.
  • a polysilicon film is formed on the gate insulating film 14 to a thickness of about 100 using a low pressure CVD method using silane as a reaction gas.
  • a conductive film 16 for a gate electrode is employed as film formation conditions at this time.
  • a substrate temperature of 600 ° C., a pressure of 27 Pa, and a silane flow rate of 120 sccm are employed.
  • the conductive film 16 for gate electrode is not particularly limited as long as it is a conductive material containing silicon, and may be an amorphous silicon film.
  • the weakly bonded Hf atoms present in the surface layer portion of the gate insulating film 14 are removed together with the sacrificial film 15 in advance. Therefore, even if the gate electrode conductive film 16 is formed on the gate insulating film 14 as described above, the H source element remaining in the gate insulating film 14 is strongly bonded to surrounding atoms. The source element is difficult to diffuse into the gate electrode conductive film 16. As a result, as shown in the dotted circle, the gate electrode conductive film 16 is substantially composed of only silicon atoms, and metal atoms such as H source elements are almost present in the gate conductive film 16. do not do.
  • the gate electrode conductive film 16 is patterned by photolithography to form a gate electrode 16a.
  • the gate insulating film 14 and the buffer layer 12 under the gate electrode 16a are also etched and patterned into a gate electrode shape.
  • a p-type impurity such as boron is formed on the silicon substrate 10 to form a p-type source Z drain extension 18.
  • a silicon dioxide film is formed on the entire surface and etched back so that an insulating sidewall 19 is formed beside the gate electrode 16a. Leave as. Then, a p-type impurity such as boron is implanted into the silicon substrate 10 on the side of the gate electrode 16a by ion implantation using the insulating sidewall 19 as a mask to form the p-type source Z drain region 20.
  • a p-type impurity such as boron
  • a force for injecting boron also into the gate electrode 16a constitutes the gate insulating film 14.
  • the nitrogen in the film can prevent boron from penetrating into the silicon substrate 10 under the gate insulating film 14, and can suppress the deterioration of the electrical characteristics of the channel due to the penetrating nitrogen. .
  • a cobalt film is formed on the entire surface by a sputtering method
  • the cobalt film is subjected to a heat treatment to react cobalt and silicon.
  • a cobalt silicide layer 22 is formed on the surface layer of the p-type source Z drain region 20.
  • the cobalt silicide layer 22 is also formed on the surface layer of the gate electrode 16a, whereby the gate electrode 16a has a polycide structure.
  • the basic structure of the p-type MOS transistor Tr is completed through the steps so far. Thereafter, the process proceeds to a process of forming a first interlayer insulating film covering the transistor Tr and forming a conductive plug electrically connected to the p-type source Z drain region 20 in the interlayer insulating film. The details are omitted.
  • the H source element that is weakly bonded to surrounding atoms in the vicinity of the surface layer of the gate insulating film 14 is absorbed by the sacrificial film 15. Only the Hf atoms that are strongly bonded to the surroundings are left on the surface layer of the gate insulating film 14. Therefore, even if the gate electrode conductive film 16 is formed on the gate insulating film 14 in the step of FIG. 5A, the H source layer on the surface of the gate insulating film 14 is difficult to diffuse into the gate conductive film 16. In addition, Fermi level pinning associated with Hf atoms diffused in the gate electrode 16a can be suppressed. As a result, it is possible to avoid an increase in the threshold voltage of the transistor and to prevent an increase in power consumption in the transistor Tr.
  • FIG. 8 is a CV curve of the MOS transistor Tr created as described above.
  • the CV curve is a curve showing the relationship between the gate-to-substrate capacitance C and the gate voltage Vg, and was obtained when the planar size force of the gate electrode 16a is 3 ⁇ 40 m ⁇ 80 m.
  • the CV curve of the transistor Tr created in Fig. 1 is also shown as a comparative example. So
  • the transistor Tr according to the comparative example is obtained by directly forming the polysilicon gate electrode 4 on the gate insulating film 3 without forming the sacrificial film 15 as in the present embodiment.
  • the CV curve according to the present embodiment is shifted to the + side of the gate voltage Vg compared to the comparative example.
  • the capacitance C in this embodiment is smaller than that of the comparative example. This indicates that, in the present embodiment, unstable Hf atoms remaining at the interface between the gate electrode 16a and the gate insulating film 14 are reduced, and the capacitance caused by the Hf atoms is reduced.
  • FIG. 9 is a graph obtained by calculating the shift amount AVl of the flat band voltage Vl of each of the comparative example of FIG. 8 and the present embodiment.
  • the standard of the shift amount ⁇ Vl is the flat band voltage in the ideal case where there is no unstable H source.
  • the shift amount AVl is about ⁇ 0.72 V
  • the shift amount ⁇ Vl in this embodiment is about 0.67 V, which is 0 compared to the comparative example. close. Since the flat band voltage increases as the number of unstable Hf atoms remaining at the interface between the gate electrode 16a and the gate insulating film 14 increases, the result of FIG. 9 indicates that such H source elements are reduced in this embodiment. It became clear that
  • the present invention is not limited to the above-described embodiments.
  • an n-type MOS transistor may be formed! /.
  • the unstable metal atoms existing on the surface layer of the insulating metal oxide film serving as the gate insulating film are absorbed by the sacrificial film, so that the Fermi level caused by the metal atoms is absorbed. Pinning can be suppressed.
  • the threshold voltage of the MOS transistor can be prevented from increasing, and the power consumption of the MOS transistor can be prevented from increasing.
  • a method for manufacturing a semiconductor device comprising:
  • the step of removing the sacrificial film is performed by wet etching using an etchant in which an etch rate of the gate insulating film is lower than an etch rate of the sacrificial film.
  • a method for manufacturing a semiconductor device (Supplementary note 6) The method of manufacturing a semiconductor device according to supplementary note 5, wherein a TMAH (Tetramethyl ammonium hydroxide) solution is used as the etching solution.
  • TMAH Tetramethyl ammonium hydroxide
  • Supplementary note 7 characterized in that NH OH solution is used as the etching solution
  • the method Before the step of forming the gate insulating film, the method includes a step of forming a buffer layer on the semiconductor substrate, and the gate insulating film is formed on the buffer layer. 2. The method for manufacturing a semiconductor device according to appendix 1, wherein:
  • Appendix 11 The semiconductor according to appendix 10, wherein the step of forming the buffer layer is performed by thermally oxidizing the surface of the semiconductor substrate to form an oxide silicon film. Device manufacturing method.
  • a the number per unit area of the metal atoms of the insulating metal oxide diffused into the gate electrode from the gate insulating film is reduced to 1 X 10 12 (cm- 2) or less.
  • insulating metal oxide is any one of Hf, Zr, Ta, Ti, and Y.

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Abstract

A semiconductor device manufacturing method is provided with a process of forming an insulating metal oxide film as a gate insulating film (14) on a silicon (semiconductor) substrate (10); a process of forming a sacrificial film (15) on the gate insulating film (14); a process of removing the sacrificial film (15) from the gate insulating film (14); a process of forming a gate electrode conductive film (16) on the gate insulating film (14) after removing the sacrificial film (15); a process of patterning the gate electrode conductive film (16) into a gate electrode (16a); a process of forming a source/drain region (20) on the silicon substrate (10) and forming an MOS transistor (Tr) with the source/drain region (20), the gate electrode (16a) and the gate insulating film (14).

Description

明 細 書  Specification
半導体装置とその製造方法  Semiconductor device and manufacturing method thereof
技術分野  Technical field
[0001] 本発明は、半導体装置とその製造方法に関する。  The present invention relates to a semiconductor device and a method for manufacturing the same.
背景技術  Background art
[0002] 近年、 LSI等の半導体装置の微細化に伴!、、 MOS(Metal Oxide Semiconductor)トラ ンジスタのゲート絶縁膜は一層の薄膜ィ匕が進んでいる。ゲート絶縁膜としては、二酸 化シリコン (SiO )膜ゃ酸窒化シリコン (SiON)膜を使用するのが一般的である。しかし、  In recent years, with the miniaturization of semiconductor devices such as LSIs, the gate insulating film of MOS (Metal Oxide Semiconductor) transistors is becoming increasingly thin. As the gate insulating film, a silicon dioxide (SiO 2) film or a silicon oxynitride (SiON) film is generally used. But,
2  2
これらの膜の厚さが薄くなると、絶縁性能の低下によりゲート一基板間のリーク電流が 増大して消費電力が増えたり、ゲート電極にドープしたボロン等の不純物がゲート絶 縁膜を介してチャネルに達したりして、 MOSトランジスタの性能や信頼性が低下する という不都合が生じる。  When the thickness of these films is reduced, leakage current between the gate and the substrate increases due to a decrease in insulation performance, and power consumption increases, or impurities such as boron doped in the gate electrode are channeled through the gate insulation film. This results in a disadvantage that the performance and reliability of the MOS transistor deteriorates.
[0003] そこで、二酸化シリコン膜や酸窒化シリコン膜よりも誘電率の高!、高誘電率 (High-k) 絶縁膜をゲート絶縁膜として使用することにより、物理的な厚さを維持しながら酸ィ匕膜 換算膜厚（EOT: Effective Oxide Thickness)を薄くし、それにより MOS構造の容量値 の増大を図り、 MOSトランジスタの高集積ィ匕を目指すことに注目が集まって 、る。  Therefore, by using an insulating film having a dielectric constant higher than that of a silicon dioxide film or a silicon oxynitride film as a gate insulating film, while maintaining a physical thickness, Attention has been focused on aiming for high integration of MOS transistors by reducing the equivalent oxide thickness (EOT), thereby increasing the capacitance value of the MOS structure.
[0004] そのような高誘電率絶縁膜にはいくつかある力 なかでも ΗβίΟ膜のような絶縁性金 属酸化膜は、その比誘電率の高さ (約 20程度)や、シリコン結晶に対するバリアハイト 、及びチャネルへの影響から、次世代のゲート絶縁膜として最も有力視されている。  [0004] Among such high dielectric constant insulating films, there are some strengths. Insulative metal oxide films such as ΟβίΟ film have a high relative dielectric constant (about 20) and a barrier height against silicon crystals. In view of the influence on the channel, it is regarded as the most promising next-generation gate insulating film.
[0005] 特許文献 1では、熱処理によって変質した ΗβίΟ膜をエッチングするために、プラズ マによって ΗβίΟ膜の表層にダメージ層を意図的に形成し、そのダメージ層をゥエツト エッチングすることが開示されて 、る。  [0005] Patent Document 1 discloses that a damaged layer is intentionally formed on the surface layer of a ββί film by plasma in order to etch the ββ film formed by heat treatment, and the damaged layer is wet-etched. The
[0006] その他に、本発明に関連する技術が特許文献 2にも開示されている。  [0006] In addition, Patent Document 2 discloses a technique related to the present invention.
特許文献 1：特開 2003— 234325号公報  Patent Document 1: Japanese Patent Laid-Open No. 2003-234325
特許文献 2 :特開 2002-198521号公報  Patent Document 2: JP-A-2002-198521
発明の開示  Disclosure of the invention
[0007] 本発明の目的は、絶縁性金属酸ィ匕膜をゲート絶縁膜に使用した MOSトランジスタ の特性を向上させることができる半導体装置とその製造方法を提供することにある。 An object of the present invention is to provide a MOS transistor using an insulating metal oxide film as a gate insulating film An object of the present invention is to provide a semiconductor device capable of improving the characteristics of the semiconductor device and a method for manufacturing the same.
[0008] 本発明の一観点によれば、半導体基板の上に、ゲート絶縁膜として絶縁性金属酸 化膜を形成する工程と、前記ゲート絶縁膜の上に犠牲膜を形成する工程と、前記犠 牲膜を前記ゲート絶縁膜の上から除去する工程と、前記犠牲膜を除去した後、前記 ゲート絶縁膜の上にゲート電極用導電膜を形成する工程と、前記ゲート電極用導電 膜をパター-ングしてゲート電極にする工程と、前記ゲート電極の側方の前記半導 体基板に不純物を注入してソース Zドレイン領域を形成し、該ソース Zドレイン領域、 前記ゲート電極、及び前記ゲート絶縁膜で MOSトランジスタを構成する工程と、を有 する半導体装置の製造方法が提供される。  [0008] According to one aspect of the present invention, a step of forming an insulating metal oxide film as a gate insulating film on a semiconductor substrate, a step of forming a sacrificial film on the gate insulating film, Removing the sacrificial film from above the gate insulating film; forming the gate electrode conductive film on the gate insulating film after removing the sacrificial film; and patterning the gate electrode conductive film. Forming a gate electrode by implanting impurities into the semiconductor substrate on the side of the gate electrode to form a source Z drain region, the source Z drain region, the gate electrode, and the gate And a process for forming a MOS transistor with an insulating film.
[0009] 本発明によれば、ゲート絶縁膜の上に犠牲膜を形成する工程において、ゲート絶 縁膜を構成する絶縁性金属酸ィ匕膜の表層部分で周囲の元素と弱く結合している不 安定な金属原子が犠牲膜に吸収させられ、周囲と強く結合して安定的な金属原子の みがゲート絶縁膜の表層に残される。従って、ゲート絶縁膜上にシリコンを含有する ゲート電極用導電膜を形成する工程において、ゲート絶縁膜の表層の金属原子がゲ ート用導電膜に拡散し難くなるので、ゲート電極に拡散した金属原子に伴うフェルミ レベルピン-ングを抑制できる。その結果、 MOSトランジスタの閾値電圧の高電圧化 力 S避けられ、トランジスタで消費電力が増大するのを防ぐことが可能となる。  [0009] According to the present invention, in the step of forming the sacrificial film on the gate insulating film, the surface layer portion of the insulating metal oxide film constituting the gate insulating film is weakly bonded to surrounding elements. Unstable metal atoms are absorbed by the sacrificial film, and only the stable metal atoms are left on the surface layer of the gate insulating film by strongly bonding with the surroundings. Therefore, in the step of forming the gate electrode conductive film containing silicon on the gate insulating film, the metal atoms on the surface layer of the gate insulating film are difficult to diffuse into the gate conductive film. Fermi level pinning associated with atoms can be suppressed. As a result, the MOS transistor can be prevented from increasing power consumption S and the power consumption of the transistor can be prevented from increasing.
[0010] 特に、犠牲膜を加熱する工程を行うことにより、ゲート絶縁膜から犠牲膜への金属 原子の拡散が熱によって促進されるので、結合力の弱い不安定な金属原子をゲート 絶縁膜の表層力も確実に取り除くことがき、上記したフェルミレベルピンユングをより 一層効果的に抑制することが可能となる。  [0010] In particular, by performing the step of heating the sacrificial film, the diffusion of metal atoms from the gate insulating film to the sacrificial film is promoted by heat, so that unstable metal atoms having a weak binding force are removed from the gate insulating film. Surface force can also be reliably removed, and the above Fermi level pinning can be more effectively suppressed.
[0011] また、本発明の別の観点によれば、半導体基板と、前記半導体基板の上に形成さ れ、絶縁性金属酸化物で構成されるゲート絶縁膜と、前記ゲート絶縁膜の上に形成 されたゲート電極と、前記ゲート電極の側方の前記半導体基板に形成され、前記ゲ ート絶縁膜と前記ゲート電極と共に MOSトランジスタを構成するソース/ドレイン領域 とを有し、前記ゲート絶縁膜から前記ゲート電極に拡散する前記絶縁性金属酸化物 の金属原子の単位面積あたりの個数が 1 X 1012 (cm— 2)個以下に低減された半導体 装置が提供される。 [0012] 本願発明者が行ったシミュレーションによれば、このようにゲート絶縁膜からゲート 電極に拡散する絶縁性金属酸ィ匕物の金属原子の単位面積あたりの個数を 1 X ιο12( cm"2)個以下に低減することにより、拡散した金属原子に起因するフェルミレベルピン ユングを抑制することができ、 MOSトランジスタの閾値電圧の高電圧化を防止できるこ とが明ら力となった。 [0011] According to another aspect of the present invention, a semiconductor substrate, a gate insulating film formed on the semiconductor substrate and made of an insulating metal oxide, and on the gate insulating film A gate electrode formed; and a source / drain region formed on the semiconductor substrate on a side of the gate electrode and constituting a MOS transistor together with the gate insulating film and the gate electrode; the number per unit area of the metal atoms of the insulating metal oxide diffused into the gate electrode is a semiconductor device that is reduced in 1 X 10 12 (cm- 2) or less is provided from the. [0012] According to the simulation conducted by the present inventor, the number of metal atoms per unit area of the insulating metal oxide diffused from the gate insulating film to the gate electrode is 1 X ιο 12 (cm " 2 ) By reducing it to less than the number, Fermi level pinning caused by diffused metal atoms can be suppressed, and it has become clear that the threshold voltage of the MOS transistor can be prevented from being increased.
図面の簡単な説明  Brief Description of Drawings
[0013] [図 1]図 1は、 ΗβίΟ膜をゲート絶縁膜として採用した MOSトランジスタ Trの断面図であ る。  FIG. 1 is a cross-sectional view of a MOS transistor Tr that employs a ββ film as a gate insulating film.
[図 2]図 2は、 MOSトランジスタのゲート電圧 (Vg)—ドレイン電流 (Id)特性を示すグラフで ある。  FIG. 2 is a graph showing the gate voltage (Vg) -drain current (Id) characteristics of a MOS transistor.
[図 3]図 3は、本発明の実施の形態に係る半導体装置の製造途中の断面図（その 1) である。  FIG. 3 is a cross-sectional view (part 1) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
[図 4]図 4は、本発明の実施の形態に係る半導体装置の製造途中の断面図（その 2) である。  FIG. 4 is a cross-sectional view (part 2) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
[図 5]図 5は、本発明の実施の形態に係る半導体装置の製造途中の断面図（その 3) である。  FIG. 5 is a cross-sectional view (part 3) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
[図 6]図 6は、本発明の実施の形態に係る半導体装置の製造途中の断面図（その 4) である。  FIG. 6 is a cross-sectional view (part 4) of the semiconductor device according to the embodiment of the present invention in the middle of manufacture.
[図 7]図 7は、 TMAH溶液をエッチング液として使用した場合における犠牲膜の残厚と 浸漬時間との関係を示すグラフである。  FIG. 7 is a graph showing the relationship between the remaining thickness of the sacrificial film and the immersion time when a TMAH solution is used as an etching solution.
[図 8]図 8は、本発明の実施の形態と比較例のそれぞれの MOSトランジスタの CVカー ブである。  FIG. 8 is a CV curve of each MOS transistor according to the embodiment of the present invention and a comparative example.
[図 9]図 9は、本発明の実施の形態と比較例のそれぞれの MOSトランジスタのフラット バンド電圧 Vlのシフト量 AVlを算出して得られたグラフである。  FIG. 9 is a graph obtained by calculating the shift amount AVl of the flat band voltage Vl of each MOS transistor of the embodiment of the present invention and the comparative example.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0014] 次に、本発明の実施の形態について、添付図面を参照しながら詳細に説明する。 Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0015] (1)予備的事項の説明 [0015] (1) Explanation of preliminary matters
本発明の実施の形態を説明する前に、まず、予備的事項について説明する。 [0016] 既述の高誘電率絶縁膜がゲート絶縁膜として採用される世代では、そのゲート絶縁 膜に対して、 EOT力 . 2-1. 4nmでリーク電流が 8mA/cm2以下という条件や、ゲート 絶縁膜下のチャネルの移動度に対して高い値 (SiO膜の 90%以上）が要求される。 Before describing the embodiment of the present invention, first, preliminary matters will be described. [0016] In the generation where the above-described high dielectric constant insulating film is adopted as the gate insulating film, the gate insulating film has an EOT force of .2-1.4 nm and a leakage current of 8 mA / cm 2 or less. A high value (90% or more of SiO film) is required for the mobility of the channel under the gate insulating film.
2  2
このような要求を叶える高誘電率絶縁膜としては、 ΗβίΟ等の絶縁性金属酸ィ匕膜があ る。  An example of a high dielectric constant insulating film that satisfies such a requirement is an insulating metal oxide film such as “ββ”.
[0017] 図 1は、その ΗβίΟ膜をゲート絶縁膜として採用した ρ型 MOSトランジスタ Trの断面  [0017] Figure 1 shows a cross section of a ρ-type MOS transistor Tr that uses the ΗβίΟ film as a gate insulating film.
0 図である。  FIG.
[0018] その MOSトランジスタ Trは、シリコン基板 1の上に酸化シリコンよりなるバッファ層 2と  The MOS transistor Tr includes a buffer layer 2 made of silicon oxide on a silicon substrate 1 and
0  0
、 ΗβίΟよりなるゲート絶縁膜 3とを有し、そのゲート絶縁膜 3の上にポリシリコンよりな るゲート電極 4が形成される。  A gate electrode 4 made of polysilicon is formed on the gate insulating film 3.
[0019] そして、そのゲート電極 4の横には、酸ィ匕シリコン膜が絶縁性サイドウォール 5として 形成され、この絶縁性サイドウォール 5をマスクにするイオン注入により形成された ρ型 ソース Ζドレイン領域 6がシリコン基板 1の表層に形成される。 Next, an oxide silicon film is formed as an insulating sidewall 5 on the side of the gate electrode 4, and a ρ-type source and drain formed by ion implantation using the insulating sidewall 5 as a mask. Region 6 is formed in the surface layer of silicon substrate 1.
[0020] 図 2は、 MOSトランジスタのゲート電圧 (Vg)—ドレイン電流 (Id)特性を示すグラフであ る。図 2では、図 1で説明した MOSトランジスタの特性を Aで示していると共に、比較の ために、ゲート絶縁膜として二酸ィ匕シリコン膜を使用した MOSトランジスタの特性を B で示している。 FIG. 2 is a graph showing the gate voltage (Vg) -drain current (Id) characteristics of the MOS transistor. In FIG. 2, the characteristics of the MOS transistor described in FIG. 1 are indicated by A, and for comparison, the characteristics of a MOS transistor using a silicon dioxide film as a gate insulating film are indicated by B.
[0021] 図 2に示されるように、例えば Idなるドレイン電流を得るためには、二酸ィ匕シリコン膜  [0021] As shown in FIG. 2, for example, in order to obtain a drain current of Id, a silicon dioxide film is used.
0  0
をゲート絶縁膜とする通常の MOSトランジスタ (グラフ B)ではゲート電圧を Vgiとすれ ばよいのに対し、 ΗβίΟ膜をゲート絶縁膜にした MOSトランジスタ (グラフ A)では、 Vg In a normal MOS transistor (graph B) with a gate insulating film, the gate voltage should be V gi , whereas in a MOS transistor (graph A) with a ΗβίΟ film as the gate insulating film, Vg
1 よりも高い Vgをゲート電極に印加する必要がある。  Vg higher than 1 must be applied to the gate electrode.
2  2
[0022] このことは、ゲート絶縁膜として二酸ィ匕シリコン膜を使用する場合と比較して、 HlSiO 膜を使用する場合にはトランジスタの閾値電圧 Vthが高くなることを意味するが、閾値 電圧 Vthの高電圧化はトランジスタにおける消費電力の増大を招くので好ましくない。  [0022] This means that the threshold voltage Vth of the transistor is higher when the HlSiO film is used than when the silicon dioxide film is used as the gate insulating film. An increase in voltage of Vth is not preferable because it causes an increase in power consumption in the transistor.
[0023] このような閾値電圧 Vthの高電圧化は、既述のように ΗβίΟ膜をゲート絶縁膜として 使用したことに起因する力 そのメカニズムとしては色々なモデルが考えられる。その モデルの中で、本願発明者は、図 1の点線円内に示すように、ゲート絶縁膜 3中の Hf 原子がポリシリコンよりなるゲート電極 4中に移動し、ゲート電極 4において Hf-Si結合 が形成されると 、うモデルに着目して 、る。 [0023] The increase in threshold voltage Vth as described above is caused by the use of the ββ film as a gate insulating film as described above, and various models can be considered as its mechanism. In the model, the inventor of the present application moves the Hf atom in the gate insulating film 3 into the gate electrode 4 made of polysilicon as shown in the dotted circle in FIG. Join When it is formed, pay attention to the model.
[0024] Hf-Si結合は金属結合であるため禁制帯中にエネルギ準位を形成する。従って、ゲ ート電極 4に電圧を印加すると、価電子帯や導電帯から移動してきたキャリアがその 準位〖こトラップされること〖こなる。そのようにトラップされたキャリアはフェルミレベルを 固定ィ匕するように作用するので、ゲート電極 4にある程度大きな電圧を印加してもドレ イン電流 Idが上昇せず、図 2で説明したような閾値電圧の高電圧化を引き起こす。こ のようにしてフェルミレベルが固定化される現象は、フェルミレベルピ-ンング (Fermi [0024] Since the Hf-Si bond is a metal bond, an energy level is formed in the forbidden band. Therefore, when a voltage is applied to the gate electrode 4, carriers that have moved from the valence band and the conduction band are trapped in their levels. Since the trapped carriers act to fix the Fermi level, the drain current Id does not increase even when a certain amount of voltage is applied to the gate electrode 4, and the threshold value as described in FIG. Causes high voltage. The phenomenon in which the Fermi level is fixed in this way is the Fermi level peering (Fermi level
Level Pinning)と呼ばれる。 Called Level Pinning).
[0025] また、図 1で作製した MOSトランジスタ TRの断面を TEM(Transmission Electron  [0025] The cross section of the MOS transistor TR fabricated in FIG.
o  o
Microscope)で観察すると、ゲート電極 4とゲート絶縁膜 3との界面が明瞭に現れてい るのが確認された。このことは、ゲート絶縁膜 3の中の大部分の Hf原子がゲート電極 3 に移動するのではなぐ界面付近の少量の Hf原子のみが移動すること示唆している ので、界面近くの Hf原子の移動を阻止することができれば、上記したフェルミレベル ピンニングを防ぐことができる。  When observed with a microscope, it was confirmed that the interface between the gate electrode 4 and the gate insulating film 3 appeared clearly. This suggests that only a small amount of Hf atoms in the vicinity of the interface move rather than most of the Hf atoms in the gate insulating film 3 move to the gate electrode 3. If the movement can be prevented, the Fermi level pinning described above can be prevented.
[0026] 本願発明者は、このような考察に基づき、以下に説明するような本発明の実施の形 態に想到した。  [0026] Based on such considerations, the inventor of the present application has come up with an embodiment of the present invention as described below.
[0027] (2)本発明の実施の形態  (2) Embodiment of the present invention
図 3—図 6は、本実施形態に係る半導体装置の製造途中の断面図である。  3 to 6 are cross-sectional views of the semiconductor device according to this embodiment in the middle of manufacture.
[0028] 最初に、図 3 (a)に示す断面構造を得るまでの工程について説明する。  [0028] First, steps required until a sectional structure shown in FIG.
[0029] まず、表面が（100)面となる p型シリコン（半導体）基板 10に STI(Shallow Trench [0029] First, a p-type silicon (semiconductor) substrate 10 having a (100) surface is formed on an STI (Shallow Trench).
Isolation)用の溝 10aを形成した後、その溝 10a内に二酸ィ匕シリコン膜を埋め込んで 素子分離用絶縁膜 11とする。なお、素子分離構造は STIに限定されず、 After forming a trench 10a for isolation, a silicon dioxide film is buried in the trench 10a to form an element isolation insulating film 11. The element isolation structure is not limited to STI,
LuCuS(Local Oxidation of； silicon)であってもよい。  LuCuS (Local Oxidation of; silicon) may also be used.
[0030] 続いて、素子分離絶縁膜 11で画定されるシリコン基板 10のトランジスタ形成領域に 、例えばリン等の n型不純物をイオン注入し、 nゥエル 13を形成する。なお、そのィォ ン注入は、シリコン基板 10の表面に形成された不図示の熱酸ィ匕膜をスルー膜として 行われ、 nゥエル 13を形成した後にその熱酸ィ匕膜は除去される。  Subsequently, n-type impurities such as phosphorus are ion-implanted into a transistor formation region of the silicon substrate 10 defined by the element isolation insulating film 11 to form an n-well 13. The ion implantation is performed using a thermal oxide film (not shown) formed on the surface of the silicon substrate 10 as a through film, and after the n-well 13 is formed, the thermal oxide film is removed. .
[0031] その後に、シリコン基板 10の表面を熱酸ィ匕することにより厚さ約 1應の酸ィ匕シリコン 膜を形成し、それをバッファ層 12とする。 [0031] Thereafter, the surface of the silicon substrate 10 is subjected to thermal oxidation, so that the silicon oxide having a thickness of about 1 mm is obtained. A film is formed and used as a buffer layer 12.
[0032] 次に、図 3 (b)に示すように、基板温度を約 600度に維持しながら、 HKN(CH ) ) 、 Next, as shown in FIG. 3 (b), while maintaining the substrate temperature at about 600 ° C., HKN (CH)),
3 2 4 3 2 4
SiH(N(CH ) )、及び NOガスを反応ガスとする MOCVD(Metal Organic CVD)法により By MOCVD (Metal Organic CVD) method using SiH (N (CH)) and NO gas as reaction gas
3 2 3  3 2 3
、 ノ ッファ層 12の上にゲート絶縁膜 14として ΗβίΟΝ膜を厚さ約 4nmに形成する。そ の MOCVDで使用される H N(CH ) )と SiH(N(CH ) )は室温（20°C)で液体であるた  Then, a ββ film is formed as a gate insulating film 14 on the notch layer 12 to a thickness of about 4 nm. H N (CH)) and SiH (N (CH)) used in MOCVD are liquid at room temperature (20 ° C).
3 2 4 3 2 3  3 2 4 3 2 3
め、窒素でパブリングした後、窒素等のキャリアガスと共にシリコン基板 10の上方に 導入される。そのキャリアガスと NOガスのそれぞれの流量は特に限定されないが、本 実施形態ではキャリアガスの総流量を約 500sccmとし、 NOガスの流量を約 300sccm とする。更に、成膜雰囲気の圧力も特に限定されないが、本実施形態ではその圧力 を約 30Paとする。  Therefore, after publishing with nitrogen, it is introduced above the silicon substrate 10 together with a carrier gas such as nitrogen. The flow rates of the carrier gas and NO gas are not particularly limited, but in this embodiment, the total flow rate of carrier gas is about 500 sccm, and the flow rate of NO gas is about 300 sccm. Further, the pressure of the film forming atmosphere is not particularly limited, but in this embodiment, the pressure is set to about 30 Pa.
[0033] 本実施形態では、そのようなゲート絶縁膜 14をシリコン基板 10の上に直接形成す るのではなぐノ ッファ層 12の上に形成するので、ゲート絶縁膜 14とシリコン基板 10 との間に界面準位が形成されず、良好な特性を持った MOSトランジスタが形成される  In the present embodiment, since such a gate insulating film 14 is formed on the notch layer 12 rather than directly on the silicon substrate 10, the gate insulating film 14 and the silicon substrate 10 are not formed. Interfacial states are not formed between them, and MOS transistors with good characteristics are formed
[0034] また、ゲート絶縁膜 14は、絶縁性金属酸ィ匕膜であれば ΗβίΟΝ膜に限定されな 、。 In addition, the gate insulating film 14 is not limited to a ββ film as long as it is an insulating metal oxide film.
そのような絶縁性金属酸ィ匕膜としては、 ΗβίΟΝ膜の他に、 ZrSiON膜、 AlSiON膜、 TaSiON膜、 TiSiON膜、及び YSiON膜がある。これらの膜のうち、 TaSiON膜は、液体 材料である TPE(Tantalum Pent ethoxyd: Ta(OC H ) )を窒素でパブリングしたガスを  Examples of such an insulating metal oxide film include a ZrSiON film, an AlSiON film, a TaSiON film, a TiSiON film, and a YSiON film in addition to the ββ film. Among these films, the TaSiON film is a gas obtained by publishing TPE (Tantalum Pent ethoxyd: Ta (OC H)), which is a liquid material, with nitrogen.
2 5 5  2 5 5
反応ガスとして形成され得る。また、これ以外の絶縁性金属酸化膜を成膜するガスと しては、既述の H N(CH ) )の Η¾それぞれの膜の金属元素で置換した材料を窒素  It can be formed as a reaction gas. In addition, as a gas for forming an insulating metal oxide film other than this, a material obtained by substituting a metal element of each film of H N (CH 3) described above with nitrogen is used.
3 2 4  3 2 4
でパブリングしたものが使用される。  The one published with is used.
[0035] なお、本明細書における ΗβίΟΝ膜は、化学量論的な膜である必要はなぐ Hf、 Si、 O、及び Nの原子数比が 1:1:1： 1力 変動して 、ても構わな 、。  [0035] Note that the ββ film in this specification does not have to be a stoichiometric film, and the atomic ratio of Hf, Si, O, and N varies by 1: 1: 1: 1. It ’s okay.
[0036] その後に、窒素雰囲気中で基板温度を 800°C、処理時間を 30秒とする熱処理をゲ ート絶縁膜 14に対して施し、このゲート絶縁膜 14を構成する ΗβίΟΝを焼結させる。 このような熱処理は、 PDA(Post Deposition Anneal)とも呼ばれる。  [0036] Thereafter, the gate insulating film 14 is subjected to a heat treatment in a nitrogen atmosphere at a substrate temperature of 800 ° C and a processing time of 30 seconds, and the βΟΝ constituting the gate insulating film 14 is sintered. . Such heat treatment is also called PDA (Post Deposition Anneal).
[0037] 次に、図 4 (a)に示す断面構造を得るまでの工程について説明する。  [0037] Next, steps required until a sectional structure shown in FIG.
[0038] まず、基板温度を 600°C、圧力を 27Pa、シラン（SiH )の流量を 120sccmとする条件 を採用し、減圧 CVD法によりゲート絶縁膜 14の上にポリシリコン膜を厚さ約 110應に 形成して、それを犠牲膜 15とする。 [0038] First, the substrate temperature is 600 ° C, the pressure is 27 Pa, and the flow rate of silane (SiH) is 120 sccm. Then, a polysilicon film is formed on the gate insulating film 14 to a thickness of about 110 by a low pressure CVD method, and this is used as the sacrificial film 15.
[0039] 犠牲膜 15は、シリコンを含む膜であればポリシリコン膜に限定されない。そのような 膜としては、ポリシリコン膜の他に、アモルファスシリコン膜、シリサイド膜、及びシリケ ート膜等がある。これらのうち、アモルファスシリコン膜は、シランやジシラン (Si H )等 The sacrificial film 15 is not limited to a polysilicon film as long as it is a film containing silicon. Examples of such a film include an amorphous silicon film, a silicide film, and a silicate film in addition to the polysilicon film. Of these, amorphous silicon films are silane, disilane (SiH), etc.
2 6 を反応ガスとするプラズマ CVD法により形成される。また、シリサイド膜は、コバルト等 の高融点金属のターゲットと、シリコンのターゲットとをシリコン基板 10の上方に別々 に配置し、 Ar等のスパッタガスでこれらのターゲット表面を叩き、気相中やゲート絶縁 膜 14上で高融点金属とシリコンとを反応させることにより形成され得る。更に、シリケ ート膜は、液体材料であるトリジメチルァミノハイド口シリコン (SiH(N(CH )；) )をバブリ  It is formed by plasma CVD using 2 6 as a reactive gas. In addition, the silicide film has a target of a refractory metal such as cobalt and a silicon target separately disposed above the silicon substrate 10 and strikes the surface of these targets with a sputtering gas such as Ar, in the gas phase or in the gate. It can be formed by reacting a refractory metal and silicon on the insulating film 14. Furthermore, the silicate film is made of a liquid material such as tridimethylamino hydride silicon (SiH (N (CH);)).
3 2 3 ング等で気化して得られたガスを反応ガスとする CVD法により形成される。  It is formed by the CVD method using the gas obtained by vaporization with 3 2 3
[0040] ところで、ゲート絶縁膜 14の表面付近の Hf原子には、周りの 0元素、 Si元素、及び N 元素等との結合が弱い不安定なものが存在する。このように不安定な Hf原子は、点 線円内に示すように、ゲート絶縁膜 14から離れて犠牲膜 15の中に容易に拡散し、犠 牲膜 15の中で Hf-Si結合を形成する。そのため、犠牲膜 15を形成した後では、不安 定な H源子がゲート絶縁膜 14の表層部分力も除去されることになる。 [0040] Incidentally, some Hf atoms in the vicinity of the surface of the gate insulating film 14 are unstable and have weak bonds with surrounding 0 elements, Si elements, N elements, and the like. Such unstable Hf atoms are easily diffused into the sacrificial film 15 away from the gate insulating film 14 and form Hf-Si bonds in the sacrificial film 15 as shown in the dotted circle. To do. Therefore, after the sacrificial film 15 is formed, the unstable H source element also removes the surface layer partial force of the gate insulating film 14.
[0041] 但し、このように単に犠牲膜 15を形成しただけでは、不安定な Hf原子がゲート絶縁 膜 14中に未だ残存する可能性がある。 However, if the sacrificial film 15 is simply formed in this way, unstable Hf atoms may still remain in the gate insulating film 14.
[0042] そこで、本実施形態では、そのような H源子をなるベく多く取り除くため、犠牲膜 15 に対して熱処理を施し、熱エネルギによって Hf原子の犠牲膜 15への拡散を促進する 。その熱処理は、例えば窒素雰囲気中で基板温度を 800°C、処理時間を 30秒とす る条件で行われる。 Therefore, in this embodiment, in order to remove as many H source elements as possible, the sacrificial film 15 is subjected to heat treatment to promote the diffusion of Hf atoms into the sacrificial film 15 by thermal energy. The heat treatment is performed, for example, in a nitrogen atmosphere under conditions where the substrate temperature is 800 ° C. and the processing time is 30 seconds.
[0043] この熱処理の結果、周囲の元素との結合が弱い状態でゲート絶縁膜 14に残存して いた大部分の Hf元素は犠牲膜 15に吸収されるので、ゲート絶縁膜 14には、周囲と 強く結合した安定的な Hf元素のみが残ることになる。  [0043] As a result of this heat treatment, most of the Hf element remaining in the gate insulating film 14 in a state where the bond with the surrounding elements is weak is absorbed by the sacrificial film 15, so that the gate insulating film 14 Only the stable Hf element, which is strongly bonded, remains.
[0044] 次に、図 4 (b)に示す断面構造を得るまでの工程について説明する。 [0044] Next, steps required until a sectional structure shown in FIG.
[0045] まず、フッ酸を水で 1： 200 (体積比）に希釈した室温のフッ酸溶液に犠牲膜 15を約 1分間だけ曝し、犠牲膜 15の表面に形成されているシリコンの自然酸化膜を除去す る。次いで、犠牲膜 15の表面に残存するフッ酸を除去するために、犠牲膜 15を室温 の純水中に約 10分間浸して洗浄する。 [0045] First, the sacrificial film 15 is exposed to a hydrofluoric acid solution at room temperature diluted 1: 200 (volume ratio) with water for about 1 minute to naturally oxidize silicon formed on the surface of the sacrificial film 15. Remove the membrane The Next, in order to remove the hydrofluoric acid remaining on the surface of the sacrificial film 15, the sacrificial film 15 is immersed in pure water at room temperature for about 10 minutes for cleaning.
[0046] その後、既述のように H源子を吸収した犠牲膜 15をエッチング液中に浸漬し、その 犠牲膜 15を選択的にウエットエッチングしてゲート絶縁膜 14の上から除去する。この とき使用されるエッチング液は、ゲート絶縁膜 14のエッチレートが犠牲膜 15のエッチ レートよりも低くなるエッチング液であれば特に限定されない。本実施形態では、その ようなエッチング液として、 TMAH(Tetramethyl ammonium nydr oxide: (N(Cri ) )OH-ar Thereafter, as described above, the sacrificial film 15 that has absorbed the H source element is immersed in an etching solution, and the sacrificial film 15 is selectively wet-etched to be removed from the gate insulating film 14. The etchant used at this time is not particularly limited as long as the etchant of the gate insulating film 14 is lower than the etch rate of the sacrificial film 15. In this embodiment, TMAH (Tetramethyl ammonium nydr oxide: (N (Cri))) OH-ar is used as such an etchant.
3 4 水に 5wt%の濃度で溶解させてなる溶液を使用する。  3 4 Use a solution dissolved in water at a concentration of 5 wt%.
[0047] 図 7は、液温力 0°Cの TMAH溶液をエッチング液として使用した場合における犠牲 膜 15の残厚と浸漬時間との関係を示すグラフである。これに示されるように、元々 11 Onmの厚さに形成されて!、た犠牲膜 15は、約 15分後には略全てエッチングされるこ とになる。 FIG. 7 is a graph showing the relationship between the remaining thickness of the sacrificial film 15 and the immersion time when a TMAH solution having a liquid temperature of 0 ° C. is used as an etching solution. As shown in the figure, the sacrificial film 15 originally formed with a thickness of 11 Onm is almost etched after about 15 minutes.
[0048] そこで、本実施形態では、 TMAH溶液の液温を 40°Cにし、犠牲膜 15が 15分だけ オーバーエッチングとなるようにエッチング時間を 30分に設定して、 TMAH溶液で犠 牲膜 15をエッチングして完全に除去する  Therefore, in this embodiment, the liquid temperature of the TMAH solution is set to 40 ° C., the etching time is set to 30 minutes so that the sacrificial film 15 is over-etched for 15 minutes, and the sacrificial film is formed using the TMAH solution. Etch 15 to remove completely
なお、エッチング液としては、上記の TMAH溶液の他に、 NH OHを C H OHに溶解  In addition to the above TMAH solution, NH OH is dissolved in C H OH as the etchant.
4 2 5 させてなる溶液ちある。  4 2 5 There is a solution made up of.
[0049] また、このウエットエッチングの前に、犠牲膜 15の表面の自然酸化膜をフッ酸溶液 で予め除去しておいたので、犠牲膜 15のウエットエッチングは、自然酸ィ匕膜で妨害さ れずにスムーズに進行する。  [0049] Further, since the natural oxide film on the surface of the sacrificial film 15 was previously removed with a hydrofluoric acid solution before the wet etching, the wet etching of the sacrificial film 15 was hindered by the natural acid film. Proceed smoothly without any problems.
[0050] このように犠牲膜 15をエッチングすると、下地のゲート絶縁膜 14から犠牲膜 15の 中に移動した結合力の弱い Hf原子も一緒に除去されるので、ゲート絶縁膜 14の表 層には、周囲の元素と強く結合した H源子のみが残ることになる。  [0050] When the sacrificial film 15 is etched in this way, the weakly bonded Hf atoms that have moved from the underlying gate insulating film 14 into the sacrificial film 15 are also removed, so that the surface layer of the gate insulating film 14 is removed. Will leave only the H source, which is strongly bound to the surrounding elements.
[0051] 次いで、露出したゲート絶縁膜 14の表面を室温で約 10分間だけ水洗し、ゲート絶 縁膜 14上に残る TMAH溶液を洗 、流す。  [0051] Next, the exposed surface of the gate insulating film 14 is washed with water for about 10 minutes at room temperature, and the TMAH solution remaining on the gate insulating film 14 is washed and poured.
[0052] また、ゲート絶縁膜 14上に Hf等の金属化合物が残存すると汚染の原因になるので 、ゲート絶縁膜 14を沸騰した SC2溶液に約 10分間浸し、その表面の金属化合物を 完全にエッチングして除去する。なお、このエッチングで使用される SC2溶液は、塩酸 、過酸化水素、及び純水を所定の割合で混合させてなる溶液である。 [0052] Further, if a metal compound such as Hf remains on the gate insulating film 14, it causes contamination. Therefore, the gate insulating film 14 is immersed in a boiling SC2 solution for about 10 minutes, and the metal compound on the surface is completely etched. And remove. The SC2 solution used in this etching is hydrochloric acid. , Hydrogen peroxide, and pure water mixed at a predetermined ratio.
[0053] その後に、室温においてゲート絶縁膜 14を約 10分間水洗して SC2溶液を洗い流 すことにより、上記した一連のウエットエッチングを終了する。  [0053] Thereafter, the gate insulating film 14 is washed with water at room temperature for about 10 minutes to wash away the SC2 solution, thereby completing the series of wet etching described above.
[0054] 次に、図 5 (a)に示すように、シランを反応ガスとする減圧 CVD法を用いて、ゲート 絶縁膜 14の上にポリシリコン膜を厚さ約 100應に形成し、それをゲート電極用導電 膜 16とする。このときの成膜条件としては、例えば、基板温度 600°C、圧力 27Pa、及 びシラン流量 120sccmが採用される。  Next, as shown in FIG. 5 (a), a polysilicon film is formed on the gate insulating film 14 to a thickness of about 100 using a low pressure CVD method using silane as a reaction gas. Is a conductive film 16 for a gate electrode. As film formation conditions at this time, for example, a substrate temperature of 600 ° C., a pressure of 27 Pa, and a silane flow rate of 120 sccm are employed.
[0055] また、ゲート電極用導電膜 16は、シリコンを含有する導電性材料であれば特に限 定されず、アモルファスシリコン膜であってもよい。  The conductive film 16 for gate electrode is not particularly limited as long as it is a conductive material containing silicon, and may be an amorphous silicon film.
[0056] このとき、ゲート絶縁膜 14の表層部分に存在していた結合の弱い Hf原子は、犠牲 膜 15と一緒に予め除去されている。従って、上記のようにゲート電極用導電膜 16を ゲート絶縁膜 14の上に形成しても、ゲート絶縁膜 14に残る H源子は周囲の原子と強 固に結合しているので、その H源子はゲート電極用導電膜 16に拡散し難くなる。そ の結果、点線円内に示されるように、ゲート電極用導電膜 16は実質的にはシリコン原 子のみで構成され、 H源子のような金属原子はそのゲート用導電膜 16に殆ど存在し ない。  At this time, the weakly bonded Hf atoms present in the surface layer portion of the gate insulating film 14 are removed together with the sacrificial film 15 in advance. Therefore, even if the gate electrode conductive film 16 is formed on the gate insulating film 14 as described above, the H source element remaining in the gate insulating film 14 is strongly bonded to surrounding atoms. The source element is difficult to diffuse into the gate electrode conductive film 16. As a result, as shown in the dotted circle, the gate electrode conductive film 16 is substantially composed of only silicon atoms, and metal atoms such as H source elements are almost present in the gate conductive film 16. do not do.
[0057] 次に、図 5 (b)に示す断面構造を得るまでの工程について説明する。  [0057] Next, steps required until a sectional structure shown in FIG.
[0058] まず、フォトリソグラフィによりゲート電極用導電膜 16をパターユングしてゲート電極 16aとする。そのパター-ングでは、ゲート電極 16aの下のゲート絶縁膜 14とバッファ 層 12もエッチングされてゲート電極形状にパターユングされる。  First, the gate electrode conductive film 16 is patterned by photolithography to form a gate electrode 16a. In the patterning, the gate insulating film 14 and the buffer layer 12 under the gate electrode 16a are also etched and patterned into a gate electrode shape.
[0059] 続いて、このゲート電極 16aをマスクにしながら、ボロン等の p型不純物をシリコン基 板 10に形成し、 p型ソース Zドレインエクステンション 18を形成する。  Subsequently, using the gate electrode 16a as a mask, a p-type impurity such as boron is formed on the silicon substrate 10 to form a p-type source Z drain extension 18.
[0060] 次 、で、図 6 (a)に示すように、二酸ィ匕シリコン膜を全面に形成してそれをエッチバ ックすること〖こより、ゲート電極 16aの横に絶縁性サイドウォール 19として残す。そして 、この絶縁性サイドウォール 19をマスクにするイオン注入により、ゲート電極 16aの側 方のシリコン基板 10にボロン等の p型不純物を注入して、 p型ソース Zドレイン領域 2 0を形成する。  Next, as shown in FIG. 6 (a), a silicon dioxide film is formed on the entire surface and etched back so that an insulating sidewall 19 is formed beside the gate electrode 16a. Leave as. Then, a p-type impurity such as boron is implanted into the silicon substrate 10 on the side of the gate electrode 16a by ion implantation using the insulating sidewall 19 as a mask to form the p-type source Z drain region 20.
[0061] このとき、ゲート電極 16aにもボロンが注入される力 ゲート絶縁膜 14を構成する ΗβίΟΝ膜中の窒素により、ボロンがゲート絶縁膜 14の下のシリコン基板 10に突き抜 けるのを防止でき、突き抜けた窒素に起因してチャネルの電気的特性が劣化するの を抑制することができる。但し、このような利点が不要の場合や、 η型 MOSトランジスタ のようにゲート電極にボロンを注入しない場合には、ゲート絶縁膜 14に窒素を含有さ せる必要は無ぐ例えば ΗβίΟをゲート絶縁膜 14としてもよい。 At this time, a force for injecting boron also into the gate electrode 16a constitutes the gate insulating film 14. The nitrogen in the film can prevent boron from penetrating into the silicon substrate 10 under the gate insulating film 14, and can suppress the deterioration of the electrical characteristics of the channel due to the penetrating nitrogen. . However, when such advantages are not required or when boron is not implanted into the gate electrode as in the η-type MOS transistor, it is not necessary to contain nitrogen in the gate insulating film 14. It may be 14.
[0062] 続、て、図 6 (b)に示すように、スパッタ法によりコバルト膜を全面に形成した後、そ のコノ レト膜に対して熱処理を行うことにより、コバルトとシリコンとを反応させ、 p型ソ ース Zドレイン領域 20の表層にコバルトシリサイド層 22を形成する。そのコバルトシリ サイド層 22は、ゲート電極 16aの表層にも形成され、それによりゲート電極 16aはポリ サイド構造となる。 Subsequently, as shown in FIG. 6B, after a cobalt film is formed on the entire surface by a sputtering method, the cobalt film is subjected to a heat treatment to react cobalt and silicon. Then, a cobalt silicide layer 22 is formed on the surface layer of the p-type source Z drain region 20. The cobalt silicide layer 22 is also formed on the surface layer of the gate electrode 16a, whereby the gate electrode 16a has a polycide structure.
[0063] その後に、素子分離絶縁膜 11等の上で未反応となって 、るコバルト膜をウエットェ ツチングして除去する。  [0063] Thereafter, the cobalt film that has not reacted on the element isolation insulating film 11 and the like is removed by wet etching.
[0064] ここまでの工程により、 p型 MOSトランジスタ Trの基本構造が完成したことになる。こ の後は、このトランジスタ Trを覆う一層目の層間絶縁膜を形成し、 p型ソース Zドレイ ン領域 20と電気的に接続される導電性プラグをその層間絶縁膜に形成する工程に 移るが、その詳細については省略する。  The basic structure of the p-type MOS transistor Tr is completed through the steps so far. Thereafter, the process proceeds to a process of forming a first interlayer insulating film covering the transistor Tr and forming a conductive plug electrically connected to the p-type source Z drain region 20 in the interlayer insulating film. The details are omitted.
[0065] 以上説明した本実施形態によれば、図 4 (a)で説明したように、ゲート絶縁膜 14の 表層付近で周囲の原子と弱く結合している H源子を犠牲膜 15に吸収し、周囲と強く 結合している Hf原子のみをゲート絶縁膜 14の表層に残すようにした。従って、図 5 (a )の工程でゲート絶縁膜 14上にゲート電極用導電膜 16を形成しても、ゲート絶縁膜 14の表層の H源子がゲート用導電膜 16に拡散し難くなるので、ゲート電極 16aに拡 散した Hf原子に伴うフェルミレベルピンユングを抑制できる。その結果、トランジスタお の閾値電圧の高電圧化を避けることができ、トランジスタ Trで消費電力が増大するの を防ぐことが可能となる。  According to the present embodiment described above, as described with reference to FIG. 4A, the H source element that is weakly bonded to surrounding atoms in the vicinity of the surface layer of the gate insulating film 14 is absorbed by the sacrificial film 15. Only the Hf atoms that are strongly bonded to the surroundings are left on the surface layer of the gate insulating film 14. Therefore, even if the gate electrode conductive film 16 is formed on the gate insulating film 14 in the step of FIG. 5A, the H source layer on the surface of the gate insulating film 14 is difficult to diffuse into the gate conductive film 16. In addition, Fermi level pinning associated with Hf atoms diffused in the gate electrode 16a can be suppressed. As a result, it is possible to avoid an increase in the threshold voltage of the transistor and to prevent an increase in power consumption in the transistor Tr.
[0066] しカゝも、犠牲膜 15に対して熱処理を施すことにより、ゲート絶縁膜 14から犠牲膜 15 への Hf原子の拡散を促進したので、ゲート絶縁膜 14の表層に存在する不安定な Hf 原子を確実に犠牲膜 15に吸収させることができ、上記のフェルミレベルピンユングを 効果的に防止することができる。 [0067] また、本願発明者が行ったシミュレーションによれば、フェルミレベルピンユングは、 ゲート絶縁膜 14力もゲート電極 16aに拡散する Hf原子の単位面積あたりの個数を 1 X 1012 (cnf 2)個以下にすることで、効果的に抑制できることが明ら力となった。 [0066] Shika also promoted the diffusion of Hf atoms from the gate insulating film 14 to the sacrificial film 15 by performing a heat treatment on the sacrificial film 15, so that the instability existing on the surface layer of the gate insulating film 14 Thus, the Hf atoms can be surely absorbed by the sacrificial film 15, and the above Fermi level pinning can be effectively prevented. [0067] Further, according to the simulation conducted by the inventor of the present application, Fermi level pinning indicates that the number of Hf atoms per unit area in which the gate insulating film 14 force also diffuses into the gate electrode 16a is 1 X 10 12 (cnf 2 ) It became clear that it was possible to effectively suppress the number of pieces or less.
[0068] 図 8は、上記のようにして作成された MOSトランジスタ Trの CVカーブである。その CVカーブは、ゲート一基板間容量 Cとゲート電圧 Vgとの関係を示すカーブであり、ゲ ート電極 16aの平面サイズ力 ¾0 m X 80 mの場合に得られたものである。なお、同 図では、比較例として、図 1で作成したトランジスタ Trの CVカーブも併記してある。そ  FIG. 8 is a CV curve of the MOS transistor Tr created as described above. The CV curve is a curve showing the relationship between the gate-to-substrate capacitance C and the gate voltage Vg, and was obtained when the planar size force of the gate electrode 16a is ¾0 m × 80 m. In the figure, the CV curve of the transistor Tr created in Fig. 1 is also shown as a comparative example. So
0  0
の比較例に係るトランジスタ Trは、本実施形態のような犠牲膜 15を形成せずに、ゲー ト絶縁膜 3の上にポリシリコンのゲート電極 4を直接形成して得られたものである。  The transistor Tr according to the comparative example is obtained by directly forming the polysilicon gate electrode 4 on the gate insulating film 3 without forming the sacrificial film 15 as in the present embodiment.
[0069] 同図に示されるように、本実施形態に係る CVカーブは、比較例と比べてゲート電圧 Vgの +側にシフトしている。そして、本実施形態と比較例のそれぞれのトランジスタに 同じゲート電圧を印カロした場合、本実施形態における容量 Cの方が比較例よりも小さ くなる。このことは、本実施形態では、ゲート電極 16aとゲート絶縁膜 14の界面に残 存する不安定な Hf原子が減少し、その Hf原子に起因する容量が低減されて 、ること を示している。 [0069] As shown in the figure, the CV curve according to the present embodiment is shifted to the + side of the gate voltage Vg compared to the comparative example. When the same gate voltage is applied to the transistors of this embodiment and the comparative example, the capacitance C in this embodiment is smaller than that of the comparative example. This indicates that, in the present embodiment, unstable Hf atoms remaining at the interface between the gate electrode 16a and the gate insulating film 14 are reduced, and the capacitance caused by the Hf atoms is reduced.
[0070] また、図 9は、図 8の比較例と本実施形態のそれぞれのフラットバンド電圧 Vl のシフ ト量 AVl を算出して得られたグラフである。なお、シフト量 Δ Vl の基準は、上記した 不安定な H源子が存在しない理想的な場合のフラットバンド電圧である。  FIG. 9 is a graph obtained by calculating the shift amount AVl of the flat band voltage Vl of each of the comparative example of FIG. 8 and the present embodiment. The standard of the shift amount Δ Vl is the flat band voltage in the ideal case where there is no unstable H source.
[0071] 図 9に示されるように、比較例ではシフト量 AVl が約—0. 72Vであるのに対し、本 実施形態のシフト量 Δ Vl は約 0. 67Vであり比較例よりも 0に近い。フラットバンド電 圧は、ゲート電極 16aとゲート絶縁膜 14の界面に残存する不安定な Hf原子が多い程 高くなるので、図 9の結果より、本実施形態ではそのような H源子が低減されることが 明らかとなった。  As shown in FIG. 9, in the comparative example, the shift amount AVl is about −0.72 V, whereas the shift amount ΔVl in this embodiment is about 0.67 V, which is 0 compared to the comparative example. close. Since the flat band voltage increases as the number of unstable Hf atoms remaining at the interface between the gate electrode 16a and the gate insulating film 14 increases, the result of FIG. 9 indicates that such H source elements are reduced in this embodiment. It became clear that
[0072] 上記した図 8及び図 9の調査結果より、本実施形態で作製した MOSトランジスタ TR では、フェルミレベルピンユングが抑制されることが実際に確認された。  [0072] From the above investigation results of FIGS. 8 and 9, it was actually confirmed that the Fermi level pinning is suppressed in the MOS transistor TR fabricated in this embodiment.
[0073] 以上、本発明の実施の形態について詳細に説明したが、本発明は上記実施形態 に限定されない。例えば、上記では p型 MOSトランジスタ Trを作製した力 これに代え て n型 MOSトランジスタを形成してもよ!/、。 [0074] 本発明によれば、ゲート絶縁膜となる絶縁性金属酸ィ匕膜の表層に存在する不安定 な金属原子を犠牲膜に吸収させるようにしたので、その金属原子に起因するフェルミ レベルピン-ングを抑制することができる。これにより、 MOSトランジスタの閾値電圧の 高電圧化を防ぐことができ、ひ 、ては MOSトランジスタにお 、て消費電力が増大する のを防止することができる。 [0073] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments. For example, in the above, the force that produced the p-type MOS transistor Tr. Alternatively, an n-type MOS transistor may be formed! /. [0074] According to the present invention, the unstable metal atoms existing on the surface layer of the insulating metal oxide film serving as the gate insulating film are absorbed by the sacrificial film, so that the Fermi level caused by the metal atoms is absorbed. Pinning can be suppressed. As a result, the threshold voltage of the MOS transistor can be prevented from increasing, and the power consumption of the MOS transistor can be prevented from increasing.
[0075] 以下に、本発明の特徴を付記する。  [0075] The features of the present invention will be described below.
[0076] (付記 1) 半導体基板の上に、ゲート絶縁膜として絶縁性金属酸化膜を形成する 工程と、  (Supplementary Note 1) A step of forming an insulating metal oxide film as a gate insulating film on a semiconductor substrate;
前記ゲート絶縁膜の上に犠牲膜を形成する工程と、  Forming a sacrificial film on the gate insulating film;
前記犠牲膜を前記ゲート絶縁膜の上から除去する工程と、  Removing the sacrificial film from above the gate insulating film;
前記犠牲膜を除去した後、前記ゲート絶縁膜の上にゲート電極用導電膜を形成す る工程と、  Forming a conductive film for a gate electrode on the gate insulating film after removing the sacrificial film;
前記ゲート電極用導電膜をパターユングしてゲート電極にする工程と、 前記ゲート電極の側方の前記半導体基板に不純物を注入してソース Zドレイン領 域を形成し、該ソース Zドレイン領域、前記ゲート電極、及び前記ゲート絶縁膜で Patterning the gate electrode conductive film to form a gate electrode; and implanting impurities into the semiconductor substrate lateral to the gate electrode to form a source Z drain region, the source Z drain region, A gate electrode and the gate insulating film;
MOSトランジスタを構成する工程と、 A step of forming a MOS transistor;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
(付記 2) 前記犠牲膜を形成した後、該犠牲膜を加熱する工程を有することを特徴 とする付記 1に記載の半導体装置の製造方法。  (Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, further comprising a step of heating the sacrificial film after the sacrificial film is formed.
(付記 3) 前記犠牲膜として、アモルファスシリコン膜、ポリシリコン膜、シリサイド膜 、及びシリケート膜の!ヽずれかを形成することを特徴とする付記 1に記載の半導体装 置の製造方法。  (Supplementary note 3) The method of manufacturing a semiconductor device according to supplementary note 1, wherein as the sacrificial film, any one of an amorphous silicon film, a polysilicon film, a silicide film, and a silicate film is formed.
(付記 4) 前記絶縁性金属酸ィ匕膜として、 Hf、 Zr、 Ta、 Ti、及び Yのいずれかの酸ィ匕 物よりなる絶縁膜を形成することを特徴とする付記 1に記載の半導体装置の製造方 法。  (Supplementary note 4) The semiconductor according to supplementary note 1, wherein an insulating film made of any one of Hf, Zr, Ta, Ti, and Y is formed as the insulating metal oxide film. How to make the device.
(付記 5) 前記犠牲膜を除去する工程は、前記ゲート絶縁膜のエッチレートが前記 犠牲膜のエッチレートよりも低くなるエッチング液を用いるウエットエッチングにより行 われることを特徴とする付記 1に記載の半導体装置の製造方法。 (付記 6) 前記エッチング液として TMAH(Tetramethyl ammonium hydroxide)溶液を 使用することを特徴とする付記 5に記載の半導体装置の製造方法。 (Supplementary note 5) The step of removing the sacrificial film is performed by wet etching using an etchant in which an etch rate of the gate insulating film is lower than an etch rate of the sacrificial film. A method for manufacturing a semiconductor device. (Supplementary note 6) The method of manufacturing a semiconductor device according to supplementary note 5, wherein a TMAH (Tetramethyl ammonium hydroxide) solution is used as the etching solution.
(付記 7) 前記エッチング液として NH OH溶液を使用することを特徴とする付記 5に  (Supplementary note 7) In Supplementary note 5, characterized in that NH OH solution is used as the etching solution
4  Four
記載の半導体装置の製造方法。  The manufacturing method of the semiconductor device of description.
(付記 8) 前記ゲート電極用導電膜として、シリコンを含有する導電膜を形成するこ とを特徴とする付記 1に記載の半導体装置の製造方法。  (Supplementary note 8) The method for manufacturing a semiconductor device according to supplementary note 1, wherein a conductive film containing silicon is formed as the conductive film for the gate electrode.
(付記 9) 前記ゲート電極用導電膜としてポリシリコン膜を形成することを特徴とす る付記 8に記載の半導体装置の製造方法。  (Supplementary note 9) The method of manufacturing a semiconductor device according to supplementary note 8, wherein a polysilicon film is formed as the conductive film for the gate electrode.
[0077] (付記 10) 前記ゲート絶縁膜を形成する工程の前に、前記半導体基板の上にバッ ファ層を形成する工程を有し、前記バッファ層の上に前記ゲート絶縁膜を形成するこ とを特徴とする付記 1に記載の半導体装置の製造方法。 (Appendix 10) Before the step of forming the gate insulating film, the method includes a step of forming a buffer layer on the semiconductor substrate, and the gate insulating film is formed on the buffer layer. 2. The method for manufacturing a semiconductor device according to appendix 1, wherein:
[0078] (付記 11) 前記バッファ層を形成する工程は、前記半導体基板の表面を熱酸化し て酸ィ匕シリコン膜を形成することにより行われることを特徴とする付記 10に記載の半 導体装置の製造方法。 (Appendix 11) The semiconductor according to appendix 10, wherein the step of forming the buffer layer is performed by thermally oxidizing the surface of the semiconductor substrate to form an oxide silicon film. Device manufacturing method.
[0079] (付記 12) 半導体基板と、 [0079] (Appendix 12) A semiconductor substrate,
前記半導体基板の上に形成され、絶縁性金属酸ィ匕物で構成されるゲート絶縁膜と 前記ゲート絶縁膜の上に形成されたゲート電極と、  A gate insulating film formed on the semiconductor substrate and made of an insulating metal oxide; and a gate electrode formed on the gate insulating film;
前記ゲート電極の側方の前記半導体基板に形成され、前記ゲート絶縁膜と前記ゲ ート電極と共に MOSトランジスタを構成するソース Zドレイン領域とを有し、  A source Z drain region formed on the semiconductor substrate on the side of the gate electrode and constituting a MOS transistor together with the gate insulating film and the gate electrode;
前記ゲート絶縁膜から前記ゲート電極に拡散する前記絶縁性金属酸化物の金属 原子の単位面積あたりの個数が 1 X 1012 (cm— 2)個以下に低減されたことを特徴とする 半導体装置。 Wherein a the number per unit area of the metal atoms of the insulating metal oxide diffused into the gate electrode from the gate insulating film is reduced to 1 X 10 12 (cm- 2) or less.
(付記 13) 前記絶縁性金属酸化物は、 Hf、 Zr、 Ta、 Ti、及び Yのいずれかの酸ィ匕 物であることを特徴とする付記 12に記載の半導体装置。  (Supplementary note 13) The semiconductor device according to supplementary note 12, wherein the insulating metal oxide is any one of Hf, Zr, Ta, Ti, and Y.

Claims

請求の範囲 The scope of the claims
[1] 半導体基板の上に、ゲート絶縁膜として絶縁性金属酸化膜を形成する工程と、 前記ゲート絶縁膜の上に犠牲膜を形成する工程と、  [1] forming an insulating metal oxide film as a gate insulating film on a semiconductor substrate; forming a sacrificial film on the gate insulating film;
前記犠牲膜を前記ゲート絶縁膜の上から除去する工程と、  Removing the sacrificial film from above the gate insulating film;
前記犠牲膜を除去した後、前記ゲート絶縁膜の上にゲート電極用導電膜を形成す る工程と、  Forming a conductive film for a gate electrode on the gate insulating film after removing the sacrificial film;
前記ゲート電極用導電膜をパターユングしてゲート電極にする工程と、 前記ゲート電極の側方の前記半導体基板に不純物を注入してソース Zドレイン領 域を形成し、該ソース Zドレイン領域、前記ゲート電極、及び前記ゲート絶縁膜で Patterning the gate electrode conductive film to form a gate electrode; and implanting impurities into the semiconductor substrate lateral to the gate electrode to form a source Z drain region, the source Z drain region, A gate electrode and the gate insulating film;
MOSトランジスタを構成する工程と、 A step of forming a MOS transistor;
を有することを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
[2] 前記犠牲膜を形成した後、該犠牲膜を加熱する工程を有することを特徴とする請 求項 1に記載の半導体装置の製造方法。  [2] The method for manufacturing a semiconductor device according to claim 1, further comprising a step of heating the sacrificial film after the sacrificial film is formed.
[3] 前記犠牲膜として、アモルファスシリコン膜、ポリシリコン膜、シリサイド膜、及びシリ ケート膜のいずれかを形成することを特徴とする請求項 1に記載の半導体装置の製 造方法。 [3] The method for manufacturing a semiconductor device according to [1], wherein any one of an amorphous silicon film, a polysilicon film, a silicide film, and a silicate film is formed as the sacrificial film.
[4] 前記絶縁性金属酸ィ匕膜として、 Hf、 Zr、 Ta、 Ti、及び Yの 、ずれかの酸化物よりなる 絶縁膜を形成することを特徴とする請求項 1に記載の半導体装置の製造方法。  [4] The semiconductor device according to [1], wherein an insulating film made of any of oxides of Hf, Zr, Ta, Ti, and Y is formed as the insulating metal oxide film. Manufacturing method.
[5] 前記犠牲膜を除去する工程は、前記ゲート絶縁膜のエッチレートが前記犠牲膜の エッチレートよりも低くなるエッチング液を用いるウエットエッチングにより行われること を特徴とする請求項 1に記載の半導体装置の製造方法。 [5] The step of removing the sacrificial film is performed by wet etching using an etchant in which an etch rate of the gate insulating film is lower than an etch rate of the sacrificial film. A method for manufacturing a semiconductor device.
[6] 前記エッチング液として TMAH(Tetramethyl ammonium hydroxide)溶液を使用する ことを特徴とする請求項 5に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein a TMAH (Tetramethyl ammonium hydroxide) solution is used as the etching solution.
[7] 前記エッチング液として NH OH溶液を使用することを特徴とする請求項 5に記載の [7] The method according to claim 5, wherein an NH OH solution is used as the etching solution.
4  Four
半導体装置の製造方法。  A method for manufacturing a semiconductor device.
[8] 前記ゲート電極用導電膜として、シリコンを含有する導電膜を形成することを特徴と する請求項 1に記載の半導体装置の製造方法。 8. The method for manufacturing a semiconductor device according to claim 1, wherein a conductive film containing silicon is formed as the conductive film for the gate electrode.
[9] 前記ゲート電極用導電膜としてポリシリコン膜を形成することを特徴とする請求項 8 に記載の半導体装置の製造方法。 9. A polysilicon film is formed as the gate electrode conductive film. The manufacturing method of the semiconductor device as described in any one of.
[10] 前記ゲート絶縁膜を形成する工程の前に、前記半導体基板の上にバッファ層を形 成する工程を有し、前記バッファ層の上に前記ゲート絶縁膜を形成することを特徴と する請求項 1に記載の半導体装置の製造方法。  [10] The method includes forming a buffer layer on the semiconductor substrate before the step of forming the gate insulating film, and forming the gate insulating film on the buffer layer. The method for manufacturing a semiconductor device according to claim 1.
[11] 前記バッファ層を形成する工程は、前記半導体基板の表面を熱酸ィ匕して酸ィ匕シリ コン膜を形成することにより行われることを特徴とする請求項 10に記載の半導体装置 の製造方法。 11. The semiconductor device according to claim 10, wherein the step of forming the buffer layer is performed by thermally oxidizing the surface of the semiconductor substrate to form an acid silicon film. Manufacturing method.
[12] 半導体基板と、  [12] a semiconductor substrate;
前記半導体基板の上に形成され、絶縁性金属酸化物で構成されるゲート絶縁膜と 前記ゲート絶縁膜の上に形成されたゲート電極と、  A gate insulating film formed on the semiconductor substrate and made of an insulating metal oxide; and a gate electrode formed on the gate insulating film;
前記ゲート電極の側方の前記半導体基板に形成され、前記ゲート絶縁膜と前記ゲ ート電極と共に MOSトランジスタを構成するソース Zドレイン領域とを有し、  A source Z drain region formed on the semiconductor substrate on the side of the gate electrode and constituting a MOS transistor together with the gate insulating film and the gate electrode;
前記ゲート絶縁膜から前記ゲート電極に拡散する前記絶縁性金属酸化物の金属 原子の単位面積あたりの個数が 1 X 1012 (cm— 2)個以下に低減されたことを特徴とする 半導体装置。 Wherein a the number per unit area of the metal atoms of the insulating metal oxide diffused into the gate electrode from the gate insulating film is reduced to 1 X 10 12 (cm- 2) or less.
[13] 前記絶縁性金属酸化物は、 Hf、 Zr、 Ta、 Ti、及び Yの 、ずれかの酸ィ匕物であること を特徴とする付記 12に記載の半導体装置。  [13] The semiconductor device according to appendix 12, wherein the insulating metal oxide is any one of Hf, Zr, Ta, Ti, and Y.
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