WO2006070452A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
WO2006070452A1
WO2006070452A1 PCT/JP2004/019602 JP2004019602W WO2006070452A1 WO 2006070452 A1 WO2006070452 A1 WO 2006070452A1 JP 2004019602 W JP2004019602 W JP 2004019602W WO 2006070452 A1 WO2006070452 A1 WO 2006070452A1
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WO
WIPO (PCT)
Prior art keywords
plating
plating solution
forming
manufacturing
film
Prior art date
Application number
PCT/JP2004/019602
Other languages
French (fr)
Japanese (ja)
Inventor
Taku Kanaoka
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2004/019602 priority Critical patent/WO2006070452A1/en
Priority to JP2006550520A priority patent/JPWO2006070452A1/en
Publication of WO2006070452A1 publication Critical patent/WO2006070452A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00—Processes for servicing or operating cells for electrolytic coating
    • C25D21/12—Process control or regulation
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]

Definitions

  • the present invention relates to a semiconductor device manufacturing technology, and more particularly to a technology effective when applied to a CSP (Chip Size Package) technology that completes a packaging process by applying a wafer process.
  • CSP Chip Size Package
  • Patent Document 1 discloses a technique in which a plating treatment tank and a plating solution storage tank are provided, and a magnet is disposed in the plating solution storage tank. Specifically, the plating solution storage tank is divided into a first storage tank and a second storage tank, and the plating solution from the plating tank is poured into the weir provided in the first storage tank. And by placing the magnets that adsorb magnetic particles diagonally in the first storage tank, large magnetic particles of several millimeters, such as 100 m force, are adsorbed at the lower part of the magnet, while from 1 ⁇ m at the upper part of the magnet.
  • a corrosion-resistant resin such as polytetrafluoroethylene
  • Patent Document 2 discloses a device for removing magnetic sludge in a plating tank by a magnet installed in the plating tank, or for circulation of a plating tank. An apparatus in which a magnet is installed in a pipe portion is disclosed.
  • Patent Document 3 in a method for forming a nickel film, magnet particles are placed in an anode rod filled with nickel pellets to generate a positive pole force. A technique for adhering sludge to be adhered to magnet grains so that the sludge does not come out of the anode rod is disclosed.
  • Patent Document 4 discloses an apparatus in which a magnet for adsorbing magnetic particles is provided inside or outside a transport pipe for transporting a plating solution.
  • Patent Document 5 Japanese Patent Application Laid-Open No. 09-003694 (Patent Document 5) describes a lower part of a metal processing tank. Discloses a device for attaching to the bottom of a staking treatment tank using a magnet provided on the surface.
  • Patent Document 1 Japanese Patent Laid-Open No. 09-137229
  • Patent Document 2 Japanese Patent Laid-Open No. 05-306500
  • Patent Document 3 Japanese Patent Application Laid-Open No. 07-138799
  • Patent Document 4 Japanese Patent Laid-Open No. 06-220698
  • Patent Document 5 Japanese Patent Laid-Open No. 09-003694
  • Wafer Level CSP A technology that integrates the packaging process (post-process) and wafer process (pre-process) and completes packaging in the wafer state, the so-called Wafer Level CSP, applies the wafer process.
  • This is a technology for processing up to the packaging process. For this reason, there is an advantage that the number of steps can be greatly reduced as compared with the conventional method in which the semiconductor / cage process is performed for each semiconductor chip (hereinafter referred to as a chip) cut from a semiconductor wafer (hereinafter referred to as a wafer).
  • Wafer level CSP is also called a wafer process package (WPP).
  • the wafer level CSP can replace the wiring layer inside the CSP called an interposer, which converts the bonding pad pitch into the bump electrode pitch, with a rewiring layer formed on the wafer, reducing the number of processes. As well as the CSP manufacturing cost.
  • a rewiring that connects a bonding pad and a bump electrode is formed.
  • This rewiring is formed of a laminated film of a copper film and a nickel film, for example.
  • an electrolytic plating method is used to form the copper film and the nickel film.
  • an electrode made of nickel is used for the anode electrode (anode), and a wafer is placed on the force sword electrode (cathode). Then, the gap between the anode electrode and the cathode electrode is filled with the squeezing solution.
  • nickel atoms are also ionized into the anode electrode force and dissolved into the plating solution. And the melted nickel ions are connected to the force sword electrode A nickel film is formed on the wafer. In this way, a nickel film is formed on the wafer.
  • nickel atoms are dissolved as ions. Elution of ions occurs not only from the surface of the anode electrode but also from the inside. For this reason, as the anode electrode is used, the anode electrode becomes pumice and tends to collapse. Fine nickel particles (hereinafter referred to as “sludge”) are generated from the anode electrode due to the motive force of the plating solution jet and the change in current density. In other words, sludge is generated from the anode electrode simply by melting nickel atoms as ions. When this sludge adheres to the wafer, it causes an abnormal appearance (defective appearance), resulting in a decrease in product yield.
  • Patent Document 1 Japanese Patent Laid-Open No. 09-137299
  • a sludge is removed by arranging a magnet in the first storage tank. For this reason, it is necessary to increase the flow rate of the plating solution when forming a nickel film at the wafer level CSP. For this reason, a phenomenon occurs that the level of the plating solution in the first storage tank becomes high. In this case, there is a problem that sludge cannot be captured sufficiently at the top of the magnet.
  • Patent Document 2 Japanese Patent Laid-Open No. 05-306500
  • a magnet is arranged in a plating tank.
  • the force of forming a nickel film on the wafer When the magnet is placed in the processing bath, the thickness of the nickel film formed on the wafer varies due to the influence of the magnetic field. There is. In particular, when the plating tank is small, it is easily affected by the magnetic field.
  • Patent Document 3 magnet particles are put in an anode bar filled with nickel pellets.
  • the distance between the wafer and the positive electrode placed on the force sword electrode is short, there is a problem that the film thickness of the nickel film formed on the wafer varies under the influence of the magnetic field by the magnet.
  • Patent Document 4 a magnet for adsorbing magnetic particles is provided inside or outside a transport pipe for transporting a plating solution.
  • the sludge is very small and the flow rate of the fitting liquid is large in wafer level CSP.
  • Patent Document 5 Japanese Patent Application Laid-Open No. 09-003694 (Patent Document 5), a magnet is disposed at the lower part of the fitting processing tank. However, some sludge is very small, and there is a problem that it cannot be captured by the magnet installed at the bottom of the plating tank. In addition, when the magnetic force of the magnet is increased, the thickness of the nickel film formed on the wafer may be affected by the influence of the magnetic field.
  • An object of the present invention is to provide a technique capable of efficiently removing sludge present in a plating solution while preventing fluctuations in the thickness of a nickel film formed on a wafer. .
  • a method of manufacturing a semiconductor device is a method of manufacturing a semiconductor device that completes packaging in the state of a semiconductor wafer, and includes: ( a ) forming internal connection terminals on the semiconductor wafer; And (c) forming a rewiring that connects one end to the internal connection terminal, and (c) forming an external connection terminal that connects to the other end of the rewiring. (Bl) forming a nickel film using an electrolytic plating method, wherein the (bl) process is a tank separate from the plating process tank for forming the nickel film on the semiconductor wafer.
  • the plating solution is circulated between the plating solution tank, and the nickel film is attached to the plating solution while placing a magnet in the plating solution inflow portion, the plating solution outflow portion, and the surface layer portion of the plating solution. It forms in a processing tank, It is characterized by the above-mentioned.
  • It is a tank different from the plating treatment tank, and circulates the plating solution between the plating treatment tanks.
  • the plating solution inflow portion In the plating solution inflow portion, the plating solution outflow portion, and the surface layer portion of the plating solution of the plating solution storage tank. Since the magnet is arranged, it prevents the film thickness fluctuation of the nickel film formed on the wafer. However, sludge present in the plating solution can be efficiently removed.
  • FIG. 1 is a flowchart showing a manufacturing process of a wafer level CSP (WPP).
  • WPP wafer level CSP
  • FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device in the embodiment.
  • FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 2;
  • FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3;
  • FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 4;
  • FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5.
  • FIG. 7 is a partial cross-sectional view showing the configuration of the plating apparatus in the embodiment.
  • FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6;
  • FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8;
  • FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 9;
  • FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10;
  • FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11;
  • FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12;
  • FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13;
  • the number of elements when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly limited to a specific number when clearly indicated and in principle. Except in some cases, the number is not limited to the specific number, and may be a specific number or more.
  • FIG. 1 is a flowchart showing a manufacturing process of wafer level CSP (WPP).
  • WPP wafer level CSP
  • the wafer level CSP manufacturing process will be briefly described with reference to FIG.
  • a semiconductor element such as a metal insulator semiconductor field effect transistor (MISFET) is formed on a semiconductor substrate, and then one or more wirings are formed on the semiconductor element. Then, the uppermost layer wiring is formed to form a bonding pad as an internal connection terminal.
  • MISFET metal insulator semiconductor field effect transistor
  • a wafer test is performed (S102).
  • MISFETs formed on a semiconductor substrate are checked for threshold values and value voltages.
  • the rewiring is a wiring for connecting a bonding pad and a bump electrode described later, and is formed of a laminated film of a copper film and a nickel film, for example.
  • the feature of this embodiment is in the step of forming the nickel film by the electrolytic plating method, and details will be described later.
  • a probe test is performed (S103).
  • the probe is pressed against the bump land formed by rewiring to inspect the electrical characteristics of the semiconductor element.
  • the back surface of the semiconductor substrate is ground (S106).
  • bump electrodes are formed on the bump lands formed by rewiring (S107).
  • the appearance inspection is performed again (S108), and the subsequent process is performed (S109).
  • individual chip regions of the semiconductor substrate on which the bump electrodes are formed are cut into individual chips by dicing. Then, the cut chips are selected, and the non-defective products are stored in a tray and shipped.
  • a MISFET is formed on a semiconductor substrate (semiconductor wafer) 1, and one or more layers are formed on the MISFET. Form wiring.
  • an interlayer insulating film 2 is formed as shown in FIG.
  • the interlayer insulating film 2 is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD (Chemical Vapor D mark osition) method.
  • CVD Chemical Vapor D mark osition
  • a laminated film made of a titanium nitride film and an aluminum film is formed on the interlayer insulating film 2 by using, for example, a sputtering method. Then, the laminated film is patterned using photolithography technology and etching technology to form the uppermost layer wiring. Bonding pads 3 as internal connection terminals are also formed in the process of forming the uppermost layer wiring.
  • a silicon nitride film 4 is formed on the interlayer insulating film 2 including the bonding pad 3.
  • the silicon nitride film 4 can be formed using, for example, a CVD method.
  • a photosensitive polyimide resin film 5 is applied on the silicon nitride film 4.
  • the silicon nitride film 4 and the photosensitive polyimide resin film 5 form a passivation film (first insulating film).
  • the passivation film is a film provided to protect the semiconductor element and wiring formed inside in order to protect the mechanical stress and the intrusion force of impurities.
  • the photosensitive polyimide resin film 5 is patterned by subjecting the photosensitive polyimide resin film 5 to exposure / development treatment. Patterning is performed so as to open on the bonding pad 3. Then, using the patterned photosensitive polyimide resin film 5 as a mask, the underlying silicon nitride film 4 is etched. As a result, the opening 6 is formed on the bonding pad 3.
  • the seed layer 7 is formed on the photosensitive polyimide resin film 5 including the bonding pad 3.
  • the seed layer 7 is formed of, for example, a laminated film of a chromium (Cr) film and a copper (Cu) film, and can be formed using, for example, a sputtering method.
  • the seed layer 7 has a function as an electrode layer for growing a plated film described later.
  • FIG. 5 is a partial cross-sectional view showing a schematic configuration of a plating apparatus for forming a nickel film on the semiconductor substrate 1.
  • FIG. 7 is a partial cross-sectional view showing a schematic configuration of a plating apparatus for forming a nickel film on the semiconductor substrate 1.
  • the plating apparatus in the present embodiment has a plating treatment tank 20 and a mating liquid storage tank 21.
  • the plating tank 20 and the plating solution storage tank 21 are provided separately, and are connected to each other by a pipe 23 and a pipe 24 provided with a pump 22.
  • the plating treatment tank 20 is a tank for forming a nickel film on the semiconductor substrate 1, and the inside of the outer frame body 26 is filled with a fitting liquid 27.
  • a pipe 23 is provided at the bottom of the outer frame body 26, and the plating solution flows from the pipe 23 into the mating treatment tank 20.
  • An anode electrode (anode) 28 is provided on the bottom of the outer frame body 26.
  • the anode electrode 28 is composed mainly of nickel.
  • a cathode electrode (cathode) 29 is formed on the upper surface of the outer frame body 26, and the semiconductor substrate 1 is installed so as to be connected to the force sword electrode 29.
  • the semiconductor substrate 1 is disposed so as to face the anode electrode 28.
  • An anode back 30 is provided around the anode electrode 28.
  • the anode knock 30 is provided to prevent the nickel fine particles (sludge) coming out of the anode electrode from being diffused into the squeeze solution.
  • the plating solution 27 flowing into the plating tank 20 flows out of the plating tank 20 through the pipe 24.
  • the plating solution 27 flows from the pipe 24 into the outer frame 31 of the plating solution storage tank 21.
  • the plating solution 27 stored in the plating solution storage tank 21 flows out from the plating solution storage tank 21 through the pipe 23 to which the pump 22 is connected.
  • a weir 32 is provided at the inlet of the plating solution 27 of the plating solution storage tank 21. This weir 32 is provided to prevent bubbles from remaining in the plating solution 27 stored in the fitting solution storage tank 21. That is, the plating solution 27 flows into the plating solution storage tank 21 vigorously. At this time, bubbles are taken into the plating solution 27 stored in the plating solution storage tank 21.
  • plating solution A weir 32 is provided at the inlet of the storage tank 21 so that no bubbles remain inside the plating solution 27.
  • a plurality of magnets 33a to 33d are installed in the plating solution storage tank 21.
  • the magnets 33a to 33d are provided in the plating solution storage tank 21 as described above.
  • the anode electrode 28 of the plating bath 20 not only elutes as -eckerka S ions but also releases nickel fine particles (sludge). .
  • This sludge is prevented from scattering into the plating solution 27 by the anode back 30.
  • the anode back 30 cannot prevent fine sludge from scattering. For this reason, sludge is released into the plating solution 27.
  • This sludge is circulated through the plating tank 20 and the plating liquid storage tank 21 together with the plating liquid 27.
  • the magnets 33a to 33d are installed in the adhesive liquid 27 by utilizing the property that sludge made of nickel is adsorbed to the magnet. Thereby, since the sludge discharged to the plating solution 27 can be captured by the magnets 33a to 33d, the sludge can also be removed by the intermediate force of the plating solution 27.
  • the magnets 33a to 33d are provided not in the plating treatment tank 20 but in the plating solution storage tank 21 that is separated from the plating treatment tank 20. As a result, the film thickness variation due to the magnetic field of the nickel film formed on the semiconductor substrate 1 can be prevented.
  • magnets 33a to 33d are installed in the staking treatment tank 20, the magnets 33a to 33d and the semiconductor substrate 1 on which the nickel film is formed are brought close to each other. Then, since it becomes easy to be affected by the magnetic field by the magnets 33a-33d, the thickness of the nickel film formed on the semiconductor substrate 1 is likely to fluctuate.
  • magnets 33a-33d are provided in the plating solution storage tank 21 sufficiently separated from the plating processing tank 20 in which the semiconductor substrate 1 is installed. Therefore, sludge that does not change the thickness of the nickel film formed on the semiconductor substrate 1 can be removed.
  • the magnets 33a to 33d are installed at the following locations. That is, first, the magnet 33a is provided in the weir 32 which is the inlet (inflow part) of the fitting liquid storage tank 21. As a result, sludge flowing from the plating tank 20 can be sufficiently removed.
  • the magnet 33b is provided on the surface layer portion of the plating solution 27, fine sludge flowing through the surface portion of the plating solution 27 can be captured. Furthermore, by installing a magnet 33c near the outlet (outflow part) of the plating solution storage tank 21, it is possible to capture the sludge, which cannot be removed by the magnet 33a and the magnet 33b, before returning to the plating tank 20. it can. Thus, the sludge can be effectively removed by installing the magnets 33a-33c at the positions described above. In addition, by providing the magnet 33d in the stagnation region of the bottom of the plating solution 27, sludge that is relatively large and easily sinks can be captured. According to the present embodiment, the magnets 33a to 33d are installed to sufficiently remove sludge even when the plating solution 27 flows at a flow rate of 30 liters per minute to 50 liters per minute. Can do.
  • the magnets 33a to 33d installed in the plating solution storage tank 21 are covered with, for example, fluorine resin to prevent corrosion caused by contact with the plating solution 27.
  • the plating tank 20 connected to the plating solution storage tank 21 is a single force, and it may be connected to a plurality of plating tanks 20. .
  • sludge generated in the multiple plating tanks 20 can be removed by the magnets 33a to 33d provided in one plating solution storage tank 21. Therefore, the cost can be reduced as compared with the case where the magnets 33a to 33d are respectively installed in the plurality of plating tanks 20.
  • the plating apparatus in the present embodiment is configured as described above, and the operation will be described below.
  • the rewiring forming surface of the semiconductor substrate 1 is immersed in the solution 27.
  • the semiconductor substrate 1 is placed on the force sword electrode 29 so as to be in contact with each other.
  • a predetermined voltage is applied between the anode electrode 28 and the force sword electrode 29.
  • the nickel force constituting the anode electrode 29 is turned on and eluted. Move the eluted nickel ion fitting solution 27.
  • it is deposited on the semiconductor substrate 1 connected to the force sword electrode 29 and a nickel film 10 is formed on the copper film 9 as shown in FIG.
  • the seed layer 7 covered with the resist film 8 is removed by wet etching.
  • the surface of the rewiring is also etched at the same time. The thickness of the rewiring is much thicker than the thickness of the seed layer 7, so there is no problem. Absent.
  • a photosensitive polyimide resin film (second insulating film) 11 is formed on the upper part of the rewiring composed of the copper film 9 and the nickel film 10. Then, the photosensitive polyimide resin film 11 is exposed and developed to form an opening (second opening) 12 in the bump electrode formation region.
  • a gold (Au) film 13 is formed on the rewiring (bump land) exposed from the opening 12 using an electroless plating method. Then, a probe inspection is performed by pressing a probe (probe) on the rewiring exposed from the opening 12. Next, after the appearance inspection is performed, the back surface of the semiconductor substrate 1 is ground as shown in FIG.
  • a solder paste 14 is printed on the gold film 13 using a solder printing technique.
  • the solder paste 14 immediately after printing is printed almost flatly over an area wider than the bump land.
  • the semiconductor substrate 1 is heated to reflow the solder paste 14, thereby forming a hemispherical bump electrode 15 as shown in FIG. 14 on the gold film 19.
  • the pole 15 is also composed of, for example, a lead (Pb) -free soldering force that also has tin (Sn), silver (Ag) and copper (Cu) forces.
  • the bump electrode 15 can be formed by using a plating method instead of the printing method described above.
  • the bump electrodes 15 can be formed by supplying solder balls formed into a spherical shape on the bump lands and then heating the semiconductor substrate 1 to reflow the solder balls. In this way, it is possible to form a rewiring having one end connected to the bonding pad 3 and the other end connected to the bump electrode 15.
  • the semiconductor substrate 1 is cut into individual chips using a dicing blade. In this way, the Ueha Level CSP is completed. Furthermore, after being subjected to various final inspections such as performance and appearance as necessary, they are stored in tray jigs and shipped.
  • the present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

Abstract

A method for manufacturing a semiconductor device, which comprises providing a tank (21) for storing a plating solution in addition to a plating treatment tank (20), and arranging magnets (33a to 33d) in the plating solution storage tank, specifically, arranging a magnet (33a) in a dam provided at the inlet of the plating solution (27) in the plating solution storage tank (21), a magnet (33b) at the surface layer of the plating solution (27) stored therein, a magnet (33c) in the vicinity of the outlet of the plating solution (27) and a magnet (33d) at a bottom portion of the plating solution (27). The above method can be suitably employed for removing the sludge present in a plating solution efficiently while preventing the fluctuation of the film thickness of a nickel film formed on a wafer.

Description

明 細 書  Specification
半導体装置の製造方法  Manufacturing method of semiconductor device
技術分野  Technical field
[0001] 本発明は、半導体装置の製造技術に関し、特に、ウェハプロセスを応用してパッケ ージ工程を完了する CSP (Chip Size Package)技術に適用して有効な技術に関す るものである。  TECHNICAL FIELD [0001] The present invention relates to a semiconductor device manufacturing technology, and more particularly to a technology effective when applied to a CSP (Chip Size Package) technology that completes a packaging process by applying a wafer process.
背景技術  Background art
[0002] 日本特開平 09— 137299号公報 (特許文献 1)には、めっき処理槽とめつき液貯蔵 槽とを設けて、めっき液貯蔵槽に磁石を配置する技術が開示されている。具体的に は、めっき液貯蔵槽を第 1貯蔵槽と第 2貯蔵槽に分け、めっき処理槽カゝらのめつき液 を第 1貯蔵槽に設けた堰に流入させる。そして、第 1貯蔵槽に磁性粒子を吸着する磁 石を斜めに配置することにより、磁石の下部で 100 m力ゝら数 mmの大きな磁性粒子 を吸着する一方、磁石の上部で 1 μ mから数十/ z mの小さな磁性粒子を吸着する。 続いて、磁性粒子を除去しためっき液を第 1貯蔵槽力 第 2貯蔵槽に通した後、めつ き液を第 2貯蔵槽カもめつき処理槽に循環させる技術が開示されている。また、めつ き液貯蔵槽にあるめつき液内にポリテトラフルォロエチレンなどの耐蝕性榭脂で被覆 した磁石を沈めておき、めっき液中の磁性粒子を除去する技術が開示されている。  [0002] Japanese Patent Application Laid-Open No. 09-137299 (Patent Document 1) discloses a technique in which a plating treatment tank and a plating solution storage tank are provided, and a magnet is disposed in the plating solution storage tank. Specifically, the plating solution storage tank is divided into a first storage tank and a second storage tank, and the plating solution from the plating tank is poured into the weir provided in the first storage tank. And by placing the magnets that adsorb magnetic particles diagonally in the first storage tank, large magnetic particles of several millimeters, such as 100 m force, are adsorbed at the lower part of the magnet, while from 1 μm at the upper part of the magnet. Adsorbs small magnetic particles of several tens / zm. Subsequently, a technique is disclosed in which a plating solution from which magnetic particles have been removed is passed through a first storage tank force and a second storage tank, and then the plating solution is circulated through the second storage tank fitting process tank. In addition, a technique is disclosed in which a magnet coated with a corrosion-resistant resin such as polytetrafluoroethylene is submerged in a plating solution in a plating solution storage tank to remove magnetic particles in the plating solution. Yes.
[0003] 日本特開平 05— 306500号公報 (特許文献 2)には、めっき処理槽内の磁性スラッ ジをめっき処理槽内に設置した磁石により除去する装置、またはめつき処理槽の循 環用配管部分に磁石を設置した装置について開示されている。  [0003] Japanese Patent Application Laid-Open No. 05-306500 (Patent Document 2) discloses a device for removing magnetic sludge in a plating tank by a magnet installed in the plating tank, or for circulation of a plating tank. An apparatus in which a magnet is installed in a pipe portion is disclosed.
[0004] 日本特開平 07— 138799号公報 (特許文献 3)には、ニッケル膜を形成するめつき 方法において、ニッケルペレットを充填した陽極棒のなかに磁石粒を入れておき、陽 極棒力 発生するスラッジを磁石粒に付着させて、スラッジが陽極棒の外部に出な!/ヽ ようにする技術が開示されて 、る。  [0004] In Japanese Patent Application Laid-Open No. 07-138799 (Patent Document 3), in a method for forming a nickel film, magnet particles are placed in an anode rod filled with nickel pellets to generate a positive pole force. A technique for adhering sludge to be adhered to magnet grains so that the sludge does not come out of the anode rod is disclosed.
[0005] 日本特開平 06— 220698号公報 (特許文献 4)には、めっき液を輸送する輸送管の 内部または外部に磁性粒子を吸着する磁石を設ける装置について開示されている。  [0005] Japanese Unexamined Patent Publication No. 06-220698 (Patent Document 4) discloses an apparatus in which a magnet for adsorbing magnetic particles is provided inside or outside a transport pipe for transporting a plating solution.
[0006] 日本特開平 09-003694号公報 (特許文献 5)には、金属物をめつき処理槽の下部 に設けられた磁石によってめつき処理槽の底部に付着させる装置について開示され ている。 [0006] Japanese Patent Application Laid-Open No. 09-003694 (Patent Document 5) describes a lower part of a metal processing tank. Discloses a device for attaching to the bottom of a staking treatment tank using a magnet provided on the surface.
特許文献 1：特開平 09— 137229号公報  Patent Document 1: Japanese Patent Laid-Open No. 09-137229
特許文献 2：特開平 05— 306500号公報  Patent Document 2: Japanese Patent Laid-Open No. 05-306500
特許文献 3 :特開平 07 - 138799号公報  Patent Document 3: Japanese Patent Application Laid-Open No. 07-138799
特許文献 4：特開平 06— 220698号公報  Patent Document 4: Japanese Patent Laid-Open No. 06-220698
特許文献 5：特開平 09-003694号公報  Patent Document 5: Japanese Patent Laid-Open No. 09-003694
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0007] パッケージプロセス（後工程）とウェハプロセス（前工程）とを一体化し、ウェハ状態で パッケージングを完了する技術、いわゆるウェハレベル (Wafer Level) CSPと呼ばれ る技術は、ウェハプロセスを応用してパッケージプロセスまで処理する技術である。こ のため、半導体ウェハ（以下、ウェハという）から切断した半導体チップ (以下、チップ という）毎にノ¾ /ケージプロセスを処理する従来の方法に比べて工程数を大幅に削減 できるという利点がある。ウェハレベル CSPは、ウェハプロセス 'パッケージ（Wafer Process Package ; WPP)とも呼ばれる。  [0007] A technology that integrates the packaging process (post-process) and wafer process (pre-process) and completes packaging in the wafer state, the so-called Wafer Level CSP, applies the wafer process. This is a technology for processing up to the packaging process. For this reason, there is an advantage that the number of steps can be greatly reduced as compared with the conventional method in which the semiconductor / cage process is performed for each semiconductor chip (hereinafter referred to as a chip) cut from a semiconductor wafer (hereinafter referred to as a wafer). . Wafer level CSP is also called a wafer process package (WPP).
[0008] また、ウェハレベル CSPは、ボンディングパッドのピッチをバンプ電極のピッチに変 換するインターポーザと呼ばれる CSP内部の配線層を、ウェハ上に形成した再配線 層によって代用できるため、工程数削減を図ることができるとともに CSPの製造コスト を低減することができる。  [0008] In addition, the wafer level CSP can replace the wiring layer inside the CSP called an interposer, which converts the bonding pad pitch into the bump electrode pitch, with a rewiring layer formed on the wafer, reducing the number of processes. As well as the CSP manufacturing cost.
[0009] ウェハレベル CSPでは、ボンディングパッドとバンプ電極とを接続する再配線が形 成されるが、この再配線は例えば銅膜とニッケル膜の積層膜で構成される。銅膜およ びニッケル膜の形成には例えば電解めつき法が使用される。  In the wafer level CSP, a rewiring that connects a bonding pad and a bump electrode is formed. This rewiring is formed of a laminated film of a copper film and a nickel film, for example. For example, an electrolytic plating method is used to form the copper film and the nickel film.
[0010] ニッケル膜を電解めつき法で形成するには、アノード電極（陽極）にニッケルよりなる 電極を使用し、力ソード電極（陰極）にウェハを設置する。そして、アノード電極とカソ ード電極との間をめつき液で満たす。このような構成のもとアノード電極と力ソード電 極との間に電圧を印加すると、アノード電極力もニッケル原子がイオンとなってめっき 液中に溶け出す。そして、溶け出したニッケルイオンは、力ソード電極に接続している ウェハ上に付着してニッケル膜が形成される。このようにして、ウェハ上にニッケル膜 が形成される。 In order to form a nickel film by the electrolytic plating method, an electrode made of nickel is used for the anode electrode (anode), and a wafer is placed on the force sword electrode (cathode). Then, the gap between the anode electrode and the cathode electrode is filled with the squeezing solution. Under such a configuration, when a voltage is applied between the anode electrode and the force sword electrode, nickel atoms are also ionized into the anode electrode force and dissolved into the plating solution. And the melted nickel ions are connected to the force sword electrode A nickel film is formed on the wafer. In this way, a nickel film is formed on the wafer.
[0011] アノード電極では、ニッケル原子がイオンとなって溶け出していく力 イオンの溶出 はアノード電極の表面だけでなく内部からも生じる。このため、アノード電極を使用し ていくうちにアノード電極は軽石状になって崩れやすくなる。そして、めっき液の噴流 の勢いや電流密度の変化などにより、微小なニッケル粒子（以下、スラッジという）が アノード電極から発生する。すなわち、アノード電極からはニッケル原子がイオンとし て溶け出すだけでなぐスラッジも発生する。このスラッジがウェハに付着すると外観 異常 (外観不良）となるため、製品の歩留まり低下をもたらすという問題点がある。  [0011] In the anode electrode, nickel atoms are dissolved as ions. Elution of ions occurs not only from the surface of the anode electrode but also from the inside. For this reason, as the anode electrode is used, the anode electrode becomes pumice and tends to collapse. Fine nickel particles (hereinafter referred to as “sludge”) are generated from the anode electrode due to the motive force of the plating solution jet and the change in current density. In other words, sludge is generated from the anode electrode simply by melting nickel atoms as ions. When this sludge adheres to the wafer, it causes an abnormal appearance (defective appearance), resulting in a decrease in product yield.
[0012] ここで、日本特開平 09— 137299号公報 (特許文献 1)では、第 1貯蔵槽に磁石を 配置してスラッジの除去を行なっている。し力し、ウェハレベル CSPにおけるニッケル 膜の形成では、めっき液の流量を大きくする必要がある。このため、第 1貯蔵槽にお けるめっき液の液面が高くなる現象が生ずる。この場合、磁石の上部においてスラッ ジの捕獲が充分に行なえなくなる問題点が生じる。  [0012] Here, in Japanese Patent Laid-Open No. 09-137299 (Patent Document 1), a sludge is removed by arranging a magnet in the first storage tank. For this reason, it is necessary to increase the flow rate of the plating solution when forming a nickel film at the wafer level CSP. For this reason, a phenomenon occurs that the level of the plating solution in the first storage tank becomes high. In this case, there is a problem that sludge cannot be captured sufficiently at the top of the magnet.
[0013] また、日本特開平 05— 306500号公報 (特許文献 2)では、めっき処理槽内に磁石 を配置している。めっき処理槽ではウェハ上にニッケル膜の形成が行なわれる力 め つき処理槽内に磁石を配置すると、磁界の影響によりにウェハ上に形成される-ッケ ル膜の膜厚が変動する問題点がある。特に、めっき処理槽の大きさが小さい場合に は磁界の影響を受け易い。  [0013] Further, in Japanese Patent Laid-Open No. 05-306500 (Patent Document 2), a magnet is arranged in a plating tank. In the plating bath, the force of forming a nickel film on the wafer When the magnet is placed in the processing bath, the thickness of the nickel film formed on the wafer varies due to the influence of the magnetic field. There is. In particular, when the plating tank is small, it is easily affected by the magnetic field.
[0014] さらに、日本特開平 07— 138799号公報（特許文献 3)では、ニッケルペレットを充 填した陽極棒に磁石粒を入れている。しかし、力ソード電極に配置されるウェハと陽 極棒との距離が近いため、磁石による磁界の影響を受けてウェハ上に形成される-ッ ケル膜の膜厚が変動する問題点がある。  [0014] Further, in Japanese Patent Laid-Open No. 07-138799 (Patent Document 3), magnet particles are put in an anode bar filled with nickel pellets. However, since the distance between the wafer and the positive electrode placed on the force sword electrode is short, there is a problem that the film thickness of the nickel film formed on the wafer varies under the influence of the magnetic field by the magnet.
[0015] また、日本特開平 06— 220698号公報 (特許文献 4)では、めっき液を輸送する輸 送管の内部または外部に磁性粒子を吸着する磁石を設けている。しかし、スラッジは 微小なものがあるとともにウェハレベル CSPにおいてはめつき液の流量も大きいため [0015] Further, in Japanese Patent Laid-Open No. 06-220698 (Patent Document 4), a magnet for adsorbing magnetic particles is provided inside or outside a transport pipe for transporting a plating solution. However, the sludge is very small and the flow rate of the fitting liquid is large in wafer level CSP.
、輸送管の側壁に磁石を設ける構成では、充分に微小スラッジを捕獲できない。また 、輸送管の内壁にスラッジが堆積して輸送管が詰るおそれがある。 [0016] さらに、日本特開平 09-003694号公報 (特許文献 5)にはめつき処理槽の下部に 磁石を配置している。しかし、スラッジは微小なものもあり、めっき処理槽の下部に設 けた磁石によっては微小なスラッジを捕獲できない問題点がある。また、磁石の磁力 を大きくすると、磁界の影響を受けてゥヱハ上に形成するニッケル膜の膜厚が変動す るおそれがある。 In the configuration in which the magnet is provided on the side wall of the transport pipe, the fine sludge cannot be captured sufficiently. Further, there is a possibility that sludge accumulates on the inner wall of the transport pipe and the transport pipe is clogged. [0016] Further, in Japanese Patent Application Laid-Open No. 09-003694 (Patent Document 5), a magnet is disposed at the lower part of the fitting processing tank. However, some sludge is very small, and there is a problem that it cannot be captured by the magnet installed at the bottom of the plating tank. In addition, when the magnetic force of the magnet is increased, the thickness of the nickel film formed on the wafer may be affected by the influence of the magnetic field.
[0017] 本発明の目的は、ウェハ上に形成されるニッケル膜の膜厚変動を防止しながら、め つき液中に存在するスラッジを効率的に除去することができる技術を提供することに ある。  [0017] An object of the present invention is to provide a technique capable of efficiently removing sludge present in a plating solution while preventing fluctuations in the thickness of a nickel film formed on a wafer. .
[0018] 本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添 付図面から明らかになるであろう。  [0018] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
課題を解決するための手段  Means for solving the problem
[0019] 本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 次のとおりである。 Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0020] 本発明による半導体装置の製造方法は、半導体ウェハの状態でパッケージングを 完了する半導体装置の製造方法であって、 (a)前記半導体ウェハに内部接続端子を 形成する工程と、 (b)前記内部接続端子に一端部を接続する再配線を形成するェ 程と、 (c)前記再配線の他端部に接続する外部接続端子を形成する工程とを備え、 前記 (b)工程は、（bl)電解めつき法を使用してニッケル膜を形成する工程を含み、 前記 (bl)工程は、前記半導体ウェハ上に前記ニッケル膜を形成するめつき処理槽と は別の槽であって前記めつき処理槽との間でめっき液を循環させるめっき液貯蔵槽 のめつき液流入部、めっき液流出部およびめつき液の表層部に磁石を配置しながら 、前記ニッケル膜を前記めつき処理槽で形成することを特徴とするものである。 [0020] A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device that completes packaging in the state of a semiconductor wafer, and includes: ( a ) forming internal connection terminals on the semiconductor wafer; And (c) forming a rewiring that connects one end to the internal connection terminal, and (c) forming an external connection terminal that connects to the other end of the rewiring. (Bl) forming a nickel film using an electrolytic plating method, wherein the (bl) process is a tank separate from the plating process tank for forming the nickel film on the semiconductor wafer. The plating solution is circulated between the plating solution tank, and the nickel film is attached to the plating solution while placing a magnet in the plating solution inflow portion, the plating solution outflow portion, and the surface layer portion of the plating solution. It forms in a processing tank, It is characterized by the above-mentioned.
発明の効果  The invention's effect
[0021] 本願において開示される発明のうち、代表的なものによって得られる効果を簡単に 説明すれば以下のとおりである。  [0021] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
[0022] めっき処理槽とは別の槽であって前記めつき処理槽との間でめっき液を循環させる めっき液貯蔵槽のめっき液流入部、めっき液流出部およびめつき液の表層部に磁石 を配置するように構成したので、ウェハ上に形成されるニッケル膜の膜厚変動を防止 しながら、めっき液中に存在するスラッジを効率的に除去することができる。 [0022] It is a tank different from the plating treatment tank, and circulates the plating solution between the plating treatment tanks. In the plating solution inflow portion, the plating solution outflow portion, and the surface layer portion of the plating solution of the plating solution storage tank. Since the magnet is arranged, it prevents the film thickness fluctuation of the nickel film formed on the wafer. However, sludge present in the plating solution can be efficiently removed.
図面の簡単な説明  Brief Description of Drawings
[0023] [図 1]ウェハレベル CSP (WPP)の製造工程を示したフローチャートである。  FIG. 1 is a flowchart showing a manufacturing process of a wafer level CSP (WPP).
[図 2]実施の形態における半導体装置の製造工程を示した断面図である。  FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device in the embodiment.
[図 3]図 2に続く半導体装置の製造工程を示した断面図である。  FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 2;
[図 4]図 3に続く半導体装置の製造工程を示した断面図である。  FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3;
[図 5]図 4に続く半導体装置の製造工程を示した断面図である。  FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 4;
[図 6]図 5に続く半導体装置の製造工程を示した断面図である。  6 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 5.
[図 7]実施の形態におけるめっき装置の構成を示した部分断面図である。  FIG. 7 is a partial cross-sectional view showing the configuration of the plating apparatus in the embodiment.
[図 8]図 6に続く半導体装置の製造工程を示した断面図である。  FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6;
[図 9]図 8に続く半導体装置の製造工程を示した断面図である。  FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 8;
[図 10]図 9に続く半導体装置の製造工程を示した断面図である。  FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 9;
[図 11]図 10に続く半導体装置の製造工程を示した断面図である。  FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10;
[図 12]図 11に続く半導体装置の製造工程を示した断面図である。  FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11;
[図 13]図 12に続く半導体装置の製造工程を示した断面図である。  FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12;
[図 14]図 13に続く半導体装置の製造工程を示した断面図である。  FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13;
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0024] 以下の実施の形態においては便宜上その必要があるときは、複数のセクションまた は実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに 無関係なものではなぐ一方は他方の一部または全部の変形例、詳細、補足説明等 の関係にある。 [0024] In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not independent of each other unless otherwise specified. One is related to some or all of the other modification, details, supplementary explanation, etc.
[0025] また、以下の実施の形態において、要素の数等 (個数、数値、量、範囲等を含む） に言及する場合、特に明示した場合および原理的に明らかに特定の数に限定される 場合等を除き、その特定の数に限定されるものではなぐ特定の数以上でも以下でも よい。  [0025] Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly limited to a specific number when clearly indicated and in principle. Except in some cases, the number is not limited to the specific number, and may be a specific number or more.
[0026] さらに、以下の実施の形態において、その構成要素（要素ステップ等も含む）は、特 に明示した場合および原理的に明らかに必須であると考えられる場合等を除き、必 ずしも必須のものではな 、ことは言うまでもな 、。 [0027] 同様に、以下の実施の形態において、構成要素等の形状、位置関係等に言及す るときは、特に明示した場合および原理的に明らかにそうではないと考えられる場合 等を除き、実質的にその形状等に近似または類似するもの等を含むものとする。この ことは、上記数値および範囲についても同様である。 [0026] Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily specified unless explicitly stated or considered to be clearly essential in principle. Needless to say, it's not essential. [0027] Similarly, in the following embodiments, when referring to the shape, positional relationship, and the like of components, etc., unless explicitly stated or otherwise apparently not in principle, Those substantially including or similar to the shape or the like are included. The same applies to the above numerical values and ranges.
[0028] また、実施の形態を説明するための全図において、同一の部材には原則として同 一の符号を付し、その繰り返しの説明は省略する。  [0028] In all the drawings for explaining the embodiments, the same members are, in principle, given the same reference numerals, and the repeated explanation thereof is omitted.
[0029] 図 1は、ウェハレベル CSP (WPP)の製造工程を示したフローチャートである。図 1 を参照しながらウェハレベル CSPの製造工程について簡単に説明する。まず、前ェ 程での処理を実施する（S 101)。前工程では、半導体基板上に MISFET(Metal Insulator Semiconductor Field Effect Transistor)などの半導体素子を形成した後、こ の半導体素子上に一層以上の配線を形成する。そして、最上層の配線を形成して、 内部接続端子であるボンディングパッドを形成する。  FIG. 1 is a flowchart showing a manufacturing process of wafer level CSP (WPP). The wafer level CSP manufacturing process will be briefly described with reference to FIG. First, the processing in the previous step is performed (S 101). In the pre-process, a semiconductor element such as a metal insulator semiconductor field effect transistor (MISFET) is formed on a semiconductor substrate, and then one or more wirings are formed on the semiconductor element. Then, the uppermost layer wiring is formed to form a bonding pad as an internal connection terminal.
[0030] 続いて、ウェハテストを行なう（S102)。ウェハテストでは、例えば半導体基板に形 成した MISFETのしき!/、値電圧の検査が実施される。  Subsequently, a wafer test is performed (S102). In the wafer test, for example, MISFETs formed on a semiconductor substrate are checked for threshold values and value voltages.
[0031] 次に、ウェハレベル CSPにおける再配線を形成する。再配線は、ボンディングパッ ドと後述するバンプ電極とを接続するための配線であり、例えば銅膜とニッケル膜の 積層膜で形成される。本実施の形態の特徴はニッケル膜を電解めつき法で形成する 工程にあるが、詳細は後述する。  Next, rewiring in the wafer level CSP is formed. The rewiring is a wiring for connecting a bonding pad and a bump electrode described later, and is formed of a laminated film of a copper film and a nickel film, for example. The feature of this embodiment is in the step of forming the nickel film by the electrolytic plating method, and details will be described later.
[0032] 続いて、プローブテストを実施する（S103)。プローブテストは再配線で形成された バンプランドに探針を押し当てて半導体素子の電気的特性を検査するものである。  Next, a probe test is performed (S103). In the probe test, the probe is pressed against the bump land formed by rewiring to inspect the electrical characteristics of the semiconductor element.
[0033] そして、外観検査が実施された後（S105)、半導体基板の裏面を研削する（S106) 。次に、再配線で形成されたバンプランド上にバンプ電極を形成する（S107)。その 後、再び外観検査が実施され (S108)、後工程の処理が実施される（S109)。後ェ 程では、バンプ電極が形成された半導体基板の個々のチップ領域をダイシングによ り個々のチップに切断する。そして、切断したチップの選別を行い、良品をトレーに収 納して出荷する。  [0033] After the appearance inspection is performed (S105), the back surface of the semiconductor substrate is ground (S106). Next, bump electrodes are formed on the bump lands formed by rewiring (S107). Thereafter, the appearance inspection is performed again (S108), and the subsequent process is performed (S109). In the later step, individual chip regions of the semiconductor substrate on which the bump electrodes are formed are cut into individual chips by dicing. Then, the cut chips are selected, and the non-defective products are stored in a tray and shipped.
[0034] 次に、本実施の形態における半導体装置の製造工程を詳細に説明する。まず、半 導体基板（半導体ウェハ） 1上に MISFETを形成し、この MISFET上に一層以上の 配線を形成する。そして、図 2に示すように層間絶縁膜 2を形成する。層間絶縁膜 2 は、例えば酸化シリコン膜から形成されており、例えば CVD (Chemical Vapor D印 osition)法を使用して形成することができる。なお、図 2では、半導体基板 1上に 形成される MISFETおよび一層以上の配線の図示を省略している。 Next, a manufacturing process of the semiconductor device in the present embodiment will be described in detail. First, a MISFET is formed on a semiconductor substrate (semiconductor wafer) 1, and one or more layers are formed on the MISFET. Form wiring. Then, an interlayer insulating film 2 is formed as shown in FIG. The interlayer insulating film 2 is made of, for example, a silicon oxide film, and can be formed by using, for example, a CVD (Chemical Vapor D mark osition) method. In FIG. 2, the illustration of the MISFET formed on the semiconductor substrate 1 and one or more layers is omitted.
[0035] 続いて、層間絶縁膜 2上に窒化チタン膜およびアルミニウム膜よりなる積層膜を例 えばスパッタリング法を使用して形成する。そして、フォトリソグラフィ技術およびエツ チング技術を使用して積層膜をパターユングし、最上層配線を形成する。この最上 層配線を形成する工程で内部接続端子であるボンディングパッド 3も形成する。  Subsequently, a laminated film made of a titanium nitride film and an aluminum film is formed on the interlayer insulating film 2 by using, for example, a sputtering method. Then, the laminated film is patterned using photolithography technology and etching technology to form the uppermost layer wiring. Bonding pads 3 as internal connection terminals are also formed in the process of forming the uppermost layer wiring.
[0036] 次に、図 3に示すように、ボンディングパッド 3上を含む層間絶縁膜 2上に窒化シリコ ン膜 4を形成する。窒化シリコン膜 4は、例えば CVD法を使用して形成することができ る。そして、窒化シリコン膜 4上に感光性ポリイミド榭脂膜 5を塗布する。この窒化シリ コン膜 4および感光性ポリイミド榭脂膜 5によりパッシベーシヨン膜 (第 1絶縁膜)が形 成される。パッシベーシヨン膜は、内部に形成された半導体素子や配線を機械的応 力や不純物の侵入力 保護するために設けられる膜である。  Next, as shown in FIG. 3, a silicon nitride film 4 is formed on the interlayer insulating film 2 including the bonding pad 3. The silicon nitride film 4 can be formed using, for example, a CVD method. Then, a photosensitive polyimide resin film 5 is applied on the silicon nitride film 4. The silicon nitride film 4 and the photosensitive polyimide resin film 5 form a passivation film (first insulating film). The passivation film is a film provided to protect the semiconductor element and wiring formed inside in order to protect the mechanical stress and the intrusion force of impurities.
[0037] 続いて、感光性ポリイミド榭脂膜 5に対して露光 ·現像処理を施すことにより、感光性 ポリイミド榭脂膜 5をパターニングする。パターニングは、ボンディングパッド 3上を開 口するように行なわれる。そして、パターユングした感光性ポリイミド榭脂膜 5をマスク にして、下層にある窒化シリコン膜 4をエッチングする。これにより、ボンディングパッド 3上に開口部 6が形成される。  Subsequently, the photosensitive polyimide resin film 5 is patterned by subjecting the photosensitive polyimide resin film 5 to exposure / development treatment. Patterning is performed so as to open on the bonding pad 3. Then, using the patterned photosensitive polyimide resin film 5 as a mask, the underlying silicon nitride film 4 is etched. As a result, the opening 6 is formed on the bonding pad 3.
[0038] 次に、ウェハテストが実施された後、図 4に示すように、シード層 7を形成する。この シード層 7は、ボンディングパッド 3上を含む感光性ポリイミド榭脂膜 5上に形成される 。シード層 7は、例えばクロム (Cr)膜と銅 (Cu)膜との積層膜から形成され、例えばス ノ ッタリング法を使用して形成することができる。シード層 7は後述するめつき膜を成 長させるための電極層としての機能を有するものである。  Next, after the wafer test is performed, a seed layer 7 is formed as shown in FIG. The seed layer 7 is formed on the photosensitive polyimide resin film 5 including the bonding pad 3. The seed layer 7 is formed of, for example, a laminated film of a chromium (Cr) film and a copper (Cu) film, and can be formed using, for example, a sputtering method. The seed layer 7 has a function as an electrode layer for growing a plated film described later.
[0039] 続いて、図 5に示すように、シード層 7上にレジスト膜 8を形成した後、このレジスト膜 8に対して露光'現像処理を施すことによりパターユングする。パターユングは、再配 線を形成する領域にレジスト膜 8が残らないように行なわれる。そして、図 6に示すよう に、露出したシード層 7上に電解めつき法を使用して銅膜 9を形成する。 [0040] 次に、電解めつき法を使用して銅膜 9上にニッケル膜を形成するため、図 7に示す めっき装置に半導体基板 1が搬入される。図 7は、半導体基板 1にニッケル膜を形成 するためのめっき装置の概略構成を示した部分断面図である。図 7において、本実 施の形態におけるめっき装置は、めっき処理槽 20とめつき液貯蔵槽 21とを有してい る。めっき処理槽 20とめつき液貯蔵槽 21とは別々に設けられた槽であり、互いにボン プ 22を設けた配管 23と配管 24によって接続されている。 Subsequently, as shown in FIG. 5, after a resist film 8 is formed on the seed layer 7, the resist film 8 is subjected to exposure and development processing to be patterned. The patterning is performed so that the resist film 8 does not remain in the region where the redistribution is formed. Then, as shown in FIG. 6, a copper film 9 is formed on the exposed seed layer 7 using an electrolytic plating method. Next, in order to form a nickel film on the copper film 9 using the electrolytic plating method, the semiconductor substrate 1 is carried into the plating apparatus shown in FIG. FIG. 7 is a partial cross-sectional view showing a schematic configuration of a plating apparatus for forming a nickel film on the semiconductor substrate 1. In FIG. 7, the plating apparatus in the present embodiment has a plating treatment tank 20 and a mating liquid storage tank 21. The plating tank 20 and the plating solution storage tank 21 are provided separately, and are connected to each other by a pipe 23 and a pipe 24 provided with a pump 22.
[0041] めっき処理槽 20は、半導体基板 1上にニッケル膜を形成するための槽であり、外枠 体 26の内部にはめつき液 27が充填されている。外枠体 26の底部には、配管 23が設 けられており、めっき液が配管 23からめつき処理槽 20内に流入するようになっている 。また、外枠体 26の底部にはアノード電極（陽極） 28が設けられている。このアノード 電極 28はニッケルを主成分として構成されている。一方、外枠体 26の上面にはカソ ード電極（陰極） 29が形成されており、この力ソード電極 29に接続するように半導体 基板 1が設置される。半導体基板 1は、アノード電極 28に対向するように配置されて いる。また、アノード電極 28の周囲にはアノードバック 30が設けられている。アノード ノ ック 30は、アノード電極から出てくるニッケルの微細粒 (スラッジ）がめつき液中に拡 散するのを防止するために設けられて 、る。めっき処理槽 20に流入しためっき液 27 は配管 24によってめっき処理槽 20から流出するようになって 、る。  [0041] The plating treatment tank 20 is a tank for forming a nickel film on the semiconductor substrate 1, and the inside of the outer frame body 26 is filled with a fitting liquid 27. A pipe 23 is provided at the bottom of the outer frame body 26, and the plating solution flows from the pipe 23 into the mating treatment tank 20. An anode electrode (anode) 28 is provided on the bottom of the outer frame body 26. The anode electrode 28 is composed mainly of nickel. On the other hand, a cathode electrode (cathode) 29 is formed on the upper surface of the outer frame body 26, and the semiconductor substrate 1 is installed so as to be connected to the force sword electrode 29. The semiconductor substrate 1 is disposed so as to face the anode electrode 28. An anode back 30 is provided around the anode electrode 28. The anode knock 30 is provided to prevent the nickel fine particles (sludge) coming out of the anode electrode from being diffused into the squeeze solution. The plating solution 27 flowing into the plating tank 20 flows out of the plating tank 20 through the pipe 24.
[0042] 次に、めっき液貯蔵槽 21の外枠体 31内には、配管 24からめつき液 27が流入する ようになつている。そして、めっき液貯蔵槽 21に貯蔵されているめっき液 27は、ボン プ 22が接続された配管 23を介してめつき液貯蔵槽 21から流出するようになっている 。また、めっき液貯蔵槽 21のめつき液 27の流入口には堰 32が設けられている。この 堰 32はめつき液貯蔵槽 21に貯蔵されているめっき液 27の内部に気泡が残らないよ うにするために設けられている。すなわち、めっき液貯蔵槽 21には、勢い良くめっき 液 27が流入する。このとき、めっき液貯蔵槽 21に貯蔵されているめっき液 27の内部 に気泡が取り込まれる。この内部に取り込まれた気泡がめっき液貯蔵槽 21から配管 2 3を介してめつき処理槽 20に移動すると、半導体基板 1の表面に気泡が付着すること になる。すると、気泡が付着した領域において、半導体基板 1はめつき液 27と接しな くなるため、ニッケル膜が成長しなくなる。このような不都合を回避するため、めっき液 貯蔵槽 21の流入口に堰 32を設けてめっき液 27の内部に気泡が残らないようにして いる。 Next, the plating solution 27 flows from the pipe 24 into the outer frame 31 of the plating solution storage tank 21. The plating solution 27 stored in the plating solution storage tank 21 flows out from the plating solution storage tank 21 through the pipe 23 to which the pump 22 is connected. A weir 32 is provided at the inlet of the plating solution 27 of the plating solution storage tank 21. This weir 32 is provided to prevent bubbles from remaining in the plating solution 27 stored in the fitting solution storage tank 21. That is, the plating solution 27 flows into the plating solution storage tank 21 vigorously. At this time, bubbles are taken into the plating solution 27 stored in the plating solution storage tank 21. When the air bubbles taken into the interior move from the plating solution storage tank 21 to the plating treatment tank 20 via the pipe 23, the air bubbles adhere to the surface of the semiconductor substrate 1. Then, since the semiconductor substrate 1 does not come into contact with the fitting liquid 27 in the region where the bubbles are attached, the nickel film does not grow. In order to avoid such inconvenience, plating solution A weir 32 is provided at the inlet of the storage tank 21 so that no bubbles remain inside the plating solution 27.
[0043] 次に、めっき液貯蔵槽 21には複数の磁石 33a— 33dが設置されて 、る。このように めっき液貯蔵槽 21内に磁石 33a— 33dを設けたことが本実施の形態における特徴 の一つである。めっき処理中にお!、てめつき処理槽 20のアノード電極 28からは-ッ ケルカ Sイオンとして溶出するだけでなく、イオンィ匕して 、な 、ニッケルの微細粒 (スラッ ジ)も放出される。このスラッジはアノードバック 30によってめっき液 27中に飛散する ことが防止されている力 アノードバック 30では微細なスラッジの飛散を防止すること ができない。このため、めっき液 27中にスラッジが放出される。このスラッジはめつき 液 27とともにめっき処理槽 20およびめつき液貯蔵槽 21を循環する。そして、スラッジ のうち一部はめつき処理槽 20に配置した半導体基板 1に付着する。すると、付着した スラッジにより半導体基板 1上に形成するニッケル膜に外観不良が発生する。また、 再配線を構成するニッケル膜にスラッジが付着すると以下に示す不具合が発生する 。すなわち、その後の工程で再配線上に保護膜を形成するが、再配線上にスラッジ が付着して 、ると保護膜が充分に形成されな 、おそれがある。保護膜が充分に形成 されないと、水分などの異物が半導体基板 1の内部に侵入する不具合が発生する。 したがって、めっき液 27中に飛散したスラッジを除去する必要がある。  Next, a plurality of magnets 33a to 33d are installed in the plating solution storage tank 21. One of the features of the present embodiment is that the magnets 33a to 33d are provided in the plating solution storage tank 21 as described above. During the plating process, the anode electrode 28 of the plating bath 20 not only elutes as -eckerka S ions but also releases nickel fine particles (sludge). . This sludge is prevented from scattering into the plating solution 27 by the anode back 30. The anode back 30 cannot prevent fine sludge from scattering. For this reason, sludge is released into the plating solution 27. This sludge is circulated through the plating tank 20 and the plating liquid storage tank 21 together with the plating liquid 27. Then, part of the sludge adheres to the semiconductor substrate 1 disposed in the fitting treatment tank 20. Then, an appearance defect occurs in the nickel film formed on the semiconductor substrate 1 due to the attached sludge. In addition, if sludge adheres to the nickel film constituting the rewiring, the following problems occur. That is, a protective film is formed on the rewiring in a subsequent process. If sludge adheres on the rewiring, the protective film may not be sufficiently formed. If the protective film is not sufficiently formed, a problem that foreign matter such as moisture enters the semiconductor substrate 1 occurs. Therefore, it is necessary to remove the sludge scattered in the plating solution 27.
[0044] そこで、本実施の形態では、ニッケルよりなるスラッジが磁石に吸着する性質を利用 してめつき液 27中に磁石 33a— 33dを設置している。これにより、めっき液 27に放出 されたスラッジを磁石 33a— 33dで捕獲することができるので、めっき液 27中力もスラ ッジを除去することができる。特に、本実施の形態では、磁石 33a— 33dをめつき処 理槽 20ではなくめっき処理槽 20から離れためっき液貯蔵槽 21に設けている。これに より、半導体基板 1に形成するニッケル膜の磁界による膜厚の変動を防止できる。例 えば、磁石 33a— 33dをめつき処理槽 20内に設置するようにした場合、磁石 33a— 3 3dとニッケル膜を形成する半導体基板 1とが近接することになる。すると、磁石 33a— 33dによる磁界の影響を受け易くなるので、半導体基板 1に形成されるニッケル膜の 膜厚が変動しやすくなる。これに対し、本実施の形態では、半導体基板 1を設置する めっき処理槽 20から充分に離れためっき液貯蔵槽 21内に磁石 33a— 33dを設けた ので、半導体基板 1に形成するニッケル膜の膜厚に変動を与えることなぐスラッジを 除去することができる。 [0044] Therefore, in the present embodiment, the magnets 33a to 33d are installed in the adhesive liquid 27 by utilizing the property that sludge made of nickel is adsorbed to the magnet. Thereby, since the sludge discharged to the plating solution 27 can be captured by the magnets 33a to 33d, the sludge can also be removed by the intermediate force of the plating solution 27. In particular, in the present embodiment, the magnets 33a to 33d are provided not in the plating treatment tank 20 but in the plating solution storage tank 21 that is separated from the plating treatment tank 20. As a result, the film thickness variation due to the magnetic field of the nickel film formed on the semiconductor substrate 1 can be prevented. For example, when the magnets 33a to 33d are installed in the staking treatment tank 20, the magnets 33a to 33d and the semiconductor substrate 1 on which the nickel film is formed are brought close to each other. Then, since it becomes easy to be affected by the magnetic field by the magnets 33a-33d, the thickness of the nickel film formed on the semiconductor substrate 1 is likely to fluctuate. On the other hand, in the present embodiment, magnets 33a-33d are provided in the plating solution storage tank 21 sufficiently separated from the plating processing tank 20 in which the semiconductor substrate 1 is installed. Therefore, sludge that does not change the thickness of the nickel film formed on the semiconductor substrate 1 can be removed.
[0045] また、ウェハレベル CSPにおいて、再配線のニッケル膜を形成するには、めっき液 2 7の流量を例えば毎分 30リットルから毎分 50リットルという大流量で流す必要がある。 したがって、このような大流量でめっき液 27を循環させる場合、磁石の設置場所を充 分に考慮しなければ、効率的にめっき液 27中のスラッジを除去することができない。 このため、本実施の形態では、磁石 33a— 33dを以下に示す場所に設置している。 すなわち、まず、磁石 33aはめつき液貯蔵槽 21の流入口（流入部）である堰 32に設 けられている。これにより、めっき処理槽 20から流入するスラッジを充分に除去するこ とができる。また、磁石 33bは、めっき液 27の表層部に設けられているので、めっき液 27の表層部を流れる微細なスラッジを捕獲することができる。さらに、めっき液貯蔵槽 21の流出口（流出部)付近に磁石 33cを設けることにより、磁石 33aや磁石 33bで除 去できな力つたスラッジをめつき処理槽 20に戻る前に捕獲することができる。このよう に、磁石 33a— 33cを上述した位置に設置することにより、効果的にスラッジを除去す ることができる。また、めっき液 27の底部のよどんだ領域に磁石 33dを設けることによ り、比較的大きく沈み易いスラッジを捕獲することができる。本実施の形態によれば、 磁石 33a— 33dを設置することにより、めっき液 27が毎分 30リットルから毎分 50リット ルの流量で流れている場合であっても充分にスラッジを除去することができる。  In addition, in the wafer level CSP, in order to form a nickel film for rewiring, it is necessary to flow the plating solution 27 at a large flow rate of, for example, 30 liters per minute to 50 liters per minute. Therefore, when the plating solution 27 is circulated at such a large flow rate, the sludge in the plating solution 27 cannot be efficiently removed unless the location of the magnet is sufficiently considered. For this reason, in the present embodiment, the magnets 33a to 33d are installed at the following locations. That is, first, the magnet 33a is provided in the weir 32 which is the inlet (inflow part) of the fitting liquid storage tank 21. As a result, sludge flowing from the plating tank 20 can be sufficiently removed. Further, since the magnet 33b is provided on the surface layer portion of the plating solution 27, fine sludge flowing through the surface portion of the plating solution 27 can be captured. Furthermore, by installing a magnet 33c near the outlet (outflow part) of the plating solution storage tank 21, it is possible to capture the sludge, which cannot be removed by the magnet 33a and the magnet 33b, before returning to the plating tank 20. it can. Thus, the sludge can be effectively removed by installing the magnets 33a-33c at the positions described above. In addition, by providing the magnet 33d in the stagnation region of the bottom of the plating solution 27, sludge that is relatively large and easily sinks can be captured. According to the present embodiment, the magnets 33a to 33d are installed to sufficiently remove sludge even when the plating solution 27 flows at a flow rate of 30 liters per minute to 50 liters per minute. Can do.
[0046] めっき液貯蔵槽 21に設置される磁石 33a— 33dは、めっき液 27に接触することに よる腐食などを防止するため、例えばフッ素榭脂で表面を覆っている。なお、図 7で は、めっき液貯蔵槽 21に接続されているめっき処理槽 20がーつである力 一つであ る必要はなく複数のめっき処理槽 20に接続されて 、てもよ 、。めっき液貯蔵槽 21に 複数のめっき処理槽 20を接続することにより、複数のめっき処理槽 20で発生するス ラッジを一つのめっき液貯蔵槽 21に設けた磁石 33a— 33dにより除去することができ るので、複数のめっき処理槽 20にそれぞれ磁石 33a— 33dを設置する場合に比べ てコストを低減することができる。  [0046] The magnets 33a to 33d installed in the plating solution storage tank 21 are covered with, for example, fluorine resin to prevent corrosion caused by contact with the plating solution 27. In FIG. 7, it is not necessary that the plating tank 20 connected to the plating solution storage tank 21 is a single force, and it may be connected to a plurality of plating tanks 20. . By connecting multiple plating tanks 20 to the plating solution storage tank 21, sludge generated in the multiple plating tanks 20 can be removed by the magnets 33a to 33d provided in one plating solution storage tank 21. Therefore, the cost can be reduced as compared with the case where the magnets 33a to 33d are respectively installed in the plurality of plating tanks 20.
[0047] 本実施の形態におけるめっき装置は上記のように構成されており、以下に動作に ついて説明する。図 7に示すように、半導体基板 1の再配線形成面をめつき液 27に 接触させるようにして半導体基板 1を力ソード電極 29に設置する。続いて、アノード電 極 28と力ソード電極 29の間に所定の電圧を印加する。すると、アノード電極 29を構 成するニッケル力 オンィ匕して溶出する。溶出したニッケルイオンはめつき液 27を移 動する。そして、力ソード電極 29に接続された半導体基板 1上に析出して図 8に示す ように、銅膜 9上にニッケル膜 10が形成される。このとき、アノード電極 28は、 -ッケ ルイオンの溶出により軽石状になっているため、ニッケルの微細粒であるスラッジも放 出される。このスラッジの一部はアノードバック 30により飛散が防止される力 一部は アノードバック 30を通り抜けてめっき液 27中に飛散する。飛散したスラッジはめつき 処理槽 20からめつき液貯蔵槽 21へ運ばれる力 めっき液貯蔵槽 21の流入口に設け られている磁石 33aに吸着して除去される。除去されなかったスラッジも磁石 33b、 3 3cおよび 33dにより効果的に除去される。このようにして半導体基板 1上にスラッジが 付着することを防止できるので、再配線の外観不良を低減することができる。 [0047] The plating apparatus in the present embodiment is configured as described above, and the operation will be described below. As shown in Fig. 7, the rewiring forming surface of the semiconductor substrate 1 is immersed in the solution 27. The semiconductor substrate 1 is placed on the force sword electrode 29 so as to be in contact with each other. Subsequently, a predetermined voltage is applied between the anode electrode 28 and the force sword electrode 29. Then, the nickel force constituting the anode electrode 29 is turned on and eluted. Move the eluted nickel ion fitting solution 27. Then, it is deposited on the semiconductor substrate 1 connected to the force sword electrode 29 and a nickel film 10 is formed on the copper film 9 as shown in FIG. At this time, since the anode electrode 28 is pumice-like due to the elution of -kel ions, sludge that is fine nickel particles is also released. A part of the sludge is prevented from being scattered by the anode back 30 and part of the sludge passes through the anode back 30 and is scattered in the plating solution 27. The scattered sludge is transported from the mating treatment tank 20 to the mating liquid storage tank 21 and is removed by adsorption to the magnet 33a provided at the inlet of the plating liquid storage tank 21. The sludge that has not been removed is also effectively removed by the magnets 33b, 33c and 33d. In this way, it is possible to prevent the sludge from adhering to the semiconductor substrate 1, so that the appearance defect of rewiring can be reduced.
[0048] 続いて、図 9に示すように、パターユングしたレジスト膜 8を除去した後、レジスト膜 8 で覆われていたシード層 7をウエットエッチングで除去する。ここで、レジスト膜 8で覆 われていたシード層 7をエッチングする際、再配線の表面も同時にエッチングされる 力 再配線の膜厚はシード層 7の膜厚に比べて遥かに厚いので支障はない。  Subsequently, as shown in FIG. 9, after the patterned resist film 8 is removed, the seed layer 7 covered with the resist film 8 is removed by wet etching. Here, when the seed layer 7 covered with the resist film 8 is etched, the surface of the rewiring is also etched at the same time. The thickness of the rewiring is much thicker than the thickness of the seed layer 7, so there is no problem. Absent.
[0049] 次に、図 10に示すように、銅膜 9およびニッケル膜 10よりなる再配線の上部に感光 性ポリイミド榭脂膜 (第 2絶縁膜) 11を形成する。そして、感光性ポリイミド榭脂膜 11に 対して露光'現像処理を行なうことにより、バンプ電極形成領域に開口部 (第 2開口部 ) 12を形成する。  Next, as shown in FIG. 10, a photosensitive polyimide resin film (second insulating film) 11 is formed on the upper part of the rewiring composed of the copper film 9 and the nickel film 10. Then, the photosensitive polyimide resin film 11 is exposed and developed to form an opening (second opening) 12 in the bump electrode formation region.
[0050] 続いて、図 11に示すように、開口部 12から露出した再配線 (バンプランド)上に無 電解めつき法を使用して金 (Au)膜 13を形成する。そして、開口部 12から露出した 再配線上に探針 (プローブ）を押し当ててプローブ検査を実施する。次に、外観検査 が実施された後、図 12に示すように、半導体基板 1の裏面を研削する。  Subsequently, as shown in FIG. 11, a gold (Au) film 13 is formed on the rewiring (bump land) exposed from the opening 12 using an electroless plating method. Then, a probe inspection is performed by pressing a probe (probe) on the rewiring exposed from the opening 12. Next, after the appearance inspection is performed, the back surface of the semiconductor substrate 1 is ground as shown in FIG.
[0051] そして、図 13に示すように、金膜 13上に半田印刷技術を使用して半田ペースト 14 を印刷する。印刷直後の半田ペースト 14は、バンプランドよりも広い領域にほぼ平坦 に印刷される。続いて、半導体基板 1を加熱して半田ペースト 14をリフローさせること により、金膜 19上に図 14に示すような半球状のバンプ電極 15を形成する。バンプ電 極 15は、例えば錫（Sn)、銀 (Ag)および銅 (Cu)力もなる鉛 (Pb)フリー半田力も構 成される。なお、バンプ電極 15は、上記した印刷法に代えてめっき法を使用して形 成することもできる。また、あら力じめ球状に成形した半田ボールをバンプランド上に 供給し、その後、半導体基板 1を加熱して半田ボールをリフローすることによってもバ ンプ電極 15を形成することができる。このようにして、ボンディングパッド 3に一端部が 接続する一方、バンプ電極 15に他端部が接続する再配線を形成することができる。 Then, as shown in FIG. 13, a solder paste 14 is printed on the gold film 13 using a solder printing technique. The solder paste 14 immediately after printing is printed almost flatly over an area wider than the bump land. Subsequently, the semiconductor substrate 1 is heated to reflow the solder paste 14, thereby forming a hemispherical bump electrode 15 as shown in FIG. 14 on the gold film 19. Bump Den The pole 15 is also composed of, for example, a lead (Pb) -free soldering force that also has tin (Sn), silver (Ag) and copper (Cu) forces. The bump electrode 15 can be formed by using a plating method instead of the printing method described above. Alternatively, the bump electrodes 15 can be formed by supplying solder balls formed into a spherical shape on the bump lands and then heating the semiconductor substrate 1 to reflow the solder balls. In this way, it is possible to form a rewiring having one end connected to the bonding pad 3 and the other end connected to the bump electrode 15.
[0052] 続いて、半導体基板 1をバーンイン検査に付して最終検査を行なった後、ダイシン グブレードを使用して半導体基板 1を個々のチップに切断する。このようにして、ゥェ ハレベル CSPが完成する。さらに必要に応じて性能、外観などの各種最終検査に付 された後、トレー治具に収納されて出荷される。  Subsequently, after subjecting the semiconductor substrate 1 to burn-in inspection and final inspection, the semiconductor substrate 1 is cut into individual chips using a dicing blade. In this way, the Ueha Level CSP is completed. Furthermore, after being subjected to various final inspections such as performance and appearance as necessary, they are stored in tray jigs and shipped.
[0053] 以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが 、本発明は前記実施の形態に限定されるものではなぐその要旨を逸脱しない範囲 で種々変更可能であることは 、うまでもな!/、。  As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. There's nothing wrong!
産業上の利用可能性  Industrial applicability
[0054] 本発明は、半導体装置を製造する製造業に幅広く利用することができる。 The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

Claims

請求の範囲 The scope of the claims
[1] 半導体ウェハの状態でパッケージングを完了する半導体装置の製造方法であって  [1] A method of manufacturing a semiconductor device that completes packaging in the state of a semiconductor wafer.
(a)前記半導体ウェハに内部接続端子を形成する工程と、 (a) forming internal connection terminals on the semiconductor wafer;
(b)前記内部接続端子に一端部を接続する再配線を形成する工程と、 (b) forming a rewiring that connects one end to the internal connection terminal;
(c)前記再配線の他端部に接続する外部接続端子を形成する工程とを備え、 前記 (b)工程は、 (c) a step of forming an external connection terminal connected to the other end of the rewiring, and the step (b)
(bl)電解めつき法を使用してニッケル膜を形成する工程を含み、  (bl) including a step of forming a nickel film using an electrolytic plating method,
前記 (bl)工程は、  The step (bl)
前記半導体ウェハ上に前記ニッケル膜を形成するめつき処理槽とは別の槽であつ て前記めつき処理槽との間でめっき液を循環させるめっき液貯蔵槽のめつき液流入 部、めっき液流出部およびめつき液の表層部に磁石を配置しながら、前記ニッケル 膜を前記めつき処理槽で形成することを特徴とする半導体装置の製造方法。  A plating solution inflow section of a plating solution storage tank that circulates the plating solution between the plating treatment tank and a plating treatment tank that is separate from the plating treatment tank for forming the nickel film on the semiconductor wafer. The nickel film is formed in the plating process tank while a magnet is disposed on the surface layer portion of the plating solution and the plating solution.
[2] 前記めつき液流入部には堰が設けられ、前記堰内に前記磁石が配置されているこ とを特徴とする請求項 1記載の半導体装置の製造方法。  2. The method for manufacturing a semiconductor device according to claim 1, wherein a weir is provided in the infusion portion of the plating liquid, and the magnet is disposed in the weir.
[3] さらに前記めつき液貯蔵槽にあるめつき液の底部にも磁石が配置されていることを 特徴とする請求項 1記載の半導体装置の製造方法。  [3] The method for manufacturing a semiconductor device according to [1], wherein a magnet is also arranged at the bottom of the plating solution in the plating solution storage tank.
[4] 前記めつき液は毎分 30リットル以上毎分 50リットル以下の流量で前記めつき処理 槽と前記めつき液貯蔵槽とを循環していることを特徴とする請求項 1記載の半導体装 置の製造方法。  [4] The semiconductor according to claim 1, wherein the plating solution is circulated between the plating processing tank and the plating solution storage tank at a flow rate of 30 to 50 liters per minute. Device manufacturing method.
[5] 前記 (b)工程は、電解めつき法を使用して銅膜を形成した後、さらに電解めつき法 を使用して前記銅膜上にニッケル膜を形成することを特徴とする請求項 1記載の半 導体装置の製造方法。  [5] The step (b) is characterized in that after forming a copper film using an electrolytic plating method, a nickel film is further formed on the copper film using an electrolytic plating method. A method for manufacturing a semiconductor device according to Item 1.
[6] 前記磁石は、フッ素榭脂で覆われていることを特徴とする請求項 1記載の半導体装 置の製造方法。  6. The method of manufacturing a semiconductor device according to claim 1, wherein the magnet is covered with fluorine resin.
[7] 前記めつき液貯蔵槽は、複数の前記めつき液処理槽と接続されて ヽることを特徴と する請求項 1記載の半導体装置の製造方法。  7. The method for manufacturing a semiconductor device according to claim 1, wherein the plating liquid storage tank is connected to a plurality of the plating liquid processing tanks.
[8] (a)半導体基板上に内部接続端子を形成する工程と、 (b)前記内部接続端子上に第 1絶縁膜を形成した後、前記内部接続端子上の前記 第 1絶縁膜に第 1開口部を形成する工程と、 [8] (a) forming an internal connection terminal on the semiconductor substrate; (b) after forming a first insulating film on the internal connection terminal, forming a first opening in the first insulating film on the internal connection terminal;
(c)前記内部接続端子上を含む前記第 1絶縁膜上に再配線を形成する工程と、 (c) forming a rewiring on the first insulating film including on the internal connection terminal;
(d)前記再配線上に第 2絶縁膜を形成する工程と、 (d) forming a second insulating film on the rewiring;
(e)前記第 2絶縁膜に第 2開口部を形成して前記再配線の一部を露出する工程と、 (e) forming a second opening in the second insulating film to expose a part of the rewiring;
(f)前記第 2開口部上に外部接続端子を形成する工程とを備え、 (f) forming an external connection terminal on the second opening,
前記 (c)工程は、  The step (c)
(cl)電解めつき法を使用してニッケル膜を形成する工程を含み、  (cl) forming a nickel film using an electrolytic plating method,
前記 (cl)工程は、  The step (cl)
前記半導体基板上にニッケル膜を形成するめつき処理槽とは別の槽であって前記 めっき処理槽との間でめっき液を循環させるめっき液貯蔵槽のめつき液流入部、めつ き液流出部およびめつき液の表層部に磁石を配置しながら、前記ニッケル膜を前記 めっき処理槽で形成することを特徴とする半導体装置の製造方法。  A plating solution inflow section and a plating solution outflow of a plating solution storage tank that is separate from the plating treatment tank for forming a nickel film on the semiconductor substrate and circulates the plating solution between the plating treatment tank and the plating treatment tank. The nickel film is formed in the plating tank while arranging magnets on the surface portion and the surface layer portion of the plating solution.
[9] 前記めつき液流入部には堰が設けられ、前記堰内に前記磁石が配置されているこ とを特徴とする請求項 8記載の半導体装置の製造方法。  9. The method for manufacturing a semiconductor device according to claim 8, wherein a weir is provided at the infusion portion of the plating liquid, and the magnet is disposed in the weir.
[10] さらに前記めつき液貯蔵槽にあるめつき液の底部にも磁石が配置されていることを 特徴とする請求項 8記載の半導体装置の製造方法。 10. The method of manufacturing a semiconductor device according to claim 8, wherein a magnet is also arranged at the bottom of the plating solution in the plating solution storage tank.
[11] 前記めつき液は毎分 30リットル以上毎分 50リットル以下の流量で前記めつき処理 槽と前記めつき液貯蔵槽とを循環していることを特徴とする請求項 8記載の半導体装 置の製造方法。 [11] The semiconductor according to claim 8, wherein the nail solution circulates between the nail treatment tank and the nail solution storage tank at a flow rate of 30 liters per minute or more and 50 liters or less per minute. Device manufacturing method.
[12] 前記 (c)工程は、電解めつき法を使用して銅膜を形成した後、さらに電解めつき法 を使用して前記銅膜上にニッケル膜を形成することを特徴とする請求項 8記載の半 導体装置の製造方法。  [12] The step (c) is characterized in that after the copper film is formed using an electrolytic plating method, a nickel film is further formed on the copper film using the electrolytic plating method. Item 9. A method of manufacturing a semiconductor device according to Item 8.
[13] 前記磁石は、フッ素榭脂で覆われていることを特徴とする請求項 8記載の半導体装 置の製造方法。  13. The method of manufacturing a semiconductor device according to claim 8, wherein the magnet is covered with fluorine resin.
[14] 前記めつき液貯蔵槽は、複数の前記めつき液処理槽と接続されて ヽることを特徴と する請求項 8記載の半導体装置の製造方法。  14. The method for manufacturing a semiconductor device according to claim 8, wherein the plating liquid storage tank is connected to a plurality of the plating liquid processing tanks.
PCT/JP2004/019602 2004-12-28 2004-12-28 Method for manufacturing semiconductor device WO2006070452A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008211187A (en) * 2007-02-26 2008-09-11 Nepes Corp Semiconductor package and method of manufacturing the same
JP2008276069A (en) * 2007-05-02 2008-11-13 Ricoh Co Ltd Developer supply member, developing device, process cartridge, image forming apparatus and developer supply method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09137299A (en) * 1995-11-08 1997-05-27 Kao Corp Plating liquid preparing vessel
JPH1088387A (en) * 1996-09-18 1998-04-07 Yamaha Motor Co Ltd Plating device
JPH10118634A (en) * 1996-10-16 1998-05-12 Minamimachi Sangyo Kk Filter apparatus
JP2003183896A (en) * 2001-12-17 2003-07-03 Nec Electronics Corp Plating apparatus
JP2003227000A (en) * 2002-02-05 2003-08-15 Tokushu Giken Kk Implement for removing iron powder in chrome plating solution, device for removing iron powder and method of removing iron powder
JP2004193211A (en) * 2002-12-09 2004-07-08 Hitachi Ltd Electronic component and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09137299A (en) * 1995-11-08 1997-05-27 Kao Corp Plating liquid preparing vessel
JPH1088387A (en) * 1996-09-18 1998-04-07 Yamaha Motor Co Ltd Plating device
JPH10118634A (en) * 1996-10-16 1998-05-12 Minamimachi Sangyo Kk Filter apparatus
JP2003183896A (en) * 2001-12-17 2003-07-03 Nec Electronics Corp Plating apparatus
JP2003227000A (en) * 2002-02-05 2003-08-15 Tokushu Giken Kk Implement for removing iron powder in chrome plating solution, device for removing iron powder and method of removing iron powder
JP2004193211A (en) * 2002-12-09 2004-07-08 Hitachi Ltd Electronic component and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008211187A (en) * 2007-02-26 2008-09-11 Nepes Corp Semiconductor package and method of manufacturing the same
JP2008276069A (en) * 2007-05-02 2008-11-13 Ricoh Co Ltd Developer supply member, developing device, process cartridge, image forming apparatus and developer supply method

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