WO2006051612A1 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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Publication number
WO2006051612A1
WO2006051612A1 PCT/JP2004/016934 JP2004016934W WO2006051612A1 WO 2006051612 A1 WO2006051612 A1 WO 2006051612A1 JP 2004016934 W JP2004016934 W JP 2004016934W WO 2006051612 A1 WO2006051612 A1 WO 2006051612A1
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WO
WIPO (PCT)
Prior art keywords
circuit
clock
semiconductor integrated
integrated circuit
clock supply
Prior art date
Application number
PCT/JP2004/016934
Other languages
French (fr)
Japanese (ja)
Inventor
Yoshiyuki Motoba
Noboru Sugihara
Toshikazu Yanagihara
Minoru Uchita
Hiroyuki Orihara
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2004/016934 priority Critical patent/WO2006051612A1/en
Priority to JP2006544716A priority patent/JPWO2006051612A1/en
Publication of WO2006051612A1 publication Critical patent/WO2006051612A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Definitions

  • the present invention relates to clock control of a semiconductor integrated circuit, for example, a clock supply stop mode (for example, low power consumption) that stops clock synchronous operation in a circuit module while maintaining supply of operating power to a circuit module after a power-on reset.
  • a clock supply stop mode for example, low power consumption
  • the present invention relates to a technology that is effective when applied to a data processor that enables setting of a power mode.
  • Patent Document 1 by supplying clock signals with different phases for each block of a semiconductor integrated circuit, the rate of simultaneous change is reduced to reduce instantaneous power consumption, thereby suppressing malfunctions due to radiation noise. Techniques to do are described.
  • Patent Document 2 regarding power-on of a system to a plurality of computer devices, a counter is provided for each device, a different count target value is set based on a unique manufacturing number of the computer device, and a count value is set. It is described that the inrush current is reduced by shifting the power-on time for the computer device based on the difference in the timing when the value reaches the target value.
  • Patent Document 1 JP 2002-366250 A
  • Patent Document 2 JP-A-7-253832
  • the present inventor has examined an undesired decrease in the operating power supply when returning from the low power consumption mode after power-on reset to the normal mode.
  • operation power is supplied to the circuit module, so the storage nodes in the combinational circuit and sequential circuit in the circuit module statically hold the state when the low power consumption mode is set. be able to. If the low power consumption mode is canceled, the interrupted operation can be resumed from the middle. Therefore, if stored information such as register information held in the circuit module is destroyed when the low power consumption mode is set, malfunctions cannot be avoided after the low power consumption mode is canceled.
  • the inventor has low power consumption When canceling the mode, restarting clock supply to many circuit modules at the same time will generate an inrush current, and the operating power supply voltage will fall below the allowable voltage, causing the storage information such as the register information to be undesired. It was found that there is a risk of being destroyed.
  • This data destruction problem is an inherent problem in the low power consumption mode where the clock synchronization operation is stopped while retaining the internal information.
  • a voltage drop becomes apparent when a power source with a small power capacity is used.
  • semiconductor integrated circuits are being provided in which an internal power supply is stepped down by a step-down circuit that operates an internal circuit at a low voltage. The current supply capability of the circuit is limited, and it has become clear that there is a higher possibility of data corruption when returning from such a low power consumption mode than when an external power supply is used directly.
  • An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing a situation in which internal information held in a circuit module is undesirably destroyed when returning from a clock supply stop mode.
  • a semiconductor integrated circuit includes a control circuit and other circuit modules that operate in synchronization with a clock signal, and maintains a supply of operating power to the circuit module after a power-on reset.
  • the clock supply stop mode can be set to stop the clock signal supply operation to the inside, and when the control circuit cancels the clock supply stop mode, the internal clock supply operation is started among a plurality of circuit modules. Control that shifts the timing is enabled.
  • a central processing unit is provided as one of the circuit modules, and the central processing unit is capable of write access to the register.
  • the central processing unit instructs the setting of the clock supply stop mode, and the release of the clock supply stop mode is an external signal supplied from the outside of the semiconductor integrated circuit Directed by The external signal is, for example, an interrupt request signal.
  • step-down circuit that steps down an external power supply voltage to generate an internal power supply voltage
  • the circuit module is an internal power supply that outputs the step-down circuit power as an operation power supply. Use the power supply voltage.
  • the semiconductor integrated circuit includes a control circuit and another circuit module that operates in synchronization with the clock signal, and maintains a supply of operation power to the circuit module after a power-on reset.
  • the control circuit is enabled to set a clock supply stop mode for stopping the operation of supplying the clock signal to the inside.
  • the control circuit receives the instruction to set the clock supply stop mode from a predetermined circuit module. The clock supply operation to the other circuit modules and other circuit modules is stopped, and when the clock supply stop mode is released, the start timing of the internal clock supply operation can be shifted among multiple circuit modules. Is done.
  • the predetermined one circuit module is a central processing unit, and the control circuit is given an instruction to cancel the clock supply stop mode from the outside of the semiconductor integrated circuit.
  • the control circuit has a register that can be accessed for writing by the central processing unit, and the data set in the register cancels the clock supply stop mode. This specifies the amount of deviation in the start timing of the clock supply operation that is shifted between multiple circuit modules.
  • step-down circuit that generates an internal power supply voltage by stepping down an external power supply voltage, and the circuit module uses the internal power supply voltage output as the operation power supply.
  • FIG. 1 is a block diagram of a data processor according to an example of a semiconductor integrated circuit according to the present invention.
  • FIG. 2 is a block diagram showing an example of a low power consumption control circuit.
  • FIG. 3 is a timing chart showing an operation when canceling a low power consumption mode.
  • FIG. 4 is a block diagram of a data processor according to a comparative example in which clock supply to circuit modules is performed simultaneously for all circuit modules when returning from the low power consumption mode.
  • FIG. 5 is a block diagram showing an example of a low power consumption control circuit in the data processor according to the comparative example of FIG.
  • FIG. 6 is a timing chart showing an operation when the low power consumption mode is canceled in the data processor according to the comparative example of FIG.
  • FIG. 1 shows a data processor as an example of a semiconductor integrated circuit according to the present invention.
  • the data processor shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a CMOS integrated circuit manufacturing technique.
  • the data processor (MPU) 1 includes a central processing unit (CPU) 2, a representative input / output circuit module (MDLA) 3, a representative memory module (MDLB) 4, and a clock pulse.
  • a generator (CPG) 5, a step-down circuit (SDC) 6, and a low power consumption control circuit (PD CM) 7 are included.
  • the central processing unit 2 includes an instruction control unit that decodes an instruction execution procedure and an instruction, and an instruction execution unit that executes an instruction by performing an address operation or a data operation according to an instruction decoding result.
  • the step-down circuit 6 steps down the external power supply voltage VDD to generate the internal power supply voltage vdd.
  • the internal circuit of data processor 1 directly uses the external power supply voltage VDD.
  • It consists of a first circuit that uses the operating power supply, a second circuit that uses the internal power supply voltage as the operating power supply, and a third circuit that uses both as the operating power supply.
  • CPU 2 and memory module 4 are composed of the second circuit.
  • a noferr interfaced with the outside is configured by the first circuit, and a logic unit for performing input / output control, a data latch, and the like are configured by the second circuit.
  • the first circuit and the second circuit The level shift circuit that connects to is composed of the third circuit.
  • the low power consumption control circuit 7 outputs an oscillation control signal ⁇ OSC and a clock supply enable signal ⁇ S PLA, ⁇ SPLB, and ⁇ SPLC.
  • the clock pulse generator 5 starts oscillating in response to the high level of the oscillation control signal ⁇ OSC and outputs the clock signal CLK.
  • the clock supply enable signal ⁇ SPLA is set to the high level
  • the input / output circuit module 3 can supply the clock signal CLK to the inside and can operate synchronously with the clock signal CLK.
  • the clock supply enable signal ⁇ SPLB is set to the high level
  • the memory module 4 can supply the clock signal CLK internally, and can operate synchronously with the clock signal CLK.
  • the CPU 2 can supply the clock signal CLK internally and can operate synchronously with the clock signal CLK.
  • the CPU 2 asserts the low power consumption control signal ⁇ PDS to a high level by executing a transition routine to the low power consumption mode by executing a predetermined instruction, setting a bit to a predetermined register, an interrupt, or the like.
  • the low power consumption control circuit 7 stops the supply of the clock signal CLK to the input / output circuit module (MDLA) 3, the memory module (MDLB) 4, and the CPU 2 and sets the low power consumption mode in the data processor 1. Is done.
  • the internal power supply such as the input / output circuit module (MDLA) 3, the memory module (MDLB) 4, and the CPU 2 is maintained.
  • the low power consumption mode is an operation mode that can be set after a power-on reset.
  • the low power consumption control circuit 7 shifts the enable timing of the clock supply enable signals ⁇ SPLA, ⁇ SPLB, ⁇ SPLC, and Control to shift the supply start timing of the clock signal CLK to the module 3, the memory module 4, and the CPU 2 is made possible.
  • External signal ACT is an interrupt signal such as NMI (non-maskable 'interrupt), for example.
  • NMI non-maskable 'interrupt
  • FIG. 2 illustrates a logical configuration of the low power consumption control circuit 7.
  • the logic circuit (CNT) 10 is supplied with a low power consumption control signal ⁇ i) PDS, a representative external signal ACT, and a power-on reset signal (not shown) .
  • the control signal ⁇ RST, ⁇ S ET is output.
  • the control signal 0 RST is supplied to the reset terminal (R) of the flip-flops (FF) 11 and 20-22, and the control signal ⁇ SET is supplied to the set terminal (S) of the flip-flop 11.
  • the output of flip-flop 11 is used as the oscillation control signal ⁇ OSC. Not shown No.
  • the logic circuit 10 sets the flip-flop 11 by the control signal ⁇ SET. Oscillation control signal ⁇ OSC is set to the noise level, and clock pulse generator 5 starts oscillation.
  • the logic circuit 10 resets the flip-flop 11 with the control signal ⁇ RST and sets the oscillation control signal ⁇ OSC to the low level to the clock pulse generator 5 Stops oscillation.
  • Counter (CUNT) 12 counts the divided clock from frequency divider (DIV) 13 as count-up signal ⁇ UP in response to the change of oscillation control signal ⁇ OSC to high level.
  • a comparison circuit (CMPA) 17 that detects whether the count value NMB of the counter 12 has reached the set value of the register (REGA) 14 is provided, and the detection signal ⁇ of the comparison circuit 17 is received at the set terminal (S).
  • a flip-flop (FF) 20 for receiving the control signal ⁇ RST at the reset terminal (R) and outputting the clock supply enable signal ⁇ SPLA is provided.
  • the flip-flop (FF) 20 is reset at the high level of the control signal ⁇ RST, and the clock supply enable signal ⁇ SPLA is negated to a low level, so that the clock supply to the inside of MDLA3 is cut off. After this, the oscillation control signal ⁇ i) The count value of the counting operation started in synchronization with the high level change of OSC.
  • the flip-flop 20 is set only after the NMB reaches the value of the register 14, and the clock supply enable signal Since ⁇ SPLA is asserted high, clock supply to MDLA3 is started.
  • CMPB comparison circuit
  • the oscillation control signal ⁇ i) The count value of the counting operation started in synchronization with the high level change of OSC, the flip-flop 21 is set only when the value NMB reaches the value in register 15, and the clock supply enable signal ⁇ SPLB is asserted high, so the clock supply to MDLB4 is started.
  • CMPC comparison circuit
  • the clock supply enable signal () SPLA, SPLB, ⁇ SPLC assertion timing to the high level can be variably shifted according to the set values of the registers 14, 15, and 16. For example, if the set values of all the registers 14, 15, 16 are made equal, the supply of the clock signal CLK to the MDL A3, MDLB4, and CPU2 is started simultaneously. If the set values of registers 14 and 15 are equal, supply of the clock signal CLK to MDLA3 and MDLB4 is started at the same time, and the timing of clock supply to CPU2 is different. If the set values of the three registers 14, 15, and 16 are made different from each other, the supply timing of the clock signal CLK to the MDLA3, MDLB4, and CPU2 can be sequentially shifted. In FIG.
  • reference numeral 23 denotes a clock distribution circuit (DSB).
  • the clock signal CLK is divided into the logic circuit 10, the counter 12, the registers 14, 15, 16, and the flip-flops 11, 20-22, This is supplied to the clock frequency divider circuit 13.
  • the clock divider circuit 13 divides the clock signal CLK to generate the count up signal ⁇ UP.
  • FIG. 3 shows the operation timing when the low power consumption mode is canceled.
  • the clock signal CLK is 50 MHz
  • the division ratio by the clock divider 13 is 256.
  • the setting value of register (REGA) 14 is Hex32 in hexadecimal
  • the setting value of register (RE GB) 15 is Hex40 in hexadecimal
  • the setting value of register (REGC) 16 is Hex48 in hexadecimal.
  • the oscillation control signal 0 OSC is set to the low level, and the oscillation operation of the clock pulse generator 5 is stopped.
  • the flip-flop 11 When the external signal ACT is asserted at time tO, the flip-flop 11 is set by the set signal ⁇ SET, and the clock pulse generator 5 starts oscillating at the high level of the oscillation control signal ⁇ OSC. At this time, since the flip-flops 20-22 are reset by the high level control signal 0 RST, the clock supply enable signal ⁇ SPLA— ⁇ SPLC is negated to the low level, and the time tO power clock pulse Even when the generator 5 starts oscillating, the supply of the clock signal CLK to the inside of the circuit modules 2-4 is still maintained in the cut-off state.
  • the count value of the count operation started in synchronization with the high level change of the oscillation control signal ⁇ OSC.
  • NMB reaches the set value (Hex32) in register 14
  • flip-flop 20 is set and clock is supplied.
  • the enable signal ⁇ SPLA is asserted high, and this starts the supply of the clock signal CLK to the inside of MDLA3.
  • the clock signal CLK is supplied, the MDLA3 tries to change its internal state all at once in response to the change of the clock signal CLK, which causes a relatively large inrush current to flow inside the MDLA3, thereby causing the internal power supply to change.
  • the voltage vdd drops.
  • the internal power supply voltage Vdd is rated at 3.2V, and the operation guarantee lower limit voltage is 2.7V.
  • the inrush current at this time is Ircl, and the voltage drop due to this is assumed to be 2.8V, which is the minimum operating guarantee voltage of 2.7V.
  • the time for which the voltage drop due to the inrush current Ire is, for example, 20 microseconds). It takes 40.96 ⁇ s (8 counts) by time t2 when the count value NMB reaches the set value of register 15 (Hex40), and the voltage drop that started at time tl has already converged at time t2.
  • the group of circuit modules for shifting the clock supply timing may be determined so that the voltage drop due to the inrush current does not become lower than the operation guarantee lower limit voltage. For example, if it is clear that the voltage drop does not become lower than the operation guarantee lower limit voltage even when the clock supply to MDLA3 and MDLB4 is started together, do so in terms of shortening the recovery time of the low power consumption mode. Is good.
  • the set value of the register corresponding to the circuit module that first starts supplying the clock signal may be determined in consideration of the oscillation stabilization time of the clock signal. The difference in the register setting value corresponding to the circuit module whose clock supply timing is changed should be determined in consideration of the convergence time of the voltage drop due to the inrush current generated in the previous stage.
  • FIGS. 4 to 6 illustrate a configuration according to a comparative example in which the clock supply to the circuit modules is performed simultaneously for all the circuit modules when returning from the low power consumption mode.
  • 0 SPL is shared by circuit modules (MDLA, MDLB, CPU).
  • the counter (CUNT) sets the flip-flop (FF) with a predetermined carry signal at the timing when the oscillation stabilization time elapses and sets the clock supply enable signal ⁇ SPL. Assert.
  • the low power consumption mode is instructed at time to, and the clock signal to the circuit modules (MDLA, MDLB, CPU) is received at time tl when the oscillation stabilization time has elapsed.
  • the supply of the issue begins. All circuit modules (MDLA, MDLB, CPU)- ⁇ Since the clock signal supply starts all at once, a large inrush current Irc4 flows at once compared to Fig. 3, and the voltage drop is below the guaranteed operating voltage. It is expected that the internal state of the internal circuit such as register information held in the low power consumption state will be destroyed, and the control operation will not be guaranteed when returning from the low power consumption mode. For example, if the values of the general-purpose registers of the CPU and the control registers of the peripheral circuits are destroyed, the computation control operation cannot be continued normally even if the CPU exits the low power consumption mode.
  • the setting of the registers 14-16 is not limited to setting by access by the CPU. You may set by hardware at the time of reset. Of course, subsequent rewriting by the CPU is guaranteed.
  • the register initial value should be initialized by hardware at reset. At power-on reset, it is normal that information that is lost due to a voltage drop and inconvenient information is not yet retained, so each register setting value can be the same. From the beginning, it is not hindered to make a difference considering the return from the low power consumption mode.
  • the low power consumption control circuit is also configured to perform clock control at the time of power-on reset, it is a matter of course that another logic configuration may be adopted for clock oscillation control at the time of power-on reset. is there. In general, information that is lost due to a voltage drop at the time of power-on reset is still retained.
  • the configuration of the present invention is a data having such an internal voltage down circuit, especially considering the case where the current supply capacity of the internal voltage down converter is low. Suitable for a processor.
  • the circuit module is not limited to the input / output circuit module, the memory module, and the CPU, and can be changed as appropriate.
  • the present invention maintains the supply of operating power to the circuit module after a power-on reset.
  • the present invention can be widely applied to semiconductor integrated circuits such as data processors that can be set to a clock supply stop mode that stops the clock synchronization operation in the circuit module.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor integrated circuit has a control circuit (7) and circuit modules (2, 3, 4) operating synchronously with a clock signal. A clock supply stop mode in which supply of a clock signal (CLK) to the circuit modules is stopped while the supply of the operating power to the circuit modules after power-on reset is maintained can be set. The control circuit can control the start timings of clock supply to the inside of the circuit modules in such a way that the start timings are shifted from one another when the clock supply stop mode is cancelled. By thus shifting the start timings from one another, the magnitudes of the rush currents caused in the circuit modules are reduced, and consequently significant drop of the power supply voltage can be suppressed.

Description

明 細 書  Specification
半導体集積回路  Semiconductor integrated circuit
技術分野  Technical field
[0001] 本発明は半導体集積回路のクロック制御に関し、例えばパワーオンリセット後に回 路モジュールへの動作電源の供給を維持したまま回路モジュール内のクロック同期 動作を停止するクロック供給停止モード (例えば低消費電力モードと称される）の設 定が可能にされるデータプロセッサに適用して有効な技術に関する。  The present invention relates to clock control of a semiconductor integrated circuit, for example, a clock supply stop mode (for example, low power consumption) that stops clock synchronous operation in a circuit module while maintaining supply of operating power to a circuit module after a power-on reset. The present invention relates to a technology that is effective when applied to a data processor that enables setting of a power mode.
背景技術  Background art
[0002] 特許文献 1には、半導体集積回路のブロック毎に位相の異なるクロック信号を供給 することで同時変化の割合を減らして瞬時電力消費量を低減し、輻射ノイズによる動 作の不具合を抑制する技術が記載される。  [0002] In Patent Document 1, by supplying clock signals with different phases for each block of a semiconductor integrated circuit, the rate of simultaneous change is reduced to reduce instantaneous power consumption, thereby suppressing malfunctions due to radiation noise. Techniques to do are described.
[0003] 特許文献 2には、複数のコンピュータ装置に対するシステムの電源投入に関し、装 置毎にカウンタを設け、コンピュータ装置の固有の製造番号に基づいて相違するカウ ント目標値を設定し、カウント値が目標値に達するタイミングの相違に基づ 、てコンビ ユータ装置に対する電源投入時間をずらして突入電流を減らすことが記載される。  [0003] In Patent Document 2, regarding power-on of a system to a plurality of computer devices, a counter is provided for each device, a different count target value is set based on a unique manufacturing number of the computer device, and a count value is set. It is described that the inrush current is reduced by shifting the power-on time for the computer device based on the difference in the timing when the value reaches the target value.
[0004] 特許文献 1：特開 2002-366250号公報  [0004] Patent Document 1: JP 2002-366250 A
特許文献 2：特開平 7-253832号公報  Patent Document 2: JP-A-7-253832
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] 本発明者は、パワーオンリセット後の低消費電力モードから通常モードに復帰する ときの動作電源の不所望な低下について検討した。低消費電力モードでは回路モジ ユールには動作電源が供給されているから、回路モジュール内の組み合わせ回路や 順序回路における記憶ノードは低消費電力モードが設定されたときの状態をスタティ ックに保持することができる。低消費電力モードが解除されれば、中断された動作を 途中から再開することができる。したがって、低消費電力モードが設定されているとき 回路モジュール内で保持されているレジスタ情報などの記憶情報が破壊されれば、 低消費電力モードが解除された後に誤動作を免れない。本発明者は、低消費電力 モードを解除するとき、一度に多くの回路モジュールに同じタイミングでクロックの供 給を再開すると突入電流を生じ、動作電源電圧が許容電圧以下になって、前記レジ スタ情報などの記憶情報が不所望に破壊される虞のあることを見出した。このデータ 破壊の問題は内部情報を保持したままでクロック同期動作を停止する低消費電力モ ードにおける固有の課題である。し力も、そのような電圧低下は、電力容量の小さな 電源を用いる場合に顕在化される。今日、低消費電力や動作速度の高速化の観点 より、外部電源を内蔵される降圧回路で降圧して内部回路を低電圧動作させるように した半導体集積回路が提供されており、そのような降圧回路による電流供給能力に は限りがあり、外部電源を直接用いる場合よりもそのような低消費電力モードから復 帰するときのデータ破壊の可能性が高いことが明らかになった。 [0005] The present inventor has examined an undesired decrease in the operating power supply when returning from the low power consumption mode after power-on reset to the normal mode. In the low power consumption mode, operation power is supplied to the circuit module, so the storage nodes in the combinational circuit and sequential circuit in the circuit module statically hold the state when the low power consumption mode is set. be able to. If the low power consumption mode is canceled, the interrupted operation can be resumed from the middle. Therefore, if stored information such as register information held in the circuit module is destroyed when the low power consumption mode is set, malfunctions cannot be avoided after the low power consumption mode is canceled. The inventor has low power consumption When canceling the mode, restarting clock supply to many circuit modules at the same time will generate an inrush current, and the operating power supply voltage will fall below the allowable voltage, causing the storage information such as the register information to be undesired. It was found that there is a risk of being destroyed. This data destruction problem is an inherent problem in the low power consumption mode where the clock synchronization operation is stopped while retaining the internal information. However, such a voltage drop becomes apparent when a power source with a small power capacity is used. Nowadays, from the viewpoint of low power consumption and high operating speed, semiconductor integrated circuits are being provided in which an internal power supply is stepped down by a step-down circuit that operates an internal circuit at a low voltage. The current supply capability of the circuit is limited, and it has become clear that there is a higher possibility of data corruption when returning from such a low power consumption mode than when an external power supply is used directly.
[0006] 本発明の目的は、回路モジュールで保持されて内部情報がクロック供給停止モー ドからの復帰に際して不所望に破壊される事態を抑制することができる半導体集積 回路を提供することにある。  [0006] An object of the present invention is to provide a semiconductor integrated circuit capable of suppressing a situation in which internal information held in a circuit module is undesirably destroyed when returning from a clock supply stop mode.
[0007] 本発明の前記並びにその他の目的と新規な特徴は本明細書の記述及び添付図面 力 明らかになるであろう。  [0007] The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
課題を解決するための手段  Means for solving the problem
[0008] 本願において開示される発明のうち代表的なものの概要を簡単に説明すれば下記 の通りである。 [0008] The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.
[0009] 〔1〕半導体集積回路は、制御回路と、クロック信号に同期動作するその他の回路モ ジュールとを有し、パワーオンリセット後に回路モジュールへの動作電源の供給を維 持したまま回路モジュール内へのクロック信号の供給動作を停止するクロック供給停 止モードの設定が可能にされ、前記制御回路は前記クロック供給停止モードを解除 するとき複数の回路モジュール間で内部へのクロック供給動作の開始タイミングをず らす制御が可能にされる。  [1] A semiconductor integrated circuit includes a control circuit and other circuit modules that operate in synchronization with a clock signal, and maintains a supply of operating power to the circuit module after a power-on reset. The clock supply stop mode can be set to stop the clock signal supply operation to the inside, and when the control circuit cancels the clock supply stop mode, the internal clock supply operation is started among a plurality of circuit modules. Control that shifts the timing is enabled.
[0010] 前記クロック供給停止モードを解除するとき複数の回路モジュール間で内部へのク ロック供給動作の開始タイミングをずらすことにより、回路モジュールで発生する突入 電流の大きさが抑えられ、これにより、電源電圧が大きく降下する事態の発生を抑制 することができる。 [0011] 本発明の具体的形態として、前記開始タイミングをずらす制御に用いる制御データ が設定されるレジスタを有する。前記レジスタの設定値は開始タイミングのずれ量を 指定する。半導体集積回路に利用する電源電圧やクロック周波数の相違に対して前 記ずれ量を最適化するのが容易になる。 [0010] When the clock supply stop mode is canceled, by shifting the start timing of the clock supply operation to the inside among a plurality of circuit modules, the magnitude of the inrush current generated in the circuit modules can be suppressed. The occurrence of a situation where the power supply voltage drops significantly can be suppressed. [0011] As a specific form of the present invention, there is provided a register in which control data used for control for shifting the start timing is set. The set value of the register specifies the amount of start timing deviation. It becomes easy to optimize the deviation amount with respect to the difference in power supply voltage and clock frequency used in the semiconductor integrated circuit.
[0012] 本発明の別の具体的形態として、前記回路モジュールの一つとして中央処理装置 を有し、前記中央処理装置は前記レジスタに対する書き込みアクセス可能である。  As another specific form of the present invention, a central processing unit is provided as one of the circuit modules, and the central processing unit is capable of write access to the register.
[0013] 本発明の更に別の具体的形態として、前記クロック供給停止モードの設定は前記 中央処理装置が指示し、前記クロック供給停止モードの解除は半導体集積回路の外 部から供給される外部信号によって指示される。前記外部信号は例えば割り込み要 求信号である。  As yet another specific form of the present invention, the central processing unit instructs the setting of the clock supply stop mode, and the release of the clock supply stop mode is an external signal supplied from the outside of the semiconductor integrated circuit Directed by The external signal is, for example, an interrupt request signal.
[0014] 本発明の更に別の具体的形態として、外部電源電圧を降圧して内部電源電圧を生 成する降圧回路を有し、前記回路モジュールは動作電源として前記降圧回路力 出 力される内部電源電圧を用いる。  [0014] As yet another specific form of the present invention, there is a step-down circuit that steps down an external power supply voltage to generate an internal power supply voltage, and the circuit module is an internal power supply that outputs the step-down circuit power as an operation power supply. Use the power supply voltage.
[0015] 〔2〕半導体集積回路は、制御回路と、クロック信号に同期動作するその他の回路モ ジュールとを有し、パワーオンリセット後に回路モジュールへの動作電源の供給を維 持したまま回路モジュール内へのクロック信号の供給動作を停止するクロック供給停 止モードの設定が可能にされる、前記制御回路は、所定の一の回路モジュールから 前記クロック供給停止モードを設定する指示を受けて前記一の回路モジュール及び 他の回路モジュール内へのクロック供給動作を停止させ、前記クロック供給停止モー ドを解除するとき複数の回路モジュール間で内部へのクロック供給動作の開始タイミ ングをずらす制御が可能にされる。  [2] The semiconductor integrated circuit includes a control circuit and another circuit module that operates in synchronization with the clock signal, and maintains a supply of operation power to the circuit module after a power-on reset. The control circuit is enabled to set a clock supply stop mode for stopping the operation of supplying the clock signal to the inside. The control circuit receives the instruction to set the clock supply stop mode from a predetermined circuit module. The clock supply operation to the other circuit modules and other circuit modules is stopped, and when the clock supply stop mode is released, the start timing of the internal clock supply operation can be shifted among multiple circuit modules. Is done.
[0016] 前記クロック供給停止モードを解除するとき複数の回路モジュール間で内部へのク ロック供給動作の開始タイミングをずらすことにより、回路モジュールで発生する突入 電流の大きさが抑えられ、これにより、電源電圧が大きく降下する事態の発生を抑制 することができる。  [0016] When the clock supply stop mode is canceled, by shifting the start timing of the clock supply operation to the inside among a plurality of circuit modules, the magnitude of the inrush current generated in the circuit modules can be suppressed. The occurrence of a situation where the power supply voltage drops significantly can be suppressed.
[0017] 本発明の具体的形態として、前記所定の一の回路モジュールは中央処理装置で あり、前記制御回路は前記クロック供給停止モードを解除する指示が半導体集積回 路の外部から与えられる。 [0018] 本発明の更に具体的形態として、前記制御回路は、前記中央処理装置によって書 き込みアクセス可能にされるレジスタを有し、前記レジスタに設定されるデータは前記 クロック供給停止モードを解除するとき複数の回路モジュールの間でずらされるクロッ ク供給動作の開始タイミングのずれ量を規定する。 As a specific form of the present invention, the predetermined one circuit module is a central processing unit, and the control circuit is given an instruction to cancel the clock supply stop mode from the outside of the semiconductor integrated circuit. As a more specific form of the present invention, the control circuit has a register that can be accessed for writing by the central processing unit, and the data set in the register cancels the clock supply stop mode. This specifies the amount of deviation in the start timing of the clock supply operation that is shifted between multiple circuit modules.
[0019] 本発明の更に具体的形態として、外部電源電圧を降圧して内部電源電圧を生成 する降圧回路を有し、前記回路モジュールは動作電源として前記降圧回路力 出力 される内部電源電圧を用いる。  As a more specific form of the present invention, there is a step-down circuit that generates an internal power supply voltage by stepping down an external power supply voltage, and the circuit module uses the internal power supply voltage output as the operation power supply. .
発明の効果  The invention's effect
[0020] 本願において開示される発明のうち代表的なものによって得られる効果を簡単に説 明すれば下記の通りである。  [0020] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0021] すなわち、クロック同期停止モード力もの復帰に際して回路モジュールで保持され ている内部情報が不所望に破壊される事態を抑制することができる。 That is, it is possible to suppress a situation in which the internal information held in the circuit module is undesirably destroyed when the clock synchronization stop mode is restored.
図面の簡単な説明  Brief Description of Drawings
[0022] [図 1]本発明に係る半導体集積回路の一例に係るデータプロセッサのブロック図であ る。  FIG. 1 is a block diagram of a data processor according to an example of a semiconductor integrated circuit according to the present invention.
[図 2]低消費電力制御回路の一例を示すブロック図である。  FIG. 2 is a block diagram showing an example of a low power consumption control circuit.
[図 3]低消費電力モードを解除するときの動作を示すタイミングチャートである。  FIG. 3 is a timing chart showing an operation when canceling a low power consumption mode.
[図 4]低消費電力モードから復帰するとき回路モジュールに対するクロック供給を全て の回路モジュールに対して一斉に行うようにした比較例に係るデータプロセッサのブ ロック図である。  FIG. 4 is a block diagram of a data processor according to a comparative example in which clock supply to circuit modules is performed simultaneously for all circuit modules when returning from the low power consumption mode.
[図 5]図 4の比較例に係るデータプロセッサにおける低消費電力制御回路の一例を 示すブロック図である。  FIG. 5 is a block diagram showing an example of a low power consumption control circuit in the data processor according to the comparative example of FIG.
[図 6]図 4の比較例に係るデータプロセッサにおける低消費電力モードを解除すると きの動作を示すタイミングチャートである。  FIG. 6 is a timing chart showing an operation when the low power consumption mode is canceled in the data processor according to the comparative example of FIG.
符号の説明  Explanation of symbols
[0023] 1 データプロセッサ [0023] 1 data processor
2 中央処理装置  2 Central processing unit
3 入出力回路モジユーノレ 4 メモリモジュール 3 Input / output circuit module 4 Memory module
5 クロックパノレスジェネレータ  5 Clock panoramic generator
6 降圧回路  6 Step-down circuit
7 低消費電力制御回路 7 Low power consumption control circuit
OSC 発振制御信号  OSC oscillation control signal
SPLA, SPLB, SPLC クロック供給イネ一ブル信号  SPLA, SPLB, SPLC Clock supply enable signal
CLK クロック信号 CLK clock signal
PDS 低消費電力制御信号  PDS low power control signal
ACT 外部信号  ACT External signal
10 ロジック回路  10 Logic circuit
11 フリップフロップ  11 flip-flops
12 カウンタ  12 counter
13 分周回路  13 divider circuit
14一 16 レジスタ  14 1 16 registers
17— 19 比較回路  17—19 Comparison circuit
20—22 フリップフロップ  20-22 Flip-flop
MCHA— MCHC 検出信号  MCHA— MCHC detection signal
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0024] 図 1には本発明に係る半導体集積回路の一例としてデータプロセッサが示される。  FIG. 1 shows a data processor as an example of a semiconductor integrated circuit according to the present invention.
同図に示されるデータプロセッサは、特に制限されないが、単結晶シリコンのような 1 個の半導体基板に CMOS集積回路製造技術によって形成される。  The data processor shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a CMOS integrated circuit manufacturing technique.
[0025] データプロセッサ (MPU)lは、中央処理装置（CPU) 2、代表的に示された入出力 回路モジュール（MDLA) 3、代表的に示されたメモリモジュール（MDLB) 4、クロッ クパルスジェネレータ（CPG) 5、降圧回路（SDC) 6、及び低消費電力制御回路（PD CM) 7を有する。前記中央処理装置 2は、命令実行手順や命令の解読を行う命令制 御部と、命令解読結果に従ってアドレス演算やデータ演算などを行って命令を実行 する命令実行部とから成る。降圧回路 6は外部電源電圧 VDDを降圧して内部電源 電圧 vddを生成する。データプロセッサ 1の内部回路は、直接外部電源電圧 VDDを 動作電源とする第 1回路、内部電源電圧を動作電源とする第 2回路、及び双方を動 作電源とする第 3回路から構成される。例えば CPU2及びメモリモジュール 4は第 2回 路から構成される。例えば入出力回路モジュール 3では、外部とインタフェースされる ノ ッファが第 1回路で構成され、入出力制御などを行うロジック部やデータラッチなど が第 2回路で構成され、第 1回路と第 2回路を接続するレベルシフト回路が第 3回路 で構成される。 [0025] The data processor (MPU) 1 includes a central processing unit (CPU) 2, a representative input / output circuit module (MDLA) 3, a representative memory module (MDLB) 4, and a clock pulse. A generator (CPG) 5, a step-down circuit (SDC) 6, and a low power consumption control circuit (PD CM) 7 are included. The central processing unit 2 includes an instruction control unit that decodes an instruction execution procedure and an instruction, and an instruction execution unit that executes an instruction by performing an address operation or a data operation according to an instruction decoding result. The step-down circuit 6 steps down the external power supply voltage VDD to generate the internal power supply voltage vdd. The internal circuit of data processor 1 directly uses the external power supply voltage VDD. It consists of a first circuit that uses the operating power supply, a second circuit that uses the internal power supply voltage as the operating power supply, and a third circuit that uses both as the operating power supply. For example, CPU 2 and memory module 4 are composed of the second circuit. For example, in the input / output circuit module 3, a noferr interfaced with the outside is configured by the first circuit, and a logic unit for performing input / output control, a data latch, and the like are configured by the second circuit. The first circuit and the second circuit The level shift circuit that connects to is composed of the third circuit.
[0026] 低消費電力制御回路 7は発振制御信号 φ OSC、クロック供給イネ一ブル信号 φ S PLA、 φ SPLB、及び φ SPLCを出力する。クロックパルスジェネレータ 5は発振制 御信号 φ OSCのハイレベルに応答して発振動作を開始し、クロック信号 CLKを出力 する。クロック供給イネ一ブル信号 φ SPLAがハイレベルにされることにより入出力回 路モジュール 3はクロック信号 CLKが内部に供給可能にされ、クロック信号 CLKに同 期動作可能になる。クロック供給イネ一ブル信号 φ SPLBがハイレベルにされること によりメモリモジュール 4はクロック信号 CLKが内部に供給可能にされ、クロック信号 CLKに同期動作可能になる。クロック供給イネ一ブル信号 φ SPLCがハイレベルに されることにより CPU2はクロック信号 CLKが内部に供給可能にされ、クロック信号 C LKに同期動作可能になる。 CPU2は所定命令の実行、所定レジスタへのビットの設 定、割り込みなどによって低消費電力モードへの遷移ルーチンを実行することによつ て、低消費電力制御信号 φ PDSをハイレベルにアサートする。これを受ける低消費 電力制御回路 7は入出力回路モジュール（MDLA) 3、メモリモジュール（MDLB) 4 、及び CPU2へのクロック信号 CLKの供給を停止して、データプロセッサ 1に低消費 電力モードが設定される。低消費電力モードにおいて、入出力回路モジュール (MD LA) 3、メモリモジュール（MDLB) 4、及び CPU2などの内部回路には動作電源の 供給が維持されている。低消費電力モードはパワーオンリセット後に設定可能な動作 モードとされる。  The low power consumption control circuit 7 outputs an oscillation control signal φ OSC and a clock supply enable signal φ S PLA, φ SPLB, and φ SPLC. The clock pulse generator 5 starts oscillating in response to the high level of the oscillation control signal φ OSC and outputs the clock signal CLK. When the clock supply enable signal φSPLA is set to the high level, the input / output circuit module 3 can supply the clock signal CLK to the inside and can operate synchronously with the clock signal CLK. When the clock supply enable signal φSPLB is set to the high level, the memory module 4 can supply the clock signal CLK internally, and can operate synchronously with the clock signal CLK. When the clock supply enable signal φSPLC is set to the high level, the CPU 2 can supply the clock signal CLK internally and can operate synchronously with the clock signal CLK. The CPU 2 asserts the low power consumption control signal φPDS to a high level by executing a transition routine to the low power consumption mode by executing a predetermined instruction, setting a bit to a predetermined register, an interrupt, or the like. In response to this, the low power consumption control circuit 7 stops the supply of the clock signal CLK to the input / output circuit module (MDLA) 3, the memory module (MDLB) 4, and the CPU 2 and sets the low power consumption mode in the data processor 1. Is done. In the low power consumption mode, the internal power supply such as the input / output circuit module (MDLA) 3, the memory module (MDLB) 4, and the CPU 2 is maintained. The low power consumption mode is an operation mode that can be set after a power-on reset.
[0027] 外部信号 ACTによって低消費電力モードの解除が指示されると、低消費電力制御 回路 7はクロック供給イネ一ブル信号 φ SPLA、 φ SPLB, φ SPLCのィネーブルタ イミングをずらして、入出力回路モジュール 3、メモリモジュール 4、及び CPU2内部 へのクロック信号 CLKの供給開始タイミングをずらす制御が可能にされる。外部信号 ACTは例えば NMI (ノン ·マスカブル'インタラプト）のような割り込み信号であり、上 述のように低消費電力モードが解除されると、クロック同期動作可能になった CPU2 はその割り込み信号に対応する割り込み処理の実行に遷移する。 [0027] When the low power consumption mode is instructed by the external signal ACT, the low power consumption control circuit 7 shifts the enable timing of the clock supply enable signals φSPLA, φSPLB, φSPLC, and Control to shift the supply start timing of the clock signal CLK to the module 3, the memory module 4, and the CPU 2 is made possible. External signal ACT is an interrupt signal such as NMI (non-maskable 'interrupt), for example. When the low power consumption mode is released as described above, the CPU2 that is enabled for clock synchronous operation is interrupted by the interrupt signal. Transition to process execution.
[0028] 図 2は低消費電力制御回路 7の論理構成が例示される。ロジック回路 (CNT) 10は 低消費電力制御信号 <i) PDS、代表的に示された外部信号 ACT、そして図示を省略 するパワーオンリセット信号が入力され、それら入力に応じて制御信号 φ RST、 φ S ETを出力する。制御信号 0 RSTはフリップフロップ (FF) 11、 20— 22のリセット端子 (R)に、制御信号 φ SETはフリップフロップ 11のセット端子（S)に供給される。フリツ プフロップ 11の出力は前記発振制御信号 φ OSCとして利用される。図示を省略する ノ ヮ一オンリセット信号によるリセット指示、或 、は外部信号 ACTによる低消費電力 解除の指示があると、ロジック回路 10は制御信号 φ SETにてフリップフロップ 11をセ ットして発振制御信号 φ OSCをノヽィレベルとして、クロックパルスジェネレータ 5に発 振動作を開始させる。低消費電力制御信号 φ PDSによって低消費電力モードが指 示されたときロジック回路 10は制御信号 φ RSTにてフリップフロップ 11をリセットして 発振制御信号 Φ OSCをローレベルとして、クロックパルスジェネレータ 5に発振動作 を停止させる。 FIG. 2 illustrates a logical configuration of the low power consumption control circuit 7. The logic circuit (CNT) 10 is supplied with a low power consumption control signal <i) PDS, a representative external signal ACT, and a power-on reset signal (not shown) .The control signal φ RST, φ S ET is output. The control signal 0 RST is supplied to the reset terminal (R) of the flip-flops (FF) 11 and 20-22, and the control signal φSET is supplied to the set terminal (S) of the flip-flop 11. The output of flip-flop 11 is used as the oscillation control signal φ OSC. Not shown No. When there is a reset instruction by the on-reset signal or an instruction to release low power consumption by the external signal ACT, the logic circuit 10 sets the flip-flop 11 by the control signal φSET. Oscillation control signal φ OSC is set to the noise level, and clock pulse generator 5 starts oscillation. When the low power consumption mode is specified by the low power consumption control signal φ PDS, the logic circuit 10 resets the flip-flop 11 with the control signal φ RST and sets the oscillation control signal φ OSC to the low level to the clock pulse generator 5 Stops oscillation.
[0029] カウンタ (CUNT)12は発振制御信号 φ OSCのハイレベルへの変化に応答して分 周回路（DIV) 13からの分周クロックをカウントアップ信号 φ UPとして計数する。カウ ンタ 12の計数値 NMBがレジスタ (REGA) 14の設定値に到達したかを検出する比 較回路 (CMPA) 17が設けられ、比較回路 17の検出信号 φ ΜΟΗΑをセット端子 (S )に受け、制御信号 φ RSTをリセット端子 (R)に受け、クロック供給イネ一ブル信号 φ SPLAを出力するフリップフロップ (FF) 20が設けられる。制御信号 φ RSTのハイレ ベルにてフリップフロップ (FF)20はリセットされ、クロック供給イネ一ブル信号 φ SPL Aはローレベルにネゲートされるので MDLA3の内部へのクロック供給は遮断される 。この後、発振制御信号 <i) OSCのハイレベル変化に同期して開始された計数動作 の計数値 NMBがレジスタ 14の値に到達して初めてフリップフロップ 20がセットされ、 クロック供給イネ一ブル信号 φ SPLAがハイレベルにアサートされるので MDLA3の 内部へのクロック供給が開始される。 [0030] 同様に、カウンタ 12の計数値 NMBがレジスタ（REGB) 15の設定値に到達したか を検出する比較回路 (CMPB) 18が設けられ、比較回路 18の検出信号 φ MCHBを セット端子 (S)に受け、制御信号 φ RSTをリセット端子 (R)に受け、クロック供給イネ 一ブル信号 φ SPLBを出力するフリップフロップ (FF) 21が設けられる。制御信号 φ RSTのハイレベルにてフリップフロップ (FF)21はリセットされ、クロック供給イネーブ ル信号 φ SPLBはローレベルにネゲートされるので MDLB4の内部へのクロック供給 は遮断される。この後、発振制御信号 <i) OSCのハイレベル変化に同期して開始され た計数動作の計数値 NMBがレジスタ 15の値に到達して初めてフリップフロップ 21 がセットされ、クロック供給イネ一ブル信号 φ SPLBがハイレベルにアサートされるの で MDLB4の内部へのクロック供給が開始される。 [0029] Counter (CUNT) 12 counts the divided clock from frequency divider (DIV) 13 as count-up signal φUP in response to the change of oscillation control signal φOSC to high level. A comparison circuit (CMPA) 17 that detects whether the count value NMB of the counter 12 has reached the set value of the register (REGA) 14 is provided, and the detection signal φΜΟΗΑ of the comparison circuit 17 is received at the set terminal (S). A flip-flop (FF) 20 for receiving the control signal φ RST at the reset terminal (R) and outputting the clock supply enable signal φ SPLA is provided. The flip-flop (FF) 20 is reset at the high level of the control signal φRST, and the clock supply enable signal φSPLA is negated to a low level, so that the clock supply to the inside of MDLA3 is cut off. After this, the oscillation control signal <i) The count value of the counting operation started in synchronization with the high level change of OSC. The flip-flop 20 is set only after the NMB reaches the value of the register 14, and the clock supply enable signal Since φSPLA is asserted high, clock supply to MDLA3 is started. Similarly, a comparison circuit (CMPB) 18 is provided for detecting whether the count value NMB of the counter 12 has reached the set value of the register (REGB) 15, and the detection signal φ MCHB of the comparison circuit 18 is set to the set terminal ( A flip-flop (FF) 21 is provided which receives the control signal φRST at the reset terminal (R) and outputs the clock supply enable signal φSPLB. The flip-flop (FF) 21 is reset by the high level of the control signal φRST, and the clock supply enable signal φSPLB is negated to the low level, so that the clock supply to the inside of the MDLB4 is cut off. After this, the oscillation control signal <i) The count value of the counting operation started in synchronization with the high level change of OSC, the flip-flop 21 is set only when the value NMB reaches the value in register 15, and the clock supply enable signal φ SPLB is asserted high, so the clock supply to MDLB4 is started.
[0031] 同様に、カウンタ 12の計数値 NMBがレジスタ（REGC) 16の設定値に到達したか を検出する比較回路 (CMPC) 19が設けられ、比較回路 19の検出信号 φ MCHCを セット端子 (S)に受け、制御信号 φ RSTをリセット端子 (R)に受け、クロック供給イネ 一ブル信号 φ SPLCを出力するフリップフロップ (FF) 22が設けられる。制御信号 φ RSTのハイレベルにてフリップフロップ (FF)22はリセットされ、クロック供給イネーブ ル信号 φ SPLCはローレベルにネゲートされるので CPU2の内部へのクロック供給は 遮断される。この後、発振制御信号 <i) OSCのハイレベル変化に同期して開始された 計数動作の計数値 NMBがレジスタ 16の値に到達して初めてフリップフロップ 22が セットされ、クロック供給イネ一ブル信号 φ SPLCがハイレベルにアサートされるので CPU2の内部へのクロック供給が開始される。  Similarly, a comparison circuit (CMPC) 19 is provided for detecting whether the count value NMB of the counter 12 has reached the set value of the register (REGC) 16, and the detection signal φ MCHC of the comparison circuit 19 is set to the set terminal ( A flip-flop (FF) 22 is provided which receives the control signal φRST at the reset terminal (R) and outputs the clock supply enable signal φSPLC. The flip-flop (FF) 22 is reset when the control signal φ RST is high, and the clock supply enable signal φ SPLC is negated to low level, so that the clock supply to the CPU 2 is cut off. After this, the oscillation control signal <i) The count value of the count operation started in synchronization with the high level change of OSC. The flip-flop 22 is set only when the NMB reaches the value of the register 16, and the clock supply enable signal Since φSPLC is asserted high, clock supply to CPU2 is started.
[0032] 上記より、クロック供給イネ一ブル信号 () SPLA、 SPLB, φ SPLCのハイレベル へのアサートタイミングはレジスタ 14、 15、 16の設定値に従って可変可能にずらすこ とが可能にされる。例えば全てのレジスタ 14、 15、 16の設定値を等しくすれば MDL A3、 MDLB4、 CPU2へのクロック信号 CLKの供給は同時に開始される。レジスタ 1 4、 15の設定値を等しくすれば MDLA3と MDLB4へのクロック信号 CLKの供給は 同時に開始され、 CPU2へのクロック供給タイミングが相違される。 3個のレジスタ 14 、 15、 16の設定値を夫々相違させれば MDLA3、 MDLB4、 CPU2へのクロック信 号 CLKの供給タイミングを順次ずらすことができる。 [0033] 図 2において 23はクロック分配回路（DSB)であり、クロック信号 CLKをロジック回路 10、カウンタ 12、レジスタ 14、 15、 16、フリップフロップ 11, 20— 22に分酉己すると共 に、クロック分周回路 13に供給する。クロック分周回路 13はクロック信号 CLKを分周 してカウントアップ信号 φ UPを生成する。 From the above, the clock supply enable signal () SPLA, SPLB, φSPLC assertion timing to the high level can be variably shifted according to the set values of the registers 14, 15, and 16. For example, if the set values of all the registers 14, 15, 16 are made equal, the supply of the clock signal CLK to the MDL A3, MDLB4, and CPU2 is started simultaneously. If the set values of registers 14 and 15 are equal, supply of the clock signal CLK to MDLA3 and MDLB4 is started at the same time, and the timing of clock supply to CPU2 is different. If the set values of the three registers 14, 15, and 16 are made different from each other, the supply timing of the clock signal CLK to the MDLA3, MDLB4, and CPU2 can be sequentially shifted. In FIG. 2, reference numeral 23 denotes a clock distribution circuit (DSB). The clock signal CLK is divided into the logic circuit 10, the counter 12, the registers 14, 15, 16, and the flip-flops 11, 20-22, This is supplied to the clock frequency divider circuit 13. The clock divider circuit 13 divides the clock signal CLK to generate the count up signal φUP.
[0034] 図 3には低消費電力モードを解除するときの動作タイミングが示される。特に制限さ れないが、ここでは、クロック信号 CLKが 50MHz、クロック分周回路 13による分周率 は 256分周とする。レジスタ（REGA) 14の設定値は 16進数で Hex32、レジスタ（RE GB) 15の設定値は 16進数で Hex40、レジスタ（REGC) 16の設定値は 16進数で H ex48とされる。時刻 tO以前において発振制御信号 0 OSCはローレベルにされ、クロ ックパルスジェネレータ 5の発振動作は停止されて 、る。時刻 tOに外部信号 ACTが アサートされると、セット信号 φ SETによってフリップフロップ 11がセットされ、発振制 御信号 φ OSCのハイレベルにてクロックパルスジェネレータ 5の発振動作が開始され る。このとき、フリップフロップ 20— 22はハイレベルの制御信号 0 RSTにてリセットさ れているので、クロック供給イネ一ブル信号 φ SPLA— φ SPLCはローレベルにネゲ ートされ、時刻 tO力 クロックパルスジェネレータ 5が発振動作を開始しても、回路モ ジュール 2— 4の内部へのクロック信号 CLKの供給は依然遮断状態を維持して ヽる。  FIG. 3 shows the operation timing when the low power consumption mode is canceled. Although not particularly limited, here, the clock signal CLK is 50 MHz, and the division ratio by the clock divider 13 is 256. The setting value of register (REGA) 14 is Hex32 in hexadecimal, the setting value of register (RE GB) 15 is Hex40 in hexadecimal, and the setting value of register (REGC) 16 is Hex48 in hexadecimal. Before time tO, the oscillation control signal 0 OSC is set to the low level, and the oscillation operation of the clock pulse generator 5 is stopped. When the external signal ACT is asserted at time tO, the flip-flop 11 is set by the set signal φSET, and the clock pulse generator 5 starts oscillating at the high level of the oscillation control signal φ OSC. At this time, since the flip-flops 20-22 are reset by the high level control signal 0 RST, the clock supply enable signal φSPLA—φSPLC is negated to the low level, and the time tO power clock pulse Even when the generator 5 starts oscillating, the supply of the clock signal CLK to the inside of the circuit modules 2-4 is still maintained in the cut-off state.
[0035] 時刻 tlに発振制御信号 φ OSCのハイレベル変化に同期して開始された計数動作 の計数値 NMBがレジスタ 14の設定値（Hex32)に到達すると、フリップフロップ 20が セットされ、クロック供給イネ一ブル信号 φ SPLAがハイレベルにアサートされ、これ によって MDLA3の内部へクロック信号 CLKの供給が開始される。クロック信号 CLK が供給されると、 MDLA3はクロック信号 CLKの変化に応答して内部状態が一斉に 変化しようとし、これによつて MDLA3の内部では比較的大きな突入電流が流れ、そ れによって内部電源電圧 vddは電圧降下する。内部電源電圧 Vddの定格は 3. 2V、 動作保証下限電圧は 2. 7Vとされる。このときの突入電流は Irclとされ、其れによる 電圧降下は、動作保証下限電圧は 2. 7V以上の 2. 8Vまでとされる。突入電流 Ireに よる電圧降下を生ずる時間は例えば 20マイクロ秒 s)である。計数値 NMBがレジ スタ 15の設定値 (Hex40)に到達する時刻 t2までには 40. 96 μ s (8カウント分）を要 し、時刻 tlで始まった電圧降下は時刻 t2では既に収束して 、る。 [0036] 時刻 t2に計数値 NMBがレジスタ 15の設定値（Hex40)に到達すると、フリップフロ ップ 21がセットされ、これによつて MDLB4の内部へクロック信号 CLKの供給が開始 される。このときも MDLB4はクロック信号 CLKの変化に応答して内部状態が一斉に 変化しようとし、これによつて MDLB4の内部では比較的大きな突入電流が流れ、そ れによって内部電源電圧 vddは電圧降下する。このときの突入電流は Irc2とされ、其 れによる電圧降下は動作保証下限電圧は 2. 7V以上の 2. 8Vまでとされる。時刻 t3 に計数値 NMCがレジスタ 16の設定値（Hex48)に到達すると、 CPU2の内部へクロ ック信号 CLKの供給が開始される。このときも CPU2内部では比較的大きな突入電 流が流れ、それによつて内部電源電圧 vddは電圧降下するが、上記同様に、突入電 流は Irc3とされ、其れによる電圧降下は動作保証下限電圧は 2. 7V以上の 2. 8Vま でとされる。 [0035] At the time tl, the count value of the count operation started in synchronization with the high level change of the oscillation control signal φ OSC. When NMB reaches the set value (Hex32) in register 14, flip-flop 20 is set and clock is supplied. The enable signal φSPLA is asserted high, and this starts the supply of the clock signal CLK to the inside of MDLA3. When the clock signal CLK is supplied, the MDLA3 tries to change its internal state all at once in response to the change of the clock signal CLK, which causes a relatively large inrush current to flow inside the MDLA3, thereby causing the internal power supply to change. The voltage vdd drops. The internal power supply voltage Vdd is rated at 3.2V, and the operation guarantee lower limit voltage is 2.7V. The inrush current at this time is Ircl, and the voltage drop due to this is assumed to be 2.8V, which is the minimum operating guarantee voltage of 2.7V. The time for which the voltage drop due to the inrush current Ire is, for example, 20 microseconds). It takes 40.96 μs (8 counts) by time t2 when the count value NMB reaches the set value of register 15 (Hex40), and the voltage drop that started at time tl has already converged at time t2. RU [0036] When the count value NMB reaches the set value (Hex40) of the register 15 at time t2, the flip-flop 21 is set, thereby starting to supply the clock signal CLK to the inside of the MDLB4. At this time as well, MDLB4 tries to change its internal state all at once in response to the change of clock signal CLK, which causes a relatively large inrush current to flow inside MDLB4, which causes the internal power supply voltage vdd to drop. . The inrush current at this time is Irc2, and the voltage drop due to this is the operation guarantee lower limit voltage of 2.7V to 2.8V. When the count value NMC reaches the set value (Hex48) in register 16 at time t3, supply of the clock signal CLK to the inside of CPU2 is started. At this time as well, a relatively large inrush current flows inside CPU2, which causes the internal power supply voltage vdd to drop, but in the same way as above, the inrush current is Irc3, and the resulting voltage drop is the operation guarantee lower limit voltage. Is taken from 2.7V to 2.8V.
[0037] 図 3のタイミングより明らかなように、突入電流による降下電圧が動作保証下限電圧 よりも低くならな 、ように、クロック供給タイミングをずらす回路モジュールのグループ を決めればよい。例えば MDLA3と MDLB4に一緒にクロック供給を開始しても降下 電圧が動作保証下限電圧よりも低くならないことが明らかな場合には、低消費電力モ ードカもの復帰時間短縮の点でそのようにするのがよい。また、最初にクロック信号の 供給を開始する回路モジュールに対応するレジスタの設定値は、クロック信号の発振 安定時間を考慮して決定すればよい。クロック供給タイミングが前後される回路モジュ ールに対応されるレジスタ設定値の差は、前段で生ずる突入電流による電圧降下が 収束する時間を考慮して決定すればょ 、。  As is clear from the timing of FIG. 3, the group of circuit modules for shifting the clock supply timing may be determined so that the voltage drop due to the inrush current does not become lower than the operation guarantee lower limit voltage. For example, if it is clear that the voltage drop does not become lower than the operation guarantee lower limit voltage even when the clock supply to MDLA3 and MDLB4 is started together, do so in terms of shortening the recovery time of the low power consumption mode. Is good. In addition, the set value of the register corresponding to the circuit module that first starts supplying the clock signal may be determined in consideration of the oscillation stabilization time of the clock signal. The difference in the register setting value corresponding to the circuit module whose clock supply timing is changed should be determined in consideration of the convergence time of the voltage drop due to the inrush current generated in the previous stage.
[0038] 図 4乃至図 6には低消費電力モードから復帰するとき回路モジュールに対するクロ ック供給を全ての回路モジュールに対して一斉に行うようにした比較例に係る構成が 例示される。図 4のように 0 SPLは回路モジュール（MDLA, MDLB, CPU)に対し て共通化されている。図 5の低消費電力制御回路（PDCM)では、カウンタ（CUNT) は発振安定時間を経過するタイミングで所定の桁上げ信号でフリップフロップ (FF) をセットしてクロック供給イネ一ブル信号 φ SPLをアサートする。図 6のタイミングチヤ ートに示されるように、時刻 toで低消費電力モードの解除が指示され、発振安定ィ匕 時間を経過した時刻 tlに回路モジュール（MDLA、 MDLB, CPU)へのクロック信 号の供給が開始される。全ての回路モジュール（MDLA、 MDLB、 CPU) - ^一斉に クロック信号の供給が開始されるから、図 3に比べて一度に大きな突入電流 Irc4が流 れ、電圧降下も動作保証下限電圧を下回り、低消費電力状態で保持していたレジス タ情報などの内部回路の内部状態が破壊され、低消費電力モードから復帰したとき の制御動作が保証されないことが予想される。例えば CPUの汎用レジスタや、周辺 回路のコントロールレジスタの値が破壊されてしまうと、低消費電力モードから抜けて も演算制御動作を正常に継続することができなくなる。 [0038] FIGS. 4 to 6 illustrate a configuration according to a comparative example in which the clock supply to the circuit modules is performed simultaneously for all the circuit modules when returning from the low power consumption mode. As shown in Fig. 4, 0 SPL is shared by circuit modules (MDLA, MDLB, CPU). In the low power consumption control circuit (PDCM) in Fig. 5, the counter (CUNT) sets the flip-flop (FF) with a predetermined carry signal at the timing when the oscillation stabilization time elapses and sets the clock supply enable signal φSPL. Assert. As shown in the timing chart of Figure 6, the low power consumption mode is instructed at time to, and the clock signal to the circuit modules (MDLA, MDLB, CPU) is received at time tl when the oscillation stabilization time has elapsed. The supply of the issue begins. All circuit modules (MDLA, MDLB, CPU)-^ Since the clock signal supply starts all at once, a large inrush current Irc4 flows at once compared to Fig. 3, and the voltage drop is below the guaranteed operating voltage. It is expected that the internal state of the internal circuit such as register information held in the low power consumption state will be destroyed, and the control operation will not be guaranteed when returning from the low power consumption mode. For example, if the values of the general-purpose registers of the CPU and the control registers of the peripheral circuits are destroyed, the computation control operation cannot be continued normally even if the CPU exits the low power consumption mode.
[0039] 以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、 本発明はそれに限定されるものではなぐその要旨を逸脱しない範囲において種々 変更可能であることは言うまでもな 、。  [0039] Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. .
[0040] 例えば、レジスタ 14一 16の設定は CPUによるアクセスで設定することに限定されな い。リセット時にハードウェアで設定してもよい。当然その後の CPUによる書き換えは 保証される。特に、パワーオンリセット時におけるクロック制御にも低消費電力制御回 路 10を用いる場合には、レジスタ初期値はリセット時にハードウェアで初期設定され るのがよい。パワーオンリセット時には電圧降下によって消失されて不都合な情報は 未だ保持されていないのが普通であるから、各レジスタ設定値は同一であって差し支 えない。最初から、低消費電力モードからの復帰を考慮して相違させておくことは妨 げられない。  [0040] For example, the setting of the registers 14-16 is not limited to setting by access by the CPU. You may set by hardware at the time of reset. Of course, subsequent rewriting by the CPU is guaranteed. In particular, when the low power consumption control circuit 10 is also used for clock control at power-on reset, the register initial value should be initialized by hardware at reset. At power-on reset, it is normal that information that is lost due to a voltage drop and inconvenient information is not yet retained, so each register setting value can be the same. From the beginning, it is not hindered to make a difference considering the return from the low power consumption mode.
[0041] また、低消費電力制御回路は、パワーオンリセット時におけるクロック制御も行うよう に構成したが、パワーオンリセット時のクロック発振制御には別の論理構成を採用し てよいのは当然である。パワーオンリセット時には電圧降下によって消失されて不都 合な情報は未だ保持されて 、な 、のが普通である。  [0041] Although the low power consumption control circuit is also configured to perform clock control at the time of power-on reset, it is a matter of course that another logic configuration may be adopted for clock oscillation control at the time of power-on reset. is there. In general, information that is lost due to a voltage drop at the time of power-on reset is still retained.
[0042] また、データプロセッサは内部降圧回路を備えなくてもよいが、特に内部降圧回路 の電流供給能力が低い場合を考慮すれば、本発明の構成はそのような内部降圧回 路を有するデータプロセッサに好適となる。また、回路モジュールは入出力回路モジ ユール、メモリモジュール、及び CPUに限定されず、適宜変更可能である。  [0042] Although the data processor does not have to include an internal voltage down converter, the configuration of the present invention is a data having such an internal voltage down circuit, especially considering the case where the current supply capacity of the internal voltage down converter is low. Suitable for a processor. The circuit module is not limited to the input / output circuit module, the memory module, and the CPU, and can be changed as appropriate.
産業上の利用可能性  Industrial applicability
[0043] 本発明は、パワーオンリセット後に回路モジュールへの動作電源の供給を維持した まま回路モジュール内のクロック同期動作を停止するクロック供給停止モードの設定 が可能にされるデータプロセッサなどの半導体集積回路に広く適用することができる [0043] The present invention maintains the supply of operating power to the circuit module after a power-on reset. The present invention can be widely applied to semiconductor integrated circuits such as data processors that can be set to a clock supply stop mode that stops the clock synchronization operation in the circuit module.

Claims

請求の範囲 The scope of the claims
[1] 制御回路と、クロック信号に同期動作する複数の回路モジュールとを有し、パワー オンリセット後に回路モジュールへの動作電源の供給を維持したまま回路モジュール 内へのクロック信号の供給動作を停止するクロック供給停止モードの設定が可能にさ れる半導体集積回路であって、  [1] Having a control circuit and a plurality of circuit modules that operate in synchronization with the clock signal, stop supplying the clock signal into the circuit module while maintaining the operation power supply to the circuit module after a power-on reset A semiconductor integrated circuit capable of setting a clock supply stop mode to
前記制御回路は前記クロック供給停止モードを解除するとき複数の回路モジユー ル間で内部へのクロック供給開始タイミングをずらす制御が可能にされる半導体集積 回路。  A semiconductor integrated circuit in which the control circuit is capable of performing control to shift the internal clock supply start timing among a plurality of circuit modules when releasing the clock supply stop mode.
[2] 前記クロック供給開始タイミングをずらす制御に用いる制御データが設定されるレジ スタを有し、前記レジスタの設定値はクロック供給開始タイミングのずれ量を指定する 請求項 1記載の半導体集積回路。  2. The semiconductor integrated circuit according to claim 1, further comprising a register in which control data used for control for shifting the clock supply start timing is set, and the set value of the register specifies a shift amount of the clock supply start timing.
[3] 前記複数の回路モジュールの一つとして中央処理装置を有し、前記中央処理装置 は前記レジスタに対する書き込みアクセス可能である請求項 2記載の半導体集積回 路。 3. The semiconductor integrated circuit according to claim 2, further comprising a central processing unit as one of the plurality of circuit modules, wherein the central processing unit is capable of write access to the register.
[4] 前記クロック供給停止モードの設定は前記中央処理装置が指示し、前記クロック供 給停止モードの解除は半導体集積回路の外部力 供給される外部信号によって指 示される請求項 3記載の半導体集積回路。  4. The semiconductor integrated circuit according to claim 3, wherein the central processing unit instructs the setting of the clock supply stop mode, and the release of the clock supply stop mode is instructed by an external signal supplied from an external force of the semiconductor integrated circuit. circuit.
[5] 前記外部信号は割り込み要求信号である請求項 4記載の半導体集積回路。  5. The semiconductor integrated circuit according to claim 4, wherein the external signal is an interrupt request signal.
[6] 外部電源電圧を降圧して内部電源電圧を生成する降圧回路を有し、前記複数の 回路モジュールは動作電源として前記降圧回路力 出力される内部電源電圧を用 いる請求項 1記載の半導体集積回路。  6. The semiconductor according to claim 1, further comprising a step-down circuit that steps down an external power supply voltage to generate an internal power supply voltage, wherein the plurality of circuit modules use the internal power supply voltage output from the step-down circuit power as an operation power supply. Integrated circuit.
[7] 制御回路と、クロック信号に同期動作する複数の回路モジュールとを有し、パワー オンリセット後に前記複数の回路モジュールへの動作電源の供給を維持したまま回 路モジュール内へのクロック信号の供給を停止するクロック供給停止モードの設定が 可能にされる半導体集積回路であって、  [7] A control circuit and a plurality of circuit modules that operate in synchronization with a clock signal, and after the power-on reset, the clock signal into the circuit module is maintained while the operation power is supplied to the plurality of circuit modules. A semiconductor integrated circuit capable of setting a clock supply stop mode for stopping supply,
前記制御回路は、前記複数の回路モジュールのうち所定の一の回路モジュールか ら前記クロック供給停止モードを設定する指示を受けて前記一の回路モジュール及 び他の回路モジュール内へのクロック供給動作を停止させ、前記クロック供給停止モ ードを解除するときの複数の回路モジュール間で内部へのクロック供給開始タイミン グをずらす制御が可能にされる半導体集積回路。 The control circuit receives a command to set the clock supply stop mode from a predetermined one of the plurality of circuit modules and performs a clock supply operation into the one circuit module and the other circuit modules. Stop the clock supply stop mode. A semiconductor integrated circuit that enables control to shift the internal clock supply start timing between multiple circuit modules when releasing the mode.
[8] 前記所定の一の回路モジュールは中央処理装置であり、  [8] The predetermined one circuit module is a central processing unit,
前記制御回路は前記クロック供給停止モードを解除する指示が半導体集積回路の 外部から与えられる請求項 7記載の半導体集積回路。  8. The semiconductor integrated circuit according to claim 7, wherein the control circuit is given an instruction to cancel the clock supply stop mode from the outside of the semiconductor integrated circuit.
[9] 前記制御回路は、前記中央処理装置によって書き込みアクセス可能にされるレジ スタを有し、前記レジスタに設定されるデータは前記クロック供給停止モードを解除 するとき複数の回路モジュールの間でずらされるクロック供給動作の開始タイミングの ずれ量を規定する請求項 8記載の半導体集積回路。 [9] The control circuit includes a register that is made write accessible by the central processing unit, and data set in the register is shifted between a plurality of circuit modules when the clock supply stop mode is canceled. 9. The semiconductor integrated circuit according to claim 8, which defines a deviation amount of a start timing of a clock supply operation.
[10] 外部電源電圧を降圧して内部電源電圧を生成する降圧回路を有し、前記複数の 回路モジュールは動作電源として前記降圧回路力 出力される内部電源電圧を用[10] A step-down circuit that generates an internal power supply voltage by stepping down an external power supply voltage, and the plurality of circuit modules use the internal power supply voltage output as the operation power supply.
V、る請求項 9記載の半導体集積回路。 The semiconductor integrated circuit according to claim 9, wherein V is V.
[11] 前記中央処理装置は書き換え可能な複数のレジスタを有し、前記クロック供給停止 モード時とは前記複数のレジスタに格納されたデータを保持可能なモードである請 求項 10記載の半導体集積回路。 [11] The semiconductor integrated circuit according to claim 10, wherein the central processing unit has a plurality of rewritable registers, and the clock supply stop mode is a mode in which data stored in the plurality of registers can be held. circuit.
PCT/JP2004/016934 2004-11-15 2004-11-15 Semiconductor integrated circuit WO2006051612A1 (en)

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