WO2006011107A1 - Procede de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur ainsi obtenu - Google Patents

Procede de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur ainsi obtenu Download PDF

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WO2006011107A1
WO2006011107A1 PCT/IB2005/052382 IB2005052382W WO2006011107A1 WO 2006011107 A1 WO2006011107 A1 WO 2006011107A1 IB 2005052382 W IB2005052382 W IB 2005052382W WO 2006011107 A1 WO2006011107 A1 WO 2006011107A1
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layer
semiconductor
insulating
semiconductor layer
region
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PCT/IB2005/052382
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English (en)
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Philippe Meunier-Beillard
Claire Ravit
Johannes J. T. M. Donkers
Petrus H. C Magnee
Erwin Hijzen
Marcelino A. Verheijen
Youri Ponomarev
Josine J. G. P. Loo
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Koninklijke Philips Electronics N.V.
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Publication of WO2006011107A1 publication Critical patent/WO2006011107A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Definitions

  • the invention relates to a method of manufacturing a semiconductor device in which a semiconductor body comprising silicon and comprising a substrate is provided, at a surface thereof, with a first semiconductor layer having a lattice of a mixed crystal of silicon and germanium, which lattice is substantially relaxed, and on top of the first semiconductor layer a second semiconductor layer is situated comprising strained silicon, in which layer a part of the semiconductor device is formed, and wherein the first semiconductor layer is formed above a patterned insulating layer which is present in the semiconductor body.
  • the invention also relates to a semiconductor device obtained with such a method.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • a method as mentioned in the opening paragraph is known from US patent application US 2003/0139000 Al that was published on July 24, 2003. Therein such a method is described in which e.g. a MOSFET is made using a strained silicon layer on top of a strain-relaxed SiGe layer.
  • the strain-relaxed SiGe layer is formed in two steps: in the first step, a SiGe or Ge layer is deposited on top of a silicon layer which is separated from the rest of the semiconductor body of silicon by means of an insulating layer for the purpose of functioning as a barrier layer for the diffusion of Ge. In the second step, the structure is heated to intermix the silicon layer and the SiGe (or Ge) layer, resulting in a strain-relaxed SiGe layer.
  • a drawback of such a method is that the method is rather complicated since it requires several steps. Moreover, the method involves a heat treatment at high temperatures, preferably above 1200 degrees Celsius, which requires regions or materials whose quality or definition is destroyed or deteriorated thereby to be absent at that stage. It is therefore an object of the present invention to avoid the above drawbacks and to provide a method which is simple and does not require high temperatures.
  • a method of the type described in the opening paragraph is characterized in that the insulating layer is provided on top of the semiconductor body and patterned such as to comprise a window bordering a region of the insulating layer, and in that the first semiconductor layer is directly grown on the part of the semiconductor body below the window and the region of the insulating layer is covered with the first semiconductor layer by lateral overgrowth.
  • the invention is based on the recognition that both a thin SiGe layer and also a thicker SiGe layer can be formed in such a way that they effectively become strain-relaxed.
  • a thin (strained) SiGe layer on top of the semiconductor body (of e.g. silicon) at the bottom of a window in the insulating layer, a part of the strain of the SiGe islands in de windows can be relieved by the presence of the oxide. Parameters like the oxide wall quality and the angle to the silicon surface may play a role for the SiGe relaxation. If the insulating layer is thin and hence the regions thereof after patterning are thin as well, a monocrystalline surface of the SiGe that is strain released may be formed by lateral overgrowth above the insulating region. It has to be noted that an anneal may be desirable to fully enable the relaxation of the SiGe layer.
  • the difference in thermal expansion between Si and SiO 2 may also play a role depending on the relative Si area (volume) compared to the oxide area.
  • a strained silicon layer and devices therein, which are and remain defect-free, may be formed above the window regions and even above the insulating regions.
  • Another attractive possibility for obtaining a strain-relaxed SiGe layer is provided if the insulating layer and thus the patterned regions formed thereof are relatively thick. In such a case, the strained SiGe layer grown in the window(s) in the insulating layer will become so thick during filling the windows that eventually strain relaxation will occur before lateral overgrowth of the SiGe layer takes place. However, in this case the defects formed thereby will be mostly localized in the window region(s).
  • the part of the SiGe layer which is on top of the insulating region will be, on the one hand, strain relaxed but, on the other hand, substantially free of defects.
  • the latter is caused by the fact that many defects created in the SiGe window regions will stop at the side faces of the insulating region and will not reach the SiGe area above said insulating region.
  • a strained silicon layer and devices therein, which are and remain defect-free may be formed above the insulating regions.
  • the only requirerement to be met is for the area of the insulating region to have lateral sizes that are sufficient to form - viewed in projection - a semiconductor device within that area.
  • an annealing step may be desirable to fully enable the relaxation of the SiGe layer
  • insulating layer means in this application a layer that is suitable to be grown on by lateral overgrowth.
  • the layer is electrically or thermally insulating (or isolating)
  • conventional insulating / isolating layers have been found to be most suitable for the purpose of the present invention.
  • Such layers are for example silicon dioxide or silicon nitride. Of these two, the former is preferred since better results are obtainable in that case.
  • the insulating layer is patterned in such a way that it comprises a plurality of windows separated by regions of the insulating layer which are so small and thin that the first semiconductor layer is partly or largely strain relaxed after filling the windows and laterally overgrowing the insulating layer.
  • the small thickness of the insulating layer allows for thin strain-relaxed SiGe layers to be formed, while the small lateral width of the insulating regions allows for a completely lateral overgrowth even in the case of thin SiGe layers.
  • the thickness of the SiGe layer is lower than the critical thickness which depends on the Ge content: for a Ge content of 20, 35 and 50 at.%, said critical thickness is about respectively 200 run, 75 nm and 30 nm.
  • the lateral size of the windows in the insulating layer is comparable to the lateral size of the insulating regions bordering the windows.
  • a suitable thickness for the insulating layer is chosen in the range of 1 to 100 nm, the thickness of the first semiconductor layer is chosen in the range of 2 to 200 nm. The suitable values depend, as explained above, on the Ge content.
  • the lateral size of the windows and of the insulating regions is preferably in the range of 1 to 50 nm.
  • the thickness of the insulating layer is chosen to be so substantial that the first semiconductor is already strain relaxed before the lateral overgrowth of the insulating region takes place. In this way, after lateral overgrowth, the region of the SiGe layer above the insulating region is free or substantially free of defects. This is obtainable, in particular, if the thickness of the insulating layer is higher than the critical thickness of the first semiconductor layer, i.e. the thickness at which for a given Ge content of the SiGe material, defect/dislocation formation is likely to start.
  • the lateral size of the insulating region is sufficient to provide the semiconductor device above the insulating region.
  • a suitable thickness of the insulating region is in the range of 100 to 500 nm.
  • the lateral size of the insulating region is preferably about 100 nm or more. At present this is already sufficiently large to accommodate a semiconductor device like a MOSFET.
  • the thickness of the first semiconductor layer is reduced, preferably by a chemical mechanical polishing process. In this way, defects or (surface) irregularities that may be formed where the two laterally overgrowing SiGe regions meet each other can be removed.
  • a trench is formed therein reaching as far as the transition between the silicon and the first semiconductor layer.
  • a silicon nitride spacer is provided at the side wall of the trench near its bottom and near said transition. The strain induced by the presence of such a nitride layer may trigger the formation of misfit dislocations which in this way are localized far below the region where the device is formed.
  • the trench normally surrounds an active region comprising one or more devices.
  • the trench does not only isolate the devices from their environment but is also very effective in exerting the stress for triggering the localized formation of defects/dislocations by the nitride spacers.
  • Another way to trigger the formation of defects/dislocations is the use of a thermal anneal at a temperature, e.g. in the range of 650 degrees Celsius to 950 degrees Celsius.
  • Selective SiGe growth involving a "standard" Ge concentration of around 30% may be performed by CVD with the usual, known chemistry like DCS (or SiH 4 ) + GeH 4 and hydrogen as a carrier gas.
  • the addition of HCl can also be used to enhance the selectivity.
  • the use of nitrogen as a carrier gas will be preferred for a higher Ge content of around 50%.
  • a high Ge content (higher than 80%) will preferably be grown using nitrogen as a carrier gas, at atmospheric pressure, at a temperature lower than 400 degrees Celsius (typically around 350 0 C).
  • Chlorine based chemistry like SiH 2 Cl 2 , SiHCl 3 , HCl
  • All these conditions contribute to obtaining layers with excellent properties and with a good surface morphology.
  • the low temperature further does not pose any threat to temperature-sensitive regions or materials already present in the device at this stage.
  • the semiconductor device preferably comprises a field effect transistor with source, drain, channel and gate regions, the channel region being formed in the second (strained silicon) semiconductor layer.
  • the side faces of the window(s) are preferably aligned with ⁇ 100> directions of the semiconductor body. In this way, the lateral overgrowth process of the SiGe layer is best defined and well controllable. Thus, the formation of a smooth continuous layer of SiGe above the insulating regions is favored.
  • the invention further comprises a semiconductor device obtained with a method according to the invention. It is to be noted that all manufacturing steps of a method according to the invention may be carried out at one location. However, several steps also can be performed at different locations. E.g. the first steps comprising the formation of the SiGe layer (and strained silicon layer) on top of a patterned insulating layer on top of a silicon substrate may be carried out by the manufacturer of the semiconductor substrates. The steps of forming the semiconductor device in the resulting structure may be carried out at the premises of an IC factory.
  • Fig. 1 is sectional view of a semiconductor device obtained with a first embodiment of a method according to the invention
  • Fig. 2 is sectional view of a semiconductor device obtained with a second embodiment of a method according to the invention
  • FIG. 3 is sectional view of a semiconductor device obtained with a third embodiment of a method according to the invention
  • Figs. 4 through 9 are sectional views of a typical semiconductor device at various stages in the manufacture of the device by means of a method in accordance with the invention.
  • the Figures are diagrammatic and not drawn to scale, the dimensions in the thickness direction being particularly exaggerated for greater clarity. Corresponding parts are generally given the same reference numerals and the same hatching in the various Figures.
  • Fig. 1 is a sectional view of a semiconductor device obtained with a first embodiment of a method according to the invention.
  • the device 10 which in this case is a NMOST, comprises a semiconductor body 11 made of p-type silicon, here formed by a p- type silicon substrate 11.
  • LOCOS Local Oxidation of Silicon
  • n-type source region 5 and a drain region 6 provided, in this case, with - also n-type- extensions that are more shallow and border a, in this case p-type, channel region 7 above which a dielectric region 8 is present, here comprising silicon dioxide, which separates the channel region 7 from a gate region 9, here comprising polycrystalline silicon.
  • a metal suicide may be present functioning as a connection region.
  • the channel region 8 is formed in a second semiconductor layer 2 comprising strained silicon and having a thickness, in this case, of 10 nm, which second semiconductor layer is present on top of a first semiconductor layer 1 comprising strain-relaxed SiGe with a Ge content of e.g. 30 at.% and having a thickness of e.g. 100 nm.
  • isolating regions 20 locally separate the semiconductor layer 1 from the substrate 12.
  • the areas between the isolating regions 20 have - viewed in projection - the shape of, here rectangular, windows 21 in an insulating layer which forms the insulating regions 20.
  • the thickness of the isolating regions is, in this case, 50 nm.
  • the lateral size of the windows is in this example 50 x 50 nm, while the width of the isolating regions 20 between two neighboring windows 21 is, in this case, 10 nm.
  • the thickness of the first semiconductor layer 1 of SiGe is, in this example, 100 nm.
  • a part of the stress of the SiGe layer 1 may be released, at least partly.
  • the upper part of the SiGe layer 1, which forms a continuous layer above the isolating regions 20, may be strain-relaxed although its thickness is relatively small, such as 200 nm as in this example.
  • the strained Si layer 2 on top of the strain-relaxed SiGe layer 1 is very advantageous for the mobility of the charge carriers formed in the channel during operation of the MOST of this example. The manufacturing of the device 10 of this example using a method according to the invention will be discussed later.
  • Fig. 2 is a sectional view of a semiconductor device obtained with a second embodiment of a method according to the invention.
  • the difference with respect to the device and method of the previous example is mainly that the thickness of the insulating region 20 is now chosen to be larger than the critical thickness of the SiGe layer 1, e.g. 100 nm like in this example. Consequently, the thickness of the first semiconductor layer 1 of SiGe is also larger, e.g. 150 nm like in this example.
  • the size of the isolating region 20 is chosen so large that a complete device, like a MOST in this example, can be provided - viewed in projection within the area of the isolating region 20.
  • defects that are created in the SiGe layer 1 as soon as its thickness exceeds the critical thickness will - at least partly - face a sidewall of the isolating region 20 during growth of the SiGe layer 1.
  • the area of the SiGe layer 1 that is above the isolating region 20 and grown/formed only after the SiGe layer 1 has already surpassed its critical thickness will be shielded from a part of the growing defects / dislocations.
  • the area of the SiGe layer 1 above the isolating region 20 will be free of defects or will at least contain much fewer defects than the area of the device 10 outside the isolating regions 20.
  • the isolating regions 20 are present in the form of the complement of a window, i.e. an island.
  • the isolating island 20 is preferably square in shape and has a size that is sufficiently large to accommodate the MOST of this example, e.g. 100 x 100 nm.
  • the distance between the islands 20 is not essential. It can be chosen such that a high component density is possible and, in this example, the distance between the islands is 50 nm.
  • the intermediate area also contains, in this example, further isolating regions 30 in the form of a so called trench isolation.
  • Fig. 3 is a sectional view of a semiconductor device obtained with a third embodiment of a method according to the invention.
  • This example is essentially similar to the second example. The difference is that insulating trench region 30 extends into the semiconductor body 11 to the level of the interface between the semiconductor substrate 12 of silicon and the first semiconductor layer 1 of SiGe on top thereof.
  • a silicon nitride spacer 15 is present against the wall of the trench 30 near its bottom and thus near said interface between substrate 12 and layer 1. The stress introduced at that location by the spacer 15 may trigger the formation of defects / dislocations close to said interface.
  • the crystal orientation of the substrate is preferably chosen to be the ⁇ 100> orientation and the sidefaces of the square shaped windows 21 or isolating regions 20 are aligned with major planes of said crystal, namely ⁇ 110> directions.
  • the SiGe containing layers 1 are grown using nitrogen as a carrier gas at atmospheric pressure and at a temperature lower than 400 degrees Celsius, e.g. at 350 degrees Celsius.
  • DCS DiChloroSilane
  • FIGs. 4 to 9 are sectional views of a typical semiconductor device of one of the three examples discussed above at various stages in the manufacture of the device by means of a method in accordance with the invention. The example shown in the Figures is most similar to the second example.
  • the starting point for the manufacture of the device 10 is (see Fig. 4) a p-type silicon substrate 12 - or an n-type substrate provided with a so-called p-well, which may form the channel region 7 of an NMOST - which here also forms the semiconductor body 11.
  • the thickness of the layer 200 is chosen according to which of the examples discussed above is desired.
  • isolating layer 200 is provided with a pattern 20, using e.g. photolithography and etching, said pattern depending on which of the examples discussed above is desired.
  • VPE Vapor Phase Epitaxy
  • the SiGe layer 1 starts to laterally overgrow the isolating region 20; at a later stage (see Fig. 7) a larger part of the isolating region is covered with crystalline SiGe formed by the lateral overgrowth, and at a final stage (see Fig.
  • the isolating region 20 is completely covered by a strain-relaxed SiGe layer 1.
  • the SiGe layer 1 may contain irregularities 80 at the location where the lateral overgrowing parts of the SiGe layer 1 have been unified.
  • CMP Chemical Mechanical Polishing
  • the resulting SiGe layer 1 may thus be both flat and of the desired thickness.
  • the growth process is finished by growing the strained silicon layer 2 on top of the SiGe layer 1.
  • An additional SiGe strained adjusted layer may be grown before the silicon layer 2.
  • the manufacture of e.g. a MOST is then started in a usual manner in which trench regions 30, dielectric 8, gate 9, source 5, drain 6 and spacers 14 are formed. These steps are not shown in the Figures.
  • the spacers 15 in the trenches 30 may be formed in a similar way as the spacers 14 bordering the gate. The difference is mainly that the spacers 15 are made relatively wide and that their height is reduced to a desired value by continuing - after their formation - the anisotropic etching process such that their upper parts are removed again by said etching.
  • the manufacturing of the MOST is completed by deposition of a pre- metal dielectric, e.g. of silicon dioxide, followed by patterning thereof, deposition of a contact metal layer, e.g. of aluminum, again followed by patterning whereby contact regions are formed.
  • a pre- metal dielectric e.g. of silicon dioxide
  • a contact metal layer e.g. of aluminum

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur (10), dans lequel un corps semi-conducteur (11) contenant du silicium se situe au niveau d'une surface correspondante, avec une première couche semi-conductrice (1) possédant un réseau d'un cristal mélangé de silicium et de germanium qui est en partie détendu, et sur la partie supérieure de la première couche semi-conductrice (1) est disposée une seconde couche semi-conductrice (2) qui renferme du silicium contraint. Dans cette couche (2), une partie active du dispositif semi-conducteur (10) est formée, et la seconde couche semi-conductrice (1) est constituée au-dessus d'une couche d'isolation à motif (200) qui est présente dans le corps semi-conducteur (11) de silicium. Selon cette invention, le procédé est caractérisé en ce que la couche d'isolation (200) se trouve sur la partie supérieure du corps semi-conducteur (11) et est conçue de façon à comprendre une fenêtre (21) qui borde une région (20) de la couche d'isolation et en ce que la première couche semi-conductrice (1) a crû directement sur la partie du corps semi-conducteur (11) en dessous de la fenêtre (21) et la région (20) de la couche isolation est recouverte par la première couche semi-conductrice au moyen d'une surcroissance latérale. Ainsi, est obtenue la couche détendue pratiquement sans défaut (1) ou une couche détendue (1), dont au moins la partie visualisée en saillie se trouvant au-dessus de la région d'isolation (20) est sensiblement exempte de défaut.
PCT/IB2005/052382 2004-07-22 2005-07-18 Procede de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur ainsi obtenu WO2006011107A1 (fr)

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EP04103495 2004-07-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3048815A1 (fr) * 2016-03-14 2017-09-15 Commissariat Energie Atomique Procede de co-realisation de zones sous contraintes uniaxiales differentes

Citations (2)

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Publication number Priority date Publication date Assignee Title
US20030139000A1 (en) * 2002-01-23 2003-07-24 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
WO2004023536A1 (fr) * 2002-09-03 2004-03-18 University Of Warwick Formation de substrats semi-conducteurs en accord de maille

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US20030139000A1 (en) * 2002-01-23 2003-07-24 International Business Machines Corporation Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications
WO2004023536A1 (fr) * 2002-09-03 2004-03-18 University Of Warwick Formation de substrats semi-conducteurs en accord de maille

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Title
"Dislocation filtering in SiGe and InGaAs buffer layers grown by selective lateral overgrowth method", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 66, no. 10, 6 March 1995 (1995-03-06), pages 1237 - 1239, XP012012315, ISSN: 0003-6951 *
LANGDO T A ET AL: "High quality Ge on Si by epitaxial necking", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 76, no. 25, 19 June 2000 (2000-06-19), pages 3700 - 3702, XP012025569, ISSN: 0003-6951 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3048815A1 (fr) * 2016-03-14 2017-09-15 Commissariat Energie Atomique Procede de co-realisation de zones sous contraintes uniaxiales differentes
US10665497B2 (en) 2016-03-14 2020-05-26 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions

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