WO2005109642A1 - 等位相多相クロック信号発生回路およびそれを用いたシリアルディジタルデータ受信回路 - Google Patents
等位相多相クロック信号発生回路およびそれを用いたシリアルディジタルデータ受信回路 Download PDFInfo
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- WO2005109642A1 WO2005109642A1 PCT/JP2005/006647 JP2005006647W WO2005109642A1 WO 2005109642 A1 WO2005109642 A1 WO 2005109642A1 JP 2005006647 W JP2005006647 W JP 2005006647W WO 2005109642 A1 WO2005109642 A1 WO 2005109642A1
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- 230000000295 complement effect Effects 0.000 claims abstract description 304
- 230000001360 synchronised effect Effects 0.000 claims abstract description 60
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 57
- 230000000630 rising effect Effects 0.000 claims description 10
- 238000007493 shaping process Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000001419 dependent effect Effects 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 18
- 239000000872 buffer Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 230000003139 buffering effect Effects 0.000 description 4
- 238000005070 sampling Methods 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
Definitions
- the present invention relates to a serial digital data receiving circuit, and more particularly to an equal-phase and multi-phase clock signal generating circuit using a DLL circuit used for a serial digital data receiving circuit.
- receiving circuits for high-speed serial digital data include, in demodulation of digital data, a symbol of an equiphase multiphase clock signal synchronized with a cycle of a transmission clock signal N times the number of serialization symbol bits.
- a method of sampling serial digital data using a sample signal is generally used.
- phase-frequency comparator In such a receiving circuit using a method of sampling serial digital data using an equal-phase polyphase clock signal synchronized with the cycle of the transmission clock signal, a phase-frequency comparator and a voltage-controlled oscillator are combined.
- a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit combining a phase comparator and a voltage-controlled delay element is generally used for generating an equal-phase polyphase clock.
- FIG. 24 of Patent Document 1 shown below shows a DLL circuit commonly used in the prior art!
- Patent Document 1 JP-A-9 7396
- jitter 1 In actual high-speed serial digital transmission, a short-period frequency fluctuation called "jitter 1" occurs in the transmission clock and serial transmission data due to fluctuations in the power supply of the transmission circuit and the influence of disturbance on the transmission line. I do. In a receiver circuit for high-speed serial digital transmission signals, it is necessary to make the equal-phase multi-phase clock signal used for sampling the received data follow the frequency fluctuation due to this jitter.
- a receiver circuit using a delay locked loop circuit has good follow-up to the frequency fluctuation of a transmission clock caused by this jitter. Considered to be the preferred circuit scheme It is.
- the input clock signal itself and the output signal from the voltage control delay element to which the input clock signal is input are used.
- a circuit configuration is used that generates a multiphase clock with the same phase synchronized with the cycle of the input clock signal. If such a circuit configuration is adopted, a change in the duty ratio of the input clock signal will propagate through the voltage control delay element as it is. Therefore, it was difficult to determine the duty ratio of the output multiphase clock signal constant, independent of the duty ratio of the input clock signal.
- Fig. 7 shows a configuration of a conventional example of an equal-phase and multi-phase clock signal generation circuit using a DLL circuit in a serial digital transmission signal reception circuit used for receiving serial transmission data.
- the equal-phase and multi-phase clock signal generation circuit using the DLL circuit shown in FIG. 7 there are a complementary clock signal llOlp / llOln to be input and a complementary output signal 1102 ⁇ / 1102 ⁇ from the preamplifier circuit 1102.
- This complementary output signal 1102 ⁇ / 1102 ⁇ is input to the complementary voltage control delay element array 1110, and the output signal 1105 and the signal 1103 obtained by buffering the 1102 ⁇ signal of the complementary output signal are compared by the phase detector (Phase Detector) 1120. After the comparison, the output signal 1104 shaped by the loop filter circuit (Loop Filter) 1130 is fed back as a control voltage signal of the complementary voltage control delay element array 1110.
- FIG. 8 shows the timing of the internal signal when synchronized with the period of the complementary clock signal llOlp / llOln in the equal-phase and multi-phase clock signal generation circuit using the conventional DLL circuit shown in Fig. 7.
- FIG. 8 shows the timing of the internal signal when synchronized with the period of the complementary clock signal llOlp / llOln in the equal-phase and multi-phase clock signal generation circuit using the conventional DLL circuit shown in Fig. 7.
- FIG. 8 the 1103 signal and the output signal of the complementary voltage control delay element column are shown.
- FIG. 9 shows that the input clock 1101p whose duty ratio greatly deviates from 50% is added to the co-phase polyphase clock signal generation circuit using the conventional DLL circuit shown in FIG.
- FIG. 9 shows a timing chart of internal signals when / l 101 ⁇ is input.
- FIG. Figure 10 shows a conventional example of an equal-phase and multi-phase clock signal generation circuit that uses a DLL circuit that incorporates a double frequency divider in the serial digital transmission signal reception circuit used to receive serial transmission data. Things.
- This complementary output signal 1102p / 1102n is converted to a complementary clock signal 1400p / 1400n that maintains a constant duty ratio of 50% without depending on the duty ratio of the input clock signal llOlp / llOln by a double frequency divider 1410. Is converted.
- the complementary clock signals 1400p / 1400n that maintain a constant duty ratio of 50% are input to the complementary voltage control delay element array 1110.
- FIG. 11 shows a timing diagram of internal signals when synchronizing with the cycle of the input clock in the equal-phase and multi-phase clock signal generation circuit using the DLL circuit of the conventional example shown in FIG. .
- the signal 1103 obtained by buffering the complementary clock signals 1400p / 1400n is synchronized with the output signal 1105 of the complementary voltage control delay element array 1101.
- the present invention has been made in view of the above-described problem, and minimizes the number of elements, suppresses an increase in a circuit area of a semiconductor substrate and an increase in power consumption, and reduces the duty of an input clock signal. It is an object of the present invention to realize a circuit capable of setting a constant duty ratio of an output equal-phase multiphase clock signal independently of a ratio.
- the input clock signal is once converted into a complementary clock signal which is frequency-divided by twice, and then the complementary voltage control delay is applied. Input to element row.
- the input complementary clock signal is frequency-divided into a double cycle, and this frequency-divided complementary clock signal is a clock signal that maintains a constant duty ratio (for example, 50%) without depending on the duty ratio of the input complementary clock. become.
- This divider circuit In, the positive phase or inverted phase of the frequency-divided complementary clock signal is sequentially synchronized at one cycle timing of the input complementary clock signal. In other words, in this frequency division circuit, the rise edge (or fall edge) of the input complementary clock signal and the second
- the positive phase rise edge (or fall edge) or the inverted phase rise edge (or fall edge) of the two complementary clock signals are sequentially synchronized.
- the divided complementary clock signal is input to a voltage-controlled delay element array (voltage-controlled delay circuit), and the complementary output signal from the voltage-controlled delay element array is divided into a divided complementary clock signal.
- a voltage-controlled delay element array voltage-controlled delay circuit
- the complementary output signal from the voltage-controlled delay element array is divided into a divided complementary clock signal.
- the duty ratio of the complementary clock signal input to the complementary voltage control delay element row is fixed irrespective of the duty ratio of the input clock. . Therefore, the duty ratio of the polyphase clock train output from the complementary voltage control delay element train is also kept constant. For example, if the duty ratio of the complementary clock signal input to the complementary voltage controlled delay element array is fixed at 50%, the duty ratio of the polyphase clock array output from the complementary voltage controlled delay element array is also maintained at 50%. You will be drowned.
- the edge (rise edge or fall edge) of the divided complementary clock signal whose phase is compared is alternately switched between the complementary clock signals. I do.
- the positive phase and the inverted phase of the divided complementary clock signal are sequentially synchronized with the complementary output signal of the complementary voltage control delay circuit.
- the positive phase of the divided complementary clock signal is synchronized with the inverted phase of the complementary output signal of the complementary voltage control delay circuit, and the inverted phase of the divided complementary clock signal is synchronized with the complementary voltage control delay.
- the positive phase of the complementary output signal of the circuit is synchronized.
- a complementary clock signal divided by a double cycle has a complementary clock signal separated by a phase (360 degrees) corresponding to twice the cycle of the input clock signal input to the circuit.
- the signal that is separated by a phase (180 degrees) corresponding to the period of the input clock signal input to the circuit is not synchronized. That is, as compared with.
- the clock signal output from the voltage control delay element row is synchronized with the same cycle as the original input clock signal.
- the period of the multi-phase output clock train from the voltage-controlled delay element array is twice as long as the original input clock signal. Since the duty ratio of the multiphase output clock signal is fixed, a quadrature circuit that reduces the cycle by half is added to easily realize an equiphase multiphase clock signal synchronized with the cycle of the input clock signal. Can do things.
- the in-phase and multi-phase clock signal generation circuit of the invention can operate in a wide range of 10% to 90% of the input clock signal duty cycle, and can realize high reliability against the frequency fluctuation of the input clock due to the influence of jitter and the like. it can.
- a frequency dividing circuit for dividing an input first complementary clock signal by two to generate a second complementary clock signal having a constant duty ratio
- a frequency divider having control means for sequentially synchronizing the positive phase or the inverted phase of the clock signal
- a complementary voltage control delay circuit having a plurality of voltage control delay elements connected in series, wherein the second complementary clock A complementary voltage for receiving a signal, generating an equal-phase polyphase clock signal having a phase difference from each of the plurality of voltage-controlled delay elements, and generating a complementary output signal of a final stage of the plurality of voltage-controlled delay elements.
- a control delay circuit for comparing the phase of the complementary output signal of the complementary voltage control delay circuit with the second complementary clock signal; Shaping the force signal, equiphase multiphase clock signal generator circuit having a loop filter for outputting a signal as the control voltage signal to a plurality of voltage controlled delay elements of said complementary voltage control delay circuit is provided.
- the input first complementary clock signal is divided by two and the duty ratio is Is a frequency divider circuit for generating a constant second complementary clock signal, wherein the rising edge of the first complementary clock signal and the rising edge or inverting phase of the positive phase of the second complementary clock signal are And a complementary voltage control delay circuit having a plurality of voltage control delay elements connected in series, wherein the second complementary clock signal is inputted.
- a complementary voltage control delay circuit for generating an equal phase multi-phase clock signal having a phase difference from each of the plurality of voltage control delay elements, and generating a complementary output signal from the last stage of the plurality of voltage control delay elements;
- a multi-phase comparison circuit for comparing the phase of the complementary output signal of the complementary voltage control delay circuit with the second complementary clock signal, and an output from the multi-phase comparison circuit.
- To integer form signal like the phase multiphase clock signal generator circuit having a loop filter for outputting a signal as the control voltage signals to said plurality of voltage controlled delay elements of said complementary voltage control delay circuit is provided.
- the positive phase or the inverted phase of the second complementary clock signal may be sequentially synchronized with the complementary output signal of the complementary voltage control delay circuit.
- the positive phase of the second complementary clock signal is synchronized with the inverted phase of the complementary output signal of the complementary voltage control delay circuit, and the second complementary clock signal is synchronized with the second phase.
- the opposite phase of the complementary clock signal may be synchronized with the positive phase of the complementary output signal of the complementary voltage control delay circuit!
- a rise edge of a positive phase of the second complementary clock signal and a rise edge of an inverted phase of the complementary output signal of the complementary voltage control delay circuit are used. It is preferable that the rising edge of the opposite phase of the second complementary clock signal is synchronized with the rising edge of the positive phase of the complementary output signal of the complementary voltage control delay circuit.
- the duty ratio of the first complementary clock signal is in the range of 10 to 90%.
- the apparatus may further include a quadrature circuit for converting a cycle of the equal-phase and multi-phase clock signal.
- the input first complementary clock signal is divided by two and the duty ratio is Is serially connected to a frequency dividing circuit for generating a constant second complementary clock signal, the frequency dividing circuit having control means for sequentially synchronizing the positive or inverted phase of the second complementary clock signal.
- a complementary voltage controlled delay circuit having a plurality of voltage controlled delay elements, wherein the second complementary clock signal is inputted, and the plurality of voltage controlled delay elements have a phase difference from each other.
- a complementary voltage control delay circuit for generating a complementary output signal from the last stage of the plurality of voltage control delay elements; a complementary output signal of the complementary voltage control delay circuit and the second complementary clock signal; And a plurality of voltage-controlled delay elements of the complementary voltage-controlled delay circuit, wherein the plurality of voltage-controlled delay elements of the complementary voltage-controlled delay circuit are shaped.
- a parallel-phase clock signal generating circuit having a loop filter for outputting a signal as a control voltage signal, and a parallelizer for parallelizing input serial digital data based on the same-phase multiphase clock signal.
- a serial digital data receiving circuit having the shading circuit.
- a frequency dividing circuit for dividing the input first complementary clock signal by 2 and generating a second complementary clock signal having a constant duty ratio, wherein the first complementary clock signal is divided into two.
- a frequency dividing circuit having control means for sequentially synchronizing a rising edge of the clock signal and a rising edge of a positive phase or an inverting phase of the second complementary clock signal; and a plurality of voltage control circuits connected in series.
- a complementary voltage control delay circuit for generating a complementary output signal from the last stage of the plurality of voltage control delay elements, and the complementary output signal of the complementary voltage control delay circuit and the second complementary A multiplexed phase comparison circuit for performing phase comparison with a clock signal; a signal output from the multiplexed phase comparison circuit is shaped; and a signal is supplied as a control voltage signal to the plurality of voltage control delay elements of the complementary voltage control delay circuit.
- a serial digital circuit comprising: an equal-phase multi-phase clock signal generation circuit having a loop filter for outputting; and a parallel conversion circuit for converting input serial digital data based on the equal-phase multi-phase clock signal.
- a data receiving circuit is provided.
- the multiplex phase comparison circuit it is preferable that a positive phase or an inverted phase of the second complementary clock signal is sequentially synchronized with the complementary output signal of the complementary voltage control delay circuit.
- the positive phase of the second complementary clock signal is synchronized with the inverted phase of the complementary output signal of the complementary voltage control delay circuit, and the second complementary clock signal is synchronized with the second phase.
- the opposite phase of the complementary clock signal may be synchronized with the positive phase of the complementary output signal of the complementary voltage control delay circuit!
- a rise edge of the positive phase of the second complementary clock signal and a rise edge of the inverted phase of the complementary output signal of the complementary voltage control delay circuit are used. It is preferable that the rising edge of the opposite phase of the second complementary clock signal is synchronized with the rising edge of the positive phase of the complementary output signal of the complementary voltage control delay circuit.
- the duty ratio of the first complementary clock signal is in the range of 10 to 90%.
- the apparatus may further include a quadrature circuit for converting a cycle of the equal-phase and multi-phase clock signal.
- the clock signals output from the voltage-controlled delay elements are synchronized with the same cycle as the original input clock signal. .
- This makes it possible to keep the duty ratio of the output equal-phase multiphase clock signal constant and to follow the frequency fluctuation of the input clock signal independently of the duty ratio of the input clock signal. It is possible to reduce the total number of voltage control delay element rows required to obtain the circuit, reduce the circuit scale, reduce the circuit area on the semiconductor substrate, reduce power consumption, and further reduce operation. It has an excellent effect that noise can be greatly reduced.
- equal-phase and multi-phase clock signal generation circuit normal operation can be guaranteed only when the duty ratio of the input clock is within the range of 30% to 70%.
- the equal-phase and multi-phase clock signal generation circuit of the invention can operate in a wide range of 10% to 90% of the input clock signal duty cycle, and the input clock signal is affected by jitter and the like. High reliability against frequency fluctuations can be realized.
- FIG. 1 is a diagram showing an embodiment of an equal-phase and multi-phase clock signal generation circuit according to the present invention.
- FIG. 2 is a timing chart of internal signals when the input clock signal ⁇ / lOln of the equal-phase and multi-phase clock signal generation circuit of the present invention shown in FIG. 1 is synchronized.
- FIG. 3 is a diagram showing a circuit example of a double frequency dividing circuit.
- FIG. 4 is a diagram showing a circuit example of a 1Z2 quadruple circuit.
- FIG. 5 is a timing chart of internal signals when synchronized with complementary clock signals 103p / 103n of the equal-phase and multi-phase clock signal generation circuit of the present embodiment shown in FIG.
- FIG. 6 is a diagram showing an embodiment of a serial digital data receiving circuit using the equal-phase and multi-phase clock signal generating circuit of the present invention.
- FIG. 7 is a diagram showing a conventional equal-phase and multi-phase clock signal generation circuit.
- FIG. 8 is a timing chart of internal signals when synchronizing with the period of the complementary clock signal 1101p / l 101 ⁇ in the conventional equal-phase polyphase clock signal generation circuit shown in FIG.
- FIG. 9 Internal signal when an input clock 1101p / l 101 ⁇ with a duty ratio greatly deviated from 50% is input to the equal-phase and multi-phase clock signal generation circuit using the conventional DLL circuit shown in FIG. FIG.
- FIG. 10 is a diagram showing a conventional equal-phase and multi-phase clock signal generation circuit.
- FIG. 11 is a timing chart of internal signals when synchronizing with the period of the complementary clock signal llOlp / llOln in the conventional equal-phase polyphase clock signal generation circuit shown in FIG.
- FIG. 1 shows an embodiment of a circuit configuration of an equal-phase and multi-phase clock signal generation circuit 100 according to the present invention.
- the complementary clock signal ⁇ / lOln is input to the equal-phase multiphase clock signal generation circuit 100 of the present invention, and the equal-phase multiphase clock signal 111 to 116 are generated and output by the equal-phase multiphase clock signal generation circuit 100. .
- the equal-phase polyphase clock signal generation circuit 100 includes a preamplifier circuit 102, a double frequency divider circuit 410, buffers 411, 412, 413, and 414, a double phase detector (Double Phase Detector) 420, a loop filter It has a circuit (Loop Filter) 130, a complementary voltage controlled delay element array 110 having six complementary voltage controlled delay elements, and a doubler circuit 430.
- the preamplifier circuit 102, the buffers 411, 412, 413 and 414, and the doubler circuit 430 may be provided as necessary.
- the complementary clock signal ⁇ / lOln is input to the preamplifier circuit 102 of the equal-phase and multi-phase clock signal generation circuit 100.
- the complementary clock signal ⁇ / lOln is amplified by the preamplifier circuit 102 to a complementary output clock signal 102p / 102n.
- the complementary output clock signal 102p / 102n is input to the double frequency divider 410, and is divided by two to maintain a constant duty ratio of 50% without depending on the duty ratio of the complementary clock signal ⁇ / lOln.
- the clock signal is converted to 400p / 400n.
- the frequency-divided clock signal 400p / 400n divided by 2 with a constant duty ratio of 50% is generated in the double frequency dividing circuit 410.
- the duty ratio may be slightly different from the preset duty ratio due to the circuit configuration, noise, or the like.
- the two-divided complementary clock signal 400p / 400n may be generated.
- the complementary clock signal 400p / 400n divided by 2 while maintaining a constant duty ratio of 50% is input to the complementary voltage control delay element array 110.
- the complementary clock signal 400p / 400n divided by 2 is input to six series-connected complementary voltage control delay elements, and the complementary clock signal 400p / 400n , And are propagated while generating a phase delay in the respective complementary voltage control delay elements.
- Output signals from the complementary voltage control delay element array 110 are buffered by buffers 413 and 414.
- 103p / 103n are compared by a multiplexed phase comparison circuit 420.
- the output of the multiplex phase comparison circuit 420 is shaped by the loop filter circuit 130, becomes an output signal 104, and is input to the complementary voltage control delay element array 110.
- This output signal 104 is fed back as a control voltage signal for the complementary voltage control delay element array 110.
- the period of the complementary clock signal 400p / 400n input to the complementary voltage control delay element row 110 is determined by the input clock signal ⁇ / lOln input from outside the circuit. Therefore, the cycles of the equal-phase polyphase clocks 401p / 401n, 402p / 402n, 403p / 403n, 404p / 404n, 405p / 405n, and 406p / 406n from the complementary voltage control delay element array 110 are It is twice the input clock signal ⁇ / lOln.
- the equal-phase multiphase clocks 401p / 401n, 402p / 402n, 403p / 403n, 404p / 404n, 405p / 405n, and 406p / 406n are passed through the doubling circuit 430.
- a configuration is adopted in which these periods are halved and the equal-phase multiphase clocks 111 to 116 are output in synchronization with the period of the input clock signal ⁇ / ⁇ .
- FIG. 2 is a timing chart of internal signals when the input clock signal ⁇ / lOln of the equal-phase and multi-phase clock signal generation circuit of the present invention shown in FIG. 1 is synchronized.
- the input complementary clock signal ⁇ / lOln whose duty ratio is greatly shifted by 50%, is It can be seen that, even when input, the complementary clock signal 103p / 103n after passing through the double frequency dividing circuit 410 has a 50% duty ratio.
- the positive phase 103p or the inverted phase 103 ⁇ of the frequency-divided complementary clock signal is sequentially synchronized at one cycle of the input complementary clock signal ⁇ / lOln.
- the rise edge of the input complementary clock signal ⁇ / lOln is synchronized with the rise edge of the positive phase 103p or the inverse phase 103 ⁇ of the complementary clock signal in order.
- the point a of the input complementary clock signal l ⁇ / lOln and the point a ′ of the positive phase 103 ⁇ of the divided complementary clock signal are synchronized.
- the point b of the input complementary clock signal ⁇ / lOln is synchronized with the point of the positive phase 103 ⁇ of the divided complementary clock signal
- the point c of the input complementary clock signal ⁇ / lOln is synchronized with the point c of the divided complementary clock signal.
- the point c 'of the positive phase 103 ⁇ is synchronized.
- the edge of the complementary clock signal 103 ⁇ / 103 ⁇ to be compared in phase in the multiplexed phase comparison circuit 420 ( ⁇ , rise edge in the present embodiment) is set to the positive phase of the complementary clock signal 103 ⁇ / 103 ⁇ . (103 ⁇ ) and the inverted phase (103 ⁇ ) are alternately switched, and as a result, the output signal 105 ⁇ / 105 ⁇ from the complementary voltage control delay element array 110 and the complementary clock signal 103 ⁇ / 103 ⁇ are complemented by the complementary clock signal 103 ⁇ / 103 ⁇ .
- ⁇ rise edge in the present embodiment
- the positive phase (103 ⁇ ) and the inverted phase (103 ⁇ ) of the frequency-divided complementary clock signal 103 ⁇ / 103 ⁇ are sequentially output to the complementary output signal 105 ⁇ /
- the period of the complementary clock signal 103 ⁇ / 103 ⁇ divided by two times corresponds to twice the period of the input clock signal ⁇ / lOln input to the circuit.
- the input clock signal is input to the circuit lOlp / lOln This is done by comparing the clock signal 103 ⁇ / 103 ⁇ separated by a phase (180 degrees) corresponding to the period of the period with the output 105 ⁇ / 105 ⁇ from the voltage control delay element array 110! /.
- FIG. 3 shows a double frequency dividing circuit 410 (FIG. 3 (A)) and a multi-phase comparing circuit 420 (FIG. 3 (B)) used in the equal-phase and multi-phase clock signal generating circuit of the present embodiment shown in FIG. An example is shown.
- the frequency dividing circuit 410 converts the complementary output clock signal 102p / 102n into a complementary clock signal 400p / 400n having a double cycle.
- the frequency dividing circuit 410 shown in FIG. 3A has three CMOS transfer gate circuits 801a to 801c and five CMOS inverter circuits 803. Note that the frequency dividing circuit 410 shown in FIG. 3A is merely an example, and any circuit that realizes a similar function other than the present embodiment can be used as an equal-phase multi-phase clock signal generating circuit according to the present invention. Can be used as the frequency dividing circuit 410.
- the input complementary output clock signal 102p / 102n is input to three CMOS transfer gate circuits 801a to 801c.
- the CMOS transfer gate circuits 801b and 801c control means 802 which also generates the complementary clock signal 400p / c from the frequency divider 410, converts the points a, b, and c in the input complementary clock signal ⁇ / lOln shown in FIG.
- This control means has the function of adjusting the timing to points a, b ', and c in the inverted complementary clock signal 103p / 103n obtained by inverting 400n, that is, synchronizing.
- the multi-phase comparison circuit 420 has two CMOS NAND circuits 804, two CMOS NOR circuits 805, and four D-type flip-flop circuits 806. .
- the multiplex phase comparison circuit 420 compares the phase between the positive phase 103p of the complementary clock signal and the inverted phase 105 ⁇ of the output signal from the complementary voltage control delay element array 110, and compares the inverted phase 103 ⁇ of the complementary clock signal with the inverted phase 103 ⁇ . By comparing the phase of the output signal from the complementary voltage control delay element array 110 with the positive phase 105 ⁇ , the phase difference of each signal is calculated and output.
- the multi-phase comparison circuit 420 shown in FIG. 3B is merely an example, and any circuit that realizes the same function other than the present embodiment may be used as the equal-phase multi-phase clock signal generation circuit according to the present invention. 100 multi-phase comparison circuits 420 can be used.
- FIG. 4 shows an example of the doubling circuit 430 used in the equal-phase and multi-phase clock signal generation circuit of the present embodiment shown in FIG.
- the quadruple circuit 430 has three CMOS NAND circuits 807. It should be noted that the quadruple circuit 430 shown in FIG. 4 is merely an example, and any circuit that realizes a similar function in addition to the present embodiment may be used as the quadrature circuit of the equal-phase multiphase clock signal generation circuit 100 of the present invention. Can be used as road 430.
- FIG. 5 is a timing chart of the internal signals when synchronized with the complementary clock signals 103p / 103n of the equal-phase and multi-phase clock signal generation circuit of the present embodiment shown in FIG.
- the equal-phase and multi-phase clock signal generation circuit As described above, the equal-phase and multi-phase clock signal generation circuit according to the present embodiment
- the clock signal output from the voltage control delay element row at the same cycle as the input clock signal is synchronized.
- the duty ratio of the input clock signal is made independent of the duty ratio of the input clock signal, and the duty ratio of the input clock signal is kept constant. It is possible to reduce the total number of voltage control delay element arrays required to obtain a clock array, thereby reducing the circuit scale, the circuit area on the semiconductor substrate, and power consumption. It has an excellent effect that operation noise can be greatly reduced.
- the in-phase and multi-phase clock signal generation circuit of the invention can operate in a wide range of 10% to 90% of the input clock signal duty cycle, and can realize high reliability against the frequency fluctuation of the input clock due to the influence of jitter and the like. it can.
- Reference numeral 600 denotes a serial digital data receiving circuit, which includes two buffers 601, a parallelization circuit (De-Serializer) 604, a multiplexer circuit 605, and an equal-phase and multi-phase clock signal generation circuit 100.
- Serial digital data receiving circuit 600 includes two buffers 601, a parallelization circuit (De-Serializer) 604, a multiplexer circuit 605, and an equal-phase and multi-phase clock signal generation circuit 100.
- the circuit described in the above embodiment can be used as the equal-phase and multi-phase clock signal generation circuit 100.
- the multiplex phase comparator is denoted by "PD”
- the loop filter is denoted by "LPF”
- the complementary voltage control delay element array is denoted by "VCD”.
- the serial digital data 702 to which the external power of the circuit is also input is amplified by the buffer 601 and then input to the parallelizing circuit 604.
- the reference clock 701 is also amplified by the buffer 601 and then output to the equal-phase and multi-phase clock signal generation circuit 100.
- the equal-phase multi-phase clock signal generation circuit 100 generates equal-phase multi-phase clock signals 111 to 116 based on the complementary clock signal output from the buffer 601 and inputted thereto. 604 and output outside the circuit.
- the parallelizing circuit 604 parallelizes the serial digital data 702 input based on the equal-phase and multi-phase clock signals 111 to 116, generates parallel data, and outputs the parallel data to the multiplexer circuit 605.
- the multiplexer circuit 605 selects the input parallel data according to the timing and outputs it to the outside of the circuit.
- the same-phase and multi-phase clock signal generating circuit described in the above embodiment is used.
- this equal-phase and multi-phase clock signal generating circuit the clock signals output from the voltage-controlled delay element array are synchronized with the same cycle as the original input clock signal. This makes it possible to keep the duty ratio of the output equal-phase multiphase clock signal constant and to follow the frequency fluctuation of the input clock independently of the duty ratio of the input clock signal, while maintaining the multiphase output clock at equal phase intervals. It is possible to reduce the total number of voltage-controlled delay element arrays required to obtain a serial line, and to reduce the circuit scale of the serial digital data receiving circuit of the present embodiment and the circuit area on the semiconductor substrate. This has the excellent effect of reducing power consumption and greatly reducing operating noise.
- the equal-phase and multi-phase clock signal generation circuit used in this embodiment can operate over a wide range of duty ratios of the input clock signal of 10% to 90%, This makes it possible to achieve high reliability with respect to input clock frequency fluctuations.
- the equal-phase multi-phase clock signal generation circuit of the present invention sets the duty ratio of the output equal-phase multi-phase clock signal to be constant and independent of the duty ratio of the input clock signal. It is possible to reduce the total number of voltage-controlled delay elements required to obtain a multi-phase output clock train with equal phase intervals while realizing the ability to follow fluctuations.
- the circuit scale can be reduced, the circuit area on the semiconductor substrate can be reduced, power consumption can be reduced, and operation noise can be reduced. It has an excellent effect that the size can be greatly reduced.
- the equal-phase multi-phase clock signal generation circuit of the present invention can be used not only for a serial digital data receiving circuit in a serial digital transmission system but also for any electronic circuit requiring an equal-phase multi-phase clock signal. Can be used.
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
- Dram (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05728414A EP1746724A4 (en) | 2004-05-12 | 2005-04-05 | EQUIPHASE POLYPHASE CLOCK SIGNAL GENERATOR SWITCHING AND SERIAL DIGITAL DATA RECEIVER SWITCHING SOON |
US10/592,709 US20070223638A1 (en) | 2004-05-12 | 2005-04-05 | Isophase Multiphase Clock Signal Generation Circuit and Serial Digital Data Receiving Circuit Using the Same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-141770 | 2004-05-12 | ||
JP2004141770A JP2005328109A (ja) | 2004-05-12 | 2004-05-12 | 等位相多相クロック信号発生回路およびそれを用いたシリアルディジタルデータ受信回路 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005109642A1 true WO2005109642A1 (ja) | 2005-11-17 |
Family
ID=35320520
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/006647 WO2005109642A1 (ja) | 2004-05-12 | 2005-04-05 | 等位相多相クロック信号発生回路およびそれを用いたシリアルディジタルデータ受信回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20070223638A1 (ja) |
EP (1) | EP1746724A4 (ja) |
JP (1) | JP2005328109A (ja) |
KR (1) | KR20060038354A (ja) |
CN (1) | CN1774863A (ja) |
WO (1) | WO2005109642A1 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10345236B3 (de) * | 2003-09-29 | 2005-03-10 | Infineon Technologies Ag | Verzögerungsregelkreis |
KR100776736B1 (ko) * | 2005-12-28 | 2007-11-19 | 주식회사 하이닉스반도체 | 클럭 동기 장치 |
JP4878969B2 (ja) * | 2006-09-15 | 2012-02-15 | 株式会社リコー | 遅延ロックループ回路 |
JP4774005B2 (ja) * | 2007-04-11 | 2011-09-14 | ザインエレクトロニクス株式会社 | 受信装置 |
JP5807065B2 (ja) * | 2011-07-19 | 2015-11-10 | 株式会社メガチップス | 位相比較装置およびdll回路 |
CN102761319B (zh) * | 2012-04-27 | 2015-04-08 | 北京时代民芯科技有限公司 | 一种具有占空比稳定和相位校准的时钟电路 |
CN103269215A (zh) * | 2013-06-03 | 2013-08-28 | 上海宏力半导体制造有限公司 | 倍频电路 |
JP2015149669A (ja) * | 2014-02-07 | 2015-08-20 | 富士通株式会社 | クロック制御回路,受信器および通信装置 |
KR20170005330A (ko) * | 2015-07-03 | 2017-01-12 | 에스케이하이닉스 주식회사 | 클럭 생성 회로 및 방법, 이를 이용한 반도체 장치 및 전자 시스템 |
US9912328B1 (en) * | 2016-08-23 | 2018-03-06 | Micron Technology, Inc. | Apparatus and method for instant-on quadra-phase signal generator |
KR20220001578A (ko) | 2020-06-30 | 2022-01-06 | 삼성전자주식회사 | 대칭적인 구조를 갖는 클럭 변환 회로 |
CN116996047A (zh) * | 2022-04-26 | 2023-11-03 | 长鑫存储技术有限公司 | 时钟生成电路、等距四相位信号生成方法和存储器 |
US11703905B1 (en) | 2022-04-26 | 2023-07-18 | Changxin Memory Technologies, Inc. | Clock generation circuit, equidistant four-phase signal generation method, and memory |
WO2024099557A1 (en) * | 2022-11-09 | 2024-05-16 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus for phase and frequency detection and representation |
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JPH11205102A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 遅延同期回路 |
JP2000059183A (ja) * | 1998-08-05 | 2000-02-25 | Mitsubishi Electric Corp | 同期逓倍クロック信号生成回路 |
Family Cites Families (11)
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JP3320651B2 (ja) * | 1998-05-06 | 2002-09-03 | 富士通株式会社 | 半導体装置 |
US6313688B1 (en) * | 1998-07-24 | 2001-11-06 | Gct Semiconductor, Inc. | Mixer structure and method of using same |
JP3506917B2 (ja) * | 1998-07-30 | 2004-03-15 | シャープ株式会社 | 位相比較器 |
FR2793091B1 (fr) * | 1999-04-30 | 2001-06-08 | France Telecom | Dispositif d'asservissement de frequence |
US6359486B1 (en) * | 2000-05-22 | 2002-03-19 | Lsi Logic Corporation | Modified phase interpolator and method to use same in high-speed, low power applications |
EP1537669A1 (en) * | 2002-08-30 | 2005-06-08 | Koninklijke Philips Electronics N.V. | Phase locked loop |
US7042260B2 (en) * | 2004-06-14 | 2006-05-09 | Micron Technology, Inc. | Low power and low timing jitter phase-lock loop and method |
US7274232B2 (en) * | 2005-03-17 | 2007-09-25 | Realtek Semiconductor Corp. | Variable delay clock synthesizer |
US7545188B1 (en) * | 2006-08-04 | 2009-06-09 | Integrated Device Technology, Inc | Multiphase clock generator |
TWI324858B (en) * | 2006-08-16 | 2010-05-11 | Holtek Semiconductor Inc | Dll and angle generator |
KR101499176B1 (ko) * | 2008-04-08 | 2015-03-06 | 삼성전자주식회사 | 클럭 신호의 위상 튜닝 방법 및 그 장치 |
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2004
- 2004-05-12 JP JP2004141770A patent/JP2005328109A/ja not_active Withdrawn
-
2005
- 2005-04-05 CN CNA2005800002561A patent/CN1774863A/zh active Pending
- 2005-04-05 EP EP05728414A patent/EP1746724A4/en not_active Withdrawn
- 2005-04-05 KR KR1020057014165A patent/KR20060038354A/ko active IP Right Grant
- 2005-04-05 WO PCT/JP2005/006647 patent/WO2005109642A1/ja not_active Application Discontinuation
- 2005-04-05 US US10/592,709 patent/US20070223638A1/en not_active Abandoned
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JPH11205102A (ja) * | 1998-01-13 | 1999-07-30 | Mitsubishi Electric Corp | 遅延同期回路 |
JP2000059183A (ja) * | 1998-08-05 | 2000-02-25 | Mitsubishi Electric Corp | 同期逓倍クロック信号生成回路 |
Non-Patent Citations (1)
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Also Published As
Publication number | Publication date |
---|---|
EP1746724A1 (en) | 2007-01-24 |
JP2005328109A (ja) | 2005-11-24 |
EP1746724A4 (en) | 2007-05-30 |
CN1774863A (zh) | 2006-05-17 |
US20070223638A1 (en) | 2007-09-27 |
KR20060038354A (ko) | 2006-05-03 |
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