WO2005104239A1 - Thin-film transistor and production method therefor - Google Patents

Thin-film transistor and production method therefor Download PDF

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Publication number
WO2005104239A1
WO2005104239A1 PCT/JP2005/007808 JP2005007808W WO2005104239A1 WO 2005104239 A1 WO2005104239 A1 WO 2005104239A1 JP 2005007808 W JP2005007808 W JP 2005007808W WO 2005104239 A1 WO2005104239 A1 WO 2005104239A1
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WO
WIPO (PCT)
Prior art keywords
silicon
gas
film
silicon oxide
silicon nitride
Prior art date
Application number
PCT/JP2005/007808
Other languages
French (fr)
Japanese (ja)
Inventor
Sadatsugu Wakamatsu
Toru Kikuchi
Masanori Hashimoto
Takaomi Kurata
Shin Asari
Kazuya Saito
Original Assignee
Ulvac, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac, Inc. filed Critical Ulvac, Inc.
Priority to JP2006519508A priority Critical patent/JP5066361B2/en
Priority to KR1020067005921A priority patent/KR101184232B1/en
Publication of WO2005104239A1 publication Critical patent/WO2005104239A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the present invention relates to a thin film transistor having a silicon oxide film as a gate insulating layer and a method for manufacturing the same.
  • devices such as a liquid crystal display (LCD) and an organic electroluminescent device (OLED) include amorphous silicon (a-Si) ⁇ ⁇ silicon nitride film (SiNx) and silicon oxide film (SiO X).
  • a-SiTFTs amorphous silicon TFTs
  • LTPS-TFTs low-temperature polysilicon TFTs
  • a low-temperature polysilicon TFT can have higher mobility than an amorphous silicon TFT, and can be formed on a transparent and insulating substrate such as a glass substrate.
  • a typical structure of a low-temperature polysilicon TFT is, for example, a coplanar transistor as shown in FIG.
  • a polycrystalline silicon thin film serving as an active layer 101 is formed on a glass substrate 100 having transparency and insulating properties.
  • the active layer 101 is divided into a source region 102 doped with N-type or P-type impurities, a channel region 103, and a drain region 104.
  • a gate insulating layer 105 is formed so as to cover the active layer 101.
  • a gate electrode 106 is formed on the channel region 103.
  • a source electrode 108 and a drain electrode 109 are arranged on the interlayer insulating layer 107.
  • the surface is oxidized at a high temperature (about 900 ° C to 1100 ° C) in a steam atmosphere or an oxygen atmosphere, so that the gate insulating film Is formed. Formed by this thermal oxidation
  • the gate insulating film is a very high quality film with few defects in the film, and the interface between the active layer and the gate insulating film is kept clean, so the interface between the gate insulating film and the silicon substrate The characteristics are also good.
  • Patent Document 1 JP-A-10-163193
  • an active layer 101 (a source region 102 and a drain region 104 and a channel region 103) is formed. ) Putter-Jung process is required. For this reason, it was difficult to obtain good interface characteristics between the active layer 101 and the gate insulating layer 105 as in the above-described silicon TFT manufacturing process.
  • the invention according to claim 1 provides an active layer having a source region, a drain region, and a channel region on a substrate, a gate electrode layer, an active layer, and a gate.
  • the invention according to claim 2 is characterized in that, in addition to the above configuration, a second silicon oxide film is provided between the silicon nitride film and the gate electrode layer.
  • the invention according to claim 3 is characterized in that the active layer is formed of polysilicon.
  • the invention according to claim 4 is characterized in that the ratio of the thickness of the first silicon oxide film to the thickness of the silicon nitride film is 4 to 5: 1 to 2.
  • the invention according to claim 5 is directed to a first silicon oxide film, a silicon nitride film, and a second silicon oxide film each having a specific force of 4 to 5: 1 to 2: 4 to 5%. It is characterized by being.
  • the invention according to claim 6 is characterized in that the thickness of the first silicon oxide film is 40 nm or more and 50 nm or less.
  • the invention according to claim 7 is characterized in that the thickness of the silicon nitride film is lOnm or more and 20 nm or less.
  • the invention according to claim 8 is characterized in that the total thickness of the gate insulating layer is 50 nm or more and 200 nm or less.
  • the invention according to claim 9 includes a step of forming an active layer on a substrate surface, a step of forming a first silicon oxide film on the active layer, A step of forming a silicon nitride film on the silicon oxide film and a step of forming a gate electrode layer on the silicon nitride film.
  • the step of forming the gate electrode layer is a step of forming a second silicon oxide film on the silicon nitride film and then forming the gate electrode layer. It is characterized by the following.
  • the first silicon-containing gas containing silicon atoms and the oxygen-containing oxygen atoms are contained in the pressure-adjusted reaction vessel.
  • a pressure-adjusted reaction vessel containing silicon atoms is used. 2.
  • a silicon nitride film is formed by a plasma CVD method by introducing at least one of each of a silicon imparting gas, a nitrogen imparting gas containing nitrogen atoms, and a diluting gas.
  • the first silicon-imparting gas is one kind of gas selected from the group consisting of tetraethoxyorthosilicate, hexamethyldisilazane, monosilane, and disilane.
  • the oxygen-providing gas is at least one kind of gas selected from the group consisting of oxygen, nitrous oxide, ozone, carbon dioxide, and water.
  • the invention according to claim 13 is characterized in that the composition ratio between the first silicon-providing gas and the oxygen-providing gas is 1:30 to 50.
  • the invention according to claim 14 is characterized in that the pressure during the formation of the silicon oxide film is 80 to 200 Pa, and the substrate temperature is 330 to 430 ° C! /
  • the second silicon-imparting gas is one gas selected from the group consisting of tetraethoxyorthosilicate, hexamethyldisilazane, monosilane, and disilane power.
  • the application gas is selected from the group consisting of ammonia, nitric oxide, and hydrazine power, and is characterized by being one type of gas.
  • the invention according to claim 16 is characterized in that the composition ratio of the second silicon-providing gas, the nitrogen-providing gas, and the diluent gas is 1: 10-25: 10 to 30.
  • the invention according to claim 17 is characterized in that the pressure at the time of forming the silicon nitride film is 200 to 400 Pa and the substrate temperature is 330 to 430 ° C.
  • the invention according to claim 18 is characterized in that, when the first silicon oxide film, the second silicon oxide film, and the silicon nitride film are formed by the plasma CVD method, the frequency of the high-frequency voltage applied to the electrode is 27.1 MHz. It is characterized by being! /
  • the threshold voltage and the S value can be reduced, and excellent characteristics can be obtained.
  • FIG. 1 is a schematic cross-sectional view showing a polysilicon TFT as a thin film transistor formed by a manufacturing method according to an embodiment of the present invention.
  • FIG. 2 is a schematic sectional view showing a plasma CVD apparatus for forming a gate insulating layer of a polysilicon TFT according to the present invention.
  • FIG. 3 is a view showing the respective film forming process conditions of a gate insulating layer according to the present invention and a conventional gate insulating layer.
  • FIG. 4 is a view showing a relationship between a film forming temperature and a film forming rate when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
  • FIG. 5 is a view showing the relationship between the film forming temperature and the relationship between Dit and Vl when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
  • FIG. 6 is a diagram showing the relationship between the oxygen gas composition ratio to the silicon-imparting gas and the film formation rate when forming the silicon oxide films as the first and third layers of the gate insulating layer according to the present invention.
  • FIG. 7 is a view showing a relationship between an oxygen gas composition ratio and Dit and Vlb when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
  • FIG. 8 is a view showing a relationship between a process pressure, a film forming rate, and a distribution in a substrate surface when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
  • FIG. 9 is a view showing the relationship between the composition ratio of ammonia gas as a nitrogen-imparting gas to silicon-imparting gas and the film formation rate when forming a silicon nitride film as a second layer of the gate insulating layer according to the present invention.
  • FIG. 10 is a view showing the relationship between the composition ratio of an ammonia gas, Dit, and Vl when forming a silicon nitride film as the second layer of the gate insulating layer according to the present invention.
  • FIG. 11 is a view showing a relationship between a composition ratio of a nitrogen-imparting gas to a silicon-imparting gas, a film-forming rate, and a distribution in a substrate surface when a silicon nitride film as a second layer of the gate insulating layer according to the present invention is formed. .
  • FIG. 12 is a diagram illustrating a process for forming a silicon nitride film as a second layer of a gate insulating layer according to the present invention.
  • FIG. 4 is a diagram illustrating a relationship between a process pressure, a film forming speed, and a distribution in a substrate surface.
  • FIG. 13 is a diagram showing a relationship between a film forming temperature and a film forming rate when forming a silicon nitride film as a second layer of the gate insulating layer according to the present invention.
  • FIG. 14 is a view showing the relationship between the film forming temperature, Dit, and Vlb when forming a silicon nitride film as the second layer of the gate insulating layer according to the present invention.
  • FIG. 15 is a diagram showing a relationship between the thickness of each silicon oxide film as the first and second layers of the gate insulating layer according to the present invention, and Dit and Vlb.
  • FIG. 16 is a view showing the relationship between the thickness of the silicon nitride film as the second layer of the gate insulating layer according to the present invention, Dit, and Vl.
  • FIG. 17 is a diagram showing a sub-threshold swing value (S value) and a threshold voltage (Vth) in each polysilicon TFT using the gate insulating layer according to the present invention and the conventional gate insulating layer.
  • S value sub-threshold swing value
  • Vth threshold voltage
  • FIG. 1 is a schematic cross-sectional view showing a low-temperature polysilicon TFT (hereinafter, referred to as a polysilicon TFT) as a thin film transistor formed by a manufacturing method according to the present invention, and (a) shows a gate insulating layer having a first oxide film. A three-layer structure of a silicon oxide film, a silicon nitride film and a second silicon oxide film is shown, and (b) shows a two-layer structure of a first silicon oxide film and a silicon nitride film.
  • a polysilicon TFT low-temperature polysilicon TFT
  • the thin film transistor of the present embodiment includes an active layer 11 having a source region 17, a drain region 19, and a channel region 18 on a substrate 9, a gate electrode layer 16, a gate electrode layer 16, and a gate.
  • the threshold voltage and the S value can be reduced.
  • the gate insulating layer has a two-layer structure of the first silicon oxide film and the silicon nitride film, if the insulating property of the gate insulating film is satisfied, the structure shown in FIG. It is not necessary to form the second silicon oxide film shown in a).
  • FIG. 2 is a schematic sectional view showing a plasma CVD apparatus for forming a gate insulating layer of this polysilicon TFT.
  • a gas introduction system 3 to which a plurality of gas sources (not shown) such as gas cylinders is connected is provided above the reaction vessel 2 of the plasma CVD apparatus 1, and a vacuum is provided below the reaction vessel 2
  • An exhaust system 4 to which a pump (not shown) and the like are connected is provided.
  • two plate-like upper electrodes 5 and lower electrodes 6 are installed so as to face each other, and the upper electrode 5 located on the upper side is provided via a modulator 7 for pulse-modulating high-frequency power.
  • An external high-frequency power supply 8 is connected to the lower electrode 6, and a substrate 9 on which a film is to be formed is placed on the lower electrode 6 located on the lower side.
  • the lower electrode 6 also serves as a substrate holder.
  • the high-frequency power supply 8 is configured to apply a high-frequency voltage of 27.12 MHz to the upper electrode 5. Note that a power of 13.56 MHz is also possible as a high frequency voltage. It is preferable because the decomposition efficiency is increased.
  • the upper electrode 5 has a hollow portion 5a so that the shower plate 10 is provided on the front side (the lower electrode 6 side), and the front end side of the gas introduction system 3 is communicated with the hollow portion 5a.
  • the source gas is connected to the substrate 9 on the lower electrode 6 from a number of gas outlets 10a formed in the shower plate 10 so as to uniformly eject the source gas.
  • the lower electrode 6 has a built-in heater (not shown) for heating the substrate 9 to be mounted to a predetermined temperature, and is configured to be maintained at the ground potential during the film formation.
  • a xenon chloride (XeCl) excimer laser (wavelength 308 nm) or krypton fluoride
  • XeCl xenon chloride
  • KrF krypton fluoride
  • the amorphous silicon film can be crystallized to obtain a crystalline silicon film, polysilicon (Poly-Si). This is patterned using photolithography and etching to form an active layer 11.
  • the substrate 9 on which the active layer 11 is formed is placed on the lower electrode 6 in the reaction vessel 2 of the plasma CVD apparatus 1 described above, and a heater (not shown) is energized to perform resistance heating. Heat 9 to the specified temperature.
  • the inside of the reaction vessel 2 is evacuated through the exhaust system 4 and adjusted to a predetermined pressure.
  • a mixed gas (a source gas) comprising a silane-based gas such as tetraethoxyorthosilicate (TEOS) as a first silicon-providing gas and an oxygen-supplying gas such as oxygen is introduced into the reaction vessel 2 through the gas introduction system 3.
  • TEOS tetraethoxyorthosilicate
  • oxygen-supplying gas such as oxygen
  • the mixed gas is uniformly ejected from the many gas ejection ports 10 a of the shower plate 10 toward the substrate 9 on the lower electrode 6.
  • a high frequency voltage of 27.12 MHz is applied from the high frequency power supply 8 to the upper electrode 5 to generate a discharge in the space between the upper electrode 5 and the lower electrode 6 to convert the above mixed gas into plasma.
  • a first silicon oxide film 12 as a first insulating layer is formed on the active layer 11 to a thickness of 40 to 50 nm.
  • the first silicon oxide film 12 in addition to the above-mentioned silane-based gas such as tetraethoxyorthosilicate (TEOS) as the first silicon imparting gas, for example, monosilane and disilane are also used.
  • TEOS tetraethoxyorthosilicate
  • monosilane and disilane are also used.
  • any one of the gases selected from the group consisting of, for example, nitrous oxide, ozone, carbon dioxide, and water can be used as the applied gas.
  • a silica such as monosilane (SiH) is used as the second silicon imparting gas.
  • a mixed gas consisting of an oxygen-based gas, a nitrogen-imparting gas such as ammonia, and a diluent gas such as nitrogen is introduced, and the mixed gas is turned into plasma by electric discharge to form a second gas on the first silicon oxide film 12.
  • a silicon nitride film 13 as an insulating layer is formed with a thickness of 10 to 20 nm.
  • the silicon nitride film 13 is formed, in addition to monosilane as the second silicon-providing gas, any one selected from the group consisting of, for example, tetraethoxyorthosilicate, hexamethyldisilazane, and disilane is used.
  • the nitrogen-providing gas may be a gas of one kind, for example, V selected from the group consisting of nitric oxide and hydrazine power, and a shear force of one kind.
  • a mixed gas of the same gas system as that of the first silicon oxide film 12 is introduced, and the mixed gas is turned into plasma by electric discharge to form a third insulating layer on the silicon nitride film 13.
  • a second silicon oxide film 14 is formed with a thickness of 50 nm.
  • the gate insulating layer 15 is formed by patterning using photolithography and etching. Details of the gate insulating layer 15 which is a feature of the present invention will be described later.
  • the second silicon oxide film 14 need not be formed as long as the insulating properties of the gate insulating film are satisfied.
  • a mixed gas obtained by selecting at least one kind from each of a silane-based gas and an oxygen-imparting gas and mixing them in a predetermined amount is used.
  • a mixed gas obtained by selecting at least one of each of a silane-based gas, a nitrogen-imparting gas, and a diluent gas and mixing them in a predetermined amount is used.
  • an aluminum film is formed to a thickness of 250 nm by a sputtering method, and then a molybdenum film 50 nm is formed by a sputtering method. .
  • This aluminum film to scandium 0.2 weight 0/0 contained. This is to prevent the formation of needle-like projections called hillock whiskers in a later step. And this is putt réelle using photolithography and etching Thus, a gate electrode 16 is formed.
  • doping with impurities (impurities for imparting one conductivity type) for forming the source Z drain region is performed.
  • impurities impurities for imparting one conductivity type
  • P (phosphorus) doping is performed by a plasma doping method in order to obtain an N-channel thin film transistor.
  • annealing By performing annealing after the end of the doping, activation of the doped impurities and annealing of damage at the time of doping are performed.
  • a source region 17, a channel region 18, and a drain region 19 are formed in a self-aligned manner.
  • an oxide silicon film 20 is formed to a thickness of 250 nm on the gate electrode 16 and the gate insulating layer 15 by a CVD method (plasma CVD method, thermal CVD method, ECR plasma CVD method, etc.). . Then, a contact hole is formed using photolithography and etching to form an interlayer insulating layer 21. Then, a molybdenum film is formed to a thickness of 50 nm by a sputtering method, and then an aluminum film is formed to a thickness of 300 nm. By forming a film and forming the source electrode 22 and the drain electrode 23, the polysilicon TFT according to the present invention shown in FIG. 1 is obtained.
  • a CVD method plasma CVD method, thermal CVD method, ECR plasma CVD method, etc.
  • the gate insulating layer 15 has a thickness of the first layer (first silicon nitride film 12): the second layer (silicon nitride film 13): the third layer (second silicon nitride film 13).
  • Film 14) 50 nm: 10 nm: 50 nm, and the respective film forming process conditions are as shown in FIG.
  • FIG. 3 also shows typical film forming process conditions for an oxidized silicon film using TEOS as a source gas, which is used for a gate insulating layer of a conventional polysilicon TFT.
  • the film formation rate and the film thickness distribution in the substrate surface are the results when a film is formed on a glass substrate of 730 mm ⁇ 920 mm size.
  • Vl (Unit: V) is a flat band voltage as an indication of the amount of defects in the gate insulating layer
  • Dit (Unit: C m _2 'eV _1) are field surfaces of the gate insulating layer and the thin silicon film Is the interface state density as an index indicating the defect density of the sample.
  • the film formation rate of the silicon oxide film using TEOS as a source gas is about 80 nm Zmin, and the film thickness distribution in the substrate surface (10 mm end) : About ⁇ 7.5%.
  • V Dit 8 ⁇ 10 cm′eV.
  • FIG. 4 is a measurement showing the relationship between the film forming temperature and the film forming speed when forming the silicon oxide films as the first and third layers (the first and second silicon oxide films 12 and 14).
  • FIG. 5 shows the measurement results showing the relationship between the deposition temperature and Dit and Vl when forming the silicon oxide films (first and second silicon oxide films 12 and 14).
  • a is Dit and b is Vl.
  • Dit decreases as the film formation temperature increases, and the defect density at the interface decreases. However, Dit becomes approximately constant at about 430 ° C. or higher.
  • Vl increases as the deposition temperature increases, indicating a decrease in the amount of defects in the layer, but becomes constant above 430 ° C.
  • the temperature is preferably about 450 ° C. or less due to the heat resistant temperature of the substrate and the material of the device.
  • the silicon oxide film first and second silicon oxide films 12 and 14
  • the Dit and increase the Vl It is preferable to form the film in the range of about 430 ° C.
  • FIG. 6 shows the relationship between the oxygen gas composition ratio with respect to the silicon-supplied gas and the film formation rate when forming the silicon oxide films (first and second silicon oxide films 12 and 14).
  • FIG. 7 is a measurement result showing the relationship between the oxygen gas composition ratio and D it and Vl in the formation of the silicon oxide films (first and second silicon oxide films 12 and 14). is there.
  • a is Dit and b is Vl.
  • a silicon-imparting gas is required. It is preferable to form a film with an oxygen gas composition ratio in the range of 30 to 50! /.
  • FIG. 8 is a measurement result showing a relationship between a process pressure, a film formation rate, and a distribution in a substrate surface when forming silicon oxide films (first and second silicon oxide films 12, 14). It is.
  • a is the film formation rate
  • b is the in-plane distribution of the substrate.
  • increasing the process pressure decreases the deposition rate.
  • the distribution in the substrate surface takes a minimum value near a process pressure of 125 Pa.
  • the silicon oxide film should be formed at a process pressure of about 80 to 200 Pa. preferable.
  • FIG. 9 shows measurement results showing the relationship between the composition ratio of ammonia gas as a nitrogen-imparting gas to the silicon-imparting gas and the film formation rate during the formation of a silicon nitride film (silicon nitride film 13 as a second insulating layer).
  • FIG. 10 shows measurement results showing the relationship between the ammonia gas composition ratio and Dit, Vl when forming a silicon nitride film (silicon nitride film 13 as a second insulating layer). In FIG. 10, a is Dit and b is Vl.
  • the ammonia gas composition ratio is about 10 to 25. It is preferable to form a film in a range of degrees.
  • FIG. 11 shows the composition ratio of the nitrogen gas (diluent gas) to the silicon-imparting gas, the deposition rate, and the distribution in the substrate surface when the silicon nitride film (the silicon nitride film 13 as the second insulating layer) was formed. Seki It is a measurement result showing the relationship. Note that in FIG. 11, a is the film formation rate, and b is the distribution in the substrate plane.
  • FIG. 12 is a measurement result showing a relationship between a process pressure, a film formation rate, and a distribution in a substrate surface when a silicon nitride film (a silicon nitride film 13 as a second insulating layer) is formed.
  • a is the film formation rate
  • b is the in-plane distribution of the substrate.
  • the process pressure when the process pressure is increased, the film deposition rate is reduced, and the distribution in the substrate surface takes a minimum value at a process pressure of around 250 Pa. Therefore, in order to reduce the distribution of the silicon nitride film (the silicon nitride film 13 as the second insulating layer) in the substrate surface, it is preferable to form the film at a process pressure of about 200 to 400 Pa! ,.
  • FIG. 13 shows a measurement result showing a relationship between a film forming temperature and a film forming rate when forming a silicon nitride film (the silicon nitride film 13 as a second insulating layer).
  • 9 is a measurement result showing a relationship between a film forming temperature, Dit, and Vlb when forming a film (a silicon nitride film 13 as a second insulating layer).
  • a is Dit and b is Vlb.
  • the heat resistance temperature of the substrate is preferably about 450 ° C. or less.
  • FIG. 15 shows the relationship between the thicknesses of the first and second i (first and second silicon oxide films 12 and 14) of the gate insulating layer 15 and Dit and Vl in the present invention. It is a measurement result.
  • FIG. 16 shows the relationship between the thickness of the second layer (the silicon nitride film 13) of the gate insulating layer 15 and Dit and Vl in the present invention. It is a measurement result shown.
  • a is Dit and b is Vl.
  • the gate insulating layer having a three-layer structure according to the present invention (first silicon oxide film 12, silicon nitride film 13, and second silicon oxide film 14) 15
  • the sub-threshold swing value (S value) is smaller and the threshold voltage (Vth) is smaller and higher than that of a conventional gate insulating layer (silicon oxide film) having a single-layer structure.
  • a high performance polysilicon TFT can be manufactured.

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Abstract

A thin-film transistor having a gate insulation layer excellent in characteristics and high in reliability with good productivity ensured, and a production method therefore. The thin-film transistor comprises, formed on a substrate (9), an active layer (11) having a source region (17), a channel region (18) and a drain region (19), a gate electrode layer (16), and a gate insulation layer (15) formed between the active layer (11) and the gate electrode layer (16), wherein the gate insulation layer (15) is formed of a first silicon oxide film (12) formed on the active layer (11) side, a second silicon oxide film (14) formed on the gate electrode layer (16) side, and a silicon nitride film (13) formed between the first silicon oxide film (12) and the second silicon oxide film (14).

Description

明 細 書  Specification
薄膜トランジスタ及びその製造方法  Thin film transistor and method of manufacturing the same
技術分野  Technical field
[0001] 本発明は、酸ィ匕珪素膜をゲート絶縁層とする薄膜トランジスタ及びその製造方法に 関する。  The present invention relates to a thin film transistor having a silicon oxide film as a gate insulating layer and a method for manufacturing the same.
背景技術  Background art
[0002] 従来より液晶ディスプレイ (LCD)や有機エレクト口ルミネッセンス (OLED)等のデ バイスには、アモルファスシリコン (a— Si)ゃ窒化珪素膜 (SiNx)、酸ィ匕珪素膜 (SiO X)といった薄膜から形成される、薄膜トランジスタであるアモルファスシリコン TFT(a — SiTFT)、低温ポリシリコン TFT(LTPS— TFT)が利用されている。とりわけ低温ポ リシリコン TFTは、アモルファスシリコン TFTよりも高移動度化が可能であり、かつ透 明で絶縁性のある例えばガラス基板のような基板上に作製することができる。  [0002] Conventionally, devices such as a liquid crystal display (LCD) and an organic electroluminescent device (OLED) include amorphous silicon (a-Si) 珪 素 silicon nitride film (SiNx) and silicon oxide film (SiO X). Amorphous silicon TFTs (a-SiTFTs) and low-temperature polysilicon TFTs (LTPS-TFTs), which are thin film transistors formed from thin films, are used. In particular, a low-temperature polysilicon TFT can have higher mobility than an amorphous silicon TFT, and can be formed on a transparent and insulating substrate such as a glass substrate.
[0003] 低温ポリシリコン TFTの代表的な構造としては、例えば図 18に示すようなコプレー ナ型トランジスタが挙げられる。  [0003] A typical structure of a low-temperature polysilicon TFT is, for example, a coplanar transistor as shown in FIG.
コプレーナ型トランジスタの構成は、図 18に示すように、透明性及び絶縁性を有す るガラス基板 100上に、活性層 101となる多結晶珪素薄膜が形成される。この活性層 101は、 N型又は P型不純物がドーピングされてなるソース領域 102、チャネル領域 1 03、ドレイン領域 104に分けられており、この活性層 101を覆うようにゲート絶縁層 10 5が形成され、ゲート電極 106がチャネル領域 103上に形成される。更に、層間絶縁 層 107上にソース電極 108とドレイン電極 109が配置される。  In the configuration of the coplanar transistor, as shown in FIG. 18, a polycrystalline silicon thin film serving as an active layer 101 is formed on a glass substrate 100 having transparency and insulating properties. The active layer 101 is divided into a source region 102 doped with N-type or P-type impurities, a channel region 103, and a drain region 104. A gate insulating layer 105 is formed so as to cover the active layer 101. Thus, a gate electrode 106 is formed on the channel region 103. Further, a source electrode 108 and a drain electrode 109 are arranged on the interlayer insulating layer 107.
ところで、低温ポリシリコン TFTの製造工程においては、その利用される半導体素 子が大面積を必要とするため安価なガラス基板が用いられており、その耐熱性が十 分でな!、ため、比較的低温 (およそ 600°C程度以下）のプロセス温度で作製しなくて はならない。  By the way, in the manufacturing process of low-temperature polysilicon TFTs, inexpensive glass substrates are used because the semiconductor elements used need a large area, and their heat resistance is not sufficient! It must be manufactured at a very low process temperature (about 600 ° C or less).
一方、シリコン単結晶基板を用いたシリコン TFTの製造工程においては、その表面 を水蒸気雰囲気中もしくは酸素雰囲気中で表面を高温 (900°C〜1100°C程度)酸 化することで、ゲート絶縁膜である酸化珪素膜を形成する。この熱酸化により形成さ れたゲート絶縁膜は、膜中の欠陥が少ない非常に高品質な膜であり、また活性層と ゲート絶縁膜の界面もクリーンな状態に保たれるため、ゲート絶縁膜とシリコン基板と の界面特性も良質である。 On the other hand, in the process of manufacturing a silicon TFT using a silicon single crystal substrate, the surface is oxidized at a high temperature (about 900 ° C to 1100 ° C) in a steam atmosphere or an oxygen atmosphere, so that the gate insulating film Is formed. Formed by this thermal oxidation The gate insulating film is a very high quality film with few defects in the film, and the interface between the active layer and the gate insulating film is kept clean, so the interface between the gate insulating film and the silicon substrate The characteristics are also good.
[0004] これに対して、上記した従来の低温ポリシリコン TFTの製造方法では、界面特性の 良好なゲート絶縁膜を得ることが難しカゝつたが、近年、低温ポリシリコン TFTでも界面 特性の良好なゲート絶縁膜を得ることができる製造方法が提案されている (例えば、 特許文献 1参照。）。  [0004] On the other hand, in the above-mentioned conventional method for manufacturing a low-temperature polysilicon TFT, it was difficult to obtain a gate insulating film having good interface characteristics. A manufacturing method capable of obtaining a suitable gate insulating film has been proposed (for example, see Patent Document 1).
上記特許文献 1によるゲート絶縁膜の製造方法では、多結晶珪素薄膜上に酸化膜 を形成した後に触媒金属を堆積し、 600°C以下の酸化雰囲気中で熱処理するように している。  In the method of manufacturing a gate insulating film according to Patent Document 1, after forming an oxide film on a polycrystalline silicon thin film, a catalytic metal is deposited and heat-treated in an oxidizing atmosphere at 600 ° C. or lower.
特許文献 1 :特開平 10— 163193号公報  Patent Document 1: JP-A-10-163193
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0005] ところで、上記特許文献 1のような従来の低温ポリシリコン TFTの製造方法では、触 媒金属を塗布する工程ならびに熱処理により絶縁層を形成する工程、さらに実用性 を考慮し、最終的に触媒金属を活性層から除去する工程があり、生産性が良くなか つた o [0005] By the way, in the conventional method for manufacturing a low-temperature polysilicon TFT as described in Patent Document 1 described above, a step of applying a catalyst metal and a step of forming an insulating layer by heat treatment, and finally considering practicality, There is a process to remove the catalytic metal from the active layer, which has reduced productivity o
また、図 18に示したような従来の低温ポリシリコン TFT (コプレーナ型トランジスタ） の製造工程では、ゲート絶縁層 105の形成前に活性層 101 (ソース領域 102及びド レイン領域 104と、チャネル領域 103)のパターユング工程が必要となる。このため、 この活性層 101とゲート絶縁層 105の界面特性は、上記したシリコン TFTの製造ェ 程のような良好な特性を得ることが難し力つた。  Also, in the conventional process of manufacturing a low-temperature polysilicon TFT (coplanar transistor) as shown in FIG. 18, before forming a gate insulating layer 105, an active layer 101 (a source region 102 and a drain region 104 and a channel region 103) is formed. ) Putter-Jung process is required. For this reason, it was difficult to obtain good interface characteristics between the active layer 101 and the gate insulating layer 105 as in the above-described silicon TFT manufacturing process.
[0006] その結果、キャリアのトラップ及び散乱が生じ、低温ポリシリコン TFTの特性のひと つであるスレツショルド電圧（閾値電圧）の変位 (シフト）が大きくなつたり、サブスレツ ショルドスイング（S値）が大きくなつてしまうと 、う問題があった。 As a result, carriers are trapped and scattered, and the displacement (shift) of the threshold voltage (threshold voltage), which is one of the characteristics of the low-temperature polysilicon TFT, increases, and the sub-threshold swing (S value) increases. When it did, there was a problem.
そこで本発明は、良好な生産性を確保しつつ、優れた特性と信頼性の高いゲート 絶縁層を有する薄膜トランジスタ及びその製造方法を提供することを目的とする。 課題を解決するための手段 [0007] 上記目的を達成するために本発明の薄膜トランジスタのうち請求項 1記載の発明は 、基板上にソース領域、ドレイン領域、チャンネル領域を有する活性層と、ゲート電極 層と、活性層とゲート電極層との間に形成されるゲート絶縁層とを有する薄膜トランジ スタであって、ゲート絶縁層が、活性層に接して形成される第 1の酸ィ匕珪素膜と、第 1 の酸ィ匕珪素膜とゲート電極層との間に第 1の酸ィ匕珪素膜に接して形成される窒化珪 素膜とを含むことを特徴として 、る。 Accordingly, it is an object of the present invention to provide a thin film transistor having excellent characteristics and a highly reliable gate insulating layer while securing good productivity, and a method for manufacturing the same. Means for solving the problem [0007] To achieve the above object, among the thin film transistors of the present invention, the invention according to claim 1 provides an active layer having a source region, a drain region, and a channel region on a substrate, a gate electrode layer, an active layer, and a gate. A thin film transistor having a gate insulating layer formed between the first silicon oxide film and a first silicon oxide film formed in contact with an active layer. A silicon nitride film formed in contact with the first silicon oxide film between the silicon oxide film and the gate electrode layer.
[0008] さらに、請求項 2記載の発明は、上記構成に加え、窒化珪素膜とゲート電極層との 間に第 2の酸ィ匕珪素膜を有することを特徴とするものである。 [0008] Further, the invention according to claim 2 is characterized in that, in addition to the above configuration, a second silicon oxide film is provided between the silicon nitride film and the gate electrode layer.
請求項 3記載の発明は、活性層がポリシリコンで形成されることを特徴としている。 請求項 4記載の発明は、第 1の酸化珪素膜、窒化珪素膜の膜厚さの比が、 4〜5 : 1 〜2であることを特徴として 、る。  The invention according to claim 3 is characterized in that the active layer is formed of polysilicon. The invention according to claim 4 is characterized in that the ratio of the thickness of the first silicon oxide film to the thickness of the silicon nitride film is 4 to 5: 1 to 2.
請求項 5記載の発明は、第 1の酸化珪素膜、窒化珪素膜、第 2の酸ィヒ珪素膜のそ れぞれの膜厚さの比力 4〜5： 1〜2 :4〜5であることを特徴としている。  The invention according to claim 5 is directed to a first silicon oxide film, a silicon nitride film, and a second silicon oxide film each having a specific force of 4 to 5: 1 to 2: 4 to 5%. It is characterized by being.
請求項 6記載の発明は、第 1の酸ィ匕珪素膜の膜厚が、 40nm以上 50nm以下であ る、ことを特徴としている。  The invention according to claim 6 is characterized in that the thickness of the first silicon oxide film is 40 nm or more and 50 nm or less.
請求項 7記載の発明は、窒化珪素膜の膜厚が lOnm以上 20nm以下であることを 特徴としている。  The invention according to claim 7 is characterized in that the thickness of the silicon nitride film is lOnm or more and 20 nm or less.
請求項 8記載の発明は、ゲート絶縁層全体の層厚が、 50nm以上 200nm以下であ ることを特徴としている。  The invention according to claim 8 is characterized in that the total thickness of the gate insulating layer is 50 nm or more and 200 nm or less.
[0009] 本発明の薄膜トランジスタの製造方法のうち請求項 9記載の発明は、基板表面に活 性層を形成する工程と、活性層上に第 1の酸化珪素膜を形成する工程と、第 1の酸 化珪素膜上に窒化珪素膜を形成する工程と、窒化珪素膜上にゲート電極層を形成 する工程とを含むことを特徴として 、る。  [0009] In the method for manufacturing a thin film transistor of the present invention, the invention according to claim 9 includes a step of forming an active layer on a substrate surface, a step of forming a first silicon oxide film on the active layer, A step of forming a silicon nitride film on the silicon oxide film and a step of forming a gate electrode layer on the silicon nitride film.
さらに請求項 10記載の発明は、上記構成に加え、ゲート電極層を形成する工程が 、窒化珪素膜上に第 2の酸ィ匕珪素膜を形成後、ゲート電極層を形成する工程である ことを特徴とするものである。  Further, in the invention according to claim 10, in addition to the above configuration, the step of forming the gate electrode layer is a step of forming a second silicon oxide film on the silicon nitride film and then forming the gate electrode layer. It is characterized by the following.
また請求項 11記載の発明は、第 1の酸ィ匕珪素膜を形成する工程においては、圧力 調整された反応容器内に珪素原子を含む第 1の珪素付与ガス、酸素原子を含む酸 素付与ガスのそれぞれの少なくとも一種類ずつを導入して、プラズマ CVD法により酸 化珪素膜を形成し、窒化珪素膜を形成する工程においては、圧力調整された反応 容器内に珪素原子を含む第 2の珪素付与ガス、窒素原子を含む窒素付与ガス、希 釈ガスのそれぞれの少なくとも一種類ずつを導入して、プラズマ CVD法により窒化珪 素膜を形成することを特徴として 、る。 Further, in the invention according to claim 11, in the step of forming the first silicon oxide film, the first silicon-containing gas containing silicon atoms and the oxygen-containing oxygen atoms are contained in the pressure-adjusted reaction vessel. In the step of introducing a silicon oxide film by plasma CVD and introducing a silicon nitride film by introducing at least one kind of each of the oxygen-imparting gases, a pressure-adjusted reaction vessel containing silicon atoms is used. 2. A silicon nitride film is formed by a plasma CVD method by introducing at least one of each of a silicon imparting gas, a nitrogen imparting gas containing nitrogen atoms, and a diluting gas.
[0010] 請求項 12記載の発明は、第 1の珪素付与ガスは、テトラエトキシオルソシリケートと 、へキサメチルジシラザンと、モノシランと、ジシラン力 なる群より選択されるいずれ カゝ 1種類のガスであり、酸素付与ガスは、酸素、亜酸化窒素、オゾン、二酸化炭素、 水からなる群より選択される 、ずれか 1種類のガスであることを特徴として 、る。 [0010] In the invention according to claim 12, the first silicon-imparting gas is one kind of gas selected from the group consisting of tetraethoxyorthosilicate, hexamethyldisilazane, monosilane, and disilane. Wherein the oxygen-providing gas is at least one kind of gas selected from the group consisting of oxygen, nitrous oxide, ozone, carbon dioxide, and water.
請求項 13記載の発明は、第 1の珪素付与ガスと前記酸素付与ガスの組成比が、 1 : 30〜50であることを特徴として!/、る。  The invention according to claim 13 is characterized in that the composition ratio between the first silicon-providing gas and the oxygen-providing gas is 1:30 to 50.
請求項 14記載の発明は、酸ィ匕珪素膜の成膜時の圧力は 80〜200Paであり、基板 温度は 330〜430°Cであることを特徴として！/、る。  The invention according to claim 14 is characterized in that the pressure during the formation of the silicon oxide film is 80 to 200 Pa, and the substrate temperature is 330 to 430 ° C! /
請求項 15記載の発明は、第 2の珪素付与ガスは、テトラエトキシオルソシリケートと 、へキサメチルジシラザンと、モノシランと、ジシラン力 なる群より選択されるいずれ 力 1種類のガスであり、窒素付与ガスは、アンモニア、一酸化窒素、ヒドラジン力 なる 群より選択される 、ずれか 1種類のガスであることを特徴として 、る。  In the invention according to claim 15, the second silicon-imparting gas is one gas selected from the group consisting of tetraethoxyorthosilicate, hexamethyldisilazane, monosilane, and disilane power. The application gas is selected from the group consisting of ammonia, nitric oxide, and hydrazine power, and is characterized by being one type of gas.
請求項 16記載の発明は、第 2の珪素付与ガス、窒素付与ガス、希釈ガスの組成比 力 1： 10-25： 10〜30であることを特徴として!/、る。  The invention according to claim 16 is characterized in that the composition ratio of the second silicon-providing gas, the nitrogen-providing gas, and the diluent gas is 1: 10-25: 10 to 30.
請求項 17記載の発明は、窒化珪素膜の成膜時の圧力は 200〜400Paであり、基 板温度は 330〜430°Cであることを特徴としている。  The invention according to claim 17 is characterized in that the pressure at the time of forming the silicon nitride film is 200 to 400 Pa and the substrate temperature is 330 to 430 ° C.
請求項 18記載の発明は、プラズマ CVD法で第 1の酸ィ匕珪素膜、第 2の酸化珪素 膜、窒化珪素膜をそれぞれ形成する際の、電極に印加する高周波電圧の周波数が 27.1MHzであることを特徴として!/、る。  The invention according to claim 18 is characterized in that, when the first silicon oxide film, the second silicon oxide film, and the silicon nitride film are formed by the plasma CVD method, the frequency of the high-frequency voltage applied to the electrode is 27.1 MHz. It is characterized by being! /
発明の効果  The invention's effect
[0011] 本発明の薄膜トランジスタによれば、閾値電圧及び S値を小さくすることができ、優 れた特性を有することができる。  According to the thin film transistor of the present invention, the threshold voltage and the S value can be reduced, and excellent characteristics can be obtained.
さらに、本発明の薄膜トランジスタの製造方法によれば、良好な生産性を確保しつ つ、ゲート絶縁層の膜中の欠陥ならびに珪素薄膜との界面の欠陥密度を大幅に低 減して界面特性の良好なゲート絶縁層を有する薄膜トランジスタを得ることができる。 図面の簡単な説明 Further, according to the method for manufacturing a thin film transistor of the present invention, good productivity is ensured. In addition, defects in the film of the gate insulating layer and the defect density at the interface with the silicon thin film are significantly reduced, so that a thin film transistor having a gate insulating layer with favorable interface characteristics can be obtained. Brief Description of Drawings
[図 1]本発明の実施形態に係る製造方法によって形成された薄膜トランジスタとして のポリシリコン TFTを示す概略断面図。 FIG. 1 is a schematic cross-sectional view showing a polysilicon TFT as a thin film transistor formed by a manufacturing method according to an embodiment of the present invention.
[図 2]本発明に係るポリシリコン TFTのゲート絶縁層を成膜するためのプラズマ CVD 装置を示す概略断面図。  FIG. 2 is a schematic sectional view showing a plasma CVD apparatus for forming a gate insulating layer of a polysilicon TFT according to the present invention.
[図 3]本発明に係るゲート絶縁層と従来のゲート絶縁層のそれぞれの成膜プロセス条 件を示す図。  FIG. 3 is a view showing the respective film forming process conditions of a gate insulating layer according to the present invention and a conventional gate insulating layer.
[図 4]本発明に係るゲート絶縁層の第 1、第 3層としての酸ィ匕珪素膜の形成時におけ る、成膜温度と成膜速度の関係を示す図。  FIG. 4 is a view showing a relationship between a film forming temperature and a film forming rate when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
[図 5]本発明に係るゲート絶縁層の第 1、第 3層としての酸ィ匕珪素膜の形成時におけ る、成膜温度と Dit、 Vlの関係の関係を示す図。  FIG. 5 is a view showing the relationship between the film forming temperature and the relationship between Dit and Vl when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
[図 6]本発明に係るゲート絶縁層の第 1、第 3層としての酸ィ匕珪素膜の形成時におけ る、珪素付与ガスに対する酸素ガス組成比と成膜速度の関係を示す図。  FIG. 6 is a diagram showing the relationship between the oxygen gas composition ratio to the silicon-imparting gas and the film formation rate when forming the silicon oxide films as the first and third layers of the gate insulating layer according to the present invention.
[図 7]本発明に係るゲート絶縁層の第 1、第 3層としての酸ィ匕珪素膜の形成時におけ る、酸素ガス組成比と Dit、 Vlbの関係を示す図。 FIG. 7 is a view showing a relationship between an oxygen gas composition ratio and Dit and Vlb when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
[図 8]本発明に係るゲート絶縁層の第 1、第 3層としての酸ィ匕珪素膜を形成時におけ る、プロセス圧力と成膜速度及び基板面内分布の関係を示す図。  FIG. 8 is a view showing a relationship between a process pressure, a film forming rate, and a distribution in a substrate surface when forming an oxidized silicon film as the first and third layers of the gate insulating layer according to the present invention.
[図 9]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜を形成時における、珪 素付与ガスに対する窒素付与ガスとしてのアンモニアガス組成比と成膜速度の関係 を示す図。 FIG. 9 is a view showing the relationship between the composition ratio of ammonia gas as a nitrogen-imparting gas to silicon-imparting gas and the film formation rate when forming a silicon nitride film as a second layer of the gate insulating layer according to the present invention.
[図 10]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜を形成時における、ァ ンモ-ァガス組成比と Dit、 Vlの関係を示す図。  FIG. 10 is a view showing the relationship between the composition ratio of an ammonia gas, Dit, and Vl when forming a silicon nitride film as the second layer of the gate insulating layer according to the present invention.
[図 11]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜を形成時における、 珪素付与ガスに対する窒素付与ガスの組成比と、成膜速度と基板面内分布の関係 を示す図。  FIG. 11 is a view showing a relationship between a composition ratio of a nitrogen-imparting gas to a silicon-imparting gas, a film-forming rate, and a distribution in a substrate surface when a silicon nitride film as a second layer of the gate insulating layer according to the present invention is formed. .
[図 12]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜を形成時における、プ ロセス圧力と、成膜速度と基板面内分布の関係を示す図。 FIG. 12 is a diagram illustrating a process for forming a silicon nitride film as a second layer of a gate insulating layer according to the present invention. FIG. 4 is a diagram illustrating a relationship between a process pressure, a film forming speed, and a distribution in a substrate surface.
圆 13]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜を形成時における、 成膜温度と成膜速度の関係を示す図。 [13] FIG. 13 is a diagram showing a relationship between a film forming temperature and a film forming rate when forming a silicon nitride film as a second layer of the gate insulating layer according to the present invention.
圆 14]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜を形成時における、 成膜温度と Dit、 Vlbの関係を示す図。 [14] FIG. 14 is a view showing the relationship between the film forming temperature, Dit, and Vlb when forming a silicon nitride film as the second layer of the gate insulating layer according to the present invention.
圆 15]本発明に係るゲート絶縁層の第 1、第 2層としての各酸ィ匕珪素膜における膜厚 と、 Dit、 Vlbの関係を示す図。 [15] FIG. 15 is a diagram showing a relationship between the thickness of each silicon oxide film as the first and second layers of the gate insulating layer according to the present invention, and Dit and Vlb.
圆 16]本発明に係るゲート絶縁層の第 2層としての窒化珪素膜における膜厚と、 Dit、 Vlの関係を示す図。 [16] FIG. 16 is a view showing the relationship between the thickness of the silicon nitride film as the second layer of the gate insulating layer according to the present invention, Dit, and Vl.
[図 17]本発明に係るゲート絶縁層と従来のゲート絶縁層を使用した各ポリシリコン TF Tにおける、サブスレツショルドスイング値（S値）とスレツショルド電圧（Vth)を示す図。 圆 18]従来例に係る製造方法によって形成された薄膜トランジスタとしてのポリシリコ ン TFTを示す概略断面図。  FIG. 17 is a diagram showing a sub-threshold swing value (S value) and a threshold voltage (Vth) in each polysilicon TFT using the gate insulating layer according to the present invention and the conventional gate insulating layer. [18] Schematic sectional view showing a polysilicon TFT as a thin film transistor formed by a manufacturing method according to a conventional example.
符号の説明 Explanation of symbols
1 CVD装置  1 CVD equipment
2 反応容器  2 Reaction vessel
5 上部電極  5 Upper electrode
6 下部電極  6 Lower electrode
9 基板  9 PCB
12 第 1の酸ィ匕珪素膜  12 First silicon dioxide film
13 窒化珪素膜  13 Silicon nitride film
14 第 2の酸ィ匕珪素膜  14 Second silicon dioxide film
15 ゲート絶縁層  15 Gate insulation layer
16 ゲート電極  16 Gate electrode
21 層間絶縁層  21 Interlayer insulation layer
22 ソース電極  22 Source electrode
23 ドレイン電極  23 Drain electrode
発明を実施するための最良の形態 [0014] 以下、本発明を図示の実施形態に基づいて説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described based on the illustrated embodiments.
図 1は、本発明に係る製造方法によって形成された薄膜トランジスタとしての低温ポ リシリコン TFT (以下、ポリシリコン TFTという）を示す概略断面図であり、（a)はゲート 絶縁層が第 1の酸ィ匕珪素膜、窒化珪素膜及び第 2の酸ィ匕珪素膜の三層積層構造の もの、 (b)は第 1の酸化珪素膜及び窒化珪素膜の二層積層構造のものを示す。 図 1 (a)を参照して、本実施形態の薄膜トランジスタは、基板 9上にソース領域 17、 ドレイン領域 19、チャンネル領域 18を有する活性層 11と、ゲート電極層 16と、活性 層 11とゲート電極層 16との間に形成されるゲート絶縁層 15とを備え、ゲート絶縁層 1 5が、活性層 11側に形成される第 1の酸ィ匕珪素膜 12と、ゲート電極層 16側に形成さ れる第 2の酸ィ匕珪素膜 14と、第 1の酸ィ匕珪素膜 12と第 2酸ィ匕珪素膜 14の間に形成 される窒化珪素膜 13とを有している。  FIG. 1 is a schematic cross-sectional view showing a low-temperature polysilicon TFT (hereinafter, referred to as a polysilicon TFT) as a thin film transistor formed by a manufacturing method according to the present invention, and (a) shows a gate insulating layer having a first oxide film. A three-layer structure of a silicon oxide film, a silicon nitride film and a second silicon oxide film is shown, and (b) shows a two-layer structure of a first silicon oxide film and a silicon nitride film. Referring to FIG. 1A, the thin film transistor of the present embodiment includes an active layer 11 having a source region 17, a drain region 19, and a channel region 18 on a substrate 9, a gate electrode layer 16, a gate electrode layer 16, and a gate. A gate insulating layer 15 formed between the active layer 11 and the first silicon oxide film 12 formed on the active layer 11 side; and a gate insulating layer 15 formed on the gate electrode layer 16 side. It has a second silicon oxide film 14 to be formed and a silicon nitride film 13 formed between the first silicon oxide film 12 and the second silicon oxide film 14.
[0015] このような構成の本実施形態の薄膜トランジスタでは、閾値電圧及び S値を小さくす ることがでさる。  In the thin film transistor according to the present embodiment having such a configuration, the threshold voltage and the S value can be reduced.
また図 1 (b)に示すように、ゲート絶縁層が第 1の酸ィ匕珪素膜及び窒化珪素膜の二 層構造でも、ゲート絶縁膜の絶縁性が満足するものであれば、図 1 (a)で示した第 2 の酸ィ匕珪素膜を成膜しなくてもょ ヽ。  Further, as shown in FIG. 1B, even if the gate insulating layer has a two-layer structure of the first silicon oxide film and the silicon nitride film, if the insulating property of the gate insulating film is satisfied, the structure shown in FIG. It is not necessary to form the second silicon oxide film shown in a).
[0016] 次に本実施形態の製造装置について説明する。 Next, the manufacturing apparatus of the present embodiment will be described.
図 2は、このポリシリコン TFTのゲート絶縁層を成膜するためのプラズマ CVD装置 を示す概略断面図である。  FIG. 2 is a schematic sectional view showing a plasma CVD apparatus for forming a gate insulating layer of this polysilicon TFT.
このプラズマ CVD装置 1の反応容器 2の上部には、ガスボンベ等の複数のガス源（ 不図示)等が接続されているガス導入系 3が設けられており、反応容器 2の下部には 、真空ポンプ (不図示)等が接続されている排気系 4が設けられている。反応容器 2内 には、 2個の平板状の上部電極 5と下部電極 6が対向して設置されており、上側に位 置する上部電極 5には高周波電力をパルス変調させる変調器 7を介して外部の高周 波電源 8が接続され、下側に位置する下部電極 6上には成膜が施される基板 9が載 置され、下部電極 6は基板ホルダーも兼ねている。高周波電源 8は、上部電極 5に対 して 27. 12MHzの高周波電圧を印加するように構成されている。なお、高周波電圧 として 13. 56MHzも可能である力 上記 27. 12MHzの高周波電圧の方力 ガスの 分解効率が上がり好ましい。 A gas introduction system 3 to which a plurality of gas sources (not shown) such as gas cylinders is connected is provided above the reaction vessel 2 of the plasma CVD apparatus 1, and a vacuum is provided below the reaction vessel 2 An exhaust system 4 to which a pump (not shown) and the like are connected is provided. In the reaction vessel 2, two plate-like upper electrodes 5 and lower electrodes 6 are installed so as to face each other, and the upper electrode 5 located on the upper side is provided via a modulator 7 for pulse-modulating high-frequency power. An external high-frequency power supply 8 is connected to the lower electrode 6, and a substrate 9 on which a film is to be formed is placed on the lower electrode 6 located on the lower side. The lower electrode 6 also serves as a substrate holder. The high-frequency power supply 8 is configured to apply a high-frequency voltage of 27.12 MHz to the upper electrode 5. Note that a power of 13.56 MHz is also possible as a high frequency voltage. It is preferable because the decomposition efficiency is increased.
上部電極 5は、その前面側（下部電極 6側）にシャワープレート 10が設けられるよう に中空部 5aを有しており、その中空部 5aと連通するようにしてガス導入系 3の先端側 を接続して、シャワープレート 10に形成されている多数のガス噴出口 10aから下部電 極 6上の基板 9に向けて均一に原料ガスを噴出させるように構成されている。また、下 部電極 6は、載置される基板 9を所定温度に加熱するヒータ (不図示）が内蔵されて おり、成膜中はアース電位に維持されるように構成されて 、る。  The upper electrode 5 has a hollow portion 5a so that the shower plate 10 is provided on the front side (the lower electrode 6 side), and the front end side of the gas introduction system 3 is communicated with the hollow portion 5a. The source gas is connected to the substrate 9 on the lower electrode 6 from a number of gas outlets 10a formed in the shower plate 10 so as to uniformly eject the source gas. The lower electrode 6 has a built-in heater (not shown) for heating the substrate 9 to be mounted to a predetermined temperature, and is configured to be maintained at the ground potential during the film formation.
[0017] 次に、本発明に係るポリシリコン TFTの製造方法について説明する。 Next, a method for manufacturing a polysilicon TFT according to the present invention will be described.
先ず、基板 9上に減圧熱 CVD法やプラズマ CVD法などによって非晶質珪素膜を 5 Onmの厚さに成膜した後に、キセノンクロライド (XeCl)エキシマレーザー（波長 308 nm)又はクリプトンフロライド (KrF)エキシマレーザー（波長 248nm)を照射すること により、非晶質珪素膜を結晶化させて結晶性珪素膜であるポリシリコン (Poly— Si)を 得ることができる。これをフォトリソグラフィー及びエッチングを用いてパターユングして 、活性層 11を形成する。  First, after forming an amorphous silicon film to a thickness of 5 Onm on the substrate 9 by a low pressure thermal CVD method or a plasma CVD method, a xenon chloride (XeCl) excimer laser (wavelength 308 nm) or krypton fluoride ( By irradiating a KrF) excimer laser (wavelength: 248 nm), the amorphous silicon film can be crystallized to obtain a crystalline silicon film, polysilicon (Poly-Si). This is patterned using photolithography and etching to form an active layer 11.
そして、活性層 11が形成された基板 9を、上記したプラズマ CVD装置 1の反応容 器 2内の下部電極 6上に載置して、ヒータ（不図示）に通電して抵抗加熱し、基板 9を 所定温度に加熱する。この際、反応容器 2内を排気系 4を通して排気して所定の圧 力に調整する。  Then, the substrate 9 on which the active layer 11 is formed is placed on the lower electrode 6 in the reaction vessel 2 of the plasma CVD apparatus 1 described above, and a heater (not shown) is energized to perform resistance heating. Heat 9 to the specified temperature. At this time, the inside of the reaction vessel 2 is evacuated through the exhaust system 4 and adjusted to a predetermined pressure.
[0018] そして、ガス導入系 3を通して反応容器 2内に第 1の珪素付与ガスとしてのテトラエト キシオルソシリケート (TEOS)等のシラン系ガスと、酸素等の酸素付与ガスからなる 混合ガス（原料ガス）を導入し、シャワープレート 10の多数のガス噴出口 10aから下 部電極 6上の基板 9に向けて均一に混合ガスを噴出させる。この際、高周波電源 8か ら上部電極 5に対して 27. 12MHzの高周波電圧を印加して、上部電極 5と下部電 極 6との間の空間に放電を発生させて上記混合ガスをプラズマ化し、活性層 11上に 第 1の絶縁層である第 1の酸ィ匕珪素膜 12を 40〜50nmの厚さで成膜する。  [0018] Then, a mixed gas (a source gas) comprising a silane-based gas such as tetraethoxyorthosilicate (TEOS) as a first silicon-providing gas and an oxygen-supplying gas such as oxygen is introduced into the reaction vessel 2 through the gas introduction system 3. ) Is introduced, and the mixed gas is uniformly ejected from the many gas ejection ports 10 a of the shower plate 10 toward the substrate 9 on the lower electrode 6. At this time, a high frequency voltage of 27.12 MHz is applied from the high frequency power supply 8 to the upper electrode 5 to generate a discharge in the space between the upper electrode 5 and the lower electrode 6 to convert the above mixed gas into plasma. Then, a first silicon oxide film 12 as a first insulating layer is formed on the active layer 11 to a thickness of 40 to 50 nm.
なお、第 1の酸化珪素膜 12を成膜する際に、第 1の珪素付与ガスとして上記したテ トラエトキシオルソシリケート (TEOS)等のシラン系ガス以外にも、例えばモノシランと 、ジシラン力もなる群より選択されるいずれか 1種類のガスを用いてもよぐまた、酸素 付与ガスとして酸素以外にも、例えば亜酸化窒素、オゾン、二酸化炭素、水からなる 群より選択される 、ずれか 1種類のガスを用いることができる。 When the first silicon oxide film 12 is formed, in addition to the above-mentioned silane-based gas such as tetraethoxyorthosilicate (TEOS) as the first silicon imparting gas, for example, monosilane and disilane are also used. You can use any one of the selected gases. In addition to oxygen, any one of the gases selected from the group consisting of, for example, nitrous oxide, ozone, carbon dioxide, and water can be used as the applied gas.
[0019] そして、その後、同様にして第 2の珪素付与ガスとしてのモノシラン (SiH )等のシラ [0019] Then, in the same manner, a silica such as monosilane (SiH) is used as the second silicon imparting gas.
4 ン系ガスと、アンモニア等の窒素付与ガスと、窒素等の希釈ガスからなる混合ガスを 導入し、放電により上記混合ガスをプラズマ化して、第 1の酸ィ匕珪素膜 12上に第 2の 絶縁層である窒化珪素膜 13を 10〜20nmの厚さで成膜する。  A mixed gas consisting of an oxygen-based gas, a nitrogen-imparting gas such as ammonia, and a diluent gas such as nitrogen is introduced, and the mixed gas is turned into plasma by electric discharge to form a second gas on the first silicon oxide film 12. A silicon nitride film 13 as an insulating layer is formed with a thickness of 10 to 20 nm.
なお、窒化珪素膜 13を成膜する際に、第 2の珪素付与ガスとしてモノシラン以外に も、例えばテトラエトキシオルソシリケートと、へキサメチルジシラザンと、ジシランから なる群より選択されるいずれか 1種類のガスを用いてもよぐまた、前記窒素付与ガス としてアンモニア以外にも、例えば一酸化窒素、ヒドラジン力もなる群より選択される V、ずれ力 1種類のガスを用いることができる。  When the silicon nitride film 13 is formed, in addition to monosilane as the second silicon-providing gas, any one selected from the group consisting of, for example, tetraethoxyorthosilicate, hexamethyldisilazane, and disilane is used. In addition to the ammonia, the nitrogen-providing gas may be a gas of one kind, for example, V selected from the group consisting of nitric oxide and hydrazine power, and a shear force of one kind.
[0020] そして、その後、第 1の酸ィ匕珪素膜 12と同じガス系の混合ガスを導入し、放電により 上記混合ガスをプラズマ化して、窒化珪素膜 13上に第 3の絶縁層である第 2の酸ィ匕 珪素膜 14を 50nmの厚さで成膜する。そして、これをフォトリソグラフィー及びエッチ ングを用いてパターユングして、ゲート絶縁層 15を形成する。本発明の特徴であるゲ ート絶縁層 15の詳細については後述する。 Thereafter, a mixed gas of the same gas system as that of the first silicon oxide film 12 is introduced, and the mixed gas is turned into plasma by electric discharge to form a third insulating layer on the silicon nitride film 13. A second silicon oxide film 14 is formed with a thickness of 50 nm. Then, the gate insulating layer 15 is formed by patterning using photolithography and etching. Details of the gate insulating layer 15 which is a feature of the present invention will be described later.
この第 2の酸ィ匕珪素膜 14はゲート絶縁膜の絶縁性が満足するものであれば成膜し なくてもよい。  The second silicon oxide film 14 need not be formed as long as the insulating properties of the gate insulating film are satisfied.
なお、第 1、 2の酸ィ匕珪素膜 12、 14を形成する混合ガスとしては、シラン系ガス、酸 素付与ガスのそれぞれから少なくとも 1種類ずつ選んで所定量混合してなる混合ガス を用いており、窒化珪素膜 13を形成する混合ガスとしては、シラン系ガス、窒素付与 ガス、希釈ガスのそれぞれから少なくとも 1種類ずつ選んで所定量混合してなる混合 ガスを用いている。  As a mixed gas for forming the first and second silicon oxide films 12 and 14, a mixed gas obtained by selecting at least one kind from each of a silane-based gas and an oxygen-imparting gas and mixing them in a predetermined amount is used. As the mixed gas for forming the silicon nitride film 13, a mixed gas obtained by selecting at least one of each of a silane-based gas, a nitrogen-imparting gas, and a diluent gas and mixing them in a predetermined amount is used.
[0021] 次に、上記ゲート絶縁層 15 (第 2の酸ィ匕珪素膜 14)上に、アルミニウム膜をスパッタ 法で 250nmの厚さに成膜した後にモリブデン膜 50nmをスパッタ法で成膜する。この アルミニウム膜中にはスカンジウムを 0. 2重量0 /0含有させる。これは、後の工程にお いてヒロックゃゥイスカーと呼ばれる針状の突起物が形成されることを抑制するためで ある。そして、これをフォトリソグラフィー及びエッチングを用いてパターユングすること により、ゲート電極 16を形成する。 Next, on the gate insulating layer 15 (the second silicon oxide film 14), an aluminum film is formed to a thickness of 250 nm by a sputtering method, and then a molybdenum film 50 nm is formed by a sputtering method. . This aluminum film to scandium 0.2 weight 0/0 contained. This is to prevent the formation of needle-like projections called hillock whiskers in a later step. And this is putterung using photolithography and etching Thus, a gate electrode 16 is formed.
そして、ゲート電極 16を形成したら次にソース Zドレイン領域を形成するための不 純物（一導電型を付与するための不純物）のドーピングを行う。ここでは、 Nチャネル 型の薄膜トランジスタを得るために、 P (リン)のドーピングをプラズマドーピング法によ つて行う。ドーピングの終了後にァニールを行うことにより、ドーピングされた不純物の 活性ィ匕とドーピング時の損傷のァニールとを行う。上記の工程において、それぞれソ ース領域 17、チャネル領域 18、ドレイン領域 19が自己整合的に形成される。  After the gate electrode 16 is formed, doping with impurities (impurities for imparting one conductivity type) for forming the source Z drain region is performed. Here, P (phosphorus) doping is performed by a plasma doping method in order to obtain an N-channel thin film transistor. By performing annealing after the end of the doping, activation of the doped impurities and annealing of damage at the time of doping are performed. In the above steps, a source region 17, a channel region 18, and a drain region 19 are formed in a self-aligned manner.
[0022] 次に、ゲート電極 16とゲート絶縁層 15上に、 CVD法（プラズマ CVD法、熱 CVD法 、 ECRプラズマ CVD法など）により酸ィ匕珪素膜 20を 250nmの厚さで成膜する。そし て、これをフォトリソグラフィー及びエッチングを用いてコンタクトホールの形成を行な つて層間絶縁層 21を形成した後、モリブデン膜をスパッタ法で 50nmの厚さに成膜し た後にアルミニウム膜 300nmを成膜し、ソース電極 22とドレイン電極 23の形成する ことにより、図 1に示した本発明に係るポリシリコン TFTが得られる。 Next, an oxide silicon film 20 is formed to a thickness of 250 nm on the gate electrode 16 and the gate insulating layer 15 by a CVD method (plasma CVD method, thermal CVD method, ECR plasma CVD method, etc.). . Then, a contact hole is formed using photolithography and etching to form an interlayer insulating layer 21. Then, a molybdenum film is formed to a thickness of 50 nm by a sputtering method, and then an aluminum film is formed to a thickness of 300 nm. By forming a film and forming the source electrode 22 and the drain electrode 23, the polysilicon TFT according to the present invention shown in FIG. 1 is obtained.
[0023] 次に、上記した触媒 CVD装置 1によって製造される本発明に係るゲート絶縁層 15 の成膜条件等について説明する。 Next, conditions for forming the gate insulating layer 15 according to the present invention manufactured by the above-described catalytic CVD apparatus 1 will be described.
本発明に係るゲート絶縁層 15の膜厚は、第 1層（第 1の酸ィ匕珪素膜 12)：第 2層（窒 化珪素膜 13)：第 3層（第 2の酸ィ匕珪素膜 14) = 50nm: 10nm: 50nmであり、それぞ れの成膜プロセス条件は、図 3に示した通りである。なお、比較のために、従来のポリ シリコン TFTのゲート絶縁層で使用されている TEOSを原料ガスとした酸ィ匕珪素膜 の代表的な成膜プロセス条件も併せて図 3に示した。なお、成膜速度、基板面内で の膜厚分布については、 730mm X 920mmサイズのガラス基板上に成膜した場合 の結果である。また、 Vl (単位: V)は、ゲート絶縁層中の欠陥の量を示す指標として フラットバンド電圧であり、 Dit (単位: Cm_2'eV_1)は、ゲート絶縁層と珪素薄膜の界 面の欠陥密度を示す指標としての界面準位密度である。また、この場合の基板は、 P 型の Si[001]単結晶ウェハ（Na = 2 X 1015cm"3)を用いて!/、る。 The gate insulating layer 15 according to the present invention has a thickness of the first layer (first silicon nitride film 12): the second layer (silicon nitride film 13): the third layer (second silicon nitride film 13). Film 14) = 50 nm: 10 nm: 50 nm, and the respective film forming process conditions are as shown in FIG. For comparison, FIG. 3 also shows typical film forming process conditions for an oxidized silicon film using TEOS as a source gas, which is used for a gate insulating layer of a conventional polysilicon TFT. The film formation rate and the film thickness distribution in the substrate surface are the results when a film is formed on a glass substrate of 730 mm × 920 mm size. Further, Vl (Unit: V) is a flat band voltage as an indication of the amount of defects in the gate insulating layer, Dit (Unit: C m _2 'eV _1) are field surfaces of the gate insulating layer and the thin silicon film Is the interface state density as an index indicating the defect density of the sample. In this case, the substrate is a P-type Si [001] single crystal wafer (Na = 2 × 10 15 cm ″ 3 ).
図 3に示したように、従来のゲート絶縁層の場合は、 TEOSを原料ガスとした酸ィ匕珪 素膜の成膜速度: 80nmZmin程度で、基板面内での膜厚分布 (10mm端 )： ± 7. 5 %程度である。また、その膜厚を l lOnmとした場合、 Vl =— 1. 5〜― 2. 0Vであり 、 Dit = 8 X 10 cm 'eV であった。 As shown in FIG. 3, in the case of the conventional gate insulating layer, the film formation rate of the silicon oxide film using TEOS as a source gas is about 80 nm Zmin, and the film thickness distribution in the substrate surface (10 mm end) : About ± 7.5%. When the film thickness is l lOnm, Vl = —1.5 to −2.0 V Dit = 8 × 10 cm′eV.
[0024] このことを踏まえると、後述する図 4〜図 16に示す測定結果から、本発明における ゲート絶縁層の成膜プロセス条件は、ゲート絶縁層の全体の成膜速度： 78〜83nm Zmin程度で、基板面内での膜厚分布 (10mm端)： ± 5. 5〜7. 0%程度である。ま た、その膜厚を l lOnmとした場合、 Vl =— 1. 0〜一 1. 5Vであり、 Dit=4. 3 X 101 °〜9. 6 X 1010cm_2'eV_1である。 [0024] Based on this, from the measurement results shown in FIGS. 4 to 16 described later, the film forming process conditions of the gate insulating layer in the present invention are as follows: the overall film forming speed of the gate insulating layer: about 78 to 83 nm Zmin And the film thickness distribution in the substrate plane (10 mm end): about ± 5.5 to 7.0%. Also, when the film thickness is l lOnm, Vl = --1.0 to 1.5 V, and Dit = 4.3 X 10 1 ° to 9.6 X 10 10 cm _2 'eV _1 .
図 4は、第 1、第 3層としての酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の形成 時における、成膜温度と成膜速度の関係を示す測定結果であり、図 5は、酸化珪素 膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の形成時における、成膜温度と Dit、 Vlの関係 を示す測定結果である。なお、図 5において、 aは Ditであり、 bは Vlである。  FIG. 4 is a measurement showing the relationship between the film forming temperature and the film forming speed when forming the silicon oxide films as the first and third layers (the first and second silicon oxide films 12 and 14). FIG. 5 shows the measurement results showing the relationship between the deposition temperature and Dit and Vl when forming the silicon oxide films (first and second silicon oxide films 12 and 14). In FIG. 5, a is Dit and b is Vl.
図 4に示す測定結果力も明らかなように、成膜温度を上げると成膜速度が低下し生 産性が落ちる。また、図 5に示す結果力も明らかなように、 Ditは成膜温度が上がると 減少して界面の欠陥密度が低下するが、 430°C程度以上で概ね一定値になる。一 方、 Vl は成膜温度が上がると上昇して層内の欠陥量の減少を示すが、 430°C以上 で一定値となる。なお、基板の耐熱温度ならびに装置材料の都合上力 450°C程度 以下が好ましい。  As is clear from the measurement results shown in FIG. 4, as the film formation temperature is increased, the film formation rate is reduced, and the productivity is reduced. In addition, as is clear from the results shown in FIG. 5, Dit decreases as the film formation temperature increases, and the defect density at the interface decreases. However, Dit becomes approximately constant at about 430 ° C. or higher. On the other hand, Vl increases as the deposition temperature increases, indicating a decrease in the amount of defects in the layer, but becomes constant above 430 ° C. Note that the temperature is preferably about 450 ° C. or less due to the heat resistant temperature of the substrate and the material of the device.
このため、酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の成膜速度を高く維持し、 Ditを低ぐ Vlを高く成膜するためには、 330°C〜430°C程度の範囲で成膜すること が好ましい。  Therefore, in order to maintain a high deposition rate of the silicon oxide film (first and second silicon oxide films 12 and 14) and reduce the Dit and increase the Vl It is preferable to form the film in the range of about 430 ° C.
[0025] 図 6は、酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の形成時における、珪素付 与ガスに対する酸素ガス組成比と成膜速度の関係を示す測定結果であり、図 7は、 酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の形成における、酸素ガス組成比と D it、 Vl の関係を示す測定結果である。なお、図 7において、 aは Ditであり、 bは Vlで ある。  FIG. 6 shows the relationship between the oxygen gas composition ratio with respect to the silicon-supplied gas and the film formation rate when forming the silicon oxide films (first and second silicon oxide films 12 and 14). FIG. 7 is a measurement result showing the relationship between the oxygen gas composition ratio and D it and Vl in the formation of the silicon oxide films (first and second silicon oxide films 12 and 14). is there. In FIG. 7, a is Dit and b is Vl.
図 6に示す結果力も明らかなように、酸素ガス組成比を上げると成膜速度が低下し 生産性が落ちる。また、図 7に示す結果から明らかなように、 Ditは酸素ガス組成比が 上がると減少して界面の欠陥密度が低下し、酸素ガス組成比が 30以下で急激に低 下して、 50以上で概ね一定値となる。一方、 Vlbは酸素ガス組成比が上がると上昇し て層内の欠陥量の減少を示すが、 30以下で急激に上昇し 50以上で概ね一定値と なる。 As is clear from the results shown in FIG. 6, when the oxygen gas composition ratio is increased, the film formation rate is reduced and the productivity is reduced. Also, as is evident from the results shown in Fig. 7, Dit decreases as the oxygen gas composition ratio increases, and the defect density at the interface decreases. Is approximately constant. On the other hand, Vlb increases as the oxygen gas composition ratio increases. This indicates a decrease in the amount of defects in the layer, but increases sharply below 30 and becomes almost constant above 50.
このため、酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の成膜速度を高く維持し、 Ditを低ぐ Vlを高く成膜するためには、珪素付与ガスに対する酸素ガス組成比が 3 0〜50の範囲で成膜することが好まし!/、。  For this reason, in order to maintain a high deposition rate of the silicon oxide film (the first and second silicon oxide films 12 and 14) and to reduce Dit and increase Vl, a silicon-imparting gas is required. It is preferable to form a film with an oxygen gas composition ratio in the range of 30 to 50! /.
[0026] 図 8は、酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)を形成時における、プロセス 圧力と成膜速度及び基板面内分布の関係を示す測定結果である。なお、図 8におい て、 aは成膜速度、 bは基板面内分布である。この測定結果から明らかなように、プロ セス圧力を上げると成膜速度が減少する。また、基板面内分布は、プロセス圧力 125 Pa付近で最小値を取る。 FIG. 8 is a measurement result showing a relationship between a process pressure, a film formation rate, and a distribution in a substrate surface when forming silicon oxide films (first and second silicon oxide films 12, 14). It is. In FIG. 8, a is the film formation rate, and b is the in-plane distribution of the substrate. As is evident from the measurement results, increasing the process pressure decreases the deposition rate. In addition, the distribution in the substrate surface takes a minimum value near a process pressure of 125 Pa.
このため、酸ィ匕珪素膜 (第 1、第 2の酸ィ匕珪素膜 12、 14)の基板面内分布を小さく するためには、プロセス圧力 80〜200Pa程度の範囲で成膜することが好ましい。 図 9は、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13)の形成時における、珪 素付与ガスに対する窒素付与ガスとしてのアンモニアガス組成比と成膜速度の関係 を示す測定結果であり、図 10は、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13 )の形成時における、アンモニアガス組成比と Dit、 Vl の関係を示す測定結果である 。なお、図 10において、 aは Ditであり、 bは Vlである。  Therefore, in order to reduce the distribution of the silicon oxide films (the first and second silicon oxide films 12 and 14) in the substrate surface, the silicon oxide film should be formed at a process pressure of about 80 to 200 Pa. preferable. FIG. 9 shows measurement results showing the relationship between the composition ratio of ammonia gas as a nitrogen-imparting gas to the silicon-imparting gas and the film formation rate during the formation of a silicon nitride film (silicon nitride film 13 as a second insulating layer). FIG. 10 shows measurement results showing the relationship between the ammonia gas composition ratio and Dit, Vl when forming a silicon nitride film (silicon nitride film 13 as a second insulating layer). In FIG. 10, a is Dit and b is Vl.
[0027] 図 9に示す測定結果力も明らかなように、アンモニアガス組成比を上げると成膜速 度が低下し生産性が落ちる。また、図 10に示す結果から明らかなように、アンモニア ガス組成比が上がると Ditは減少して界面の欠陥密度が低下し、アンモニアガス組成 比が 20程度まで Ditは急激に低下して、 20以上で概ね一定値となる。一方、 Vlbはァ ンモユアガス組成比が上がると上昇して層内の欠陥量の減少を示す力 20程度まで 急激に上昇し 20以上で概ね一定値となる。 [0027] As is clear from the measurement results shown in Fig. 9, when the ammonia gas composition ratio is increased, the film formation rate is decreased, and the productivity is decreased. Also, as is evident from the results shown in Fig. 10, when the ammonia gas composition ratio increases, Dit decreases and the defect density at the interface decreases, and Dit decreases rapidly until the ammonia gas composition ratio becomes about 20. As a result, the value becomes substantially constant. On the other hand, Vlb rises as the composition ratio of the ammonia gas increases and rises sharply to a force of about 20, which indicates a decrease in the amount of defects in the layer, and becomes substantially constant above 20.
したがって、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13)の成膜速度を高く 維持し、 Ditを低ぐ Vlbを高く成膜するためには、アンモニアガス組成比が 10〜25程 度の範囲で成膜することが好ま 、。  Therefore, in order to maintain a high deposition rate of the silicon nitride film (silicon nitride film 13 as the second insulating layer) and to reduce Dit to increase Vlb, the ammonia gas composition ratio is about 10 to 25. It is preferable to form a film in a range of degrees.
図 11は、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13)の形成時における、珪 素付与ガスに対する窒素ガス (希釈ガス)の組成比と、成膜速度と基板面内分布の関 係を示す測定結果である。なお、図 11において、 aは成膜速度であり、 bは基板面内 分布である。 FIG. 11 shows the composition ratio of the nitrogen gas (diluent gas) to the silicon-imparting gas, the deposition rate, and the distribution in the substrate surface when the silicon nitride film (the silicon nitride film 13 as the second insulating layer) was formed. Seki It is a measurement result showing the relationship. Note that in FIG. 11, a is the film formation rate, and b is the distribution in the substrate plane.
[0028] 図 11に示す測定結果から明らかなように、窒素ガスの組成比を上げると成膜速度 が減少する。また、基板面内分布は、窒素ガスの組成比 20付近で最小値を取る。こ のため、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13)の基板面内分布を小さく するためには、窒素ガスの組成比 10〜30程度の範囲で成膜することが好ましい。 図 12は、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13)の形成時における、プ ロセス圧力と、成膜速度と基板面内分布の関係を示す測定結果である。なお、図 12 において、 aは成膜速度であり、 bは基板面内分布である。  As is clear from the measurement results shown in FIG. 11, increasing the composition ratio of the nitrogen gas decreases the film formation rate. Further, the distribution in the substrate surface takes a minimum value at a nitrogen gas composition ratio of around 20. Therefore, in order to reduce the distribution of the silicon nitride film (silicon nitride film 13 as the second insulating layer) in the substrate surface, it is preferable to form the film at a nitrogen gas composition ratio of about 10 to 30. . FIG. 12 is a measurement result showing a relationship between a process pressure, a film formation rate, and a distribution in a substrate surface when a silicon nitride film (a silicon nitride film 13 as a second insulating layer) is formed. In FIG. 12, a is the film formation rate, and b is the in-plane distribution of the substrate.
図 12に示す測定結果力も明らかなように、プロセス圧力を上げると成膜速度が減少 し、基板面内分布はプロセス圧力 250Pa付近で最小値を取る。このため、窒化珪素 膜 (第 2の絶縁層としての窒化珪素膜 13)の基板面内分布を小さくするためには、プ ロセス圧力 200〜400Pa程度の範囲で成膜することが好まし!/、。  As is clear from the measurement results shown in Fig. 12, when the process pressure is increased, the film deposition rate is reduced, and the distribution in the substrate surface takes a minimum value at a process pressure of around 250 Pa. Therefore, in order to reduce the distribution of the silicon nitride film (the silicon nitride film 13 as the second insulating layer) in the substrate surface, it is preferable to form the film at a process pressure of about 200 to 400 Pa! ,.
[0029] 図 13は、窒化珪素膜 (第 2の絶縁層としての窒化珪素膜 13)の形成時における、成 膜温度と成膜速度の関係を示す測定結果であり、図 14は、窒化珪素膜 (第 2の絶縁 層としての窒化珪素膜 13)の形成時における、成膜温度と Dit、 Vlbの関係を示す測 定結果である。なお、図 14において、 aは Ditであり、 bは Vlbである。 FIG. 13 shows a measurement result showing a relationship between a film forming temperature and a film forming rate when forming a silicon nitride film (the silicon nitride film 13 as a second insulating layer). 9 is a measurement result showing a relationship between a film forming temperature, Dit, and Vlb when forming a film (a silicon nitride film 13 as a second insulating layer). In FIG. 14, a is Dit and b is Vlb.
図 13に示す測定結果力も明らかなように、成膜温度を上げると成膜速度が低下し 生産性が落ちる。また、図 14に示す結果力も明らかなように、 Ditは成膜温度が上が ると減少して界面の欠陥密度が低下するが、 430°C程度以上で概ね一定値になる。 一方、 Vl は成膜温度が上がると上昇して層内の欠陥量の減少を示すが、 430°C程 度以上で一定値となる。なお、基板の耐熱温度力も 450°C程度以下が好ましい。 このため、窒化珪素膜（(第 2の絶縁層としての窒化珪素膜 13)の成膜速度を高く 維持し、 Ditを低ぐ Vlbを高く成膜するためには、 330°C〜430°C程度の範囲で成膜 することが好ましい。  As is clear from the measurement results shown in FIG. 13, increasing the deposition temperature decreases the deposition rate and reduces productivity. As is clear from the results shown in FIG. 14, Dit decreases as the film formation temperature increases, and the defect density at the interface decreases. However, Dit becomes approximately constant at about 430 ° C. or higher. On the other hand, Vl increases as the deposition temperature increases, indicating a decrease in the amount of defects in the layer, but becomes constant at about 430 ° C or higher. The heat resistance temperature of the substrate is preferably about 450 ° C. or less. Therefore, in order to maintain a high deposition rate of the silicon nitride film (the silicon nitride film 13 as the second insulating layer) and to reduce the Dit and to increase the Vlb, a temperature of 330 to 430 ° C. It is preferable to form the film within the range.
[0030] 図 15は、本発明におけるゲート絶縁層 15の第 1、第^ i (第 1、第 2の酸ィ匕珪素膜 1 2、 14)における膜厚と、 Dit、 Vlの関係を示す測定結果である。図 16は、本発明に おけるゲート絶縁層 15の第 2層（窒化珪素膜 13)における膜厚と、 Dit、 Vlの関係を 示す測定結果である。なお、図 15、図 16において、 aは Ditであり、 bは Vlである。 図 15、図 16に示す測定結果力も明らかなように、第 2層（窒化珪素膜 13)の膜厚を 10〜20nmとした場合に、第 1、第^ i (第 1、第 2の酸ィ匕珪素膜 12、 14)の膜厚がそ れぞれ 40〜50nmの範囲で良質な膜質（Ditが低ぐかつ Vlが高い）のゲート絶縁 層を得ることができた。 FIG. 15 shows the relationship between the thicknesses of the first and second i (first and second silicon oxide films 12 and 14) of the gate insulating layer 15 and Dit and Vl in the present invention. It is a measurement result. FIG. 16 shows the relationship between the thickness of the second layer (the silicon nitride film 13) of the gate insulating layer 15 and Dit and Vl in the present invention. It is a measurement result shown. In FIGS. 15 and 16, a is Dit and b is Vl. As is clear from the measurement results shown in FIGS. 15 and 16, when the thickness of the second layer (silicon nitride film 13) is set to 10 to 20 nm, the first and ^ i (first and second acids) When the thickness of each of the silicon films 12 and 14) was in the range of 40 to 50 nm, a gate insulating layer of good quality (low Dit and high Vl) could be obtained.
[0031] また、上記した本発明に係るゲート絶縁層 15と、 TEOSを原料ガスとした酸ィ匕珪素 膜からなる従来のゲート絶縁層をそれぞれ有する上記ポリシリコン TFTを製造した場 合における、サブスレツショルドスイング値（S値、単位: VZdec)とスレツショルド電圧 (Vth,単位: V)を測定したところ、図 17に示すような測定結果が得られた。なお、こ のときの各ゲート絶縁層の成膜プロセス条件は、図 3の場合と同様である。  In addition, when the above-described polysilicon TFT having the above-described gate insulating layer 15 according to the present invention and the conventional gate insulating layer made of an oxidized silicon film using TEOS as a source gas is manufactured, When the threshold swing value (S value, unit: VZdec) and the threshold voltage (Vth, unit: V) were measured, measurement results as shown in FIG. 17 were obtained. Note that the film forming process conditions of each gate insulating layer at this time are the same as those in FIG.
図 17に示す測定結果力も明らかなように、本発明に係る 3層構造のゲート絶縁層 ( 第 1の酸ィ匕珪素膜 12、窒化珪素膜 13、第 2の酸ィ匕珪素膜 14) 15を成膜することによ り、従来の単層構造のゲート絶縁層（酸化珪素膜）に比べて、サブスレツショルドスィ ング値（S値）を小さぐかつスレツショルド電圧 (Vth)の小さ 、高性能なポリシリコン T FTを作製することができる。  As is clear from the measurement results shown in FIG. 17, the gate insulating layer having a three-layer structure according to the present invention (first silicon oxide film 12, silicon nitride film 13, and second silicon oxide film 14) 15 By forming a film, the sub-threshold swing value (S value) is smaller and the threshold voltage (Vth) is smaller and higher than that of a conventional gate insulating layer (silicon oxide film) having a single-layer structure. A high performance polysilicon TFT can be manufactured.
[0032] このように、発明に係る製造方法によれば、良好な生産性を確保しつつ、優れた特 性 (低い基板温度 (450°C程度以下）にてゲート絶縁層の膜中の欠陥ならびに珪素 薄膜との界面の欠陥密度を大幅に低減した)のゲート絶縁層を有するポリシリコン TF Tを得ることがでさる。  [0032] As described above, according to the manufacturing method of the present invention, it is possible to ensure good productivity and to obtain excellent characteristics (defects in the gate insulating layer at low substrate temperature (about 450 ° C or less)). In addition, it is possible to obtain a polysilicon TFT having a gate insulating layer having a greatly reduced defect density at the interface with the silicon thin film.

Claims

請求の範囲 The scope of the claims
[1] 基板上にソース領域、ドレイン領域、チャンネル領域を有する活性層と、ゲート電極 層と、前記活性層と前記ゲート電極層との間に形成されるゲート絶縁層とを有する薄 膜トランジスタであって、  [1] A thin film transistor including an active layer having a source region, a drain region, and a channel region on a substrate, a gate electrode layer, and a gate insulating layer formed between the active layer and the gate electrode layer. So,
前記ゲート絶縁層が、前記活性層に接して形成される第 1の酸化珪素膜と、この第 1の酸ィ匕珪素膜と前記ゲート電極層との間に前記第 1の酸ィ匕珪素膜に接して形成さ れる窒化珪素膜とを含む、ことを特徴とする薄膜トランジスタ。  A first silicon oxide film in which the gate insulating layer is formed in contact with the active layer, and the first silicon oxide film between the first silicon oxide film and the gate electrode layer; And a silicon nitride film formed in contact with the thin film transistor.
[2] 前記窒化珪素膜と前記ゲート電極層との間に第 2の酸ィ匕珪素膜を有することを特 徴とする請求項 1に記載の薄膜トランジスタ。  2. The thin film transistor according to claim 1, further comprising a second silicon oxide film between the silicon nitride film and the gate electrode layer.
[3] 前記活性層がポリシリコンで形成される、ことを特徴とする請求項 1又は 2に記載の 薄膜トランジスタ。 3. The thin film transistor according to claim 1, wherein the active layer is formed of polysilicon.
[4] 前記第 1の酸ィ匕珪素膜、前記窒化珪素膜の膜厚の比が、 4〜5： 1〜2である、こと を特徴とする請求項 1記載の薄膜トランジスタ。  4. The thin film transistor according to claim 1, wherein a thickness ratio of the first silicon nitride film and the silicon nitride film is 4 to 5: 1 to 2.
[5] 前記第 1の酸ィヒ珪素膜、前記窒化珪素膜、前記第 2の酸ィヒ珪素膜のそれぞれの膜 厚の比力 4〜5 : 1〜2 :4〜5である、ことを特徴とする請求項 2に記載の薄膜トラン ジスタ。 [5] The specific force of the film thickness of each of the first silicon oxide film, the silicon nitride film, and the second silicon oxide film is 4 to 5: 1 to 2: 4 to 5 3. The thin film transistor according to claim 2, wherein:
[6] 前記第 1の酸ィ匕珪素膜の膜厚が 40nm以上 50nm以下である、ことを特徴とする請 求項 1又は 2に記載の薄膜トランジスタ。  [6] The thin film transistor according to claim 1 or 2, wherein the first silicon oxide film has a thickness of 40 nm or more and 50 nm or less.
[7] 前記窒化珪素膜の膜厚が lOnm以上 20nm以下である、ことを特徴とする請求項 1 又は 2に記載の薄膜トランジスタ。 7. The thin film transistor according to claim 1, wherein a thickness of the silicon nitride film is not less than lOnm and not more than 20 nm.
[8] 前記ゲート絶縁層全体の層厚が、 50nm以上 200nm以下である、ことを特徴とする 請求項 1〜7に記載の薄膜トランジスタ。 [8] The thin film transistor according to any one of claims 1 to 7, wherein a layer thickness of the entire gate insulating layer is 50 nm or more and 200 nm or less.
[9] 基板表面に活性層を形成する工程と、 [9] a step of forming an active layer on the substrate surface,
前記活性層上に第 1の酸ィ匕珪素膜を形成する工程と、  Forming a first silicon dioxide film on the active layer;
前記第 1の酸ィヒ珪素膜上に窒化珪素膜を形成する工程と、  Forming a silicon nitride film on the first silicon oxide film;
前記窒化珪素膜上にゲート電極層を形成する工程とを含む、ことを特徴とする薄膜 トランジスタの製造方法。  Forming a gate electrode layer on the silicon nitride film.
[10] 前記ゲート電極層を形成する工程が、前記窒化珪素膜上に第 2の酸ィ匕珪素膜を形 成後、ゲート電極層を形成する工程であることを特徴とする請求項 9記載の薄膜トラ ンジスタの製造方法。 [10] The step of forming the gate electrode layer includes forming a second silicon oxide film on the silicon nitride film. 10. The method for manufacturing a thin film transistor according to claim 9, wherein a step of forming a gate electrode layer after the formation is performed.
[11] 前記第 1の酸ィ匕珪素膜を形成する工程においては、圧力調整された反応容器内に 珪素原子を含む第 1の珪素付与ガス、酸素原子を含む酸素付与ガスのそれぞれの 少なくとも一種類ずつを導入して、プラズマ CVD法により酸ィ匕珪素膜を形成し、 前記窒化珪素膜を形成する工程においては、圧力調整された反応容器内に珪素 原子を含む第 2の珪素付与ガス、窒素原子を含む窒素付与ガス、希釈ガスのそれぞ れの少なくとも一種類ずつを導入して、プラズマ CVD法により窒化珪素膜を形成す る、ことを特徴とする請求項 9又は 10に記載の薄膜トランジスタの製造方法。  [11] In the step of forming the first silicon oxide film, at least one of the first silicon-imparting gas containing silicon atoms and the oxygen-imparting gas containing oxygen atoms in the pressure-adjusted reaction vessel. The silicon nitride film is formed by a plasma CVD method by introducing each type, and in the step of forming the silicon nitride film, a second silicon-containing gas containing silicon atoms is contained in a pressure-adjusted reaction vessel. 11. The thin film transistor according to claim 9, wherein a silicon nitride film is formed by a plasma CVD method by introducing at least one of each of a nitrogen imparting gas containing nitrogen atoms and a diluting gas. Manufacturing method.
[12] 前記第 1の珪素付与ガスは、テトラエトキシオルソシリケートと、へキサメチルジシラ ザンと、モノシランと、ジシラン力 なる群より選択されるいずれ力 1種類のガスであり、 前記酸素付与ガスは、酸素、亜酸化窒素、オゾン、二酸化炭素、水からなる群より 選択される!、ずれか 1種類のガスである、ことを特徴とする請求項 11に記載の薄膜ト ランジスタの製造方法。  [12] The first silicon-imparting gas is one gas selected from the group consisting of tetraethoxyorthosilicate, hexamethyldisilazane, monosilane, and disilane force. 12. The method for producing a thin film transistor according to claim 11, wherein the gas is selected from the group consisting of: nitrous oxide, ozone, carbon dioxide, and water!
[13] 前記第 1の珪素付与ガスと前記酸素付与ガスの組成比が、 1： 30〜50である、こと を特徴とする請求項 11又は 12に記載の薄膜トランジスタの製造方法。  13. The method for manufacturing a thin film transistor according to claim 11, wherein a composition ratio of the first silicon-imparting gas and the oxygen-imparting gas is 1:30 to 50.
[14] 前記酸ィ匕珪素膜の成膜時の圧力は 80〜200Paであり、基板温度は 330〜430°C である、ことを特徴とする請求項 11〜13のいずれか 1項に記載の薄膜トランジスタの 製造方法。  14. The method according to any one of claims 11 to 13, wherein the pressure during the formation of the silicon oxide film is 80 to 200 Pa, and the substrate temperature is 330 to 430 ° C. Method of manufacturing a thin film transistor.
[15] 前記第 2の珪素付与ガスは、テトラエトキシオルソシリケートと、へキサメチルジシラ ザンと、モノシランと、ジシラン力 なる群より選択されるいずれ力 1種類のガスであり、 前記窒素付与ガスは、アンモニア、一酸化窒素、ヒドラジン力 なる群より選択され る!、ずれか 1種類のガスである、ことを特徴とする請求項 11〜14の 、ずれか 1項に記 載の薄膜トランジスタの製造方法。  [15] The second silicon-providing gas is one gas selected from the group consisting of tetraethoxyorthosilicate, hexamethyldisilazane, monosilane, and disilane force. The nitrogen-providing gas is ammonia. 15. The method for manufacturing a thin film transistor according to claim 11, wherein the gas is selected from the group consisting of nitrogen monoxide, and hydrazine power!
[16] 前記第 2の珪素付与ガス、前記窒素付与ガス、前記希釈ガスの組成比が、 1： 10〜[16] The composition ratio of the second silicon-providing gas, the nitrogen-providing gas, and the dilution gas is 1:10 to
25 : 10〜30である、ことを特徴とする請求項 11〜15のいずれか 1項に記載の薄膜ト ランジスタの製造方法。 The method for producing a thin film transistor according to any one of claims 11 to 15, wherein the ratio is 25:10 to 30.
[17] 前記窒化珪素膜の成膜時の圧力は 200〜400Paであり、基板温度は 330〜430 °Cである、ことを特徴とする請求項 11〜16のいずれか 1項に記載の薄膜トランジスタ の製造方法。 [17] The pressure during the formation of the silicon nitride film is 200 to 400 Pa, and the substrate temperature is 330 to 430. 17. The method for producing a thin film transistor according to claim 11, wherein the temperature is ° C.
プラズマ CVD法で前記第 1の酸ィヒ珪素膜、前記第 2の酸ィヒ珪素膜、前記窒化珪素 膜をそれぞれ形成する際の、電極に印加する高周波電圧の周波数が 27.1MHzで ある、ことを特徴とする請求項 11〜17のいずれか 1項に記載の薄膜トランジスタの製 造方法。  When forming the first silicon oxide film, the second silicon oxide film, and the silicon nitride film by a plasma CVD method, a frequency of a high-frequency voltage applied to an electrode is 27.1 MHz. The method for producing a thin film transistor according to any one of claims 11 to 17, wherein:
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