WO2005076679A3 - Verfahren zum anordnen einer leitungsstruktur auf einem substrat und substrat mit der leitungsstruktur - Google Patents

Verfahren zum anordnen einer leitungsstruktur auf einem substrat und substrat mit der leitungsstruktur Download PDF

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Publication number
WO2005076679A3
WO2005076679A3 PCT/EP2005/050322 EP2005050322W WO2005076679A3 WO 2005076679 A3 WO2005076679 A3 WO 2005076679A3 EP 2005050322 W EP2005050322 W EP 2005050322W WO 2005076679 A3 WO2005076679 A3 WO 2005076679A3
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WO
WIPO (PCT)
Prior art keywords
substrate
conductor structure
nanotubes
transfer support
contact surface
Prior art date
Application number
PCT/EP2005/050322
Other languages
English (en)
French (fr)
Other versions
WO2005076679A2 (de
Inventor
Gerald Eckstein
Wolfram Wersing
Original Assignee
Siemens Ag
Gerald Eckstein
Wolfram Wersing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Gerald Eckstein, Wolfram Wersing filed Critical Siemens Ag
Priority to US10/587,982 priority Critical patent/US20070120273A1/en
Priority to EP05701610A priority patent/EP1712113A2/de
Priority to JP2006551839A priority patent/JP2007520887A/ja
Publication of WO2005076679A2 publication Critical patent/WO2005076679A2/de
Publication of WO2005076679A3 publication Critical patent/WO2005076679A3/de

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49877—Carbon, e.g. fullerenes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1094—Conducting structures comprising nanotubes or nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/30—Self-sustaining carbon mass or layer with impregnant or other layer

Abstract

Die Erfindung betrifft ein Verfahren zum Anordnen einer Leitungsstruktur (2) auf einem Substrat (1). Das Verfahren kann als Transferdruckverfahren bezeichnet werden. Folgende Verfahrensschritte werden durchgeführt: a) Herstellen einer trennbaren Verbindung (4) zwischen mindestens einem Transferträger (3) und der Leitungsstruktur (2), b) Zusammenbringen des Transferträgers (3) mit der Leistungsstruktur (2) und des Substrats (1), so dass eine Verbindung (5) zwischen der Leitungsstruktur (2) und dem Substrat (1) hergestellt wird, die stärker ist als die trennbare Verbindung (4) zwischen dem Transferträger (3) und der Leitungsstruktur (2) und c) Trennen der trennbaren Verbindung (4) zwischen dem Transferträger (3) und der Leitungsstruktur (2) des Transferträgers (3), wobei die Verbindung (5) zwischen der Leitungsstruktur (2) und dem Substrat (1) erhalten bleibt. Das Verfahren ist insbesondere zur lateralen Anordnung von Leitungsstrukturen mit Nanoröhren (20) bei relativ­niedrigen Temperaturen (T < 600° C) geeignet. So resultiert ein Substrat (1) mit einer Leitungsstruktur (2), die an einer Substratkontaktfläche (10, 11) des Substrats (1) und an mindestens einer weiteren Substratkontaktfläche (10, 11) des Substrats (1) mit dem Substrat (1) verbunden ist. Das Substrat (1) ist dadurch gekennzeichnet, dass die Leitungsstruktur (2) zwischen den beiden Substratkontaktflächen (10, 11) Nanoröhren (20) aufweist, die von der Substratkontaktfläche (10, 11) zur weiteren Substratkontaktfläche (10, 11) ausgerichtet sind. Die Nanoröhren (20) sind lateral angeordnet. Durch das laterale Anordnen entstehen Nanodrähte. Dabei werden die ausgezeichneten elektrischen und thermischen Eigenschaften der Nanoröhren (20) nutzbar gemacht.
PCT/EP2005/050322 2004-02-03 2005-01-26 Verfahren zum anordnen einer leitungsstruktur auf einem substrat und substrat mit der leitungsstruktur WO2005076679A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US10/587,982 US20070120273A1 (en) 2004-02-03 2005-01-26 Method for disposing a conductor structure on a substrate, and substrate comprising said conductor structure
EP05701610A EP1712113A2 (de) 2004-02-03 2005-01-26 Verfahren zum anordnen einer leitungsstruktur auf einem substrat und substrat mit der leitungsstruktur
JP2006551839A JP2007520887A (ja) 2004-02-03 2005-01-26 基板上に導体構造部を配置するための方法及び該導体構造部を備えた基板

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004005255A DE102004005255B4 (de) 2004-02-03 2004-02-03 Verfahren zum Anordnen einer Leitungsstruktur mit Nanoröhren auf einem Substrat
DE102004005255.7 2004-02-03

Publications (2)

Publication Number Publication Date
WO2005076679A2 WO2005076679A2 (de) 2005-08-18
WO2005076679A3 true WO2005076679A3 (de) 2005-12-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2005/050322 WO2005076679A2 (de) 2004-02-03 2005-01-26 Verfahren zum anordnen einer leitungsstruktur auf einem substrat und substrat mit der leitungsstruktur

Country Status (6)

Country Link
US (1) US20070120273A1 (de)
EP (1) EP1712113A2 (de)
JP (1) JP2007520887A (de)
CN (1) CN1914963A (de)
DE (1) DE102004005255B4 (de)
WO (1) WO2005076679A2 (de)

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US20060188721A1 (en) * 2005-02-22 2006-08-24 Eastman Kodak Company Adhesive transfer method of carbon nanotube layer
US8080481B2 (en) * 2005-09-22 2011-12-20 Korea Electronics Technology Institute Method of manufacturing a nanowire device
US9095639B2 (en) * 2006-06-30 2015-08-04 The University Of Akron Aligned carbon nanotube-polymer materials, systems and methods
DE102007047162B4 (de) * 2007-05-25 2011-12-08 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen einer Mikrostruktur oder Nanostruktur und mit Mikrostruktur oder Nanostruktur versehenes Substrat
WO2011103174A2 (en) * 2010-02-16 2011-08-25 Etamota Corporation Process for making thin film heat spreaders
TWI524825B (zh) 2012-10-29 2016-03-01 財團法人工業技術研究院 碳材導電膜的轉印方法
DE102016109950B3 (de) 2016-05-30 2017-09-28 X-Fab Semiconductor Foundries Ag Integrierte Schaltung mit einem - durch einen Überführungsdruck aufgebrachten - Bauelement und Verfahren zur Herstellung der integrierten Schaltung

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WO2003037791A1 (de) * 2001-10-29 2003-05-08 Siemens Aktiengesellschaft Derivatisierte nanoröhren oder nanozwiebeln, komposite mit diesen verbindungen, verfahren zur herstellung und verwendungen
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Also Published As

Publication number Publication date
US20070120273A1 (en) 2007-05-31
JP2007520887A (ja) 2007-07-26
EP1712113A2 (de) 2006-10-18
DE102004005255A1 (de) 2005-08-18
WO2005076679A2 (de) 2005-08-18
CN1914963A (zh) 2007-02-14
DE102004005255B4 (de) 2005-12-08

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