JPH01140773A - Insulated-gate transistor - Google Patents
Insulated-gate transistorInfo
- Publication number
- JPH01140773A JPH01140773A JP62297558A JP29755887A JPH01140773A JP H01140773 A JPH01140773 A JP H01140773A JP 62297558 A JP62297558 A JP 62297558A JP 29755887 A JP29755887 A JP 29755887A JP H01140773 A JPH01140773 A JP H01140773A
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- region
- source
- gate
- base
- electrode
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- 239000000758 substrate Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims 1
- 239000012535 impurity Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- -1 Arsenic ions Chemical class 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
- H01L29/0865—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野Ｊ
本発明は電力用絶縁ゲート形トランジスタに係り、特に
微細化によるオン抵抗の低減と耐圧、破壊強度とが両立
することに好適な構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J] The present invention relates to an insulated gate transistor for power use, and particularly to a structure suitable for reducing on-resistance through miniaturization and achieving both high breakdown voltage and breakdown strength.
従来の装置は、特開昭６０−２５４６５８号に記載のよ
う國、縦形構造のＭＯＳＦＥＴのソース電極と接続ちれ
るソース領域およびベース領域が周期的に形成され、該
ソース領域が島状になるように配置でれていた。In the conventional device, as described in Japanese Unexamined Patent Publication No. 60-254658, a source region and a base region connected to the source electrode of a vertical MOSFET are formed periodically, and the source region is shaped like an island. It was placed in.
上記従来技術は、ソース電極とソース領域およびベース
領域とのコンタクト面積の縮小について配慮されておら
ず、ＭＯＳＦＥＴの低オン抵抗化に関して問題があった
。The above-mentioned conventional technology does not take into consideration the reduction of the contact area between the source electrode and the source region and the base region, and there is a problem in reducing the on-resistance of the MOSFET.
本発明の目的は、ＭＯＳＦＥＴの耐圧と破壊強度を維持
し之ままで、素子の微細化を図ジ、オン抵抗の低減を達
成することＫある。An object of the present invention is to achieve miniaturization of elements and reduction of on-resistance while maintaining the breakdown voltage and breakdown strength of MOSFETs.
上記目的は、ソース電極とソース領域およびベース領域
とのコンタクト面積が縮小できるように、ゲート電極で
囲まれたベース領域内のソース領域を対向するゲート電
極間をつなぐ形で配置し、そのソース領域に隣接するよ
うにベースコンタクト唄域を配置することにより、達成
される。The above purpose is to arrange the source region in the base region surrounded by the gate electrodes so as to connect the opposing gate electrodes, so that the contact area between the source electrode and the source region and base region can be reduced. This is achieved by arranging the base contact singing area adjacent to.
ＭＯＳＦＥＴのゲート電極で回置れたソース領域は、対
向するゲート成極間をつなぐ形で配置さｎるので、その
ソース領域に直交するように配置されたソースコンタク
ト領域は、コンタクト面積が数μｍ以下に縮小さルても
確実にノース領域およびベース表面領域と接続される。The source region, which is rotated by the gate electrode of the MOSFET, is arranged to connect the opposing gate electrodes, so the source contact region, which is arranged orthogonally to the source region, has a contact area of several μm. Even if the area is reduced below, it is reliably connected to the north area and the base surface area.
このことは、本発明の構造を採用することにより、コン
タクト面、 積の縮小が図れることになる。従ってＭ
ＯＳＦＥＴのアクティブ領域を増大させることができ、
オン抵抗の低減が達成できる。This means that by employing the structure of the present invention, the contact surface and area can be reduced. Therefore M
The active area of the OSFET can be increased,
A reduction in on-resistance can be achieved.
〔実施例〕
以下、本発明の一実施例を第１図によシ説明する。第１
図は縦形パワーＭＯ８ＦＥＴの主要部の平面図であり、
第２図はそのＡ−Ａ’線の断面構造図であるう１は高濃
度ｎ形半導体基板、２はｎ形エピタキシャル層で抵抗率
が０，８Ω・鋸、４嘔が１０μｍ、３はｐ形ベース領域
で表面不純物濃度がＩ Ｘ １０ ”ｃｍ−”ｒ深さが
１．５μｍ、４はｎ形ノース領域で表面不純物濃度がＩ
Ｘ １０”ｔｍ−３，深さが０．５μｍ、５は多結晶
シリコンのゲート電極。[Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a plan view of the main parts of a vertical power MO8FET,
Figure 2 is a cross-sectional structural diagram taken along line A-A'. 1 is a high-concentration n-type semiconductor substrate, 2 is an n-type epitaxial layer with a resistivity of 0.8Ω, 4 is 10 μm, and 3 is a p-type semiconductor substrate. 4 is an n-type north region with a surface impurity concentration of I x 10 "cm-" r depth of 1.5 μm, and a surface impurity concentration of I in the n-type base region.
X 10"tm-3, depth 0.5 μm, 5 is a polycrystalline silicon gate electrode.
６はゲート酸化膜で厚さが３５１ｍ、７は保護用絶縁膜
、８はアルミニウムのソース電極、９は金属のドレイン
ｗｔ極である。ここで、ゲート電極は、平面形状がスト
ライプ形であり、その長さＬｎが６μｍ、−ｆ：の間隔
Ｌｓが２μｍである。本実施例では３のベース領域内に
配ｆｉｌｌｎる４のソース領域の平面パターンが第１図
に示すごとく、対向するゲート電極間をつなぐ形で配置
ちれ、３′のベース領域の表面部値域が、上記ソース領
域に隣接して配置され、これらの領域が交互に繰り返さ
れた配置となっている。また、これらの領域とソース電
極とは、図のごとく接続δれ、オーミックコンタクトが
とられている。ゲート’を種下に存在するベース領域と
ソース領域との表面部での長さの差がチャネル長であり
、この場合１μｍである。6 is a gate oxide film with a thickness of 351 m, 7 is a protective insulating film, 8 is an aluminum source electrode, and 9 is a metal drain wt electrode. Here, the gate electrode has a striped planar shape, a length Ln of 6 μm, and an interval Ls of −f: of 2 μm. In this embodiment, the planar pattern of the source region 4 filled in the base region 3 is arranged so as to connect the opposing gate electrodes, as shown in FIG. are arranged adjacent to the source region, and these regions are arranged alternately. Further, these regions and the source electrode are connected δ as shown in the figure, and ohmic contact is established. The difference in length at the surface portion of the base region and the source region which exist under the gate' is the channel length, and in this case is 1 μm.
本実施例によれば＋Ｌｓのゲート電極間隔が２μｍと狭
いにもかかわらず、３’、４のベース領域、ソース領域
と８のソース電極とのオーミックコンタクトが歩留シ艮
く形成された。その結果、４酎角のバ’７−Ｍ０８ＦＥ
Ｔ の特性は、耐圧７０Ｖにおいて、オン抵抗が１５ｍ
Ω、安全動作領域が５０Ｖで５Ａ以上となった。従来の
ゲート電極間隔が６μｍの同一チップサイズの素子に比
べて。According to this example, although the distance between the +Ls gate electrodes was as narrow as 2 μm, ohmic contacts between the base and source regions 3' and 4 and the source electrode 8 were formed with excellent yield. As a result, 4 chuukaku bar'7-M08FE
The characteristics of T are that the on-resistance is 15m at a withstand voltage of 70V.
Ω, the safe operating area was 50V and 5A or more. Compared to a conventional device of the same chip size with a gate electrode spacing of 6 μm.
本実施例の素子は、耐圧、安全動作領域（破壊強度）を
維持したままで、オン抵抗が約３０％低減できた。The device of this example was able to reduce the on-resistance by about 30% while maintaining the withstand voltage and safe operating range (breaking strength).
上記実施例では、１の牛導体基板が、ｎ形高濃度層であ
ったが、これをｐ形高濃度層とすることによシ絶縁ゲー
ト形バイポーラトランジスタとして動作することもでき
た。In the above embodiment, the first conductor substrate was an n-type high concentration layer, but by making it a p-type high concentration layer, it could also operate as an insulated gate type bipolar transistor.
第３図は本発明の実施例を示す縦形パワーＭＯ８ＦＥＴ
の主要な製造工程図である。Figure 3 is a vertical power MO8FET showing an embodiment of the present invention.
This is a diagram of the main manufacturing process.
（ａ） ｎ形エピタキシャル層上にゲート酸化膜６を
３５ｎｍの厚δで形成し、多結晶シリコン５ｔ−厚さ０
．４μｍ堆積し、高濃度のりん不純物をドープし、表面
不純物濃度を約ｌＸｌ０”ｔｌｌｌ−３とする。(a) A gate oxide film 6 is formed on the n-type epitaxial layer to a thickness δ of 35 nm, and a polycrystalline silicon 5t-thickness 0 is formed.
．． It is deposited to a thickness of 4 .mu.m and doped with a high concentration of phosphorus impurity to give a surface impurity concentration of about 1X10''tll-3.
しかる後、ジんガラス絶縁膜７を厚さ５ Ｑ Ｑ ｎｍ
を堆積する。After that, the resin glass insulating film 7 is formed to a thickness of 5 Q Q nm.
Deposit.
Φ）ゲート心極部を選択的に残し、絶縁膜７をマスクと
して、はう素イオン打込みを行う。このとき、多結晶シ
リコン５のゲートはオーバエッチし、絶縁ＰＡ７の端部
がひさしとなるように処理する。Φ) Boron ion implantation is performed using the insulating film 7 as a mask, leaving the gate core portion selectively. At this time, the gate of the polycrystalline silicon 5 is over-etched so that the end of the insulation PA 7 becomes an eaves.
イオン打込み条件は、エネルギ１３０ＫｅＶ 、打込み
量５ Ｘ １０１３ｃｍ−３である。これによりベース
領域３が形成できる。矢に、ホトレジスト膜１０をマス
クとして、ひ素イオン１１をイオン打込みする。そのイ
オン打込み条件は、エネルギ５０ＫｅＶ。The ion implantation conditions were an energy of 130 KeV and an implantation amount of 5×10 13 cm −3 . This allows the base region 3 to be formed. Arsenic ions 11 are implanted into the arrows using the photoresist film 10 as a mask. The ion implantation conditions were an energy of 50 KeV.
打込み量５ Ｘ １０１６ｃｍ−３である。これにより
、ソース領域４が選択的に形成できる。The implantation amount is 5 x 1016 cm-3. Thereby, the source region 4 can be selectively formed.
（Ｃ） 多結晶シリコンのゲート電極端部１２に層目
して水蒸気醸化を行う。１２の酸化膜の形成は、高濃度
のシん不純物がドーグ石れた多結晶シリコン膜が露出し
ている部分の酸化により行われる。(C) A layer of water vapor is added to the end portion 12 of the polycrystalline silicon gate electrode. The oxide film No. 12 is formed by oxidizing the exposed portion of the polycrystalline silicon film containing a high concentration of phosphorus impurities.
この酸化工程により、４や３′の領域表面も酸化さｎる
が、その膜厚は、１２の部分の膜厚よりも薄い。This oxidation process also oxidizes the surfaces of regions 4 and 3', but the film thickness thereof is thinner than that of the region 12.
（ｄ） 次に、全面ドライエツチング処理を行い、ソ
ース、ベースコンタクト上の酸化膜を除去する。(d) Next, dry etching is performed on the entire surface to remove the oxide film on the source and base contacts.
この時、ゲートを電極のひさし部分１３が残されて。At this time, the eaves part 13 of the gate electrode is left behind.
スペーサとなる。It becomes a spacer.
しかる後、ソース電極、ゲート取り出し電極ざらに裏面
にトンイン電極などを形成する。After that, a tunnel-in electrode and the like are formed on the back surface of the source electrode and the gate lead-out electrode.
本製造方法の特徴は、高濃度に不純物をドープした多結
晶シリコンの選択酸化と方向性を有するドライエツチン
グ処理と金組み合わせた点にある。The feature of this manufacturing method is that it combines selective oxidation of polycrystalline silicon doped with impurities at a high concentration, directional dry etching treatment, and gold.
その結果、ソース電極のノース及びベースコンタクト領
域がゲート電極の窓部と自己整合で形成でき１従来約３
μｍは必要であったコンタクトとゲート′電極端部との
合わせ寸法を０．５μｍ以下にすることができた。As a result, the north and base contact regions of the source electrode can be formed in self-alignment with the window of the gate electrode.
With regard to .mu.m, it was possible to reduce the required alignment dimension between the contact and the end of the gate electrode to 0.5 .mu.m or less.
次に本発明の他の実施例を第４図、第５図を用いて説明
するつ第４図は、横形高耐圧ＭＯ８ＦＥＴの主要部平面
図、第５図は、そのＡ−Ａ’線の断面図である。２はｎ
形エピタキシャル層、３はｐ形ベース領域、４はソース
領域、５はゲート電極。Next, another embodiment of the present invention will be explained using FIGS. 4 and 5. FIG. 4 is a plan view of the main part of a horizontal high voltage MO8FET, and FIG. FIG. 2 is n
3 is a p-type base region, 4 is a source region, and 5 is a gate electrode.
６はゲート酸化膜、７は絶縁膜、８はソース電極である
。嘔らに、１４はｎ形低＃に波層でイオン打込みにより
形成した。そのりんイオン打込み条件は、エネルギ５０
ＫｅＶ、 ドーズ量Ｉ Ｘ １０”ｃｍ−”で必る。6 is a gate oxide film, 7 is an insulating film, and 8 is a source electrode. Additionally, No. 14 was formed by ion implantation in an n-type low # wave layer. The phosphorus ion implantation conditions are energy 50
KeV, required at a dose of I x 10"cm-".
１５はｎ形高濃度不純物を有するドレイン領域である。15 is a drain region having n-type high concentration impurity.
１６はトンイン電極である。本実施例では、ベース領域
に形成されソース領域を有する構造で、それらの領域と
ソース電極とのコンタクトをとるために、図に示すよう
に、４０ソース領域と３′のベース領域を交互に配置し
、コンタクト面積の縮小化を図った。16 is a tunnel electrode. In this example, the structure has a source region formed in the base region, and in order to make contact between these regions and the source electrode, 40 source regions and 3' base regions are arranged alternately as shown in the figure. The contact area was also reduced.
また、第５図の高濃度ドレイン領域１５をｐ形とするこ
とにより、絶縁ゲート形バイポーラトランジスタとして
動作させ、良好な特性を得た。Furthermore, by making the heavily doped drain region 15 of FIG. 5 p-type, it was operated as an insulated gate bipolar transistor and good characteristics were obtained.
さらに本発明の他の実施例を第６図を用いて説明する。Furthermore, another embodiment of the present invention will be described using FIG. 6.
第６図は縦形パワーＭＯ８ＦＥＴの主要部の平面図であ
る。本実施例は、第１図に示したソース及びベース領域
の平面配置を変更したもので、ベース表面領域３′を島
状となるように、ソース領域４をゲート電極５の端部に
てりなげたものである。これにより、第１図で示したパ
ワーＭＯ８ＦＥＴに比べて、実効チャネル＋［を増大す
ることができた。FIG. 6 is a plan view of the main parts of the vertical power MO8FET. In this embodiment, the planar arrangement of the source and base regions shown in FIG. It's a great thing. This made it possible to increase the effective channel +[ compared to the power MO8FET shown in FIG.
本発明によれば、Ｍｄゲート形トランジスタのソース電
極のコンタクト面積が縮小できるので、低オン抵抗化に
関して効果が大きい。特に１本発明の製造方法は、従来
のゲート電極端とコンタクト領域とのマスク会わせ間隔
を１１５以下に縮小する自己整合の方法を提供するもの
であるユAccording to the present invention, since the contact area of the source electrode of the Md gate type transistor can be reduced, the effect of lowering the on-resistance is significant. In particular, the manufacturing method of the present invention provides a self-alignment method for reducing the conventional mask alignment distance between the gate electrode end and the contact region to 115 mm or less.
第１図は本発明の一笑流例の縦形パワーＭＯ８ＦＥＴの
平面図、第２図は第１図のＡ−Ａ’線断面図、第３図は
第２図に関連した製造工程図、第４図は本発明の他の実
施例の横形高耐圧ＭＯ８ＦＥＴの平面図、第５図は第４
図のＡ−Ａ’線断面図、第６図は本発明の他の実施例の
成形パワーＭＯＳＦＥＴの平面図である。
１・・・半導体基板、２・・・エピタキシャル層、３・
・・ベース領域、４・・・ノース領域、５・・・ゲート
電極、６・・・ゲート絶縁膜、８・・・ノース電極、９
，１６・・・ドレイン電極、１０・・・ホトレジスト膜
、１１・・・イオンビーム、１２・・・酸化膜、１３・
・・酸化膜スペーサ、１４・・・低濃度ドレイン層、１
５・・・高濃度ドレイン揮Ｓ図FIG. 1 is a plan view of a vertical power MO8FET as an example of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, FIG. 3 is a manufacturing process diagram related to FIG. 2, and FIG. The figure is a plan view of a horizontal high voltage MO8FET according to another embodiment of the present invention, and FIG.
A cross-sectional view taken along the line AA' in the figure, and FIG. 6 is a plan view of a shaped power MOSFET according to another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Epitaxial layer, 3...
...Base region, 4... North region, 5... Gate electrode, 6... Gate insulating film, 8... North electrode, 9
, 16... Drain electrode, 10... Photoresist film, 11... Ion beam, 12... Oxide film, 13...
...Oxide film spacer, 14...Low concentration drain layer, 1
5...High concentration drain volatilization diagram
Claims (1)
ベース領域を有し、該ベース領域中に第１導電形のソー
ス領域を有し、上記ベース領域の周辺表面部分に存在す
る絶縁膜を介してゲート電極を有する絶縁ゲート形トラ
ンジスタにおいて、上記ゲート電極で囲まれたベース領
域内のソース領域が対向するゲート電極間をつなぐ形で
配置され、該ソース領域とそれに隣接した上記ベース領
域の表面部領域とが交互に配置されてソース電極と接続
されていることを特徴とする絶縁ゲート形トランジスタ
。 ２、ゲート電極間の間隔がゲート電極の長さに比べて小
さいことを特徴とする特許請求の範囲第１項記載の絶縁
ゲート形トランジスタ。[Claims] 1. A base region of a second conductivity type is provided in a portion of a semiconductor substrate of a first conductivity type, a source region of a first conductivity type is provided in the base region, and a source region of a first conductivity type is provided in the base region; In an insulated gate type transistor having a gate electrode via an insulating film existing on a peripheral surface portion of the region, a source region in a base region surrounded by the gate electrode is arranged to connect opposing gate electrodes, and An insulated gate transistor characterized in that source regions and surface regions of the base region adjacent thereto are alternately arranged and connected to a source electrode. 2. The insulated gate transistor according to claim 1, wherein the distance between the gate electrodes is smaller than the length of the gate electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62297558A JPH01140773A (en) | 1987-11-27 | 1987-11-27 | Insulated-gate transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62297558A JPH01140773A (en) | 1987-11-27 | 1987-11-27 | Insulated-gate transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01140773A true JPH01140773A (en) | 1989-06-01 |
Family
ID=17848104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62297558A Pending JPH01140773A (en) | 1987-11-27 | 1987-11-27 | Insulated-gate transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01140773A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0848430A2 (en) * | 1996-12-12 | 1998-06-17 | Westinghouse Brake And Signal Holdings Limited | Insulated gate bipolar transistor |
| FR2784231A1 (en) * | 1998-06-26 | 2000-04-07 | Bosch Gmbh Robert | MOSFET COMPONENT |
| US6215138B1 (en) | 1998-04-16 | 2001-04-10 | Nec Corporation | Semiconductor device and its fabrication method |
| US6452222B1 (en) | 1998-12-11 | 2002-09-17 | Nec Corporation | MIS type semiconductor device and method for manufacturing the same |
| WO2005045938A3 (en) * | 2003-11-11 | 2005-08-25 | Koninkl Philips Electronics Nv | Insulated gate field-effect transistor |
| JP2007250780A (en) * | 2006-03-15 | 2007-09-27 | Sharp Corp | Semiconductor device |
| WO2011013380A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| JP2011181541A (en) * | 2010-02-26 | 2011-09-15 | Honda Motor Co Ltd | Semiconductor device |
| CN108962988A (en) * | 2017-05-19 | 2018-12-07 | 立锜科技股份有限公司 | High-voltage metal oxide semiconductor element and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688363A (en) * | 1979-12-20 | 1981-07-17 | Nec Corp | Field effect transistor |
| JPS61164263A (en) * | 1985-01-17 | 1986-07-24 | Toshiba Corp | Conductive modulation type mosfet |
-
1987
- 1987-11-27 JP JP62297558A patent/JPH01140773A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5688363A (en) * | 1979-12-20 | 1981-07-17 | Nec Corp | Field effect transistor |
| JPS61164263A (en) * | 1985-01-17 | 1986-07-24 | Toshiba Corp | Conductive modulation type mosfet |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0848430A2 (en) * | 1996-12-12 | 1998-06-17 | Westinghouse Brake And Signal Holdings Limited | Insulated gate bipolar transistor |
| EP0848430A3 (en) * | 1996-12-12 | 1999-01-13 | Westinghouse Brake And Signal Holdings Limited | Insulated gate bipolar transistor |
| US6147382A (en) * | 1996-12-12 | 2000-11-14 | Westcode Semiconductors Limited | Semiconductor switching device with segmented sources |
| US6215138B1 (en) | 1998-04-16 | 2001-04-10 | Nec Corporation | Semiconductor device and its fabrication method |
| FR2784231A1 (en) * | 1998-06-26 | 2000-04-07 | Bosch Gmbh Robert | MOSFET COMPONENT |
| US6281549B1 (en) | 1998-06-26 | 2001-08-28 | Robert Bosch Gmbh | MOSFET component |
| US6452222B1 (en) | 1998-12-11 | 2002-09-17 | Nec Corporation | MIS type semiconductor device and method for manufacturing the same |
| WO2005045938A3 (en) * | 2003-11-11 | 2005-08-25 | Koninkl Philips Electronics Nv | Insulated gate field-effect transistor |
| JP2007250780A (en) * | 2006-03-15 | 2007-09-27 | Sharp Corp | Semiconductor device |
| WO2011013380A1 (en) * | 2009-07-31 | 2011-02-03 | Fuji Electric Systems Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| JP2012527114A (en) * | 2009-07-31 | 2012-11-01 | 富士電機株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US9136352B2 (en) | 2009-07-31 | 2015-09-15 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| US9312379B2 (en) | 2009-07-31 | 2016-04-12 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| US9496370B2 (en) | 2009-07-31 | 2016-11-15 | Fuji Electric Co., Ltd. | Manufacturing method of semiconductor apparatus and semiconductor apparatus |
| JP2011181541A (en) * | 2010-02-26 | 2011-09-15 | Honda Motor Co Ltd | Semiconductor device |
| CN108962988A (en) * | 2017-05-19 | 2018-12-07 | 立锜科技股份有限公司 | High-voltage metal oxide semiconductor element and its manufacturing method |
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